AT91EB42 Evaluation Board ............................................................................. User Guide Table of Contents Section 1 Overview............................................................................................... 1-1 1.1 1.2 1.3 Scope........................................................................................................1-1 Deliverables ..............................................................................................1-1 The AT91EB42 Evaluation Board .............................................................1-1 Section 2 Setting Up the AT91EB42 Evaluation Board .................................................................................. 2-1 2.1 2.2 2.3 2.4 2.5 2.6 2.7 Electrostatic Warning ................................................................................2-1 Requirements............................................................................................2-1 Layout .......................................................................................................2-1 Jumper Settings ........................................................................................2-2 Powering Up the Board.............................................................................2-2 Measuring Current Consumption on the AT91M42800 ............................2-2 Testing the AT91EB42 Evaluation Board .................................................2-2 Section 3 The On-board Software ........................................................................ 3-1 3.1 3.2 3.3 3.4 3.5 3.6 AT91EB42 Evaluation Board ....................................................................3-1 Boot Software Program.............................................................................3-1 Programmed Default Memory Mapping ....................................................3-2 SRAM Downloader ...................................................................................3-2 Angel Monitor ............................................................................................3-2 Programmed Default Speed .....................................................................3-2 Section 4 Circuit Description................................................................................. 4-1 4.1 4.2 AT91M42800 Processor ...........................................................................4-1 Expansion Connectors and JTAG Interface..............................................4-1 4.2.1 I/O Expansion Connector ...................................................................4-1 4.2.2 EBI Expansion Connector ..................................................................4-1 4.2.3 JTAG Interface ...................................................................................4-1 4.3 4.4 4.5 4.6 4.7 Memories ..................................................................................................4-2 Analog-to-digital Converter .......................................................................4-2 Power and Crystal Quartz .........................................................................4-2 Push Buttons, LEDs, Reset and Serial Interfaces ....................................4-2 Layout Drawing .........................................................................................4-3 i Table of Contents Section 5 Appendix A – Configuration Straps....................................................... 5-1 5.1 5.2 5.3 5.4 Configuration Straps (CB1 - 23, JP1 - 8) ..................................................5-1 Power Consumption Measurement Strap (JP5) .......................................5-4 Ground Links (JP6) ...................................................................................5-4 Increasing Memory Size ...........................................................................5-4 Section 6 Appendix B – Schematics..................................................................... 6-1 6.1 ii Schematics ...............................................................................................6-1 Section 1 Overview 1.1 Scope The AT91EB42 Evaluation Board enables real-time code development and evaluation. It supports the AT91M42800. This guide focuses on the AT91EB42 Evaluation Board as an evaluation and demonstration platform: Section 1 provides an overview. 1.2 Deliverables Section 2 describes how to set up the evaluation board. Section 3 details the on-board software. Section 4 contains a description of the circuit board. Section 5 and Section 6 are two appendices covering configuration straps and schematics, including pin connectors. The evaluation board is delivered with a DB9 plug-to-DB9 socket straight-through serial cable to connect the target evaluation board to a PC. A bare power lead with a 2.1 mm jack on one end for connection to a bench power supply is also delivered. The evaluation board is also delivered with a CD-ROM that contains an evaluation version of the software development toolkit and the documentation that outlines the AT91 microcontroller family. The evaluation board is capable of supporting different kinds of debugging systems, using an ICE interface or the on-board Angel Debug Monitor. Refer to the AT91EB42 Getting Started Tutorial documents for recommendations on using the evaluation board in a full debug environment. 1.3 The AT91EB42 The board consists of an AT91M42800 together with several peripherals: Evaluation Board Two serial ports Reset push button Four user-defined push buttons Eight LEDs a 256 KB 16-bit SRAM (upgradeable to 1M byte) a 2 MB 16-bit Flash (of which 1M byte is available for user software) a 4 MB Serial Data Flash a 64 KB Serial EEPROM a 32 KB SPI EEPROM AT91EB42 Evaluation Board User Guide 1-1 Overview 2 x 32-pin EBI expansion connectors 2 x 32-pin I/O expansion connectors 20-pin JTAG interface connector If required, user-defined peripherals can also be added to the board. See Section 5 for details. Figure 1-1. AT91EB42 Evaluation Board Block Diagram AT91M42800 Reset Controller JTAG ICE Connector 8K Byte RAM SRAM ARM7TDMI Processor EBI Expansion Connector EBI ASB 32.768 KHz Crystal Push-buttons Clock Generator Reset Controller AMBA Bridge Interrupt Controller System Timer Watchdog Flash Serial EEPROM LEDs PIO APB I/O Expansion Connector Timer Counters Serial Data Flash Reset Serial EEPROM SPI PIO 2.1mm DC Power Socket Power Supply Fast-charge Controller 1-2 Serial Ports RS232 Transceivers DB9 Serial Connectors Battery Connector AT91EB42 Evaluation Board User Guide Section 2 Setting Up the AT91EB42 Evaluation Board 2.1 Electrostatic Warning The AT91EB42 Evaluation Board is shipped in protective anti-static packaging. The board must not be subjected to high electrostatic potentials. A grounding strap or similar protective device should be worn when handling the board. Avoid touching the component pins or any other metallic element. 2.2 Requirements Requirements in order to set up the AT91EB42 Evaluation Board are: The AT91EB42 Evaluation Board itself The DC power supply capable of supplying 7.5V to 9V at 1A (not supplied) 2.3 Layout Figure 2-1 shows the layout of the AT91EB42 Evaluation Board. Figure 2-1. Layout of the AT91EB42 Evaluation Board AT91EB42 Evaluation Board User Guide 2-1 Setting Up the AT91EB42 Evaluation Board 2.4 Jumper Settings JP1 is used to boot standard or user programs. For standard operations, set it in the STD position. JP8 is used to select the core power supply of the AT91M42800: 3.3V or 1.8V. For operation at 1.8V, MCK frequency shall be limited to 17 MHz. For more information about jumpers and other straps, see Section 5. 2.5 Powering Up the Board DC power is supplied to the board via the 2.1 mm socket (J1) shown in Figure 2-2. The polarity of the power supply is not critical. The minimum voltage required is 7V. Figure 2-2. 2.1 mm Socket positive (+) or negative (-) 2.1 mm connector A battery power supply can be connected to the board via the J3 connector. A battery fast-charge controller is provided on-board to charge this battery. The board has a voltage regulator providing +3.3V. The regulator allows the input voltage to range from 7 V to 9V. When you switch the power on, the red LED marked POWER lights up. If it does not, switch off and check the power supply connections. 2.6 2.7 Measuring Current Consumption on the AT91M42800 The board is designed to generate the power for the AT91 product, and only the AT91 product, through the jumper JP5 (VDDIO) and JP8 (VDDCORE). This feature enables measurements to be made of the current consumption of the AT91 product. See Section 5 for further details. Testing the To test the AT91EB42 Evaluation Board, perform the following steps: AT91EB42 1. Hold down the SW1 button and power-up the board, or generate a reset and wait for the light sequence on each LED to complete. All the LEDs light once and the Evaluation Board LED D1 remains lit. 2. Release the SW1 button. The LEDs D1 to D7 light up one after the other. If any of the LEDs lights up twice, there is an error. The LEDs represent the following components: D1 for the internal RAM D2 for the external RAM D3 for the external Flash D4 for the serial EEPROM D5 for the SPI DataFlash® D6 for the EEPROM D7 for the USART D8 is reserved If a test is not carried out, the corresponding LED remains unlit and the test sequence restarts. 2-2 AT91EB42 Evaluation Board User Guide Section 3 The On-board Software 3.1 AT91EB42 The AT91EB42 Evaluation Board embeds an AT49BV1604 Flash memory device proEvaluation Board grammed with default software. Only the lowest 8 x 8 KB sectors are used. The remaining sectors are user definable, and can be programmed using one of the Flash downloader solutions offered in the AT91 library. When delivered, the Flash memory device contains: the boot program the functional test software the SRAM downloader the Angel Debug Monitor a default user boot with a default application The boot program, functional test software (FTS) and SRAM downloader are in sector 0 of the Flash. This sector is locked to prevent accidental erase, but it can be unlocked by applying 12V to the RESET pin. 3.2 Boot Software Program The boot software program configures the AT91M42800, and thus controls the memory and other board components. The boot software program is started at reset if JP1 is in the STD position. If JP1 is in the USER position, the AT91M42800 boots from address 0x01010000 in the Flash, which must have a user-defined boot. The boot software program first initializes the EBI, then executes the REMAP procedure, and then checks the state of the buttons. When the button SW1 is pressed: All the LEDs light up together. The D1 LED remains lit until SW1 is released. The functional test software (FTS) is started. When the button SW2 is pressed: All the LEDs light up together. The D2 LED remains lit until SW2 is released. The SRAM downloader is activated. When SW3 or SW4 are pressed or no buttons are pressed: Branch at address 0x0100 2000. The Angel Debug Monitor starts from this address by recopying itself in external SRAM. AT91EB42 Evaluation Board User Guide 3-1 The On-board Software 3.3 Programmed Default Memory Mapping Table 3-1 defines the mapping defined by the boot program. Table 3-1. Memory Map Part Name Start Address End Address Size Device U1 0x01000000 0x011FFFFF 2M Bytes Flash AT49BV1604 U2-U3 0x02000000 0x02040000 256K Bytes SRAM The boot software program, FTS and SRAM downloader are in sectors 1 and 2 of the Flash device. Sectors 2 to 8 support the Angel Debug Monitor. Sector 24 at address 0x0110 0000 must be programmed with a boot sequence to be debugged. This sector can be mapped at address 0x0100 0000 (or 0x0 after a reset) when the jumper JP1 is in the USER position. 3.4 SRAM Downloader The SRAM downloader allows an application to be loaded in the SRAM at the address 0x02000000, then activated. It is started by the boot if the SW2 button is pressed at reset. The procedure is as follows: 1. Connect the AT91EB42 Evaluation Board to the host PC serial “A” connection using the straight serial cable provided. 2. Power-on or press “RESET”, holding down the SW2 button at the same time. Wait for D2 to light up and then release SW2. 3. Start the BINCOM utility, available in the AT91 library, on the host computer: Select the port for communications (COM1 or COM2, depending on where you connected the serial cable on the host PC) and the baud rate for communications (115200 bds, 1 stop bit, no parity). Open the file to be downloaded and send it. Wait for the end of the transfer. 4. Press any button to end the download. The control is switched to the address 0x02000000. 3.5 Angel Monitor The Angel monitor is located in the Flash from 0x01002000 up to 0x0100FFFF. The boot program starts it if no button is pressed at reset. When Angel starts, it recopies itself in SRAM in order to run faster. The SRAM used by Angel is from 0x02020000 to 0x02040000, i.e., the highest half part of the SRAM. The Angel on the AT91EB42 Evaluation Board can be upgraded regardless of the version programmed on it. Note that if the debugger is started through ICE while the Angel monitor is on, the Advanced Interrupt Controller (AIC) and the USART channel are enabled. 3.6 3-2 Programmed Default Speed As the speed of the AT91M42800 is programmable, the boot software program initializes the device to run as fast as possible, i.e., at 40 MHz. The boot software program and the functional test software are run at this speed. The SRAM downloader, after initialization of the USARTs, enters the processor in idle mode and activates the downloaded application at this speed. When Angel is started, it also runs at 40 MHz and the user should not modify this frequency without reprogramming the speed of the USARTs. AT91EB42 Evaluation Board User Guide Section 4 Circuit Description 4.1 AT91M42800 Processor Figure 6-1 on page 6-2 shows the AT91M42800. The footprint is for a 144-pin TQFP package. Strap CB20 enables the user to choose between the standard ICE debug mode and the JTAG boundary scan mode of operation. The operating mode is defined by the state of the JTAGSEL input detected at reset. Jumper JP5 (see Figure 6-8 on page 6-9 in Section 6, “Appendix B – Schematics”) can be removed by the user to allow measurement of the current demand by the whole microcontroller (VDDIO and VDDCORE). Jumper JP8 can be removed to measure the core microcontroller consumption (VDDCORE). 4.2 Expansion Connectors and JTAG Interface The two expansion connectors, I/O expansion connector and EBI expansion connector, and the JTAG interface are described below. 4.2.1 I/O Expansion Connector The I/O expansion connector makes the general-purpose I/O (GPIO) lines, VCC3V3 and Ground, available to the user. Configuration straps CB2, CB3, CB4, CB11, CB13, CB14, CB15, CB17, CB18 and CB19 are used to select between the I/O lines being used by the evaluation board or by the user via the I/O expansion connector. The connector is not fitted at the factory; however, the user can fit any 32 x 2 connector on a 0.1" (2.54 mm) pitch. 4.2.2 EBI Expansion Connector The schematic (Figure 6-4 on page 6-5 in Section 6, “Appendix B – Schematics”) also shows the bus expansion connector which, like the I/O expansion connector, is not fitted at the factory. The user can fit any 32 x 2 connector on a 0.1" (2.54 mm) pitch to gain access to the data, address, chip select, read/write, oscillator output and wait request pins. VCC3V3 and ground are also available on this connector. The I/O and EBI expansion connectors’ pinout and position are compatible with the other evaluation boards (except the I/O expansion connector pinout and position of the EB40) so that users can connect their prototype daughter boards to any of these evaluation boards. Configuration strap CB1, when open, allows the user to connect the EBI expansion connector to the MPI expansion connector of an AT91EB63 evaluation board without any conflicts. 4.2.3 JTAG Interface An ARM®-standard 20-pin box header (P5) is provided to enable connection of an ICE interface to the JTAG inputs on the AT91. This allows code to be developed on the board without using system resources such as memory and serial ports. AT91EB42 Evaluation Board User Guide 4-1 Circuit Description 4.3 Memories The schematic (Figure 6-3 on page 6-4 in Section 6, “Appendix B – Schematics”) shows one AT49BV1604 2 MB 16-bit Flash, one AT45DB321 4 MB serial DataFlash, one AT24C512 64 KB EEPROM, one AT25256 32 KB EEPROM and two 128K/512K x 8 SRAM devices. Note: The AT91EB42 is fitted with two 128K x 8 SRAM devices. A footprint is provided for the user to fit a multi-chip device memory that embeds Flash (1 MB) and SRAM (128 KB) in a single component in place of the Flash and SRAM devices (U7: M36W108AB from ST). Strap JP1 shown on the schematic is used to select the part of 1 MB of the Flash to be accessed. This is to enable users to Flash download their application in the second part of the Flash and to boot on it. 4.4 Analog-to-digital Converter A footprint is provided for the user to fit a 4-channel 10-bit ADC device (AD7817ARU from Analog Devices; see Figure 6-10 on page 6-11 in Section 6, “Appendix B – Schematics”). This device is interfaced to the AT91 microcontroller via the SPIA peripheral. The voltage reference used is the 2.5V on-chip. This device embeds a temperature sensor and is placed near the 32.768 KHz crystal quartz. Thus the user is able to take into account the frequency drift due to temperature evolution by a software program. By default, two of the ADC channels are dedicated to supervise the board power supply voltage levels (channel 1 for the battery power supply, channel 2 for the standard power supply). 4.5 Power and Crystal Quartz The AT91M42800 master clock is derived from a 32.768 KHz crystal quartz. The onchip low-power oscillator together with two PLL-based frequency multipliers and the prescaler results in a programmable master clock between 500 Hz and 33 MHz. Two sets of components for the PLL filters are fitted by default on the board (Figure 6-6 on page 6-7 in Section 6, "Appendix B - Schematics"). They are calculated to provide a 16.77 MHz (PLLA: multiplier factor of 512 and settling time of 600=µs) or a 33.55 MHz (PLLB: multiplier factor of 1024 and settling time of 4 ms) master clock frequency. The voltage regulator provides 3.3V to the board and will light the red POWER LED (D11) when operating. Power can be applied via the 2.1 mm connector to the regulator in either polarity because of the diode-rectifying circuit. Another regulator allows the user to power the AT91M42800 core with 3.3V or 1.8V by means of the JP8 jumper. A battery power supply can be applied via the J3 connector. The type of battery and connections to be used are shown in the schematics (Figure 6-9 on page 6-10 in Section 6, "Appendix B - Schematics"). This type of battery will ensure the power supply of the board for approximately 30 minutes. A battery fast-charge controller is provided onboard to charge this battery. The number of series cells to be charged is set to 5, but can be changed via the CB21, CB22 and CB32 configuration straps. The maximum time allowed for fast-charging is set to 264 minutes. 4.6 4-2 Push Buttons, LEDs, Reset and Serial Interfaces The IRQ0, TIOA0, PB6 and PB21 switches are debounced and buffered. A supervisory circuit has been included in the design to detect and consequently reset the board when the 3.3V supply voltage drops below 3.0V. Note that this voltage can be changed depending on the board production series. The supervisory circuit also provides a debounced reset signal. This device can also generate the reset signal in case AT91EB42 Evaluation Board User Guide Circuit Description of watchdog time-out as the pin NWDOVF of the AT91M42800 is connected to its input MR. The assertion of this reset signal will light up the red RESET LED (D10). By pressing the CLEAR RESET push button (S1), the LED can be turned off. Another supervisory circuit initializes separately the microcontroller-embedded JTAG/ICE interface when the 3.3V supply voltage drops below 3.0V. Note that this voltage can be changed, depending on the board production series. These separated reset lines allow the user to reset the board without resetting the JTAG/ICE interface while debugging. The schematic (Figure 6-5 on page 6-6 in Section 6, "Appendix B - Schematics") also shows eight general-purpose LEDs connected to port B PIO pins (PB8 to PB15). Two 9-way D-type connectors (P3/4) are provided for serial port connection. Serial port A (P3) is used primarily for host PC communication and is a DB9 female connector. TXD and RXD are swapped so that a straight-through cable can be used. CTS and RTS are connected together, as are DCD, DSR and DTR. Serial port B (P4) is a DB9 male connector with TXD and RXD obeying the standard RS-232 pinout. Apart from TXD, RXD and ground, the other pins are not connected. LEDs are connected to the TX and RX signals of both serial ports and show activity on these serial links. A MAX3223 device (U10) and associated bulk storage capacitors provide RS-232 level conversion. 4.7 Layout Drawing The layout diagram (Figure 6-1 on page 6-2 in Section 6, “Appendix B – Schematics”) shows an approximate floorplan for the board. This has been designed to give the lowest board area, while still providing access to all test points, jumpers and switches on the board. The board is provided with four mounting holes, one at each corner, into which feet are attached. The board has two signal layers and two power planes. AT91EB42 Evaluation Board User Guide 4-3 Circuit Description 4-4 AT91EB42 Evaluation Board User Guide Section 5 Appendix A – Configuration Straps 5.1 Configuration Straps (CB1 - 23, JP1 - 8) By adding the I/O and EBI expansion connectors, users can connect their own peripherals to the evaluation board. These peripherals may require more I/O lines than available while the board is in its default state. Extra I/O lines can be made available by disabling some of the on-board peripherals or features. This is done using the configuration straps detailed below. Some of these straps present a default wire (notified by the default mention) that must be cut before soldering the strap. CB1 Closed On-board PB5/A23/CS4 Signal (1) Open AT91 PB5/A23/CS4 signal is not connected to the EBI expansion connector (P1-B21). This authorizes users to connect the EBI expansion connector of this board to the MPI expansion connector of an AT91EB63 Evaluation Board without conflict problems. CB2, CB3, CB4 Closed AT91 PB5/A23/CS4 signal is connected to the EBI expansion connector (P1-B21). (1) ADC Enabling ADC (U20) control lines enabled Open ADC (U20) control lines disabled. This authorizes users to connect the corresponding PIO to their own resources via the I/O expansion connector. CB5 Battery Power Supply Supervisory Enabling Closed(1) Battery power supply is supervised by the ADC (U20) channel 1 via a resistor bridge. The ratio is set to 0.3333 so that the battery voltage range can be supervised (5.5V to 6.2V). Open Battery power supply is not connected to the ADC (U20) channel 1. This authorizes users to connect the corresponding ADC channel to their own resources via the I/O expansion connector. AT91EB42 Evaluation Board User Guide 5-1 Appendix A – Configuration Straps CB7 Closed Standard Power Supply Supervisory Enabling (1) Open Standard power supply is not connected to the ADC (U20) channel 2. This authorizes users to connect the corresponding ADC channel to their own resources via the I/O expansion connector. CB6, CB8 Closed (1) ADC Channels 3 and 4 Enabling ADC (U20) channels 3 and 4 are connected to ground. Open ADC (U20) channels 3 and 4 are not connected to ground. This authorizes users to connect the corresponding ADC channel to their own resources via the I/O expansion connector. CB9 On-board Boot Chip Select Closed (1) AT91 NCS0 select signal is connected to the Flash memory. Open AT91 NCS0 select signal is not connected to the Flash memory. This authorizes users to connect the corresponding select signal to their own resources via the EBI expansion connector. CB10 Closed 5-2 Standard power supply is supervised by the ADC (U20) channel 2 via a resistor bridge. The ratio is set to 0.1485 so that the standard power supply can be supervised up to 15V. Flash Reset (1) The on-board reset signal is connected to the Flash NRESET input. Open The on-board reset signal is not connected to the Flash NRESET input. CB11 PB22 Ready/Busy MCM Memory Signal Closed(1) AT91 PB22 signal is connected to the multi-chip device memory (U7), Ready/Busy output pin Open AT91 PB22 signal is not connected to the multi-chip device memory (U7), Ready/Busy output pin. This authorizes users to connect the corresponding signal to their own resources via the I/O expansion connector CB12 Boot Mode Strap Configuration Open BMS AT91 input pin is set for the microcontroller to boot on an external 16-bit memory at reset. Closed(1) BMS AT91 input pin is set for the microcontroller to boot on an external 8-bit memory at reset. CB13, CB14 I2C EEPROM Enabling Closed(1) EEPROM communication enabled Open EEPROM communication disabled. This authorizes users to connect the corresponding PIO to their own resources via the I/O expansion connector. AT91EB42 Evaluation Board User Guide Appendix A – Configuration Straps CB15 Serial DataFlash Enabling Closed(1) AT91 NPCSA0 select signal is connected to the serial DataFlash memory. Open AT91 NPCSA0 select signal is not connected to the serial DataFlash memory. This authorizes users to connect the corresponding PIO to their own resources via the I/O expansion connector. CB17 Closed SPI EEPROM Enabling (1) EEPROM communication enabled Open EEPROM communication disabled. This authorizes users to connect the corresponding PIO to their own resources via the I/O expansion connector. CB18 Closed PB20 ADC Write Access Signal (1) AT91 PB20 signal is used to control the RD/WR ADC (U20) input pin. Prior to a write access, position this PIO line in a low state. Position it in a high state prior to a read access. Open AT91 PB20 signal is not used to control the RD/WR ADC (U20) input pin. This authorizes users to connect the corresponding signal to their own resources via the I/O expansion connector. CB19 PB18 End of Fast Charge Signal Closed(1) AT91 PB18 signal is connected to the battery charger (U16), NFASTCHG output pin. Open AT91 PB18 signal is not connected to the battery charger (U16), NFASTCHG output pin. This authorizes users to connect the corresponding signal to their own resources via the I/O expansion connector. CB20 JTAGSEL 1-2 (1) AT91 standard ICE debug feature enabled 2-3 IEEE 1149.1 JTAG boundary scan feature enabled CB21, CB22, CB23 Charger Device (U16): Programming the Battery Number of Cells Number of Cells CB21 CB22 CB23 1 Open Closed Closed 2 Open Open Closed 4 Closed Open Closed (1) Open Closed Open 6 Open Open Open 8 Closed Open Open 5 AT91EB42 Evaluation Board User Guide 5-3 Appendix A – Configuration Straps JP1 User or Standard Boot Selection 2-3 The first half part of the Flash memory is accessible at its base address. 1-2 The second half part of the Flash memory is accessible at its base address. This authorizes users to download their own application software in this part and to boot on it. JP2 Push Button Enabling Open SW1-4 inputs to the AT91 are valid. Closed SW1-4 inputs to the AT91 are not valid. This authorizes users to connect the corresponding PIO to their own resources via the I/O expansion connector. JP3 User or Standard Boot Selection Open The RS-232 transceivers are enabled. Closed The RS-232 transceivers are disabled. This authorizes users to connect the corresponding PIO to their own resources via the I/O expansion connector. JP8 Core Power Supply Selection 2-3 The AT91 core is powered by 3.3V power supply. 1-2 The AT91 core is powered by 1.8V power supply. In this case, the maximum frequency that can be used is 17 MHz. Note: 5.2 Power Consumption Measurement Strap (JP5) 1. Hardwired default position: To cancel this default configuration, cut the wire on the board. The JP5 strap enables connection of an ammeter to measure the AT91M42800 global consumption (VDDCORE and VDDIO) when VDDCORE power supply is derived from VDDIO (JP8 in 3V3 position). Core consumption can be measured by connecting another ammeter between JP8 1-2 or 2-3, depending on the power supply used to power the core. The current measured on E11 is the total current required by the AT91M63200 on both VDDIO and VDDPLL. It is also the current consumed by the switching regulator VR1 that provides the 1.8V. 5.3 Ground Links (JP6) The JP6 strap allows the user to connect the electrical and mechanical grounds. 5.4 Increasing Memory Size The AT91EB42 Evaluation Board is supplied with two 128K x 8 byte SRAM memories. If, however, the user needs more than 256K bytes of memory, the devices can be replaced with two 512K x 8 3.3V 10/15 ns SRAMs, giving in total 1024K bytes. 5-4 AT91EB42 Evaluation Board User Guide Section 6 Appendix B – Schematics 6.1 Schematics The following schematics are appended: • Figure 6-1. PCB Layout • Figure 6-2. AT91EB42 Blocks Overview • Figure 6-3. EBI Memories • Figure 6-4. I/O and EBI Expansion Connectors • Figure 6-5. Push Buttons, LEDs and Serial Interface • Figure 6-6. AT91M42800 • Figure 6-7. Reset and JTAG Interface • Figure 6-8. Power Supply and Battery Charger • Figure 6-9. Battery Type and Connection • Figure 6-10. SPI Memories, I2C Memories and SPI ADC The pin connectors are indicated on the schematics: P1 = EBI Expansion Connector (Figure 6-4) P2 = I/O Expansion Connector (Figure 6-4) P3 = Serial A (Figure 6-5) P4 = Serial B (Figure 6-5) P5 = JTAG Interface (Figure 6-7) AT91EB42 Evaluation Board User Guide 6-1 Appendix B – Schematics Figure 6-1. PCB Layout 6-2 AT91EB42 Evaluation Board User Guide A20 PB22 IOB_32 IOB_52 EBI_[0..42] EBI_[0..42] IOB_[0..57] IOB_[0..57] EBI_41 IOB_[54..57] IOB_16 IOB_15 IOB_14 IOB_13 IOB_12 IOB_11 IOB_3 IOB_49 IOB_50 IOB_46 IOB_47 memories connected on EBI NRST VIN[1..4] NPCSA2 NPCSA1 NPCSA0 MOSIA MISOA SPCKA IRQ3 PB19 PB20 PB16 PB17 SERIAL MEMORIES MICROCONTROLLER IOB_[0..53] IOB_[0..53] IOB_[0..57] IOB_[0..57] INPUT / OUTPUT ON BOARD IOB_51 IOB_[36..45] EBI_[0..42] EBI_[0..42] IOB_[6..7] IOB_[9..10] IOB_0 micro / Rst / Wchdog / JTAG co. PB21 PB[6..15] PA[6..7] PA[9..10] PA0 Serial Connectors / P.B. / LED SUPPLY and RTC SAVE EXTENSIONS CONNECTORS IOB_[0..57] PB18 power supply / battery SERIAL MEMORIES Figure 6-2. AT91EB42 Blocks Overview AT91EB42 Evaluation Board User Guide EBI_[0..42] EBI MEMORIES IOB_[0..57] IOB_[0..57] EBI_[0..42] EBI_[0..42] IOB_48 Extension Connectors Appendix B – Schematics 6-3 6-4 9 10 14 13 25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 15 NRST_1 D5 D6 E6 E5 F6 C3 E4 F5 B3 H6 A5 A3 H2 G3 A2 H5 H4 NCS0_1 NRST_1 A17 A18 A19 D2 G4 C1 B2 F4 A4 A1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 12 N C S 0 _ 1 26 11 28 VCC3V3 R2 100k 2 2 NRD NWR0 CB10 2 1 A6 G6 1 NRST CB9 2 NCS1 VCC3V3 1 R1 100k VCC3V3 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 1 NCS0 NWE NOE A20B A[0..19] M36W108AB NEF NRP A17 A18 A19 NG NW NE1S E2S A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 U7 AT49BV1604-90TC RESET CE WE OE NC NC NC NC / Vpp A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 U1 VSS VSS VCCS VCCF NC NC NC NC NC NC NC NC NC RNB DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 GND GND VCCQ VCC I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 2Mbytes FLASH MEMORY B6 D1 B1 F2 C2 D3 E1 E2 F1 F3 G1 H1 H3 G5 D4 C6 C5 E3 C4 B5 G2 B4 46 27 47 37 29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45 Ready/busy C105 100nF VCC3V3 C106 100nF D0 D1 D2 D3 D4 D5 D6 D7 C5 100nF VCC3V3 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 R72 100K VCC3V3 D[0..15] 1 CB11 NCS1 2 IOB_52 NWR0 VCC3V3 C1 100nF VCC3V3 NWR0 VCC3V3 NCS1 A19 D2 D3 D0 D1 A18 A19 D2 D3 D0 D1 A18 A5 A6 A7 A8 A1 A2 A3 A4 A5 A6 A7 A8 A1 A2 A3 A4 PB22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 128k 512k NC A18 A17 A16 A15 OE D7 D6 GND VCC D5 D4 A14 A13 A12 A11 A10 NC 128k 512k NC NC NC A18 A17 A16 A15 OE D7 D6 GND VCC D5 D4 A14 A13 A12 A11 A10 NC NC NC A20 IDT71424S10PH NC NC A0 A1 A2 A3 A4 CS D0 D1 VCC GND D2 D3 WE A5 A6 A7 A8 A9 NC NC U4 IDT71V424S10Y A0 A1 A2 A3 A4 CS D0 D1 VCC GND D2 D3 WE A5 A6 A7 A8 A9 U2 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 A13 A12 A11 A10 A9 A17 A16 A15 A14 A13 A12 A11 A10 A9 A17 A16 A15 A14 D5 D4 D7 D6 D5 D4 D7 D6 VCC3V3 VCC3V3 C3 100nF VCC3V3 NWR1 NCS1 IOB_32 3 2 74LVC02AD 1 1 JP1 jumper_3P 1 NC A18 A17 A16 A15 OE D7 D6 GND VCC D5 D4 A14 A13 A12 A11 A10 NC 128k 512k NC NC NC A18 A17 A16 A15 OE D7 D6 GND VCC D5 D4 A14 A13 A12 A11 A10 NC NC NC IDT71424S10PH NC NC A0 A1 A2 A3 A4 CS D0 D1 VCC GND D2 D3 WE A5 A6 A7 A8 A9 NC NC U5 A20B USER BOOT 2 128k 512k IDT71V424S10Y A0 A1 A2 A3 A4 CS D0 D1 VCC GND D2 D3 WE A5 A6 A7 A8 A9 U3 STD BOOT D[0..15] EBI_[0..15] 3 A[0..19] A5 A6 A7 A8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 CTL[0..6] A19 D10 D11 D8 D9 A1 A2 A3 A4 A5 A6 A7 A8 A1 A2 A3 A4 EBI_[16..35] NWR1 GND NCS1 A18 A19 D10 D11 D8 D9 A18 EBI_[36..42] VCC3V3 U6A VCC3V3 EBI_[0..42] NRD layout for TSSOP 400mil. C2 100nF VCC3V3 NRD layout for SOJ 400mil. 1Mbytes ( two 512kX8 ) SRAM with two footprints or 256kbytes ( two 128kX8 ) SRAM with two footprints. CTL6 CTL4 CTL5 CTL2 CTL1 CTL0 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 A13 A12 A11 A10 A9 A17 A16 A15 A14 A13 A12 A11 A10 A9 A17 A16 A15 A14 NRD NRD NCS1 NCS0 VCC3V3 NOE NUB NWE VCC3V3 C4 100nF VCC3V3 NRD NRST NWR1 NWR0 D13 D12 D15 D14 D13 D12 D15 D14 Appendix B – Schematics Figure 6-3. EBI Memories AT91EB42 Evaluation Board User Guide Appendix B – Schematics Figure 6-4. I/O and EBI Expansion Connectors AT91EB42 Evaluation Board User Guide 6-5 SW3 1 R17 100K JP3 jumper_NO VAL_RS232 PA7 PA10 VCC3V3 D31 GREEN LED R75 100R VCC3V3 D32 GREEN LED R76 100R R74 100R D30 ORANGE LED VCC3V3 100nF 2 PB7 PB6 PB21 6 8 11 RXD0 RXD1 TXD0 TXD1 C22 100nF C18 100nF VCC3V3 PA0 3 74LV125D TCLK5 TCLK0 TIOA0 IRQ0 14 1 15 10 13 12 6 5 4 2 MAX3223ECAP U10 PB21 INVALID R1IN R2IN T1OUT T2OUT V- V+ FORCEOFF 100nF C16 R44 100k R43 100k FORCEON EN R1OUT R2OUT T1IN T2IN C2- C2+ C1- C1+ R45 100k R42 100k VCC3V3 GND 2 VCC3V3 PA[9..10] PA6 PA9 R73 100R D29 ORANGE LED VCC3V3 1 C12 EN U9 R5 100k JP2 jumper_NO VCC VALID RS232 on IOB PA[9..10] PA[6..7] R16 100k VCC3V3 C15 47nF 13 12 10 9 4 5 1 2 7 18 PA7 SW4 R15 100K VCC3V3 C11 47nF 1 2 19 PA[6..7] PA0 SW2 VALBP VALBP VCC3V3 14 C14 47nF R14 100K VCC3V3 C10 47nF R4 100K VCC3V3 20 11 16 9 17 8 7 3 VCC3V3 VCC3V3 4 6 8 PB9 PB10 PB11 100nF 100nF VCC3V3 C19 C17 17 PB15 22pF C26 22pF C27 100nF C13 GND SIGNAL EN EN U8 74LV244D 15 13 PB13 PB14 11 PB12 19 2 1 PB8 VALBP 20 PA0 SW1 TP 33 TP 33 R3 100K TP 33 6-6 TP 33 VCC3V3 VCC3V3 3 5 7 9 12 14 16 18 R10 R11 R12 R13 D5 D6 D7 D8 TX1 RX1 C23 22pF RX0 C24 22pF R9 D4 22pF R8 D3 C20 DTR0 DCD0 DSR0 R7 D2 TX0 R6 D1 VCC3V3 Red LED PB[6..15] C21 22pF CTS0 RTS0 100R 100R 100R 100R 100R 100R 100R 100R 1 6 2 7 3 8 4 9 5 1 6 2 7 3 8 4 9 5 VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 VCC3V3 Sub D 9b M P4 10nF C25 Sub D 9b F P3 PB[6..15] Usart 1: SERIAL B Usart 0: SERIAL A Appendix B – Schematics Figure 6-5. Push Buttons, LEDs and Serial Interface 10 AT91EB42 Evaluation Board User Guide 1 CB12 PA27 VCC3V3 AT91EB42 Evaluation Board User Guide 59 58 57 56 55 54 53 D15 D14 D13 52 51 50 GND VDDIO GND GND 49 48 D12 D11 D10 D9 D8 D7 D6 D5 D4 D[0..15] PB0 / NCS2 PB1 / NCS3 61 60 A[0..19] TCLK2 TIOB1 TIOA1 TCLK1 TIOB0 TIOA0 TCLK0 EBI_[0..15] GND VDDIO 70 69 68 67 66 65 64 63 62 EBI_[16..35] PB12 / PB11 / PB10 / PB9 / PB8 / PB7 / PB6 / TCLK5 TIOB4 TIOA4 TCLK4 TIOB3 TIOA3 TCLK3 TIOB2 TIOA2 VDDCORE 100nF VDDIO VDDCORE CTL[0..6] PB21 / PB20 / PB19 / PB18 / PB17 / PB16 / PB15 / PB14 / PB13 / C49 100nF VDDIO GND 74 73 76 75 83 82 81 80 79 78 77 72 71 PB[0..23] PB23 PB22 VDDIO VDDCORE C51 100nF VDDIO PA6 PA5 PA4 PA3 PA2 PA1 PA0 PA10 PA9 PA8 PA7 89 88 87 86 85 84 PA16 PA15 PA14 PA13 PA12 PA11 95 94 93 92 91 90 VDDIO VDDCORE GND GND VDDIO PA17 97 96 98 PA25 PA24 PA23 PA22 PA21 PA20 PA19 PA18 106 105 104 103 102 101 100 99 PB[0..23] PA[0..29] PLLRCB JTAGSEL NWDOVF NRST IOB_[30..53] IOB_[0..29] 100nF 10% C47 100nF 10% C46 IOB_[0..53] C48 1µF 10% R20 R21 680R 1% 120R 1% 1 2 1 2 PLL filter B 10nF 10% C45 2 PLL filter A C44 1 2 Y1 32,768kHz C43 1 R18 R19 1K50 1% 100R 1% 1 2 1 2 JTAGSEL NWDOVF CTL5 Guard ring PLLRCA XIN Guard ring XOUT 100K R48 2 EBI_[36..42] C50 NWDOVF PA27 / BMS PB23 / TIOB5 PB22 / TIOA5 PA6 / TXD0 PA5 / SCK0 PA4 / FIQ PA3 / IRQ3 PA2 / IRQ2 PA1 / IRQ1 PA0 / IRQ0 GND VDDIO PA10 / RXD1 PA9 / TXD1 / NTRI PA8 / SCK1 PA7 / RXD0 PA16 / NPCSA2 PA15 / NPCSA1 PA14 / NPCSA0 / NSSA PA13 / MOSIA PA12 / MISOA PA11 / SPCKA GND VDDIO PA17 / NPCSA3 PA24 / NPCSB3 PA23 / NPCSB2 PA22 / NPCSB1 PA21 / NPCSB0 / NSSB PA20 / MOSIB PA19 / MISOB PA18 / SPCKB 108 107 100nF 100nF VDDCORE EBI_[0..42] 116 PLLRCA 117 VDDPLL 118 PLLRCB 119 VDDPLL VDDCORE VDDIO 112 GND 113 XIN 114 XOUT 115 GND 35 36 D0 D1 D2 D3 NWAIT NOE / NRD NWE / NWR0 NUB / NWR1 NCS0 NCS1 31 32 33 34 VDDCORE VDDIO D0 D1 D2 D3 143 144 CS7 CS6 CS5 CS4 141 142 / / / / PB0 PB1 135 136 137 138 139 140 VDDIO GND A20 A21 A22 A23 CTL3 CTL2 CTL0 CTL1 CTL4 CTL6 PA29 / HOLD / / / / 134 A19 PB2 PB3 PB4 PB5 PA29 2 PB2 PB3 PB4 PB5 VDDIO 132 133 NRST PA28 / HOLDA VDDIO GND 130 131 24 25 CTL5 JTAGSEL TMS TDI TDO TCK NTRST 1 26 27 28 29 30 124 125 126 127 128 129 VDDIO PA28 JTAGSEL JTAG2 JTAG1 JTAG4 JTAG3 JTAG0 1 A19 PA27 122 123 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 VDDIO 120 121 PA25 / MCKO VDDIO VDDCORE C28 C29 VDDIO 14 15 16 17 18 19 20 21 22 23 NWDOVF AT91M42800 VDDPLL U11 PLLRCB PA26 2 VDDIO GND PLLRCA 1 12 13 VT XIN XOUT GND GND VDDIO GND GND 109 110 NLB / A0 A1 A2 A3 A4 A5 A6 A7 A8 111 1 2 JTAG[0..4] PA26 3 4 5 6 7 8 9 10 11 CTL[0..6] JTAG[0..4] PA[0..29] VT CB16 1 2 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A0 A1 A2 A3 A4 A5 A6 A7 A8 CTL3 PB[0..23] NWAIT 1 VDDIO C30 100nF 100K R46 2 VDDCORE VCC3V3 VCC3V3 1 PB[0..23] A[0..19] 2 BMS 2 Default boot Mode : 16 Bits R41 100K Appendix B – Schematics Figure 6-6. AT91M42800 PB21 PB20 PB19 PB18 PB17 PB16 PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 VDDIO D15 D14 D13 47 46 45 44 43 42 41 40 39 VDDIO D12 D11 D10 D9 D8 D7 D6 D5 D4 38 37 6-7 6-8 NWDOVF C78 10pF C84 10pF JTAG4 1 MR VCC 100nF C94 3 4 CTL6 NRST C85 10pF C79 10pF JTAG1 S1 B.P. 74LVC74AD MR VCC 3 4 100nF 100nF JTAG4 9 JTAG3 19 17 15 13 11 7 5 JTAG1 JTAG2 3 NRST R27 100k 1 JTAGSEL VCC3V3 JTAGSEL MAX6315US30D4-T RST GND U13 C53 C52 9 8 5 6 JTAG0 2 1 10 11 12 13 C81 10pF JTAG3 R78 100K VCC3V3 C80 10pF JTAG2 MAX6315US30D4-T RST GND U14 PBRST 2 SW5 TP 33 JTAG0 U6B 4 CLEAR RST LED 74LVC02AD 1 S C1 1D R U12 7 JTAG[0..4] 6 5 4 3 2 1 14 RESET NRST VCC3V3 1 3 R25 100k GND GND GND GND GND GND GND GND GND 20 18 16 14 12 10 8 6 4 2 G9 G8 G7 G6 G5 G4 G3 G2 G1 10nF C71 VCC3V3 VCC3V3 CTL5 VCC CB20 JTAG HE10 2x10 NC NC NRST TDO TCK TCK TMS TDI NTRST VCC P5 ICE 2 IEEE VCC3V3 VCC3V3 RSTLED NRST G4 G3 G2 G1 RESET 100R R23 C82 10nF C76 10nF C74 10nF C72 10nF D10 Red LED G9 G8 G7 G6 G5 C86 10nF C83 10nF C77 10nF C75 10nF C73 10nF 3V3 SUPPLY D11 Red LED R24 100R VCC3V3 Appendix B – Schematics Figure 6-7. Reset and JTAG Interface AT91EB42 Evaluation Board User Guide AT91EB42 Evaluation Board User Guide C61 1 F 1 2 2 5 LT1503CS8-1.8 SHDN/SS C1- C1+ Vin U17 Vbatt- GND C2- C2+ Vout 7 8 6 1 10nF C62 1 F 6 7 5 1 16 + C103 10nF C63 10 F / 16V TLO Temp THI Vlimit REF FASTCHG V+ 11 3 1 10K CTN R58 10K R59 4k7 8 15 150R CC 4 TC C102 V+ R30 Batt- PGM1 PGM0 PGM3 PGM2 Batt+ 12 4 3 10 9 2 Vbatt+ 2R5 / 1W R62d R62c 10R 10R Vbatt- 2 V+ 2 1 CB22 1 CB23 2 Vbatt- Vbatt+ 1 CB21 5 cel. NiCd Timeout 264mn U16 MAX 713CSE C64 1 F Q1 MJD45H11 GND 1 F R60 Rth2 Rth1 C100 1 F C99 10 F / 25V 10nF DRV C101 Red LED CB19 1 2 5 6 7 8 2 100R D28 NC NC NC NC C98 14 R29 LM334SM NC V+ R V- VIN VCC1V8 VDDIO SENSE 10K Rth2 in place only if Therm sensor on Batt. is not use. con. male 43045-0400+43031-0007 MOLEX D26 10MQ100N C60 3,3nF / 10% 7 1 3 2 JP8 jumper_3P D15 1N5817 C54 100nF I Vddcore VDDCORE=3.3V R79 SYNC SHTDN 3 U15 LT1507CS8-3.3 VDDCORE=1.8V Rth1 1 2 3 4 J3 D25 10MQ100N R62b R62a 10R 10R C57 10 F / 25V 4 5 VSW 8 PB18 VCC3V3 4 3 2 1 2 jumper_NO JP6 D19 10MQ100N D18 10MQ100N C57B 10 F / 25V 10MQ100N VIN 6 VCC3V3 R77 6R8 1 SMT6T15CA D17 10MQ100N D16 10MQ100N 2 VC U22 D14 VIN_1 1N914 GND C59 22pF / 25V VINplug2 1000m A/30V VIN D12 BOOST Jack Dia.2.1mm J1 22pF / 25V VIN1F D24 1 C55 VINplug1 F1 Vps 10 H L1 + C58 + TP4 Test Point Corner 4 TP1 Test Point Corner 1 100 F / 10V 100 F / 10V C58B JP5 jumper_NO I Vddio VDDIO VDDPLL VDDCORE TP3 Test Point Corner 3 TP2 Test Point Corner 2 1 2 VCC3V3 Appendix B – Schematics Figure 6-8. Power Supply and Battery Charger 13 6-9 Appendix B – Schematics Figure 6-9. Battery Type and Connection Battery : 6V / 300mAH NiCd Wire: gauge 20 AWG 1 J2 con. fem. 43025-0400+43030-0007 MOLEX 1 2 3 4 BT1 6V / 300mAH SAFT : VRE 1/2 AA Ref 139 663 R61 T˚C Wire: gauge 20 AWG 2 10K CTN SIEMENS B57861S103F40 Tmax 45˚C 6-10 AT91EB42 Evaluation Board User Guide AT91EB42 Evaluation Board User Guide PB20 VIN[1..4] NPCSA2 IRQ3 PB19 PB16 PB17 2 1 CB4 100k 100k 1 CB18 2 VCC3V3 PB20_1 R71 100k 10 18 17 16 15 14 13 19 20 7 8 6 5 1 2 3 4 Vin4 Vin3 10 9 11 12 16 15 14 13 9 8 U6D U6C 7 C89 10 100nF 1 VCC3V3 13 74LVC02AD 1 74LVC02AD A/D converter on SPIA AD7817ARU Vin1 Vin2 VDD DGND AGND REFin RD / WR SCLK Din Dout CONVST BUSY OTI CS U20 RD/WR NPB20 10µF / 16V C104 VIN4 VIN3 100nF C90 RD/WR SPCKA MOSIA MISOA C67 100nF VCC3V3 Serial EEPROM memory on PIO 12 Vps GND NC NC NC NC NC NC WP VCC AT24C512W1-10SC-2.7 SDA SCL Vbatt+ 11 12 NC NC NC NC NC NC NC A0 A1 NPCSA2_1 10pF 10pF VIN1 VIN2 SDA1 SCL1 3 4 5 6 7 8 9 1 2 U19 11 C7 C6 2 R31 100k NPB20 R 7 0 4K30 / 1% 1 1 100k R 6 9 750R / 1% CB7 2 CB5 2 R65 NPCSA2_1 NCONVST BUSY R64 R63 CB13 R68 1K50 1% 2 1 R 6 7 750R / 1% VCC3V3 2 1 CB3 VCC3V3 VCC3V3 CB14 2 1 1 CB2 SCL SDA R51 100K VCC3V3 + VCC3V3 CB8 VCC3V3 2 CB6 2 1 1 NPCSA0 MOSIA MISOA SPCKA NRST CB15 NPCSA1 1 2 1 CB17 2 9 10 11 12 4 5 6 R66 100k VCC3V3 NPCSA1_1 MOSIA MISOA SPCKA VCC3V3 R40 100k MOSIA MISOA SPCKA 13 15 16 14 NRST NPCSA0 R32 100k 1 2 3 R34 100k VCC GND HOLD WP 4 7 3 8 AT25256W-10SC-2.7 SI SO SCK CS U21 R53 100K C70 100nF VCC3V3 VCC3V3 C65 100nF VCC3V3 Serial EEPROM memory on SPIA 5 2 6 1 8 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 7 R52 100K GND NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC VCC Data Flash Memory AT45DB321-TC NC NC NC NC NC NC NC CS SI SO SCK RDY/BUSY RESET WP U18 VCC3V3 Appendix B – Schematics Figure 6-10. SPI Memories, I2C Memories and SPI ADC 14 6-11 Atmel Headquarters Atmel Operations Corporate Headquarters Atmel Colorado Springs Europe Atmel Rousset 2325 Orchard Parkway San Jose, CA 95131 TEL (408) 441-0311 FAX (408) 487-2600 Atmel U.K., Ltd. Coliseum Business Centre Riverside Way Camberley, Surrey GU15 3YL England TEL (44) 1276-686-677 FAX (44) 1276-686-697 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL (719) 576-3300 FAX (719) 540-1759 Zone Industrielle 13106 Rousset Cedex France TEL (33) 4-4253-6000 FAX (33) 4-4253-6001 Asia Atmel Asia, Ltd. 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