SCAS331 − DECEMBER 1992 − REVISED MARCH 1994 D Low Output Skew, Low Pulse Skew for D D D D D D DB OR DW PACKAGE (TOP VIEW) Clock-Distribution and Clock-Generation Applications TTL-Compatible Inputs and Outputs Distributes One Clock Input to Eight Outputs − Four Same-Frequency Outputs − Four Half-Frequency Outputs Distributed VCC and Ground Pins Reduce Switching Noise High-Drive Outputs (− 48-mA IOH, 48-mA IOL) State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages Y3 GND Y4 VCC OE CLR VCC Q4 GND Q3 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 Y2 GND Y1 VCC CLK GND VCC Q1 GND Q2 description The CDC339 is a high-performance, low-skew clock driver. It is specifically designed for applications requiring synchronized output signals at both the primary clock frequency and one-half the primary clock frequency. The four Y outputs switch in phase and at the same frequency as the clock (CLK) input. The four Q outputs switch at one-half the frequency of CLK. When the output-enable (OE) input is low and the clear (CLR) input is high, the Y outputs follow CLK and the Q outputs toggle on low-to-high transitions of CLK. Taking CLR low asynchronously resets the Q outputs to the low level. When OE is high, the outputs are in the high-impedance state. The CDC339 is characterized for operation from − 40°C to 85°C. FUNCTION TABLE INPUTS OUTPUTS OE CLR CLK Y1−Y4 Q1−Q4 H X X Z Z L L L L L L L H H L H L L L Q0† Q0† L H ↑ H † The level of the Q outputs before the indicated steady-state input conditions were established. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC-ΙΙB is a trademark of Texas Instruments Incorporated. Copyright 1994, Texas Instruments Incorporated ! "#$ %!& % "! "! '! ! !( ! %% )*& % "!+ %! !!$* $%! !+ $$ "!!& POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SCAS331 − DECEMBER 1992 − REVISED MARCH 1994 logic symbol† OE 5 logic diagram (positive logic) OE 18 18 CLK 20 16 1 3 13 T CLR 6 5 EN 11 10 R 8 Y1 Y1 Y2 20 Y3 Y2 Y4 1 Q1 Y3 Q2 Q3 3 Q4 CLK † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. T CLR Y4 16 6 13 R 11 10 8 Q1 Q2 Q3 Q4 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Voltage range applied to any output in the disabled or power-off state, VO . . . . . . . . . . . . . . . −0.5 V to 5.5 V Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DB package . . . . . . . . . . . . . . . . . . 0.6 W DW package . . . . . . . . . . . . . . . . . 1.6 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCAS331 − DECEMBER 1992 − REVISED MARCH 1994 recommended operating conditions (see Note 3) MIN MAX UNIT 4.75 5.25 V VCC VIH Supply voltage VIL VI Low-level input voltage IOH IOL High-level output current VCC −48 Low-level output current 48 mA fclock TA Input clock frequency 80 MHz 85 °C High-level input voltage 2 V 0.8 Input voltage 0 Operating free-air temperature −40 V V mA NOTE 3: Unused pins (input or I/O) must be held high or low. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT −1.2 V VIK VOH VCC = 4.75 V, VCC = 4.75 V, II = −18 mA IOH = − 48 mA VOL IIH VCC = 4.75 V, VCC = 5.25 V, IOL = 48 mA VI = 2.7 V 0.5 V 50 µA IIL IOZ IO‡ VCC = 5.25 V, VCC = 5.25 V, VI = 0.5 V VO = 2.7 V or 0.5 V −50 µA VCC = 5.25 V, VO = 2.5 V VCC = 5.25 V, VI = VCC or GND IO = 0, ICC Ci Co 2 V −50 ± 50 µA −180 mA Outputs high 70 Outputs low 85 Outputs disabled 70 VI = 2.5 V or 0.5 V VO = 2.5 V or 0.5 V mA 3 pF 8 pF † All typical values are at VCC = 5 V, TA = 25°C. ‡ Not more than one output should be tested at a time, and the duration of the test should not exceed one second. timing requirements over recommended ranges of supply voltage and operating free-air temperature MIN fclock Clock frequency tw Pulse duration tsu Setup time CLR low 4 CLK low 4 CLK high 4 CLR inactive before CLK↑ Clock duty cycle • DALLAS, TEXAS 75265 UNIT 80 MHz ns 2 40% POST OFFICE BOX 655303 MAX ns 60% 3 SCAS331 − DECEMBER 1992 − REVISED MARCH 1994 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Figures 1 and 2)12 PARAMETER fmax tPLH tPHL tPHL FROM (INPUT) TO (OUTPUT) MIN TYP† 80 CLK Any Y or Q CLR Any Q 9 3 9 4 9 2 7 3 7 2 7 2 7 OE Any Y or Q tPHZ tPLZ OE Any Y or Q Y↑ 0.75 tsk(o) CLK↑ Q↑ 0.9 Y↑ and Q↑ † All typical values are at VCC = 5 V, TA = 25°C. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT MHz 3 tPZH tPZL tr tf 4 MAX ns ns ns ns ns 0.9 0.9 ns 0.7 ns SCAS331 − DECEMBER 1992 − REVISED MARCH 1994 PARAMETER MEASUREMENT INFORMATION 7V S1 500 Ω From Output Under Test TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open GND CL = 50 pF (see Note A) S1 Open 7V Open 500 Ω tw LOAD CIRCUIT 3V Input 3V Timing Input 1.5 V 1.5 V 0V 1.5 V 0V tsu VOLTAGE WAVEFORMS th 3V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS 1.5 V 0V tPHL 2V 0.8 V tr 1.5 V 0V tPLZ 1.5 V tPLH Output 1.5 V tPZL 3V Input 3V Output Control (low-level enabling) 1.5 V VOH 2V 0.8 V VOL tf 3.5 V Output Waveform 1 S1 at 7 V (see Note C) Output Waveform 2 S1 at Open (see Note C) 1.5 V tPZH VOLTAGE WAVEFORMS VOL + 0.3 V VOL tPHZ VOH 1.5 V VOH − 0.3 V ≈0V VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SCAS331 − DECEMBER 1992 − REVISED MARCH 1994 PARAMETER MEASUREMENT INFORMATION CLK Y1 tPLH1 tPLH9 tPLH2 tPLH10 tPLH3 tPLH11 tPLH4 tPLH12 Y2 Y3 Y4 Q1 tPLH5 Q2 tPLH6 Q3 tPLH7 Q4 tPLH8 NOTES: A. Output skew, tsk(o), from CLK↑ to Y↑, is calculated as the greater of the difference between the fastest and slowest of tPLHn (n = 1, 2, 3, 4) or tPLHn (n = 9, 10, 11, 12). B. Output skew, tsk(o), from CLK↑ to Q↑, is calculated as the greater of the difference between the fastest and slowest of tPLHn (n = 5, 6, 7, 8). C. Output skew, tsk(o), from CLK↑ to Y↑ and Q↑, is calculated as the greater of the difference between the fastest and slowest of tPLHn (n = 1, 2, . . . , 8). Figure 2. Skew Waveforms and Calculations 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 30-Jul-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) CDC339DB ACTIVE SSOP DB 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CDC339DBG4 ACTIVE SSOP DB 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CDC339DBG4 ACTIVE SSOP DB 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CDC339DBLE OBSOLETE SSOP DB 20 TBD Call TI Call TI CDC339DBLE OBSOLETE SSOP DB 20 TBD Call TI Call TI CDC339DW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CDC339DW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CDC339DWG4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CDC339DWG4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CDC339NSR OBSOLETE SO NS 20 TBD Call TI Call TI CDC339NSR OBSOLETE SO NS 20 TBD Call TI Call TI CDC339NSRG4 OBSOLETE SO NS 20 TBD Call TI Call TI CDC339NSRG4 OBSOLETE SO NS 20 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 30-Jul-2011 Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 2 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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