Mitsubishi M62320P 8-bit i/o expander for i2c bus Datasheet

MITSUBISHI < STD. LINEAR ICs >
M62320P,FP
2
8-BIT I/O EXPANDER for I C BUS
GENERAL DESCRIPTION
The M62320P/FP is a CMOS 8-bit I/O expander which has
serial to parallel and parallel to serial data converting
functions.
It can communicate with a microcontroller via few wiring
2
thanks to the adoption of the two-line I C BUS.
Parallel data I/O terminal can be set to input or output
mode alternatively in individual bits.
Maximum 8 ICs can be connected to a bus by using three
chip-select pins, so that it is possible to handle up to 64 bits
data.
PIN CONFIGURATION(TOP VIEW)
SO 1
15 CS1
2
SDA
3
D0
4
D1
5
D2
6
D3
7
10 D5
GND
8
9 D4
M62320P,FP
SCL
FEATURES
• Simple two-line (SCL and SDA) communication with a
microcontroller.
• 8-bit data conversion between serial and parallel by
I2 C BUS.
• Built-in power-on reset.
16 CS0
14 CS2
13 VDD
12 D7
11 D6
Outline 16P4(P)
16P2N(FP)
APPLICATION
I/O port expansion for a microcontroller.
Data conversion between serial and parallel in
microcontroller peripherals.
BLOCK DIAGRAM
CS0 CS1 CS2
15
16
14
CHIP-SELECT
SCL
2
SDA
3
2
I C BUS
TRANSCEIVER
Output Data
8
OUTPUT DATA
LATCH
Input/Output
8
I/O SETTING
DATA LATCH
8
VDD 13
GND 8
POWER-ON
RESET
SHIFT
REGISTER
1
SO
8
INPUT DATA
LATCH
8
8
Input Data
Å@
I/O PORT
12
11
10
9
7
6
5
4
D7
D6
D5
D4
D3
D2
D1
D0
MITSUBISHI ELECTRIC
2/20,1998(rev) ( 1 / 9 )
MITSUBISHI < STD. LINEAR ICs >
M62320P,FP
2
8-BIT I/O EXPANDER for I C BUS
PIN DESCRIPTION
Pin No. Symbol
Function
I/O
2
SCL
Input
3
SDA
Input/
Output
Serial data input/output
1
SO
Output
Serial data output
16
CS0
15
CS1
14
CS2
4
D0
5
D1
6
D2
7
D3
9
D4
10
D5
11
D6
12
D7
13
VDD
Power supply
8
GND
GND
Serial clock input
Input
Chip select data input
Input/
Output
Parallel data input/output
MITSUBISHI ELECTRIC
2/20,1998(rev) ( 2 / 9 )
MITSUBISHI < STD. LINEAR ICs >
M62320P,FP
2
8-BIT I/O EXPANDER for I C BUS
ABSOLUTE MAXIMUM RATINGS
Symbol
Ratings
Conditions
Parameter
Unit
V
VDD
Supply voltage
VI
Input voltage
–0.3 to VDD+0.3
V
VO
Output voltage
–0.3 to VDD+0.3
V
IOH
Output current "Low"
D0 to D7
- 5 to 0
mA
IOL
Output current "High"
D0 to D7
0 to 30
mA
Pd
Power dissipation
Ta = 25°C
1220(P) / 980(FP)
mW
Topr
Operating temperature
Tstg
Storage temperature
–0.3 to 7.0
-20 to 85
°C
-40 to 125
°C
RECOMMENDED OPERATING CONDITIONS
• Supply voltage………VDD=5V±10%
• Input high voltage……VIH=0.8VDD to VDD
• Input low voltage………VIL=0 to 0.2VDD
ELECTRICAL CHARACTERISTICS (VDD=5V ±10%, GND=0V,Ta=20 to 85°C, unless otherwise noted)
Symbol
IDD
Parameter
Circuit current
Conditions
Min
VIH = VDD,VIL = GND,
fSCL = 400kHZ
VIH = VDD,VIL = GND,
fSCL = stop
IILK
Input leak current
-10
VIH
Input high voltage
0.8VDD
VIL
Input low voltage
VOH
Output high voltage
IOH = -1mA
VOL
Output low voltage
IOL = 5mA
IOL
Output current "Low"
Limits
Typ
Max
0.05
0.5
mA
0.1
1.0
µA
10
µA
Unit
V
0.2VDD
V
V
VDD-0.4
0.4
V
VOL = 0.4V
5
10
mA
VOL = 1.0V
15
25
mA
MITSUBISHI ELECTRIC
2/20,1998(rev) ( 3 / 9 )
MITSUBISHI < STD. LINEAR ICs >
M62320P,FP
2
8-BIT I/O EXPANDER for I C BUS
2
I C BUS CHARACTERISTICS
Limits
Symbol
Parameter
Unit
Min.
Max.
0
100
KHz
fSCL
SCL clock frequency
tBUF
Free time: the bus must be free before a new transmission can start
4.7
-
µs
tHD:STA
Hold time START Condition. After this period,the first clock pulse
is generated.
4.0
-
µs
tLOW
LOW period of the clock
4.7
-
µs
tHIGH
HIGh period of the clock
4.0
-
µs
tSU:STA
Set-up time for START condition (Only relevant for a repeated
START condition)
4.7
-
µs
tHD:DAT
Data Hold time
0
-
µs
tSU:DAT
Data Set-up time
250
-
ns
tR
Rise time of SDA and SCL signals
-
1000
ns
tF
Fall time of SDA and SCL signals
-
300
ns
tSU:STO
Set-up time for STOP condition
4.0
-
µs
• Note that a transmitter must internally provide at least a hold time to bridge the undefined region
(max.300 ns) of the falling edge of SCL.
TIMING CHART
tR, tF
tBUF
VIH
SDA
VIL
tHD:STA
SCL
tSU:DAT
tHD:DAT
tSU:STA
tSU:STO
VIH
VIL
tLOW
START
tHIGH
START
MITSUBISHI ELECTRIC
STOP
START
2/20,1998(rev) ( 4 / 9 )
MITSUBISHI < STD. LINEAR ICs >
M62320P,FP
2
8-BIT I/O EXPANDER for I C BUS
FUNCTIONAL BLOCKS
I 2 C BUS interface
The I 2 C BUS interface recognizes start/stop conditions, a slave address and a write/read mode selection
by receiving SDA,SCL,CS0,CS1 and CS2 signals and then the latch pulses, dedicated to each data latch
are generated.
Data Latch
This IC has 3 types of data latch : the I/O setting data latch, the input data latch and the output data latch
and each latch is controlled by the I2 C BUS interface.
• I/O setting data latch
These latches set input- or output-state of each parallel data terminals (D0 to D7). They are set at the next
byte after receiving the slave address byte in the write mode from the master. In case this latch is set to
high, the data is transferred from the I2 C BUS interface to the parallel data terminals. In the opposite
transmission : from the parallel data terminals to the I2 C BUS, it is set to low.
• Output data latch
In the write mode, the data from the I2 C BUS to the parallel data terminals is latched. When the master
transmits output data after a setting in write mode, the output data is taken into the latches.
• Input data latch
In the read mode, the data of parallel data terminals is latched in the input data latches. The input data is
taken into the latches from the parallel data terminals on every 8th negative edge of SCL clock . The
latched data is output to the master through the sift resistor. On the output terminal assigned by the I /
O setting latch, the input data latch takes the state of the output terminal.
Parallel input / output port
In case I/O setting latch is set to low (the input mode), each parallel terminal becomes hi-impedance and
is able to accept a input. In another case I/O setting latch is set to high (output mode), each parallel
terminal outputs a data according to the state of the output data latch.
Power on reset
When power is turned on, each latch is reset and then the parallel data I/O terminals become
hi-impedance (input mode).
MITSUBISHI ELECTRIC
2/20,1998(rev) ( 5 / 9 )
MITSUBISHI < STD. LINEAR ICs >
M62320P,FP
2
8-BIT I/O EXPANDER for I C BUS
DIGITAL DATA FORMAT
1. Write mode : I2 C BUS data input to Parallel data output
First
S
Last
SLAVE ADDRESS W
A
I/O SETTING
A
8BIT DATA A
8BIT
DATA
8BIT DATA A
A
P
2
2. Read mode :Parallel data input to I C BUS data output
First
S
Last
SLAVE ADDRESS W
A
8BIT DATA A
8BIT DATA A
8BIT
DATA
8BIT DATA A
A P
Transmission from Master (MCU etc.) to Slave (M62320)
Transmission from Slave (M62320) to Master (MCU etc.)
• S : Start Condition
While SCL level is high, SDA line level should be changed from high to low.
• Slave address
First
Last
MSB
LSB
0
1
1
1
A2
A1
• Chip select data
MSB
A2
A0
Lower three bits (A0,A1,A2) are a programmable address.
This IC is accessed only when the lower 3 bits data of slave
address coincide with the data of CS0 to CS2. (refer to the
right table)
LSB
A1
A0
CS2
CS1 CS0
0
0
0
0
0
1
0
1
0
L
L
L
L
L
H
L
H
L
1
1
1
H
H
H
(L=Low,H=High)
• W: Write (SDA = LOW), R : Read (SDA = HIGH)
• A: Acknowledge bit
• I/O setting data (I/O setting of parallel data I/O terminals.)
First
MSB
P7
Last
LSB
P6
P5
P4
P3
P2
P1
P0
• Each bit data corresponds to the I/O state of
the parallel data terminals.
DATA INPUT from parallel data terminals = Low
DATA OUTPUT to parallel data terminals = High
• 8bit data
First
MSB
D7
Last
LSB
D6
D5
D4
D3
D2
D1
D0
• P : Stop condition
While SCL level is high, SDA level should be changed from low to high.
MITSUBISHI ELECTRIC
2/20,1998(rev) ( 6 / 9 )
MITSUBISHI < STD. LINEAR ICs >
M62320P,FP
2
8-BIT I/O EXPANDER for I C BUS
FUNCTIONAL DESCRIPTION
All parallel data I/O terminals are set to the input-state after power-on. In case any terminals need to be set to
the output state, the corresponding terminals should be set during the write mode. This setting is hold until a
next setting.
2
In the write mode, 8 bits data can be transmitted from the I C BUS interface to the parallel ports continually after
the slave address and I/O setting.
In the read mode, 8 bits data can be transmitted from the parallel ports to the I2 C BUS interface continually after
the slave address setting.
In the case of a changing between the write- and read-mode, the data must be transmitted again from the
starting condition.
• In a case of a data conversion from serial to parallel.
Transmission from a master (MCU etc.)
Transmission from a slave (M62320)
starting
condition slave address
SDA
0
1
1
SCL
1
2
3
I/O setting byte
1 A2 A1 A0 0
4
5
6
7
A
8
DATA
P7 P6 P5 P4 P3 P2 P1 P0 A D17D16 D15 D14 D13D12 D11 D10 A D27D26 D25 D24 D23D22 D21 D20 A
1
2
3
4
5
6
7
8
Data output
D0
to
D7
stop condition
DATA
Hi-Z
Data output
D1X
D2X
• In a case of a data conversion from parallel to serial.
All I/O setting resistors are set to low (input) in the write mode, before a parallel data is read. (All I/O
setting resistors are set to the input mode after power-on.)
Transmission from a master (MCU etc.)
Transmission from a slave (M62320)
start
condition slave address
SDA
0
1
1
SCL
1
2
3
D0 to D7
output
I/O setting byte
1 A2 A1 A0 0
4
5
6
7
A
8
P7 P6 P5 P4 P3 P2 P1 P0 A
1
2
4
5
6
7
8
Hi-Z
start
condition slave address
SDA
0
1
1
SCL
1
2
3
D0 to D7
Input
(example)
stop condition
DATA
1 A2 A1 A0 1
4
5
6
7
8
DATA
DATA
A D17D16 D15 D14 D13D12 D11 D10 A D37 D36 D35 D34 D33 D32 D31 D30 A D47 D46 D45 D44 D43D42 D41 D40 A
1
2
D1X
3
4
5
D2X
data latch
D0 to D7
Output
3
6
7
8
D3 X
D4X
data latch
data latch
Hi-Z
MITSUBISHI ELECTRIC
2/20,1998(rev) ( 7 / 9 )
MITSUBISHI < STD. LINEAR ICs >
M62320P,FP
2
8-BIT I/O EXPANDER for I C BUS
• In case the I/O setting is different between each terminals.
An example : the parallel port terminals of D0 to D3 and D4 to D7 are assigned as output and input terminals,
respectively.
start condition
slave address
SDA
0
1
1
SCL
1
2
3
I / O setting
1 A2 A1 A0 0
4
5
6
7
8
A
DATA
stop condition
DATA
P7 P6 P5 P4 P3 P2 P1 P0 A D17 D16 D15 D14 D13D12 D11 D10 A D27 D26 D25 D24 D23D22 D21 D20 A
1
2
3
4
5
6
7
8
Data output
D0 to D3
Hi-Z
D4 to D7
Hi-Z
start condition
slave address
SDA
0
1
1
SCL
1
2
3
DATA
1 A2 A1 A0 1
4
5
6
7
8
DATA
Data output
D1X
D2X
DATA
stop condition
A D17 D16 D15 D14 D13D12 D11 D10 A D37 D36 D35 D34 D33D32 D31 D30 A D47D46 D45 D44 D43D42 D41 D40 A
1
2
3
4
5
6
7
8
D0 to D3
D4 to D7
(instance)
D1X
data latch
D4 to D7
output
D2X
D3X
data latch
D4X
data latch
Hi-Z
• Write mode
The terminal assigned as an output provides the data written in the output data latch.
After power-on, all terminals are reset to the input-state. Then an initial data low of the output latch are
output after the I/O setting has been done. Finally the assigned output are provided after the 8-bit data
transmission.
The terminal assigned as an input keeps the input condition (high-impedance) regardless of 8-bit data
setting.
• Read mode
The input data is taken into the input latch on every 8th negative-going edge of the SCL clock through the
terminal assigned as an input, and then the latched data is output via the SDA line.
The data of the output assigned terminal is also handled in the same procedures as above.
MITSUBISHI ELECTRIC
2/20,1998(rev) ( 8 / 9 )
MITSUBISHI < STD. LINEAR ICs >
M62320P,FP
2
8-BIT I/O EXPANDER for I C BUS
TYPICAL APPLICATION
10µF
13
VDD
D0 4
14 CS2
Chip select data
D1 5
15 CS1
D2 6
D3 7
16 CS0
Parallel input /
output terminal
D4 9
D5 10
D6 11
2 SCL
D7 12
MCU
3 SDA
Serial data output
SO 1
GND
10
PRECAUTION FOR USE
2
•
Purchase of MITSUBISHI ELECTRIC CORPORATION'S I C components conveys a
license under the Philips I2C Patent Rights to use these components an I2C system,
provided that the system conforms to I2 C Standard Specification as defined by Philips.
•
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor
products better and more reliable, but there is always the possibility that trouble may occur
with them. Trouble with semiconductors may lead to personal injury,fire or property
damage. Remember to give due consideration to safety when making your circuit design,
in order to prevent fires from spreading, redundancy, malfunction or other mishap.
MITSUBISHI ELECTRIC
2/20,1998(rev) ( 9 / 9 )
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