Sony ILX508A 7926-pixel ccd linear image sensor (b/w) Datasheet

ILX508A
7926-pixel CCD Linear Image Sensor (B/W)
For the availability of this product, please contact the sales office.
Description
The ILX508A is a reduction type CCD linear sensor
developed for high resolution copiers. This sensor
reads A3-size documents at a density of 600 DPI (Dot
Per Inch). A built-in timing generator and clock-drivers
ensure direct drive at 5V logic for easy use. In
addition reset pulse can switch between internal
generation and external input.
24 pin DIP (Ceramic)
Features
• Number of effective pixels: 7926 pixels
• Pixel size: 7µm × 7µm (7µm pitch)
• Built-in timing generator and clock-drivers
• Ultra high sensitivity
• Ultra low lag/low dark voltage
• Output method
• Maximum operating frequency: 12.5MHz
Absolute Maximum Ratings
• Supply voltage
VDD1
VDD2
• Operation temperature
• Storage temperature
Pin Configuration (Top View)
11
6
–10 to +60
–30 to +80
V
V
°C
°C
1
24 φCLK
VGG
1
GND
2
23 VDD1
VDD1
3
22 RS/SH
VOUT
4
21 VDD1
GND
5
20 VDD1
φROG
6
19 GND
VDD2
7
18 VDD2
VDD2
8
17 GND
RSSW
9
16 T4
T1 10
15 T3
GND 11
7926
14 T2
13 NC
NC 12
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E96X33-PS
4
1
VOUT
VGG
–2–
3
VDD1
2
GND
5
GND
VDD2
7
AAA
AAA
• Output amplifier
• Sample-and-hold circuit
• Feed through suppression
circuit
D17
D18
18
19
8
VDD2
T4
16
GND
17
Clock-drivers
S7926
D99
9
RSSW
24
φCLK
RS/SH
22
Mode selector
CCD analog shift register
Read out gate
Read out gate
CCD analog shift register
Clock-drivers
VDD2
GND
Clock-pulse generator
Sample-and-hold pulse generator
20
VDD1
S1
21
D98
VDD1
S2
23
S7925
VDD1
14
T1
10
T2
T3
15
D116
13
NC
GND
11
φROG
6
Read out gate
pulse generator
D115
Block Diagram
12
NC
ILX508A
ILX508A
Pin Description
Pin No.
Symbol
Description
1
VGG
Output circuit gate bias
2
GND
GND
3
VDD1
9V power supply
4
VOUT
Signal output
5
GND
GND
6
φROG
Clock pulse
7
VDD2
5V power supply
8
VDD2
5V power supply
9
RSSW∗
RS pulse external, internal selection
(External RS → VDD1, Internal RS → GND)
10
T1
Test pin (5V)
11
GND
GND
12
NC
NC
13
NC
NC
14
T2
Test pin (GND)
15
T3
Test pin (5V)
16
T4
Test pin (GND)
17
GND
GND
18
VDD2
5V power supply
19
GND
GND
20
VDD1
9V power supply
21
VDD1
9V power supply
22
RS/SH∗
Clock pulse or S/H switch
23
VDD1
9V power supply
24
φCLK
Clock pulse
∗ Output mode is changeable as follows.
22pin
GND
VDD1
φRS
GND
Internal RS
without S/H
Internal RS
with S/H
—
VDD1
—
—
External RS
without S/H
9pin
–3–
ILX508A
Recommended Voltage
Item
Min.
Typ.
Max.
Unit
VDD1
8.5
9.0
9.5
V
VDD2
4.75
5.0
5.25
V
Note) Rules for raising and lowering power supply voltage.
To raise power supply voltage, first raise VDD1 (9V) and then VDD2 (5V).
To lower voltage, first lower VDD2 (5V) and then VDD1 (9V).
Clock Characteristics
Item
Symbol
Min.
Typ.
Max.
Unit
Input capacity of φCLK
CφCLK
—
10
—
pF
Input capacity of φROG
CφROG
—
10
—
pF
Input capacity of RS/SH
C RS/SH
—
10
—
pF
φCLK frequency
fφCLK
—
1
12.5
MHz
φRS frequency
fφRS
—
1
12.5
MHz
–4–
ILX508A
Electrooptical Characteristics∗1
(Ta = 25°C, VDD1 = 9V, VDD2 = 5V, Light source = 3200K, φCLK = 1MHz, Internal φRS mode without S/H,
IR cut filter, CM-500S (t = 1.0mm))
Item
Symbol
Min.
Typ.
Max.
Unit
Remarks
Sensitivity1
R1
7.5
10.8
13.9
V/(lx · s)
∗2
Sensitivity2
R2
—
24.6
—
V/(lx · s)
∗3
Sensitivity nonuniformity
PRNU
—
5
12.5
%
∗4
Saturation output voltage
VSAT
1.0
1.5
—
V
∗5
Saturation exposure
SE
0.072
0.139
—
lx · s
∗6
Even and odd black level
DC difference
∆V
—
1.0
10.0
mV
∗7
Dark voltage average
VDRK
—
0.3
2
mV
∗8
Dark signal nonuniformity
DSNU
—
0.6
5
mV
∗9
Image lag
IL
—
0.02
—
%
∗10
9V supply current
IVDD1
—
16
32
mA
—
5V supply current
IVDD2
—
5
16
mA
—
Total transfer efficiency
TTE
90
97
—
%
—
Output impedance
ZO
—
600
—
Ω
Offset level
VOS
—
3.0
—
V
—
∗11
Dynamic range
DR
500
5000
—
—
∗12
∗1 In accorcance with the given electrooptical characteristics, the even black level is defined as the mean
value of D8, D10, D12, D14, and D16.
∗2 For the sensitivity test light is applied with a uniform intensity of illumination.
∗3 W lamp (2854K).
∗4 PRNU is defined as indicated below. Ray incidence conditions are the same as for ∗2.
PRNU =
∗5
∗6
(VMAX – VMIN)/2
× 100 [%]
VAVE
Where the 7926 pixels are divided into blocks of 102, even and odd pixels, respectively (Even and odd last
blocks are 87.) The maximum output of each block is set to VMAX, the minimum output to VMIN and the
average output to VAVE.
Use below the minimum value of the saturation output voltage.
Saturation exposure is defined as follows.
SE =
VSAT
R1
∗7 Indicates the DC difference in value between odd black level and even black level.
∗8 optical signal accumulated time τ int stands at 10ms.
∗9 The difference between the maximum and mean values of the dark output voltage is calculated for even
and odd respectively. The larger value is defined as the dark signal nonuniformity.
Optical signal accumulated time τ int stands at 10ms.
∗10 VOUT = 500mV (Typ.)
–5–
ILX508A
∗11 VOS is defined as indicated below.
Vout
VOS
GND
∗12 Dynamic range is defined as follows.
DR =
VSAT
VDRK
When the optical signal accumulated time is shorter, the dynamic range gets wider because the optical
signal accumulated time is in proportion to the dark voltage.
–6–
0.01µ
5V
–7–
10µ/16V
1kΩ
10µ/16V
φCLK
VGG (A)
Output signal
0.01µ
VDD1 (D)
GND (A)
16
15
14
10
11
12
0.01µ
10µ/10V
∗ When noise influence into output signal is large, connect pins indicated by (A) to the analog power supply and
pins indicated by (D) to the digital power supply, and also use a decoupling capacitor of large capacitance.
9
13
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
2SA1175
φROG
8
7
RS/SH (D)
VDD1 (A)
4
VDD1 (A)
VOUT (A)
3
6
17
5
18
VDD1 (A)
GND (A)
2
19
GND (D)
φROG
1
20
T4 (D)
PSSW (D)
21
VDD2 (D)
VDD2 (D)
23
T3 (D)
T1 (D)
22
GND (D)
VDD2 (D)
24
φRS
T2 (D)
GND (A)
9V
φCLK
NC
NC
Application Circuit (External φRS)
ILX508A
–8–
VOUT
φRS
φCLK
0
5
0
5
0
1
D1
φROG
2
3
4
Optical black
(80 pixels)
D16
D17
D18
D19
D20
AA
AA
A
A
A
AA
AA
A
A
A
A
AAAAAA AAAAA
AAAA
Effective picture
elements signal
(7926 pixels)
D96
D97
D98
S1
S2
S3
S4
1 line output period (8042 pixels)
Dummy signal (98 pixels)
D2
D3
D4
D5
D6
5
8042
Dummy signal
(18 pixels)
D7923
D7924
D7925
D7926
D99
D100
D106
D107
D108
D109
D116
Clock Timing Diagram (External φRS)
ILX508A
2
1
ILX508A
Clock pulse Waveform Conditions
φCLK, φROG pulse related
t8
t9
t2
φROG
t1
φCLK
t3
Internal φRS mode
t8
t9
t4
φCLK
Vout
t5
AAAA
AAAA
AA
AA
t10
t10
t11
External φRS mode
φCLK
t4
t5
t9
φRS
t7
t8
t6
AAAAA
AAAAA
t12
–9–
t13
AA
AA
t10
ILX508A
Symbol
Item
Min.
Typ.
Max.
Unit
φROG, φCLK pulse timing
t1
200
300
—
ns
φROG, φCLK pulse timing
t3
1200
1500
—
ns
φROG pulse high level period
t2
1200
—
ns
φCLK pulse high level period
t4
40
1500
500∗1
—
ns
φCLK pulse low level period
t5
40
—
ns
φRS pulse low level period
t6
25
500∗1
100∗1
—
ns
φCLK, φRS pulse timing
t7
60
550∗1
10 + t4 + t5
ns
Input clock pulse rise/fall time
t8, t9
—
5
10
ns
High level
VφCLK, VφROG
4.5
5.0
5.5
V
Low level
VφRS
0
—
0.5
V
t10
—
95
—
ns
t11
—
70
—
ns
t12
—
45
—
ns
t13
—
60
—
ns
Input clock pulse voltage
Internal φRS
Signal output delay time
External φRS
∗1 The frequency of φCLK is 1MHz.
– 10 –
ILX508A
Example of Representative Characteristics (VDD1 = 9V, VDD2 = 5V, Ta = 25°C)
Spectral sensitivity characteristics (Standard characteristics)
1.0
Relative sensitivity
0.8
0.6
0.4
0.2
0
400
500
600
700
800
900
1000
Wavelength [nm]
MTF of main scanning direction (Standard characteristics)
Spatial frequency [cycle/mm]
0
14.3
28.6
42.9
57.1
71.4
0
0.2
0.4
0.6
0.8
1.0
1.0
0.8
MTF
0.6
0.4
0.2
0
Normalized spatial frequency
Integration time output voltage characteristics
(Typical characteristics)
Dark signal output temperature characteristics
(Typical characteristics)
10
Output voltage rate
Output voltage rate
5
1
0.5
0.1
1
0.5
0.1
0
10
20
30
40
50
60
1
5
τ int – integration time [ms]
Ta – Ambient temperature [°C]
– 11 –
10
ILX508A
Operational frequency characteristics of the VDD1
supply current (Typical characteristics)
Operational frequency characteristics of the VDD2
supply current (Typical characteristics)
IVDD2 – VDD2 supply current [mA]
IVDD1 – VDD1 supply current [mA]
60
15
10
5
0
50
40
30
20
10
0
0
2
4
6
8
10
12.5
0
2
4
6
8
fφCLK – φCLK clock frequency [MHz]
Offset level vs. VDD1 characteristics
(Typical characteristics)
Offset level vs. VDD2 characteristics
(Typical characteristics)
6
12.5
6
Ta = 25°C
Ta = 25°C
5
VOS – Offset level [V]
5
4
3
2
∆VOS
∆VDD1
1
~
– 0.35
4
3
2
∆VOS
∆VDD2
1
0
~
– –0.14
0
8.5
9
9.5
4.75
VDD1 [V]
5
VDD2 [V]
Offset level vs. Temperature characteristics
(Typical characteristics)
6
5
VOS – Offset level [V]
VOS – Offset level [V]
10
fφCLK – φCLK clock frequency [MHz]
∆VOS
∆Ta
4
3
2
~
– – 0.8mV/°C
1
0
0
10
20
30
40
50
Ta – Ambient temperature [°C]
– 12 –
60
5.25
ILX508A
Notes on Handling
1) Static charge prevention
CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following
protective measures.
a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use conductive shoes.
b) When handling directly use an earth band.
c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.
d) Ionized air is recommended for discharge when handling CCD image sensor.
e) For the shipment of mounted substrates use boxes treated for the prevention of static charges.
2) Regulation for raising and lowering the power supply voltage.
When raising the supply voltage, first raise VDD1 (9V) and then VDD2 (5V).
Similarly, lower VDD2 (5V) first and then VDD1 (9V).
3) Soldering
a) Make sure the package temperature does not exceed 80°C.
b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30W
soldering iron and solder each pin in less then 2 seconds. For repairs and remount, cool sufficienty.
c) To dismount an imaging device do not use a solder suction equipment.
When using an electric desoldering tool, ground the controller. For the control system, use a zero cross
type.
4) Dust and dirt protection
a) Operate in clean environments.
b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should
dirt stick to a glass surface blow it off with an air blow. (For dirt stuck through static electricity ionized air
is recommended.)
c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained.
Be careful not to scratch the glass.
d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when
moving to a room with great temperature differences.
5) Exposure to high temperatures or humity will affect the characteristics.
Accordingly avoid storage or usage in such conditions.
6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks.
– 13 –
5.0 ± 0.5
– 14 –
H
1st. pin Index
V
9.21 ± 0.8
PACKAGE WEIGHT
5.8g
42ALLOY
GOLD PLATING
LEAD TREATMENT
LEAD MATERIAL
Ceramic
PACKAGE MATERIAL
1
68.0 ± 0.15
2.54 ± 0.25
No.1 Pixel
24
12
13
55.482 (7µm × 7926Pixels)
71.0 ± 0.9
0.46 ± 0.15
1.27
24Pin DIP (400mil)
9.0 ± 0.15
0 ° to 9 °
+0.1
0.25 -0.0
5
(AT STAND OFF)
10.16 ± 0.3
3.1 ± 0.5
2. The thickness of the cover glass is 0.8mm, and the refractive index is 1.5.
1. The height from the bottom to the sensor surface is 1.42 ± 0.3mm.
0.3 M
0.8 ± 0.1
Unit: mm
PACKAGE STRUCTURE
4.0 ± 0.5
10.0 ± 0.5
2.29
0.97 ± 0.3
Package Outline
ILX508A
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