LMC7101, LMC7101Q www.ti.com SNOS719F – SEPTEMBER 1999 – REVISED MARCH 2013 LMC7101/LMC7101Q Tiny Low Power Operational Amplifier with Rail-to-Rail Input and Output Check for Samples: LMC7101, LMC7101Q FEATURES 1 • 2 • • • • • Tiny 5-Pin SOT-23 Package Saves Space—Typical Circuit Layouts Take Half the Space of 8-Pin SOIC Designs Guaranteed Specs at 2.7V, 3V, 5V, 15V Supplies Typical Supply Current 0.5 mA at 5V Typical Total Harmonic Distortion of 0.01% at 5V 1.0 MHz Gain-Bandwidth Similar to Popular LMC6482/LMC6484 • • Rail-to-Rail Input and Output Temperature Range –40°C to 125°C (LMC7101Q) APPLICATIONS • • • • • Mobile Communications Notebooks and PDAs Battery Powered Products Sensor Interface Automotive Applications (LMC7101Q) DESCRIPTION The LMC7101 is a high performance CMOS operational amplifier available in the space saving 5-Pin SOT-23 Tiny package. This makes the LMC7101 ideal for space and weight critical designs. The performance is similar to a single amplifier of the LMC6482/LMC6484 type, with rail-to-rail input and output, high open loop gain, low distortion, and low supply currents. The main benefits of the Tiny package are most apparent in small portable electronic devices, such as mobile phones, pagers, notebook computers, personal digital assistants, and PCMCIA cards. The tiny amplifiers can be placed on a board where they are needed, simplifying board layout. Connection Diagram Figure 1. 5-Pin SOT-23 Top View These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1999–2013, Texas Instruments Incorporated LMC7101, LMC7101Q SNOS719F – SEPTEMBER 1999 – REVISED MARCH 2013 www.ti.com Absolute Maximum Ratings (1) (2) ESD Tolerance (3) Human Body Model 1000V Machine Model 200V Charged Device Model 1000V Difference Input Voltage ±Supply Voltage (V+) + 0.3V, (V−) − 0.3V Voltage at Input/Output Pin Supply Voltage (V+ − V−) 16V Current at Input Pin Current at Output Pin ±5 mA (4) ±35 mA Current at Power Supply Pin 35 mA Lead Temp. (Soldering, 10 sec.) 260°C −65°C to +150°C Storage Temperature Range Junction Temperature (1) (5) 150°C Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics. If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications. Human Body Model is 1.5 kΩ in series with 100 pF. Applies to both single-supply and split-supply operation. Continuous short operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature at 150°C. The maximum power dissipation is a function of TJ(MAX), θJA and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) − TA)/θJA. All numbers apply for packages soldered directly into a PC board. (2) (3) (4) (5) Recommended Operating Conditions (1) 2.7V ≤ V+ ≤ 15.5V Supply Voltage Temperature Range −40°C to 85°C LMC7101AI, LMC7101BI −40°C to 125°C LMC7101Q Thermal Resistance (θJA) 5-Pin SOT-23 (1) 325°C/W Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics. 2.7V Electrical Characteristics Unless otherwise specified, all limits guaranteed for TJ = 25°C, V+ = 2.7V, V− = 0V, VCM = VO = V+/2 and RL > 1 MΩ. Boldface limits apply at the temperature extremes. Symbol Parameter Conditions V+ = 2.7V Typ (1) LMC7101AI Limit LMC7101BI Limit LMC7101Q Limit 0.11 6 9 9 (2) (2) (2) (3) Units mV max VOS Input Offset Voltage Average Drift TCVOS Input Offset Voltage IB Input Bias Current 1.0 64 64 1000 pA max IOS Input Offset Current 0.5 32 32 2000 pA max RIN Input Resistance >1 CMRR Common-Mode Rejection Ratio 0V ≤ VCM ≤ 2.7V V+ = 2.7V VCM Input Common Mode Voltage Range For CMRR ≥ 50 dB (1) (2) (3) 2 μV/°C 1 Tera Ω 70 55 50 50 dB min 0.0 0.0 0.0 0.0 V min 3.0 2.7 2.7 2.7 V max Typical Values represent the most likely parametric norm. All limits are guaranteed by testing or statistical analysis. When operated at temperature between −40°C and 85°C, the LMC7101Q will meet LMC7101BI specifications. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LMC7101 LMC7101Q LMC7101, LMC7101Q www.ti.com SNOS719F – SEPTEMBER 1999 – REVISED MARCH 2013 2.7V Electrical Characteristics (continued) Unless otherwise specified, all limits guaranteed for TJ = 25°C, V+ = 2.7V, V− = 0V, VCM = VO = V+/2 and RL > 1 MΩ. Boldface limits apply at the temperature extremes. Symbol Parameter PSRR Power Supply Rejection Ratio CIN Common-Mode Input Capacitance Conditions V+ = 1.35V to 1.65V V− = −1.35V to −1.65V VCM = 0 LMC7101AI Limit LMC7101BI Limit LMC7101Q Limit Units 60 50 45 45 dB min 2.15 2.15 2.15 V min (2) (2) (2) (3) 3 RL = 2 kΩ VO Typ (1) Output Swing RL = 10 kΩ 2.45 pF 0.25 0.5 0.5 0.5 V max 2.68 2.64 2.64 2.64 V min 0.025 0.06 0.06 0.06 V max 0.5 0.81 0.95 0.81 0.95 0.81 0.95 mA max IS Supply Current SR Slew Rate (4) 0.7 V/μs GBW Gain-Bandwidth Product 0.6 MHz (4) V+ = 15V. Connected as a voltage follower with a 10V step input. Number specified is the slower of the positive and negative slew rates. RL = 100 kΩ connected to 7.5V. Amp excited with 1 kHz to produce VO = 10 VPP. 3V DC Electrical Characteristics Unless otherwise specified, all limits guaranteed for TJ = 25°C, V+ = 3V, V− = 0V, VCM = 1.5V, VO = V+/2 and RL = 1 MΩ. Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Typ (1) 0.11 LMC7101AI Limit LMC7101BI Limit LMC7101Q Limit 4 6 7 9 7 mV max (2) (2) (2) (3) Units VOS Input Offset Voltage TCVOS Input Offset Voltage Average Drift IB Input Current 1.0 64 64 1000 pA max IOS Input Offset Current 0.5 32 32 2000 pA max RIN Input Resistance >1 CMRR Common-Mode Rejection Ratio 0V ≤ VCM ≤ 3V V+ = 3V VCM Input Common-Mode Voltage Range For CMRR ≥ 50 dB PSRR Power Supply Rejection Ratio V+ = 1.5V to 7.5V V− = −1.5V to −7.5V VO = VCM = 0 CIN Common-Mode Input Capacitance Output Swing RL = 600Ω IS (1) (2) (3) Tera Ω 74 64 60 60 0.0 0.0 0.0 0.0 V min 3.3 3.0 3.0 3.0 V max 80 68 60 60 dBmin 3 RL = 2 kΩ VO μV/°C 1 Supply Current db min pF 2.8 2.6 2.6 2.6 V min 0.2 0.4 0.4 0.4 V max 2.7 2.5 2.5 2.5 V min 0.37 0.6 0.6 0.6 V max 0.5 0.81 0.95 0.81 0.95 0.81 0.95 mA max Typical Values represent the most likely parametric norm. All limits are guaranteed by testing or statistical analysis. When operated at temperature between −40°C and 85°C, the LMC7101Q will meet LMC7101BI specifications. Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LMC7101 LMC7101Q Submit Documentation Feedback 3 LMC7101, LMC7101Q SNOS719F – SEPTEMBER 1999 – REVISED MARCH 2013 www.ti.com 5V DC Electrical Characteristics Unless otherwise specified, all limits guaranteed for TJ = 25°C, V+ = 5V, V− = 0V, VCM = 1.5V, VO = V+/2 and RL = 1 MΩ. Boldface limits apply at the temperature extremes. Symbol Parameter Typ Conditions (1) LMC7101AI Limit LMC7101BI Limit LMC7101Q Limit 3 5 7 9 7 9 (2) 0.11 V+ = 5V (2) (2) (3) Units mV max VOS Input Offset Voltage TCVOS Input Offset Voltage Average Drift IB Input Current 1 64 64 1000 pA max IOS Input Offset Current 0.5 32 32 2000 pA max RIN Input Resistance >1 65 60 60 55 60 55 db min Common-Mode Rejection Ratio 0V ≤ VCM ≤ 5V LMC7101Q @ 125°C 0.2V ≤ VCM ≤ 4.8V 82 CMRR +PSRR Positive Power Supply Rejection Ratio V+ = 5V to 15V V− = 0V, VO = 1.5V 82 70 65 65 62 65 62 dB min −PSRR Negative Power Supply Rejection Ratio V− = −5V to −15V V+ = 0V, VO = −1.5V 82 70 65 65 62 65 62 dB min −0.3 VCM −0.20 0.00 −0.20 0.00 −0.2 0.2 V min Input Common-Mode Voltage Range 5.3 5.20 5.00 5.20 5.00 5.2 4.8 V max CIN Common-Mode Input Capacitance 4.9 4.7 4.6 4.7 4.6 4.7 4.54 V min 0.1 0.18 0.24 0.18 0.24 0.18 0.28 V max 4.7 4.5 4.24 4.5 4.24 4.5 4.28 V min 0.3 0.5 0.65 0.5 0.65 0.5 0.8 V max For CMRR ≥ 50 dB Output Swing RL = 600Ω ISC pF VO = 0V 24 Sourcing 24 16 11 16 11 16 9 mA min VO = 5V Sinking 19 11 7.5 11 7.5 11 5.8 mA min 0.5 0.85 1.0 0.85 1.0 0.85 1.0 mA max Output Short Circuit Current IS (1) (2) (3) Tera Ω 3 RL = 2 kΩ VO μV/°C 1.0 Supply Current Typical Values represent the most likely parametric norm. All limits are guaranteed by testing or statistical analysis. When operated at temperature between −40°C and 85°C, the LMC7101Q will meet LMC7101BI specifications. 5V AC Electrical Characteristics Unless otherwise specified, all limits guaranteed for TJ = 25°C, V+ = 5V, V− = 0V, VCM = 1.5V, VO = V+/2 and RL = 1 MΩ. Boldface limits apply at the temperature extremes. Symbol Parameter Conditions f = 10 kHz, AV = −2 RL = 10 kΩ, VO = 4.0 VPP LMC7101AI Limit Typ (1) (2) (2) Units THD Total Harmonic Distortion SR Slew Rate 1.0 V/μs GBW Gain Bandwidth Product 1.0 MHz (1) (2) 4 0.01 LMC7101BI Limit % Typical Values represent the most likely parametric norm. All limits are guaranteed by testing or statistical analysis. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LMC7101 LMC7101Q LMC7101, LMC7101Q www.ti.com SNOS719F – SEPTEMBER 1999 – REVISED MARCH 2013 15V DC Electrical Characteristics Unless otherwise specified, all limits guaranteed for TJ = 25°C, V+ = 15V, V− = 0V, VCM = 1.5V, VO = V+/2 and RL = 1 MΩ. Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Typ (1) LMC7101AI Limit (2) LMC7101BI Limit (2) LMC7101Q Limit (2) (3) Units VOS Input Offset Voltage 0.11 mV max TCVOS Input Offset Voltage Average Drift 1.0 μV/°C IB Input Current 1.0 64 64 1000 pA max IOS Input Offset Current 0.5 32 32 2000 pA max RIN Input Resistance >1 70 65 65 60 65 60 dB min Common-Mode Rejection Ratio 0V ≤ VCM ≤ 15V LMC7101Q @°125C 0.2V ≤ VCM ≤ 14.8V 82 CMRR +PSRR Positive Power Supply Rejection Ratio V+ = 5V to 15V V− = 0V, VO = 1.5V 82 70 65 65 62 65 62 dB min −PSRR Negative Power Supply Rejection Ratio V− = −5V to −15V V+ = 0V, VO = −1.5V 82 70 65 65 62 65 62 dB min −0.20 0.00 −0.20 0.00 −0.2 0.2 V min VCM V+ = 5V For CMRR ≥ 50 dB −0.3 Input Common-Mode Voltage Range 15.3 15.20 15.00 15.20 15.00 15.2 14.8 V max 340 80 40 80 40 80 30 24 15 10 15 10 15 4 Sourcing 300 34 34 34 Sinking 15 6 6 6 Sourcing RL = 2 kΩ AV Large Signal Voltage Gain Sinking (4) RL = 600Ω CIN Input Capacitance V = 15V RL = 2 kΩ ISC IS (1) (2) (3) (4) (5) Output Swing Output Short Circuit Current V/mV V/mV 3 + VO Tera Ω V+ = 15V RL = 600Ω VO = 0V Sourcing VO = 12V Sinking (5) Supply Current pF 14.7 14.4 14.2 14.4 14.2 14.4 14.2 V min 0.16 0.32 0.45 0.32 0.45 0.32 0.45 V max 14.1 13.4 13.0 13.4 13.0 13.4 12.85 V min 0.5 1.0 1.3 1.0 1.3 1.0 1.5 V max 50 30 20 30 20 30 20 50 30 20 30 20 30 20 0.8 1.50 1.71 1.50 1.71 1.50 1.75 mA min mA max Typical Values represent the most likely parametric norm. All limits are guaranteed by testing or statistical analysis. When operated at temperature between −40°C and 85°C, the LMC7101Q will meet LMC7101BI specifications. V+ = 15V, VCM = 1.5V and RL connect to 7.5V. For sourcing tests, 7.5V ≤ VO ≤ 12.5V. For sinking tests, 2.5V ≤ VO ≤ 7.5V. Do not short circuit output to V+ when V+ is greater than 12V or reliability will be adversely affected. Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LMC7101 LMC7101Q Submit Documentation Feedback 5 LMC7101, LMC7101Q SNOS719F – SEPTEMBER 1999 – REVISED MARCH 2013 www.ti.com 15V AC Electrical Characteristics Unless otherwise specified, all limits guaranteed for TJ = 25°C, V+ = 15V, V− = 0V, VCM = 1.5V, VO = V+/2 and RL = 1 MΩ. Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Typ (1) LMC7101AI Limit LMC7101BI Limit LMC7101Q Limit Units 0.5 0.4 0.5 0.4 0.5 0.4 V/μs min (2) (2) (2) (3) Slew Rate (4) V+ = 15V 1.1 GBW Gain-Bandwidth Product V+ = 15V 1.1 MHz φm Phase Margin 45 deg Gm Gain Margin 10 dB en Input-Referred Voltage Noise f = 1 kHz, VCM = 1V 37 In Input-Referred Current Noise f = 1 kHz 1.5 THD Total Harmonic Distortion f = 10 kHz, AV = −2 RL = 10 kΩ, VO = 8.5 VPP 0.01 SR (1) (2) (3) (4) 6 % Typical Values represent the most likely parametric norm. All limits are guaranteed by testing or statistical analysis. When operated at temperature between −40°C and 85°C, the LMC7101Q will meet LMC7101BI specifications. V+ = 15V. Connected as a voltage follower with a 10V step input. Number specified is the slower of the positive and negative slew rates. RL = 100 kΩ connected to 7.5V. Amp excited with 1 kHz to produce VO = 10 VPP. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LMC7101 LMC7101Q LMC7101, LMC7101Q www.ti.com SNOS719F – SEPTEMBER 1999 – REVISED MARCH 2013 2.7V Typical Performance Characteristics V = 2.7V, V− = 0V, TA = 25°C, unless otherwise specified. + Open Loop Frequency Response Input Voltage vs. Output Voltage Figure 2. Figure 3. Gain and Phase vs. Capacitance Load Gain and Phase vs. Capacitance Load Figure 4. Figure 5. dVOS vs. Supply Voltage dVOS vs. Common Mode Voltage Figure 6. Figure 7. Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LMC7101 LMC7101Q Submit Documentation Feedback 7 LMC7101, LMC7101Q SNOS719F – SEPTEMBER 1999 – REVISED MARCH 2013 www.ti.com 2.7V Typical Performance Characteristics (continued) + − V = 2.7V, V = 0V, TA = 25°C, unless otherwise specified. 8 Sinking Current vs. Output Voltage Sourcing Current vs. Output Voltage Figure 8. Figure 9. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LMC7101 LMC7101Q LMC7101, LMC7101Q www.ti.com SNOS719F – SEPTEMBER 1999 – REVISED MARCH 2013 3V Typical Performance Characteristics V = 3V, V− = 0V, TA = 25°C, unless otherwise specified. + Open Loop Frequency Response Input Voltage vs. Output Voltage Figure 10. Figure 11. Input Voltage Noise vs. Input Voltage Sourcing Current vs. Output Voltage Figure 12. Figure 13. Sinking Current vs. Output Voltage CMRR vs. Input Voltage Figure 14. Figure 15. Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LMC7101 LMC7101Q Submit Documentation Feedback 9 LMC7101, LMC7101Q SNOS719F – SEPTEMBER 1999 – REVISED MARCH 2013 www.ti.com 5V Typical Performance Characteristics V = 5V, V− = 0V, TA = 25°C, unless otherwise specified. + 10 Open Loop Frequency Response Input Voltage vs. Output Voltage Figure 16. Figure 17. Input Voltage Noise vs. Input Voltage Sourcing Current vs, Output Voltage Figure 18. Figure 19. Sinking Current vs. Output Voltage CMRR vs. Input Voltage Figure 20. Figure 21. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LMC7101 LMC7101Q LMC7101, LMC7101Q www.ti.com SNOS719F – SEPTEMBER 1999 – REVISED MARCH 2013 15V Typical Performance Characteristics V = +15V, V− = 0V, TA = 25°C, unless otherwise specified. + Open Loop Frequency Response Input Voltage vs. Output Voltage Figure 22. Figure 23. Input Voltage Noise vs. Input Voltage Sourcing Current vs. Output Voltage Figure 24. Figure 25. Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LMC7101 LMC7101Q Submit Documentation Feedback 11 LMC7101, LMC7101Q SNOS719F – SEPTEMBER 1999 – REVISED MARCH 2013 www.ti.com 15V Typical Performance Characteristics (continued) + − V = +15V, V = 0V, TA = 25°C, unless otherwise specified. 12 Sinking Current vs. Output Voltage CMRR vs. Input Voltage Figure 26. Figure 27. Supply Current vs. Supply Voltage Input Current vs. Temperature Figure 28. Figure 29. Output Voltage Swing vs. Supply Voltage Input Voltage Noise vs. Frequency Figure 30. Figure 31. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LMC7101 LMC7101Q LMC7101, LMC7101Q www.ti.com SNOS719F – SEPTEMBER 1999 – REVISED MARCH 2013 15V Typical Performance Characteristics (continued) + − V = +15V, V = 0V, TA = 25°C, unless otherwise specified. Positive PSRR vs. Frequency Negative PSRR vs. Frequency Figure 32. Figure 33. CMRR vs. Frequency Open Loop Frequency Response @ −40°C Figure 34. Figure 35. Open Loop Frequency Response @ 25°C Open Loop Frequency Response @ 85°C Figure 36. Figure 37. Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LMC7101 LMC7101Q Submit Documentation Feedback 13 LMC7101, LMC7101Q SNOS719F – SEPTEMBER 1999 – REVISED MARCH 2013 www.ti.com 15V Typical Performance Characteristics (continued) + − V = +15V, V = 0V, TA = 25°C, unless otherwise specified. 14 Maximum Output Swing vs. Frequency Gain and Phase vs. Capacitive Load Figure 38. Figure 39. Gain and Phase vs. Capacitive Load Output Impedance vs. Frequency Figure 40. Figure 41. Slew Rate vs. Temperature Slew Rate vs. Supply Voltage Figure 42. Figure 43. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LMC7101 LMC7101Q LMC7101, LMC7101Q www.ti.com SNOS719F – SEPTEMBER 1999 – REVISED MARCH 2013 15V Typical Performance Characteristics (continued) + − V = +15V, V = 0V, TA = 25°C, unless otherwise specified. Inverting Small Signal Pulse Response Inverting Small Signal Pulse Response Figure 44. Figure 45. Inverting Small Signal Pulse Response Inverting Large Signal Pulse Response Figure 46. Figure 47. Inverting Large Signal Pulse Response Inverting Large Signal Pulse Response Figure 48. Figure 49. Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LMC7101 LMC7101Q Submit Documentation Feedback 15 LMC7101, LMC7101Q SNOS719F – SEPTEMBER 1999 – REVISED MARCH 2013 www.ti.com 15V Typical Performance Characteristics (continued) + − V = +15V, V = 0V, TA = 25°C, unless otherwise specified. 16 Non-Inverting Small Signal Pulse Response Non-Inverting Small Signal Pulse Response Figure 50. Figure 51. Non-Inverting Small Signal Pulse Response Non-Inverting Large Signal Pulse Response Figure 52. Figure 53. Non-Inverting Large Signal Pulse Response Non-Inverting Large Signal Pulse Response Figure 54. Figure 55. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LMC7101 LMC7101Q LMC7101, LMC7101Q www.ti.com SNOS719F – SEPTEMBER 1999 – REVISED MARCH 2013 15V Typical Performance Characteristics (continued) + − V = +15V, V = 0V, TA = 25°C, unless otherwise specified. Stability vs. Capacitive Load Stability vs. Capacitive Load Figure 56. Figure 57. Stability vs. Capacitive Load Stability vs. Capacitive Load Figure 58. Figure 59. Stability vs. Capacitive Load Stability vs. Capacitive Load Figure 60. Figure 61. Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LMC7101 LMC7101Q Submit Documentation Feedback 17 LMC7101, LMC7101Q SNOS719F – SEPTEMBER 1999 – REVISED MARCH 2013 www.ti.com APPLICATION INFORMATION BENEFITS OF THE LMC7101 TINY AMP Size The small footprint of the SOT-23-5 packaged Tiny amp, (0.120 x 0.118 inches, 3.05 x 3.00 mm) saves space on printed circuit boards, and enable the design of smaller electronic products. Because they are easier to carry, many customers prefer smaller and lighter products. Height The height (0.056 inches, 1.43 mm) of the Tiny amp makes it possible to use it in PCMCIA type III cards. Signal Integrity Signals can pick up noise between the signal source and the amplifier. By using a physically smaller amplifier package, the Tiny amp can be placed closer to the signal source, reducing noise pickup and increasing signal integrity. The Tiny amp can also be placed next to the signal destination, such as a buffer for the reference of an analog to digital converter. Simplified Board Layout The Tiny amp can simplify board layout in several ways. First, by placing an amp where amps are needed, instead of routing signals to a dual or quad device, long pc traces may be avoided. By using multiple Tiny amps instead of duals or quads, complex signal routing and possibly crosstalk can be reduced. Low THD The high open loop gain of the LMC7101 amp allows it to achieve very low audio distortion—typically 0.01% at 10 kHz with a 10 kΩ load at 5V supplies. This makes the Tiny an excellent for audio, modems, and low frequency signal processing. Low Supply Current The typical 0.5 mA supply current of the LMC7101 extends battery life in portable applications, and may allow the reduction of the size of batteries in some applications. Wide Voltage Range The LMC7101 is characterized at 15V, 5V and 3V. Performance data is provided at these popular voltages. This wide voltage range makes the LMC7101 a good choice for devices where the voltage may vary over the life of the batteries. INPUT COMMON MODE Voltage Range The LMC7101 does not exhibit phase inversion when an input voltage exceeds the negative supply voltage. Figure 62 shows an input voltage exceeding both supplies with no resulting phase inversion of the output. The absolute maximum input voltage is 300 mV beyond either rail at room temperature. Voltages greatly exceeding this maximum rating, as in Figure 63, can cause excessive current to flow in or out of the input pins, adversely affecting reliability. 18 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LMC7101 LMC7101Q LMC7101, LMC7101Q www.ti.com SNOS719F – SEPTEMBER 1999 – REVISED MARCH 2013 An input voltage signal exceeds the LMC7101 power supply voltages with no output phase inversion. Figure 62. Input Voltage A ±7.5V input signal greatly exceeds the 3V supply in Figure 64 causing no phase inversion due to RI. Figure 63. Input Signal Applications that exceed this rating must externally limit the maximum input current to ±5 mA with an input resistor as shown in Figure 64. Figure 64. RI Input Current Protection for Voltages Exceeding the Supply Voltage RAIL-TO-RAIL OUTPUT The approximate output resistance of the LMC7101 is 180Ω sourcing and 130Ω sinking at VS = 3V and 110Ω sourcing and 80Ω sinking at VS = 5V. Using the calculated output resistance, maximum output voltage swing can be estimated as a function of load. CAPACITIVE LOAD TOLERANCE The LMC7101 can typically directly drive a 100 pF load with VS = 15V at unity gain without oscillating. The unity gain follower is the most sensitive configuration. Direct capacitive loading reduces the phase margin of op amps. The combination of the op amp's output impedance and the capacitive load induces phase lag. This results in either an underdamped pulse response or oscillation. Capacitive load compensation can be accomplished using resistive isolation as shown in Figure 65. This simple technique is useful for isolating the capacitive input of multiplexers and A/D converters. Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LMC7101 LMC7101Q Submit Documentation Feedback 19 LMC7101, LMC7101Q SNOS719F – SEPTEMBER 1999 – REVISED MARCH 2013 www.ti.com Figure 65. Resistive Isolation of a 330 pF Capacitive Load COMPENSATING FOR INPUT CAPACITANCE WHEN USING LARGE VALUE FEEDBACK RESISTORS When using very large value feedback resistors, (usually > 500 kΩ) the large feed back resistance can react with the input capacitance due to transducers, photo diodes, and circuit board parasitics to reduce phase margins. The effect of input capacitance can be compensated for by adding a feedback capacitor. The feedback capacitor (as in Figure 66), Cf is first estimated by: (1) or R1 CIN ≤ R2 Cf (2) which typically provides significant overcompensation. Printed circuit board stray capacitance may be larger or smaller than that of a breadboard, so the actual optimum value for CF may be different. The values of CF should be checked on the actual circuit. (Refer to the LMC660 quad CMOS amplifier data sheet for a more detailed discussion.) Figure 66. Cancelling the Effect of Input Capacitance 20 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LMC7101 LMC7101Q LMC7101, LMC7101Q www.ti.com SNOS719F – SEPTEMBER 1999 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision E (March 2013) to Revision F • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 20 Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LMC7101 LMC7101Q Submit Documentation Feedback 21 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) LMC7101AIM5 ACTIVE SOT-23 DBV 5 1000 TBD Call TI Call TI -40 to 85 A00A LMC7101AIM5/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A00A LMC7101AIM5X ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 85 A00A LMC7101AIM5X/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A00A LMC7101BIM5 ACTIVE SOT-23 DBV 5 1000 TBD Call TI Call TI -40 to 85 A00B LMC7101BIM5/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A00B LMC7101BIM5X ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 85 A00B LMC7101BIM5X/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A00B LMC7101QM5/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AT6A LMC7101QM5X/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AT6A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com (3) 11-Apr-2013 MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) LMC7101AIM5 SOT-23 DBV 5 1000 178.0 8.4 LMC7101AIM5/NOPB SOT-23 DBV 5 1000 178.0 LMC7101AIM5X SOT-23 DBV 5 3000 178.0 LMC7101AIM5X/NOPB SOT-23 DBV 5 3000 LMC7101BIM5 SOT-23 DBV 5 LMC7101BIM5/NOPB SOT-23 DBV LMC7101BIM5X SOT-23 DBV LMC7101BIM5X/NOPB SOT-23 LMC7101QM5/NOPB LMC7101QM5X/NOPB 3.2 3.2 1.4 4.0 8.0 Q3 8.4 3.2 3.2 1.4 4.0 8.0 Q3 8.4 3.2 3.2 1.4 4.0 8.0 Q3 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 Pack Materials-Page 1 W Pin1 (mm) Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMC7101AIM5 SOT-23 DBV 5 1000 210.0 185.0 35.0 LMC7101AIM5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LMC7101AIM5X SOT-23 DBV 5 3000 210.0 185.0 35.0 LMC7101AIM5X/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LMC7101BIM5 SOT-23 DBV 5 1000 210.0 185.0 35.0 LMC7101BIM5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LMC7101BIM5X SOT-23 DBV 5 3000 210.0 185.0 35.0 LMC7101BIM5X/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 LMC7101QM5/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0 LMC7101QM5X/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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