Fairchild FAN5182 Adjustable output, 1-, 2-, or 3-phase synchronous buck controller Datasheet

FAN5182 — Adjustable Output, 1-, 2-, or 3-Phase
Synchronous Buck Controller
Features
Description
ƒ
Selectable 1-, 2-, or 3-Phase Operation at up to
1MHz per Phase
ƒ
Accuracy:
The FAN5182 is a highly efficient, multiphase,
synchronous buck switching regulator controller
optimized for converting a 12V main supply into a highcurrent, low-voltage supply for use in point-of-load (POL)
applications. It uses a multi-loop PWM architecture to
drive the logic-level outputs at a programmable
switching frequency that can be optimized for regulator
size and efficiency. The phase relationship of the output
signals can be programmed to provide 1-, 2-, or 3-phase
operation, allowing for construction of up to three
complementary, interleaved buck switching stages.
-
FAN5182
2%
FAN5182_NA3E229
1%
FAN5182_NA3E231
3%
ƒ
Externally Adjustable 0.8V to 5V Output from a
12V Supply
ƒ
Logic-Level PWM Outputs for Interface to External
High-Power Drivers
ƒ
ƒ
ƒ
Active Current Balancing Between all Phases
Built-in Power-Good / Crowbar Functions
Programmable Over-Current Protection with
Adjustable Latch-Off Delay
The FAN5182 provides accurate and reliable overcurrent protection and adjustable current limiting.
The FAN5182 is specified over the commercial
temperature range of 0°C to +85°C and is available in a
20-lead Quarter-Size Outline Package (QSOP).
Applications
ƒ
ƒ
ƒ
Auxiliary Supplies
DDR Memory Supplies
Point-of-Load Supplies
Ordering Information
Part Number
Temperature
Range
PbFree
Package
Packing
Method
Quantity
per Reel
FAN5182QSCX_NL
0°C to 85°C
Yes
QSOP-20L
Tape and Reel
2500
FAN5182QSCX_NA3E229_NL
0°C to 85°C
Yes
QSOP-20L
Tape and Reel
2500
FAN5182QSCX_NA3E231_NL
0°C to 85°C
Yes
QSOP-20L
Tape and Reel
2500
© 2005 Fairchild Semiconductor Corporation
FAN5182 Rev. 1.1.1
www.fairchildsemi.com
FAN5182 — Adjustable Output 1-, 2-, or 3-Phase Synchronous Buck Controller
March 2007
FAN5182 — Adjustable Output 1-, 2-, or 3-Phase Synchronous Buck Controller
Block Diagram
Figure 1. Block Diagram
© 2005 Fairchild Semiconductor Corporation
FAN5182 Rev. 1.1.1
www.fairchildsemi.com
2
Figure 2. Pin Assignments
Pin Definitions
Pin #
Name
Description
1
VCC
2
FBRTN
Supply Voltage for the Device.
Feedback Return. Voltage error amplifier reference for remote sensing of the output voltage.
3
FB
Feedback Input. Error amplifier input for remote sensing of the output voltage. An external
resistor divider between the output and FBRTN connected to this pin sets the output voltage.
This pin is also the reference point for the power-good and crowbar comparators.
4
COMP
5
PWRGD
6
EN
7
DELAY
8
RT
9
RAMPADJ
Error Amplifier Output and Compensation Pin.
Power Good Output. Open-drain output that signals when the output voltage is outside the
proper operating range.
Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the
PWRGD output low.
Soft-Start Delay and Current Limit Latch-Off Delay Setting Input. An external resistor and
capacitor connected between this pin and GND sets the soft-start ramp-up time and the overcurrent latch-off delay time.
Frequency Setting Resistor Input. An external resistor connected between this pin and GND
sets the oscillator frequency of the device.
FAN5182 — Adjustable Output 1-, 2-, or 3-Phase Synchronous Buck Controller
Pin Assignments
PWM Ramp Current Input. An external resistor from the converter input voltage to this pin
sets the internal PWM ramp.
10
ILIMIT
Current-Limit Set point / Enable Output. An external resistor connected from this pin to GND
sets the current limit threshold of the converter. This pin is actively pulled low when the EN
input is low, or when VCC is below its UVLO threshold, to signal to the driver IC that the driver
high-side and low-side outputs should go low.
11
CSREF
Current-Sense Reference Voltage Input. The voltage on this pin is used as the reference for
the current-sense amplifier. Connect this pin to the common point of the output inductors.
12
CSSUM
Current-Sense Summing Node. External resistors from each switch node to this pin sum the
average inductor currents to measure the total output current.
13
CSCOMP
14
GND
15–17
SW3 - SW1
Current-Sense Compensation Point. A resistor and a capacitor from this pin to CSSUM
determine the gain of the current sense amplifier.
Ground. All internal biasing and logic output signals are referenced to this ground.
Current Balance Inputs. These are inputs for measuring the current level in each phase. The
SW pins of unused phases should be connected to ground.
Logic-Level PWM Outputs. Each output is connected to the input of an external MOSFET
driver, such as the FAN5109. Connecting the PWM3 output to GND causes that phase to turn
18–20 PWM3 - PWM1
off, allowing the FAN5182 to operate as a 1- or 2-phase controller. Do not connect PWM2 to
ground for 1-phase operation.
© 2005 Fairchild Semiconductor Corporation
FAN5182 Rev. 1.1.1
www.fairchildsemi.com
3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only. Unless otherwise noted, all voltages are referenced to GND.
Symbol
VCC
Parameter
Min.
Max.
Unit
VCC
-0.3
+15
V
FBRTN
-0.3
+0.3
V
EN, DELAY, ILIMIT, RT, PWM1-PWM3, COMP
-0.3
5.5
V
-5
+25
V
-0.3
VCC + 0.3
V
SW1-SW3
All Other Inputs and Outputs
TJ
TSTG
Operating Junction Temperature
Storage Temperature
0
+125
°C
-65
+150
°C
TL
Lead Soldering Temperature (10 seconds)
300
°C
TLI
Lead Infrared Temperature (15 seconds)
260
°C
ΘJC
Thermal Resistance Junction-to-Case
38
°C/W
ΘJA
Thermal Resistance Junction-to-Ambient(1)
90
°C/W
Note:
1. Junction-to-ambient thermal resistance, ΘJA, is a strong function of PCB material, board thickness, thickness and
number of copper planes, number of via used, diameter of via used, available copper surface, and attached heat
sink characteristics. It is measured with the device mounted on a board of FR-4 material, 0.063inch thickness, no
copper plane, and zero air flow.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
VCC
Supply Voltage Range
TA
Operating Ambient Temperature
© 2005 Fairchild Semiconductor Corporation
FAN5182 Rev. 1.1.1
Min.
Typ.
Max.
Unit
10.8
12.0
13.2
V
+85
°C
0
FAN5182 — Adjustable Output 1-, 2-, or 3-Phase Synchronous Buck Controller
Absolute Maximum Ratings
www.fairchildsemi.com
4
VCC = 12V, FBRTN = GND, • indicates specifications over operating ambient temperature range.(2)
Symbol
Parameter
Conditions
Min.
Typ.
Max. Units
Oscillator
fOSC
TPHASE
VRT
Frequency Range
Frequency Variation
•
0.25
RT = 332kΩ, 3-phase
•
155
200
245
TA = 25°C, RT = 154kΩ, 3-phase
•
155
400
245
TA = 25°C, RT = 100kΩ, 3-phase •
155
600
245
Output Voltage
RT = 100kΩ to GND
•
VRAMPADJ
RAMPADJ Output Voltage
RAMPADJ - FB - 2KΩ x IRAMPADJ
(with IRAMPADJ set to 20µA)
•
IRAMPADJ
RAMPADJ Input Current Range(3)
3.00
2.0
MHz
kHz
V
-50
+50
mV
0
100
µA
0.3
V
Voltage Error Amplifier
VOL
Output Voltage Low
VOH
Output Voltage High
3.1
FAN5182
VFB
IFB
2%
•
784
800
816
mV
Accuracy (Referenced to FBRTN) FAN5182_NA3E229
1%
•
792
800
808
mV
FAN5182_NA3E231
3%
•
786
800
824
mV
•
-4
±1
+4
µA
140
µA
Input Bias Current
FB = 800mV
VCC = 10V to 14V
ΔVFB
Line Regulation
IFBRTN
FBRTN Current
IO(ERR)
Output Current
0.05
•
100
FB forced to VOUT - 3%
(3)
DC Gain
GBW(ERR)
V
(3)
%
500
µA
87
dB
Gain Bandwidth Product
COMP = FB
20
MHz
Slew Rate(3)
CCOMP = 10pF
10
V/µs
Current-Sense Amplifier
VOS(CSA)
Offset Voltage
CSSUM-CSREF (See Figure 3)
IBIAS(CSSUM) Input Bias Current
•
-5.5
+5.5
mV
•
-50
+50
nA
(3)
DC Gain
GBW(CSA)
(3)
Gain Bandwidth Product
(3)
Slew Rate
CCSCOMP = 10pF
Input Common-Mode Range
CSSUM & CSREF
VOL
Output Voltage Low
VOH
Output Voltage High
ICSCOMP
70
dB
10
MHz
10
0
V/µs
VCC-2.5
V
0.1
V
VCC-2.5
Output Current
FAN5182 — Adjustable Output 1-, 2-, or 3-Phase Synchronous Buck Controller
Electrical Characteristics
V
500
µA
Current-Balance Circuit
VSW(X)CM
Common-Mode Range(3)
-600
+200
mV
Rsw(X)
Input Resistance
SW(X) = 0V
•
20
30
40
kΩ
ISW(X)
Input Current
SW(X) = 0V
•
4
7
10
µA
Input Current Matching
SW(X) = 0V
•
-7
+7
%
ΔISW(X)
ΔVOS Match
Offset Voltage Matching
(Difference between phases)
© 2005 Fairchild Semiconductor Corporation
FAN5182 Rev. 1.1.1
FAN5182
11
mV
FAN5182_NA3E229
8
mV
FAN5182_NA3E231
8
mV
www.fairchildsemi.com
5
VCC = 12V, FBRTN = GND, • indicates specifications over operating ambient temperature range.(2)
Symbol
Parameter
Conditions
Min.
Typ. Max. Units
Current-Limit Comparator
VILIMIT(NM)
Output Voltage: Normal Mode
EN > 2.0V, RILIMIT = 250kΩ
•
VILIMIT(SD)
Output Voltage: In Shutdown
EN < 0.8V, IILIMIT = -100µA
•
Output Current: Normal Mode
EN > 2.0V, RILIMIT = 250kΩ
IILIMIT(NM)
Maximum Output Current
VCL
Current Limit Threshold
Current Limit Setting Ratio
2.9
3.0
3.1
V
400
mV
12
•
VCSREF - VCSCOMP , RILIMIT = 250kΩ
µA
60
105
VCL/IILIMIT
µA
125
145
10.4
mV
mV/µA
VDELAY(NM) Delay Normal Mode Voltage
RDELAY = 250kΩ
2.9
3.0
3.1
V
VDELAY(OC) Delay Over-Current Threshold
RDELAY = 250kΩ
1.7
1.8
1.9
V
tDELAY
(3)
Latch-Off Delay Time
RDELAY = 250kΩ, CDELAY = 12nF
1.5
ms
Soft-Start
IDELAY(SS)
tDELAY(SS)
Output Current, Soft-Start Mode
(3)
Soft-Start Delay Time
During start-up, Delay < 2.4V
•
15
RDELAY = 250kΩ, CDELAY = 12nF
20
25
500
µA
µs
Enable Input
VIL(EN)
Input Low Voltage
•
VIH(EN)
Input High Voltage
•
0.8
2.0
Input Hysteresis Voltage
IIN(EN)
V
100
Input Current
•
-1
V
mV
+1
µA
Power-Good Comparator
VPWRGD(UV) Under-Voltage Threshold
Relative to FBRTN
•
600
660
720
mV
VPWRGD(OV) Over-Voltage Threshold
Relative to FBRTN
•
880
940
1000
mV
VOL(PWRGD) Output Low Voltage
IPWRGD(SINK) = 4mA
•
225
400
mV
Power-Good Delay Time
200
VCROWBAR
Crowbar Trip Point
Relative to FBRTN
•
0.970
Crowbar Reset Point
Relative to FBRTN
•
550
tCROWBAR
Crowbar Delay Point(3)
Over-voltage to PWM going low
ns
1.050 1.105
650
750
400
V
mV
ns
FAN5182 — Adjustable Output 1-, 2-, or 3-Phase Synchronous Buck Controller
Electrical Characteristics (Continued)
PWM Outputs
VOL(PWM)
Output Low Voltage
IPWM(SINK) = 400µA
•
VOH(PWM)
Output High Voltage
IPWM(SOURCE) = -400µA
•
160
4.0
500
5
mV
V
Supply
DC Supply Current
VUVLO
UVLO Threshold Voltage
•
VCC rising
UVLO Hysteresis
5
10
mA
•
6.5
6.9
7.3
V
•
0.7
0.9
1.1
V
Notes:
2. Limits at operating temperature extremes are guaranteed by design, characterization, and statistical quality control.
3. Guaranteed by design, not tested in production.
© 2005 Fairchild Semiconductor Corporation
FAN5182 Rev. 1.1.1
www.fairchildsemi.com
6
FAN5182 — Adjustable Output 1-, 2-, or 3-Phase Synchronous Buck Controller
Test Circuit
Figure 3. Current-Sense Amplifier
Typical Performance Characteristics
Figure 4. Master Clock Frequency vs. RT
Figure 5. Normalized VFB vs. Temperature
Figure 6. Supply Current vs. Oscillator Frequency
© 2005 Fairchild Semiconductor Corporation
FAN5182 Rev. 1.1.1
www.fairchildsemi.com
7
FAN5182 — Adjustable Output 1-, 2-, or 3-Phase Synchronous Buck Controller
Typical Application Circuit
Figure 7. 1.8V, 55A Application Circuit
© 2005 Fairchild Semiconductor Corporation
FAN5182 Rev. 1.1.1
www.fairchildsemi.com
8
The FAN5182 combines a multi-loop, fixed-frequency
PWM control with multi-phase logic outputs for use in
1-, 2-, and 3-phase synchronous buck point-of-load
power supplies. Multi-phase operation is important for
producing the high current and low voltage demanded
by auxiliary supplies in desktop computers,
workstations, and servers. Handling high current in a
single-phase converter places high thermal stress on
components, such as inductors and MOSFETs, and is
not preferred.
NOTE: The exception is single-phase operation, in
which the clock frequency must be set twice the singlephase frequency required.
The multi-loop control of the FAN5182 ensures a stable,
high performance topology for:
Output Voltage Differential Sensing
ƒ
Balancing current and thermal between/among
phases
ƒ
Fast response at the lowest possible switching
frequency and output decoupling
ƒ
Reducing switching losses due to low-frequency
operation
ƒ
ƒ
Tight line and load regulation
ƒ
Better noise immunity to facilitate PCB layout
Master Clock Frequency
The clock frequency is set by an external resistor
connected from the RT pin to ground. The frequency /
resistor relationship follows the graph in Figure 4. To
determine the frequency per phase, divide the clock
frequency by the number of phases in use.
The FAN5182 uses a differential low-offset voltage error
amplifier to maintain ±2% differential sensing accuracy
over temperature. The output voltage is sensed between
the FB and FBRTN pins. The power supply output
connects to the FB pin through a resistor divider and the
FBRTN pin should be connected directly to the remote
sense ground. The internal precision reference is
referenced to FBRTN, which has a typical current of
100µA to allow accurate remote sensing. The internal
error amplifier compares the precision reference to the
FB pin to regulate the output voltage.
Reducing output ripple due to multiphase
cancellation
Output Current Sensing
The FAN5182 uses a current sense amplifier (CSA) to
monitor the total output current for current-limit
detection. Sensing the load current at the output gives
the total average current being delivered to the load,
which is an inherently more accurate method than peak
current detection or sampling the current across a sense
element, such as the low-side MOSFET. This amplifier
can be configured according to the objectives of the
system design:
Start-up Sequence
During start-up, the number of operational phases and
their phase relationship are determined by the internal
circuitry that monitors the PWM outputs. Normally, the
FAN5182 operates as a 3-phase PWM controller.
Grounding the PWM3 pin programs the FAN5182 for 1or 2-phase operation.
When the FAN5182 is enabled, the controller outputs a
voltage on PWM3, which is approximately 675mV. An
internal comparator checks this pin's voltage versus a
threshold of 300mV. If the PWM3 pin is grounded, it is
below the threshold and the phase 3 is disabled. The
output resistance of the PWM pin is approximately 5kΩ
during this detection period. Any external pull-down
resistance connected to the PWM pin should not be less
than 25kΩ to ensure proper operation. PWM1 and
PWM2 are disabled during the phase-detection interval,
which occurs during the first two clock cycles of the
internal oscillator. After this time, if the PWM3 output is
not grounded, the 5kΩ resistance is disconnected, and
PWM3 switches between 0V and 5V. If the PWM3
output is grounded, the controller operates in 1- and/or
2-phase.
ƒ
Output inductor DCR sensing without a thermistor
(for lowest cost)
ƒ
Output inductor DCR sensing with a thermistor
(for improved accuracy and moderate cost)
FAN5182 — Adjustable Output 1-, 2-, or 3-Phase Synchronous Buck Controller
Theory of Operation
ƒ
Discrete resistor sensing (for best accuracy)
The positive input of the CSA is connected to the
CSREF pin and the CSREF is tied to the power supply
output. The inverting input of the CSA, CSSUM, is the
summing node of the load current sense through
sensing elements (such as the switch node side of the
output inductors). The feedback resistor between
CSCOMP and CSSUM sets the gain of the amplifier and
a filter capacitor is placed in parallel with this resistor.
The gain of the amplifier is programmable by adjusting
the feedback resistor. The current information is given
as the difference between CSREF and CSCOMP. This
“difference” signal is used as a differential input for the
current limit comparator.
The PWM outputs logic-level signals to interface with
external gate drivers, such as the FAN5109. Since each
phase is able to operate close to 100% duty cycle, more
than one PWM output can be on at the same time.
To provide the best accuracy for sensing current, the
CSA is designed to have low-input offset voltage. The
CSA gain is determined by external resistors, so it can
be set very accurately.
© 2005 Fairchild Semiconductor Corporation
FAN5182 Rev. 1.1.1
www.fairchildsemi.com
9
The FAN5182 adopts low-side MOSFET RDSON sensing
for phase-current balance. The sensed individual phase
current is combined with a fixed internal ramp, then
compared with the common voltage error amplifier
output to balance phase current. This current-balance
information is independent of the average output current
information used for the current limit.
The magnitude of the internal ramp can be set to
optimize transient response of the system. It also tracks
the supply voltage for better line regulation and transient
response. A resistor connected from the power supply
input to the RAMPADJ pin determines the slope of the
internal PWM ramp. Resistors RSW1 through RSW3 (see
Figure 7) can be used to adjust phase current balance.
Putting placeholders for these resistors during the initial
PCB layout allows phase-current balance fine
adjustments on the bench if necessary.
Figure 8. Typical Start-Up Waveforms
Current-Limit and Latch-off Protection
The FAN5182 compares a programmable current-limit
set point to the voltage from the output of the currentsense amplifier. The level of current limit is set with the
resistor from the ILIMIT pin to ground. During normal
operation, the voltage on ILIMIT is 3V. The current
through the external resistor is internally scaled to give a
current-limit threshold of 10.4mV/µA. If the difference in
voltage between CSREF and CSCOMP rises above the
current-limit threshold, the internal current-limit amplifier
controls the COMP voltage to maintain the power supply
output current at the over-current level.
To increase the current in any given phase, increase
RSW for that phase (make RSW = 0Ω for the hottest
phase as the starting point). Increasing RSW to 500Ω
could typically make a substantial increase in this
particular phase current. Increase each RSW value by
small amounts to optimize phase-current balance,
starting with the coolest phase.
After the limit is reached, the 3V pull-up voltage source
on the DELAY pin is disconnected and the external
delay capacitor discharges through the external resistor.
A comparator monitors the DELAY pin voltage and
shuts off the controller when the voltage drops below
1.8V. The current-limit latch-off delay time is therefore
set by the RC time constant discharging the delay
voltage from 3V to 1.8V. Typical over-current latch-off
waveforms are shown in Figure 9.
Voltage Control Loop
A high gain bandwidth voltage error amplifier is used for
the voltage control loop. The non-inverting input of the
error amplifier is derived from the internal 800mV
reference. The output of the error amplifier, the COMP
pin sets the termination voltage for the internal PWM
ramps plus sensed phase current.
The controller continues to switch all phases during the
latch-off delay time. If the over-current condition is
removed before the 1.8V delay threshold is reached, the
controller resumes normal operation. The over-current
recovery characteristic also depends on the state of
PWRGD. If the output voltage is within the PWRGD
window during over current, the controller resumes normal
operation once the over-current condition is removed. If
over-current causes the output voltage to drop below the
PWRGD threshold, a soft-start cycle is initiated.
The inverting input (FB) is tied to the center point of a
resistor divider from the output voltage sense point.
Closed-loop compensation is realized via compensator
networks connecting to the FB and COMP pins.
Soft-Start
The soft-start rise time of the output voltage is set by a
parallel capacitor and resistor between the DELAY pin
and ground. The resistor capacitor (RC) time constant
also determines the current-limit latch-off delay time, as
explained in the following section. In UVLO or when EN
is logic low, the DELAY pin is held to ground. After the
UVLO threshold is reached and EN is in logic high state,
the delay capacitor is charged with an internal 20µA
current source. The output voltage follows the ramping
voltage on the DELAY pin to limit the inrush current. The
soft-start time depends on the value of CDLY with a
secondary effect from RDLY.
FAN5182 — Adjustable Output 1-, 2-, or 3-Phase Synchronous Buck Controller
Current Control Loop and Thermal
Balance
If either EN is logic low or VCC drops below UVLO, the
delay capacitor resets to ground and is ready for another
soft-start cycle.
Figure 8 shows typical start-up waveforms for a softstart sequence.
© 2005 Fairchild Semiconductor Corporation
FAN5182 Rev. 1.1.1
Figure 9. Over-Current Latch-Off Waveforms
www.fairchildsemi.com
10
Enable and UVLO
To begin switching, the input supply (VCC) to the
controller must be higher than the UVLO threshold, and
the EN pin must be higher than its logic threshold. If
UVLO is less than the threshold or the EN pin is logic
low, the FAN5182 is disabled. This holds the PWM
outputs at ground, shorts the delay capacitor to ground,
and holds the ILIMIT pin at ground.
In the application circuit, the ILIMIT pin should be
connected to the OD pins of the FAN5109 drivers.
Grounding the ILIMIT pin disables the drivers such that
both HDRV and LDRV hold low. This feature is
important in preventing fast discharge of the output
capacitors when the controller shuts off. If the driver
outputs are not disabled, a negative output voltage can
be generated due to high current discharged from the
output capacitors through the inductors.
During start-up, when the output voltage is below
200mV, a secondary current limit is activated. This is
necessary because the voltage swing of CSCOMP
cannot go below ground. This secondary current limit
clamps the COMP voltage to 2V.
An inherent, per-phase current limit protects individual
phases if one or more phases cease to function
because of a faulty component. This limit is based on
the maximum normal mode COMP voltage.
FAN5182 in Single-Phase Applications
NOTE: When the FAN5182 is configured for singlephase applications, it is actually operating internally as a
two-phase controller. It therefore should be configured
as a two-phase controller with only one phase populated
externally.
Power-Good Monitoring
The power-good comparator monitors the output voltage
via the FB pin. The PWRGD pin is an open-drain output
whose high level (when connected to a pull-up resistor)
indicates that the output voltage is within the nominal
limits specified in the Electrical Characteristic table.
PWRGD goes low if the output voltage is outside the
specified range or whenever the EN pin is pulled low.
Figure 10 shows the PWRGD response when the input
power supply is switched off.
To accomplish this, PWM3 needs be grounded (to
configure the FAN5182 as a two-phase controller) and
the clock frequency set to two times the required phase
switching frequency. PWM1 should be used to drive the
external phase electronics (driver and MOSFETs). The
SW2 and SW3 pins should be connected to ground to
minimize any potential spurious noise paths.
WARNING: Do not connect PWM2 to ground.
As noted above, when using the FAN5182 in singlephase applications, it is actually operating internally as a
two-phase controller and PWM2 may be switching.
FAN5182 as a Voltage-Mode Controller
The SW pins are used to measure the current flowing
through the bottom FET. This current information is
used to balance the phase currents in a multiphase
application and create an inner current-feedback loop in
the control loop, making the FAN5182 a current-mode
controller.
In single-phase applications where phase current
balance is not required, the current loop can be
defeated by disconnecting the SW pins from the output
FETs and shorting the SW pin to ground. This changes
the control loop from current-mode control to voltagemode control.
Figure 10. Shutdown Waveforms
As part of the protection for the load and output
components of the supply, the PWM outputs are driven
low (turning on the low-side MOSFETs) when the output
voltage exceeds the crowbar trip point. This crowbar
action stops once the output voltage falls below the
reset threshold of approximately 650mV.
WARNING: The compensation requirements for a
voltage-mode control design differ for current-mode
control design. The Application Information section of
this datasheet is for a current-mode control design. The
compensation section “Closed-Loop Compensation
Design” does not apply to voltage-mode designs.
Turning on the low-side MOSFETs pulls down the output
as the reverse current builds up in the inductors. If the
output over-voltage is due to a short in the high-side
MOSFET, this crowbar action can trip the input supply
over-current protection or blow the input fuse, protecting
the load from damage.
© 2005 Fairchild Semiconductor Corporation
FAN5182 Rev. 1.1.1
FAN5182 — Adjustable Output 1-, 2-, or 3-Phase Synchronous Buck Controller
The latch-off function can be reset by removing and
reapplying VCC or by pulling the EN pin low briefly. To
disable the over-current latch-off function, the external
resistor connecting the DELAY pin and ground should
be removed and a high-value resistor (>1MΩ) should be
connected from the DELAY pin to VCC. This prevents the
delay capacitor from discharging, so the 1.8V threshold
can never be reached. This pull-up resistor has some
impact to the soft-start time because the current through
this resistor adds additional current to the internal 20µA
soft-start current.
www.fairchildsemi.com
11
Design parameters for a typical high-current DC/DC
buck converter, as shown in Figure 7, follow. This is a
multiphase, current-mode control implementation. The
equations shown are interdependent and must be
followed in the sequence shown. For other
implementations, adjust the design requirements.
sinks part of the current source to ground. As long as
RDLY is greater than 200kΩ, this effect is minor.
NOTE: A complete MathCAD® control design program
is available from Fairchild upon request.
where tSS is the desired soft-start time. Assuming an
RDLY of 390kΩ and a desired soft-start time of 3ms, CDLY
is 71nF. The closest standard value for CDLY is 68nF.
Once CDLY is chosen, RDLY can be calculated for the
current-limit latch-off time, using:
The value for CDLY can be approximated using:
VREF ⎞ tSS
⎛
CDLY = ⎜ 20 μA −
⎟×
2 × RDLY ⎠ VREF
⎝
Design Requirements:
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
Input voltage (VIN) = 12V
EQ. 2
1.96 × t DELAY
CDLY
EQ. 3
Output voltage (VOUT) = 1.8V
RDLY =
Duty cycle (D) = 0.15
If the result for RDLY is less than 200kΩ, a smaller softstart time should be considered, by recalculating the
equation for CDLY, or a longer latch-off time should be
used. RDLY should never be less than 200kΩ. In this
example, a delay time of 9ms results in RDLY = 259kΩ.
The closest standard 1% value is 261kΩ.
Output current IO = 55A
Maximum output current (ILIM) = 110A
Number of phases (n) = 3
Switching frequency per phase (fSW ) = 250kHz
Inductor Selection
Setting the Clock Frequency
The inductance determines the ripple current in the
inductor. Small inductance leads to high ripple current,
which increases the output ripple voltage and
conduction losses in the MOSFETs and vise versa. In
any multiphase converter, it's recommended to design
the peak-to-peak inductor ripple current to be less than
50% of the maximum inductor DC current.
The FAN5182 uses fixed-frequency control architecture.
The frequency is set by an external timing resistor (RT).
The clock frequency and the number of phases
determine the switching frequency per phase, which
relates directly to switching losses and the sizes of the
inductors and the input and output capacitors. With n =
3 for three phases, a clock frequency of 750kHz sets the
switching frequency, fSW , of each phase to 250kHz,
which represents a practical trade-off between the
switching losses and the sizes of the output filter
components.
Equation 4 shows the relationship among the inductance,
oscillator frequency, and peak-to-peak ripple current:
IR =
Equation 1 shows that to achieve a 750kHz oscillator
frequency, the correct value for RT is 255kΩ.
Alternatively, the value for RT can be calculated using:
1
− 27KΩ
n × fSW × 4.7pF
1
RT =
− 27KΩ = 256KΩ
3 × 250kHz × 4.7pF
EQ. 4
Equation 5 can be used to determine the minimum
inductance based on a given output ripple voltage:
L≥
RT =
EQ. 1
VOUT × Rx × (1 − (n × D))
fSW × VRIPPLE
EQ. 5
where RX is the ESR of output bulk capacitors.
Solving Equation 5 for a 20mV peak-to-peak output
ripple voltage and 3mΩ RX yields:
where 4.7pF and 27kΩ are internal IC component
values. For good initial accuracy and frequency stability,
a 1% resistor is recommended. The closest standard
1% value for this design is 255kΩ.
L≥
NOTE: For a single-phase application, set the oscillator
frequency to two times the required per-phase switching
frequency. This can be done buy substituting “2 x fSW ”
for “fSW ” in Equation 1.
1.8 V × 0.7mΩ × (1 − (3 × 0.15))
= 277nH
250kHz × 10mV
EQ. 6
If the resulting ripple voltage is too low, the inductance
can be reduced until the desired ripple voltage is
achieved. In this example, a 600nH inductor is a good
starting point that produces a calculated ripple current of
6.6A. The inductor should not saturate at the peak
current of 21.6A and should be able to handle the total
power dissipation created by the copper and core loss.
Soft-Start and Current-Limit Latch-off
Delay Time
Another important factor in the inductor design is the
Direct Conversion Receiver (DCR), which is used for
measuring the phase current. A large DCR can cause
excessive power losses, whereas too small DCR can
increases measurement error. For this design, a DCR of
1.4mΩ was chosen.
Because the soft-start and current-limit latch-off delay
functions share the DELAY pin, these two parameters
must be considered together. The first step is to set
CDLY for the soft-start ramp. This ramp is generated with
a 20µA internal current source. The value of RDLY has a
second-order impact on the soft-start time because it
© 2005 Fairchild Semiconductor Corporation
FAN5182 Rev. 1.1.1
VOUT × (1 − D)
fSW × L
FAN5182 — Adjustable Output 1-, 2-, or 3-Phase Synchronous Buck Controller
Application Information
www.fairchildsemi.com
12
RPH( x ) = RL × R CS ×
Once the inductance and DCR are known, the next step
is to either design an inductor or find a suitable standard
inductor if one exists. Inductor design starts with
choosing appropriate core material. Some candidate
materials that have low core loss at high frequencies are
powder cores (e.g. Kool-Mµ® from Magnetics, Inc. or
from Micrometals) and gapped soft ferrite cores (e.g.
3F3 or 3F4 from Philips). Powdered iron cores have
higher core loss and are used for low-cost applications.
RPH( x ) = 1.4mΩ × 100kΩ ×
110 A
= 140kΩ
110mV
EQ. 10
Next, use Equation 8 to solve for CCS:
Ccs ≥
320nH
≥ 2.28nF
1.4mΩ × 100kΩ
EQ. 11
Choose the closest standard value that is greater than
the result given by Equation 8. This example uses a CCS
value of 5.6nF.
Some useful references for magnetics design are:
Magnetic Designer Software
Intusoft (www.intusoft.com)
Output Voltage
Designing Magnetic Components for HighFrequency DC-DC Converters, by William T.
McLyman, Kg Magnetics, Inc., ISBN 1883107008.
FAN5182 has an internal FBRTN referred 800mV
reference voltage VREF. The output voltage can be set
by using a voltage divider consisting of resistors RB1 and
RB2:
Selecting a Standard Inductor
VOUT =
The following power inductor manufacturers can provide
design consultation and deliver power inductors
optimized for high-power applications upon request:
ƒ
BI Technologies, 714-447-2345
ƒ
Taiyo Yuden (USA), 408-573-4150
www.bitechnologies.com
www.taiyo-yuden.com
Ccs ≥
×
VDRP
RL
L
RL × R CS
VOUT − VFB
× R B1
VFB
R B2 =
1 .8 V − 0 .8 V
× 1kΩ = 1.25kΩ
0 .8 V
EQ. 13
For this example, one high-side and one low-side
N-channel power MOSFET per phase have been
selected. The main selection parameters for power
MOSFETs are VGS(TH), QG, CISS, CRSS, and RDS(ON). The
minimum gate-drive voltage (the supply voltage to the
FAN5109) dictates whether standard threshold or logiclevel threshold MOSFETs can be used. With VGATE
~10V, logic-level threshold MOSFETs (VGS(TH) < 2.5V)
are recommended.
EQ. 7
EQ. 8
The maximum output current (IO) determines the RDS(ON)
requirement for the low-side (synchronous) MOSFETs.
With good current balance among phases, the current in
each low-side MOSFET is the output current divided by
the total number of the low-side MOSFETs (nSF). Since
conduction loss is dominant in low-side MOSFET, the
following expression can represent total power
dissipation in each synchronous MOSFET in terms of
the ripple current per phase (IR) and the total output
current (IO):
where:
RL is the DCR of the output inductors,
VDRP is the voltage drop from CSCOMP to CSREF.
When load current reaches its limit, VDRP is at its
maximum (VDRPMAX). VDRPMAX can be in the range of
100mV to 200mV. In this example, it is 110mV.
Designers have the flexibility of choosing either RCS or
RPH(X). It is recommended to select RCS equal to 100kΩ,
and then solve for RPH(X) by rearranging Equation 7 as:
© 2005 Fairchild Semiconductor Corporation
FAN5182 Rev. 1.1.1
R B2 =
Power MOSFETs
The output current IO is set by the following equations:
R CS
EQ. 12
The closest standard 1% resistor value for RB2 is
1.24kΩ.
The output current can be measured by summing the
voltage across each inductor and passing the signal
through a low-pass filter. The CS amplifier is configured
with resistors RPH(X) (for summing the voltage), and RCS
and CCS (for the low-pass filter).
RPH( x )
(R B1 + R B2 )
× VREF
R B1
Rearranging Equation 12 to solve RB2 and assuming a
1%, 1kΩ resistor for RB1 yields
Output Current Sense
IO =
EQ. 9
WARNING: The parallel combination of the all the Rph
resistors must be greater than 30kΩ to ensure that the
current sense amplifier does not saturate.
The best choice for a core geometry is a closed-loop
type, such as a potentiometer core, a PQ/U/E core, or a
toroid core.
ƒ
ƒ
ƒ
ILIM
VDRPMAX
FAN5182 — Adjustable Output 1-, 2-, or 3-Phase Synchronous Buck Controller
Designing an Inductor
⎡⎛ I
PSF = (1 − D) × ⎢⎜⎜ O
⎢⎝ nSF
⎣
2
⎞
1 ⎛ n × IR
⎟ +
× ⎜⎜
⎟
12
⎠
⎝ nSF
⎞
⎟
⎟
⎠
2⎤
⎥ × RDS(SF)
⎥
⎦
EQ. 14
www.fairchildsemi.com
13
where RDS(MF) is the on resistance of the main MOSFET.
Typically, for main MOSFETs, a low gate charge (CISS)
device is preferred, but low gate charge MOSFETs
usually have higher on resistance. Select a device that
meets total power dissipation around 1.5W for a single
D-PAK MOSFET.
In this example, a FDD6296 is selected as the main
MOSFET (three total; nMF = 3), with a CISS = 1440pF,
and RDS(MF) = 9mΩ (at TJ = 120°C). A FDD8896 is
selected as the synchronous MOSFET (three total; nSF
= 3), with CISS = 2525pF and RDS(SF) = 5.4mΩ (at TJ =
120°C). The synchronous MOSFET CISS is less than
6000pF. Solving for the power dissipation per MOSFET
at IO = 55A and IR = 6.6A yields 1.56W for each
synchronous MOSFET and 1.29W for each main
MOSFET. These numbers comply with the power
dissipation limit of around 1.5W per MOSFET.
WARNING: The RDS of the bottom FET is also used to
measure the current flowing in the phase. This is used
for current balance and for the current-feedback loop.
Using a FET with too low an RDS can result in poor
current balance and too large a ramp resistor calculation
in Equation 18.
Another important consideration for choosing the
synchronous MOSFET is the input and feedback
capacitance. The ratio of feedback to input capacitance
must be small (less than 10% is recommended) to
prevent accidentally turning on the synchronous
MOSFETs when the switch node goes high.
One more item that needs to be considered is the power
dissipation in the driver for each phase. The gate-drive
loss is described in terms of the QG for the MOSFETs
and is given by the following equation:
⎡f
⎤
PDRV = ⎢ SW × (nMF × Q GMF + n SF × Q GSF ) + ICC ⎥ × VCC
⎣2×n
⎦
Also, the time to switch the synchronous MOSFETs off
should not exceed the non-overlap dead time of the
MOSFET driver (40ns typical for the FAN5109). The
output impedance of the driver is approximately 2Ω and
the typical MOSFET input gate resistances are about 1Ω
to 2Ω; therefore, the total gate capacitance should be
less than 6000pF. In the event there are two MOSFETs
in parallel, the input capacitance for each synchronous
MOSFET should be limited to 3000pF.
where:
QGMF is the total gate charge for each main MOSFET,
QGSF is the total gate charge for each synchronous
MOSFET.
ICC × VCC in Equation 17 represents the driver's standby
power dissipation. For the FAN5109, the maximum
dissipation should be less than 400mW. In this example,
with ICC = 5mA, QGMF = 25nC, and QGSF = 50nC; there is
285mW in each driver, which is below the 400mW
dissipation limit. See the Thermal Information table in
the FAN5109 datasheet for details.
The high-side (main) MOSFET power dissipation
consists of two elements: conduction and switching
losses. The switching loss is related to the main
MOSFET’s turn-on and turn-off time and the current and
voltage being switched. Based on the main MOSFET’s
switching speed (rise and fall time that the gate driver
can offer) and MOSFET input capacitance, the following
expression provides the approximate switching loss for
each main MOSFET:
PS(MF) = 2 × fSW ×
VCC × IO
n
× R G × MF × CISS
nMF
n
Ramp Resistor Selection
The ramp resistor (RR) is used for setting the size of the
internal PWM ramp. The value of this resistor is chosen
to provide the best combination of phase-current
balance, stability, and transient response.
EQ. 15
where:
The following expression is used to determine the
optimum value:
nMF is the total number of main MOSFETs;
RG is the total gate resistance (2Ω for the FAN5109 and
about 1Ω for typical logic level N-channel MOSFETs,
total RG = 3Ω);
CISS is the input capacitance of the main MOSFET.
Note that adding more main MOSFETs (nMF) does not
help lower the switching loss for each main MOSFET; it
can only reduce conduction loss. The most efficient way
to reduce switching loss is to use low-gate charge /
capacitance devices.
2
⎞
1 ⎛ n × IR
⎟ +
×⎜
⎟
12 ⎜⎝ nMF
⎠
⎞
⎟
⎟
⎠
© 2005 Fairchild Semiconductor Corporation
FAN5182 Rev. 1.1.1
AR × L
3 × A D × R DS(ON)(SF ) × CR
EQ. 18
RR =
0.2 × 320nH
= 356kΩ
3 × 5 × 2.4mΩ × 5pF
EQ. 19
ƒ
ƒ
ƒ
2⎤
⎥ × RDS(MF )
⎥
⎦
RR =
where:
The conduction loss of the main MOSFET is given by:
⎡⎛ I
PC(MF ) = D × ⎢⎜⎜ O
⎢⎝ nMF
⎣
EQ. 17
FAN5182 — Adjustable Output 1-, 2-, or 3-Phase Synchronous Buck Controller
Knowing the maximum output current and the maximum
allowed power dissipation, determine the required
RDS(ON) for the MOSFET. For example, with D-PAK
MOSFETs operating up to ambient temperature of 50°C,
a safe limit for PSF is around 1W to 1.5W at 120°C
junction temperature. Therefore, in this example, RDS(SF)
(per MOSFET) < 7.5mΩ. This RDS(SF) is typically
measured at junction temperature of about 120°C. In
this example, select a lower-side MOSFET with 4.8mΩ
at 120°C.
AR is the internal ramp amplifier gain,
AD is the current balancing amplifier gain,
RDS(ON)(SF) is the equivalent low-side MOSFET on
resistance,
ƒ
CR is the internal ramp capacitor value.
The closest standard 1% resistor value is 332kΩ.
EQ. 16
www.fairchildsemi.com
14
Internal ramp voltage magnitude can be calculated by:
VR =
A R × (1 − D) × VOUT
RR × CR × fSW
EQ. 20
VR =
0.2 × (1 − 0.15) × 1.8V
= 686mV
357KΩ × 5pF × 250kHz
EQ. 21
The per-phase current limit is determined by:
IPHLIM ≅
The size of the internal ramp can be made larger or
smaller. If it is made larger, stability and transient
response improve, but thermal balance degrades. If the
ramp is made smaller, thermal balance improves, but
transient response and stability degrade. The factor of
three in the denominator of Equation 18 sets a ramp
size with optimal balance for good stability, transient
response, and thermal balance.
ƒ
0.2 is the internal current transfer ratio between
RRAMPADJ and the PWM ramp current source(s)
ƒ
ƒ
ƒ
ƒ
ƒ
VIN is the input voltage (12V)
ƒ
EQ. 24
The power stage of the synchronous buck converter
consists of two poles and one zero. A two-pole, onezero compensator of the voltage error amplifier is
adequate for proper compensation if the output bulk
capacitors are electrolytic types (low ESR zero).
Equations 25-27 are able to yield an approximate
starting point for the design. To further optimize the
design, some bench adjustments may be necessary.
where:
RRAMP is the ramp resistor connected between VIN
and FAN5182 RAMPADJ pin 9
IR
2
Optimum compensation assures the best possible load
regulation and transient response of the regulator. The
target of the compensation design is to achieve
reasonably high control bandwidth with sufficient phase
and gain margin.
EQ. 22
ƒ
+
NOTE: This section does not apply in a voltage-mode
control configuration.
When configured for single-phase voltage-mode control
(SW pin grounded), the ramp resistor is selected to
produce a fixed-ramp voltage. For example, to create a
ramp voltage of 1V, the following equation is used:
0.2 × (Vin − Vref ) × Vout
− 2000
Vin × Fsw × CR × dVr
A D × R DS(MAX )
Closed-Loop Compensation Design
Ramp Resistor Selection for Voltage-Mode
Control
RR =
VCOMP(MAX ) − VR − VBIAS
⎛
⎞
⎜
⎟
C X × RX ⎜
n × RX
⎟
CA =
×
⎜ ⎛ VR
⎟
RB 2
⎞
× RL ⎟ + ( AD × RDS ) ⎟
⎜⎜
V
OUT
⎠
⎝⎝
⎠
RA =
VREF is the internally generated reference (0.8V)
RB 2
VR ⎛ L
AD × RDS
×
×⎜
−
− C X × RX
C X × R X VOUT ⎜⎝ n × R X 2 × f sw × R X
CFB =
VOUT is the output voltage
C is the internal PWM ramp capacitor, 5pF
EQ. 25
1
2 × n × f sw × RA
⎞
⎟⎟
⎠
EQ. 26
EQ. 27
If CX is 6000µF (five 1200µF capacitors in parallel) with
an equivalent ESR of 3mΩ, the equations above give
the following compensation values:
fsw is the switching frequency defined as (Master
Osc / 2) for single- and dual-phase operation and
(Master Osc / 3) for three-phase operation
CA = 1.33nF, RA= 6.05kΩ, CFB = 110pF
dVr is the target peak ramp voltage; 1V is a typical
target voltage.
EQ. 28
Selecting the nearest standard value for each of these
components yields:
Current Limit Set Point
CA = 1.2nF, RA = 6.04kΩ, and CFB = 100pF
The current-limit threshold is set with a 3V source VLIM
across RLIM with a gain of 10.4mV/µA (ALIM).
As mentioned above, this compensation design scheme
is typically good for applications using electrolytic type
capacitors, where the capacitor ESR zero can roughly
cancel one of the power stage poles. However, for all
ceramic capacitor types of applications, since the
capacitor ESR zero can be very high, a three-pole, twozero compensator should be used.
RLIM can be found using:
RLIM =
ALIM × VLIM
VDRPMAX
EQ. 23
WARNING: Be sure to take into account the peak
current ripple current and the increase in inductor DCR
at high temperatures if the inductor is not temperature
compensated.
© 2005 Fairchild Semiconductor Corporation
FAN5182 Rev. 1.1.1
FAN5182 — Adjustable Output 1-, 2-, or 3-Phase Synchronous Buck Controller
If RLIM is greater than 500kΩ, the actual current-limit
threshold may be lower than the intended value. Some
adjustment for RLIM may be needed. Here, ILIM is the
average current limit for the output of the supply. In this
example, using the VDRPMAX value of 110mV from
Equations 7 and 8 and choosing a peak current limit of
110A for ILIM results in RLIM = 284kΩ, for which 287kΩ is
chosen as the nearest 1% value.
WARNING: The ramp resistor should be less than 1MΩ
to ensure that board contaminates don’t affect the ramp.
If the calculated value is greater than 1MΩ, verify that
the RDS of the bottom FET is not too low.
EQ. 29
www.fairchildsemi.com
15
In continuous inductor current mode, the source current
of the high-side MOSFET is approximately a square
wave with a duty ratio equal to D × VOUT/VIN and an
amplitude equal to the output current. To prevent large
voltage variation, a low-ESR input capacitor, sized for
the maximum rms current, must be used. The maximum
rms capacitor current is given by:
ICRMS = D × IO ×
1
−1
n×D
EQ. 30
1
− 1 = 9.1A
3 × 0.15
ICRMS = 0.15 × 55 A ×
Figure 11. Temperature Compensation Circuit
EQ. 31
Follow the procedures and expressions shown below for
calculation of RCS1, RCS2, and RTH (the thermistor value
at 25°C) based on a given RCS value.
Note that manufacturers often specify capacitor ripple
current rating based on only 2,000 hours of life.
Therefore, it is advisable to further derate the capacitor
or to choose a capacitor rated at a higher temperature
than required. Several capacitors may be placed in
parallel to meet size or height requirements in the
design. In this example, the input capacitor bank is
formed by two 2,700µF, 16V aluminum electrolytic
capacitors and three 4.7µF ceramic capacitors.
1. Select an NTC according to type and value. With no
value yet, start with a thermistor with a value close to
RCS. The NTC should also have an initial tolerance of
better than 5%.
2. Based on the NTC type, find its relative resistance
value at two temperatures. The temperatures that
work well are 50°C and 90°C. These resistance
values are called A (RTH(50°C)/RTH(25°C)) and
B(RTH(90°C)/RTH(25°C)). Note that the NTC's
relative value is always 1 at 25°C.
To reduce the input current di/dt to a level below the
system requirement, in this example 0.1A/µs, an
additional small inductor (L > 370nH at 10A) can be
inserted between the converter and the supply bus. This
inductor serves as a filter between the converter and the
primary power source.
3. Find the relative value of RCS required for each of
these temperatures. This is based on the percentage
of change needed, which, in this example, is initially
0.39%/°C. These are called r1 (1/ (1 + TC × (T1 25))) and r2 (1/ (1 + TC × (T2 - 25))), where TC =
0.0039 for copper. T1 = 50°C and T2 = 90°C are
chosen. From this, calculate that r1 = 0.9112 and r2
= 0.7978.
WARNING: During start-up with a pre-charged output
capacitor the capacitor, is discharged prior to the
converter starting. The energy that was stored in the
output capacitor is transferred to the input voltage
through the upper FET. This can cause a momentary
increase in VIN that could exceed the VIN maximum
specification for the controller or driver if there is
insufficient capacitance on VIN.
4. Compute the relative values for RCS1, RCS2, and RTH
using Equations 33, 34, and 35.
COUT⋅
VO
2
EQ. 33
(1 − A )
⎛
⎞ ⎛
⎞
1
A
⎜
⎟−⎜
⎟
⎜ 1− r
⎟ ⎜r −r
⎟
CS
2
1
CS
2
⎝
⎠ ⎝
⎠
1
=
⎛
⎞ ⎛
⎞
1
1
⎜
⎟−⎜
⎟
⎜ 1− r
⎟ ⎜r −r
⎟
CS2 ⎠ ⎝ 1
CS1 ⎠
⎝
rCS1 =
6
CIN
( A − B) × r1 × r2 − A × (1 − B) × r2 + B × (1 − A ) × r1
A × (1 − B) × r1 − B × (1 − A ) × r2 − ( A − B)
rCS2 =
To ensure that this does not happen, use the following
equation to calculate a minimum value of CIN:
2
VIN Max − VIN Norm
EQ. 32
rTH
Inductor DCR Temperature Correction
EQ. 34
EQ. 35
With the inductor's DCR being used as the sense
element, its necessary to compensate for temperature
changes in the inductor's winding if an accurate currentlimit set point is desired. Fortunately, copper has a wellknown temperature coefficient (TC) of 0.39%/°C.
5. Calculate RTH = rTH x RCS, then select the closest
thermistor value available. Also, compute a scaling
factor k based on the ratio of the actual thermistor
value used relative to the computed one:
If RCS is designed to have an opposite and equal
percentage of change in resistance to that of the
inductor wire, it cancels the temperature variation of the
inductor's DCR. Due to the nonlinear nature of NTC
thermistors, resistors RCS1 and RCS2 are needed. See
Figure 11 for instructions on how to linearize the NTC
and produce the desired temperature coefficient.
k=
© 2005 Fairchild Semiconductor Corporation
FAN5182 Rev. 1.1.1
FAN5182 — Adjustable Output 1-, 2-, or 3-Phase Synchronous Buck Controller
Input Capacitor Selection and Input
Current di/dt Reduction
R TH( ACTUAL )
EQ. 36
R TH( CALCULATED )
6. Calculate values for RCS1 and RCS2 using:
R CS1 = R CS × k × rCS1
EQ. 37
R CS 2 = R CS × ((1 − k ) + (k × rCS 2 ))
EQ. 38
www.fairchildsemi.com
16
to minimize the inductance in the MOSFET half bridge.
Failure to do so can lead to severe phase node ringing.
A snubber circuit is always recommended to partly kill
the phase node switching noise.
General Recommendations
To achieve the best performance, a PCB with at least four
layers is recommended. When designing the layout, keep
in mind that each square unit of 1-ounce copper has
resistance of ~0.53mΩ at room temperature.
Whenever using a power dissipating component; for
example, a power MOSFET that is soldered to the PCB;
the proper use of vias, both directly on the mounting pad
and immediately surrounding the mounting pad is
recommended. Make a mirror image of the power pad
being used on the component side to heat sink the
MOSFETs on the opposite side of the PCB. Use large
copper pour for high-current traces to lower the electrical
impedance and help dissipate heat. Do not make the
switching node copper pour unnecessarily large, since it
could radiate noise.
Whenever high currents must be routed to a different
PCB layers, vias should be used properly to create
several parallel current paths so the resistance and
inductance introduced by these current paths are
minimized and via current rating is not exceeded.
If critical signal traces must be routed close to power
circuitry, a signal ground plane must be interposed
between those signal lines and the traces of the power
circuitry. This serves as a shield to minimize noise
injection into the signals at the expense of making signal
ground a bit noisier.
An undisturbed solid power ground plane should be
used as one of the inner layers.
An analog ground island should be used around and
under the FAN5182 as a reference for the components
associated with the controller. The analog ground should
be connected to the power ground at a single point.
Signal Circuitry Recommendations
The output voltage is sensed from the FB and the
FBRTN pins. To avoid differential mode noise pickup in
these differential sensed traces, the loop area between
the FB and FBRTN traces should be minimized. In other
words, the FB and FBRTN traces should be routed
adjacent to each other with minimum spacing on top of
the analog / power ground plane back to the controller.
The components around the FAN5182 should be close
to the controller with short traces. The output capacitors
should be placed as close as possible to the load. If the
load is distributed, the capacitors should also be
distributed in proportion to the respective load.
The signal traces connecting to the switch nodes should
be tied as close as possible to the inductor pins. The
CSREF sense trace should be connected to the second
nearest inductor pin to the controller.
Power Circuitry Recommendations
The PCB layout starts with high-frequency power
component placement. Try to minimize stray inductance
of the MOSFET half bridge, which is composed of the
input capacitors and top and bottom MOSFETs. A good
practice is to use short and wide traces or copper pours
© 2005 Fairchild Semiconductor Corporation
FAN5182 Rev. 1.1.1
Detailed step-by-step PCB layout instructions are
available from Fairchild upon request.
FAN5182 — Adjustable Output 1-, 2-, or 3-Phase Synchronous Buck Controller
PCB Layout Guidelines
www.fairchildsemi.com
17
Dimensions are in millimeters (inches) unless otherwise noted.
FAN5182 — Adjustable Output 1-, 2-, or 3-Phase Synchronous Buck Controller
Physical Dimensions
Figure 12. 20-Pin Quarter-Size Outline Package (QSOP)
© 2005 Fairchild Semiconductor Corporation
FAN5182 Rev. 1.1.1
www.fairchildsemi.com
18
®
ACEx
Across the board. Around the world.™
ActiveArray™
Bottomless™
Build it Now™
CoolFET™
CROSSVOLT™
CTL™
Current Transfer Logic™
DOME™
2
E CMOS™
®
EcoSPARK
EnSigna™
FACT Quiet Series™
®
FACT
®
FAST
FASTr™
FPS™
®
FRFET
GlobalOptoisolator™
GTO™
Programmable Active Droop™
®
QFET
QS™
QT Optoelectronics™
Quiet Series™
RapidConfigure™
RapidConnect™
ScalarPump™
SMART START™
®
SPM
STEALTH™
SuperFET™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TCM™
®
The Power Franchise
HiSeC™
i-Lo™
ImpliedDisconnect™
IntelliMAX™
ISOPLANAR™
MICROCOUPLER™
MicroPak™
MICROWIRE™
MSX™
MSXPro™
OCX™
OCXPro™
®
OPTOLOGIC
®
OPTOPLANAR
PACMAN™
POP™
®
Power220
®
Power247
PowerEdge™
PowerSaver™
®
PowerTrench
®
TinyLogic
TINYOPTO™
TinyPower™
TinyWire™
TruTranslation™
μSerDes™
®
UHC
UniFET™
VCX™
Wire™
™
TinyBoost™
TinyBuck™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER
ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
2. A critical component in any component of a life support,
device, or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
FAN5182 — Adjustable Output 1-, 2-, or 3-Phase Synchronous Buck Controller
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an
exhaustive list of all such trademarks.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or In Design
This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
design.
Obsolete
Not In Production
This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I24
© 2005 Fairchild Semiconductor Corporation
FAN5182 Rev. 1.1.1
www.fairchildsemi.com
19
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