TOSHIBA Original CMOS 16-Bit Microcontroller TLCS-900/L1 Series TMP91C025FG Semiconductor Company Preface Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, “Points of Note and Restrictions”. Especially, take care below cautions. **CAUTION** How to release the HALT mode Usually, interrupts can release all halts status. However, the interrupts = (INT0 to INT3, INTRTC, INTALM0 to INTALM4, INTKEY), which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 5 clocks of fFPH) with IDLE1 or STOP mode (IDLE2 is not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficultly. The priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt. TMP91C025 CMOS 16-Bit Microcontrollers TMP91C025FG/JTMP91C025-S 1. Outline and Features TMP91C025 is a high-speed 16-bit microcontroller designed for the control of various mid- to large-scale equipment. TMP91C025FG comes in a 100-pin flat package. JTMP91C025-S comes in a 100-pad chip. Listed below are the features. (1) High-speed 16-bit CPU (900/L1 CPU) • Instruction mnemonics are upward-compatible with TLCS-90 • 16 Mbytes of linear address space • General-purpose registers and register banks • 16-bit multiplication and division instructions; bit transfer and arithmetic instructions • Micro DMA: 4 channels (444 ns/ 2 bytes at 36 MHz) (2) Minimum instruction execution time: 111 ns (at 36 MHz) RESTRICTIONS ON PRODUCT USE 070208EBP • The information contained herein is subject to change without notice. 021023_D • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. 021023_A • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. 021023_B • The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. 021023_C • The products described in this document are subject to foreign exchange and foreign trade control laws. 060925_E • For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S 91C025-1 2007-02-28 TMP91C025 (3) Built-in RAM: None Built-in ROM: None (4) External memory expansion • Expandable up to 104 Mbytes (Shared program/data area) • Can simultaneously support 8-/16-bit width external data bus ... Dynamic data bus sizing • Separate bus system (5) 8-bit timers: 4 channels (6) General-purpose serial interface: 2 channels • UART/Synchronous mode: 2 channels • IrDA Ver.1.0 (115.2 kbps) mode selectable: 1 channel (7) LCD controller • Adapt to both shift register type and built-in RAM type LCD driver (8) Timer for real-time clock (RTC) • Based on TC8521A (9) Key-on wakeup (Interrupt key input) (10) 10-bit AD converter: 4 channels (11) Touch screen interface • Available to reduce external components (12) Watchdog timer (13) Melody/alarm generator • Melody: Output of clock 4 to 5461 Hz • Alarm: Output of the 8 kinds of alarm pattern • Output of the 5 kinds of interval interrupt (14) Chip select/wait controller: 4 channels (15) MMU • Expandable up to 104 Mbytes (16) Interrupts: 37 interrupt • 9 CPU interrupts: Software interrupt instruction and illegal instruction • 23 internal interrupts: 7 priority levels are selectable • 5 external interrupts: 7 priority levels are selectable (among 4 interrupts are selectable edge mode) (17) Input/output ports: 49 pins (Except Data bus (8bit), Address bus (24bit) and RD pin) (18) Standby function Three HALT modes: IDLE2 (Programmable), IDLE1 and STOP (19) Hardware standby function (Power save function) 91C025-2 2007-02-28 TMP91C025 (20) Triple-clock controller • Clock doubler (DFM) circuit is inside • Clock gear function: Select a high-frequency clock fc/1 to fc/16 • SLOW mode (fs = 32.768 kHz) (21) Operating voltage • VCC = 3.0 V to 3.6 V (fc max = 36 MHz) • VCC = 2.7 V to 3.6 V (fc max = 27 MHz) • VCC = 2.4 V to 3.6 V (fc max = 16 MHz) (22) Package • 100-pin QFP: P-LQFP100-1414-0.50F, chip form supply also available. For details, contact your local Toshiba sales representative. 91C025-3 2007-02-28 TMP91C025 DVCC [2] DVSS [2] AN2/MX (P82) AN3/MY/ ADTRG (P83) AN0, AN1 (P80, P81) AVCC, AVSS VREFH, VREFL TXD0 (PC0) RXD0 (PC1) SCLK0/ CTS0 (PC2) TXD1 (PC3) RXD1 (PC4) SCLK1/ CTS1 (PC5) PX/INT2 (PB5) PY/INT3 (PB6) CPU (TLCS-900/L1) 10-bit 4-channel AD converter SIO/UART/IrDA (SIO0) SIO/UART (SIO1) Touch screen I/F (TSI) TA0IN/INT1 (PB4) 8-bit timer (TMRA0) TA1OUT/KO1 (PA1) 8-bit timer (TMRA1) XWA XBC XDE XHL XIX XIY XIZ XSP W A B C D E H L IX IY IZ SP Clock gear, Clock doubler L-OSC EMU0 EMU1 XT1 XT2 RESET PC WDT (Watchdog timer) X1 X2 AM0 AM1 D0 to D7 A0 to A7 A8 to A15 32 bits SR F Port 1 P10 to P17 (D8 to D15) Port 2 P20 to P27 (A16 to A23) RD WR Port 5 8-bit timer (TMRA2) TA3OUT/KO2 (PA2) H-OSC Port Z 8-bit timer (TMRA3) HWR (PZ2) WAIT (P56) R/ W / SRWR (PZ3) Port 6 CS/WAIT controller (4 blocks) CS0 to CS3 , CS2A (P60 to P63) EA24/ CS2B / SRLB (P64) Port 8 MMU EA25/ CS2C / SRUB (P65) Port 9 Interrupt controller Port A Port B Keyboard I/F Port C Port D Melody/ alarm out D1BSCP (PD0) D2BLP (PD1) D3BFR (PD2) INT0 ( PS ) INT0 to INT3 (PB3 to PB6) KI0 to KI7 (P90 to P97) KO0/ ALARM / MLDALM (PA0) KO1/TA1OUT (PA1) KO2/TA3OUT (PA2) KO3 (PA3) MLDALM (PD7) LCD controller RTC DLEBCD (PD3) ALARM / MLDALM /KO0 (PA0) DOFFB (PD4) ( ): Initial function after reset Figure 1.1 TMP91C025 Block Diagram 91C025-4 2007-02-28 TMP91C025 2. Pin Assignment and Pin Functions The assignment of input/output pins for the TMP91C025, their names and functions are as follows: 2.1 Pin Assignment Diagram 80 85 90 100 5 70 10 TMP91C025FG 65 QFP100 Top view 15 60 20 55 A11 A12 A13 A14 A15 P20/A16 P21/A17 P22/A18 P23/A19 P24/A20 P25/A21 DVCC2 PB4/INT1/TA0IN DVSS2 P26/A22 P27/A23 P17/D15 P16/D14 P15/D13 P14/D12 P13/D11 P12/D10 P11/D9 P10/D8 D7 50 45 40 25 35 PA0/KO0/ ALARM / MLDALM PA1/KO1/TA1OUT PA2/KO2/TA3OUT PA3/KO3/SCOUT PC0/TXD0 PC1/RXD1 AM0 DVCC1 75 30 P83/AN3/ ADTRG /MY PB5/PX/INT2 PB6/PY/INT3 P90/KI0 P91/KI1 P92/KI2 P93/KI3 P94/KI4 P95/KI5 P96/KI6 P97/KI7 1 X2 DVSS1 X1 AM1 RESET XT1 XT2 EMU0 EMU1 PC2/SCLK0/CTS0 PC3/TXD1 PC4/RXD1 PC5/SCLK1/CTS1 PD0/D1BSCP PD1/D2BLP PD2/D3BFR PD3/DLEBCD PD4/DOFFB D0 D1 D2 D3 D4 D5 D6 VREFL AVSS AVCC P80/AN0 P81/AN1 P82/AN2/MX 95 VREFH PB3/INT0/PS PD7/MLDALM P65/EA25/CS2C/SRUB P64/EA24/CS2B/SRLB P63/CS3 P62/CS2/CS2A P61/CS1 P60/CS0 P56/WAIT PZ3/R/W/SRWR PZ2/HWR WR RD A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 Figure 2.1.1 shows the pin assignment of the TMP91C025FG. Figure 2.1.1 Pin Assignment Diagram (100-pin QFP) 91C025-5 2007-02-28 TMP91C025 2.2 PAD Layout (Chip size 4.58 mm × 4.63 mm) Unit (μm) Pin No. Name X Point Y Point Pin No. Name X Point Y Point Pin No. Name X Point 1 VREFL −2151 1627 44 D0 852 −2175 2 AVSS −2151 1502 45 D1 977 −2175 3 AVCC −2151 1376 46 D2 1103 4 P80 −2151 1251 47 D3 5 P81 −2151 1126 48 D4 6 P82 −2151 1001 49 7 P83 −2151 876 8 PB5 −2151 751 Y Point 87 RD 210 2175 88 WR 83 2175 −2175 89 PZ2 −42 2175 1228 −2175 90 PZ3 −169 2175 1353 −2175 91 P56 −296 2175 D5 1478 −2175 92 P60 −421 2175 50 D6 1603 −2175 93 P61 −548 2175 51 D7 2151 −1636 94 P62 −674 2175 9 PB6 −2151 625 52 P10 2151 −1490 95 P63 −801 2175 10 P90 −2151 336 53 P11 2151 −1359 96 P64 −926 2175 11 P91 −2151 211 54 P12 2151 −1228 97 P65 −1051 2175 12 P92 −2151 86 55 P13 2151 −1096 98 PD7 −1177 2175 13 P93 −2151 −38 56 P14 2151 −965 99 PB3 −1302 2175 14 P94 −2151 −163 57 P15 2151 −834 100 VREFH −1606 2175 15 P95 −2151 −289 58 P16 2151 −703 16 P96 −2151 −414 59 P17 2151 −571 17 P97 −2151 −539 60 P27 2151 −440 18 PA0 −2151 −664 61 P26 2151 −309 19 PA1 −2151 −789 62 DVSS2 2151 −153 20 PA2 −2151 −914 63 PB4 2151 2 21 PA3 −2151 −1040 64 DVCC2 2151 158 22 PC0 −2151 −1165 65 P25 2151 315 23 PC1 −2151 −1290 66 P24 2151 446 24 AM0 −2151 −1415 67 P23 2151 577 25 DVCC1 −2151 −1636 68 P22 2151 708 26 X2 −1603 −2175 69 P21 2151 839 27 DVSS1 −1438 −2175 70 P20 2151 971 28 X1 −1273 −2175 71 A15 2151 1102 29 AM1 −1147 −2175 72 A14 2151 1233 30 RESET −1022 −2175 73 A13 2151 1364 31 XT1 −897 −2175 74 A12 2151 1495 32 XT2 −649 −2175 75 A11 2151 1627 33 EMU0 −524 −2175 76 A10 1603 2175 34 EMU1 −398 −2175 77 A9 1477 2175 35 PC2 −273 −2175 78 A8 1350 2175 36 PC3 −148 −2175 79 A7 1224 2175 37 PC4 −23 −2175 80 A6 1097 2175 38 PC5 101 −2175 81 A5 970 2175 39 PD0 226 −2175 82 A4 844 2175 40 PD1 352 −2175 83 A3 717 2175 41 PD2 477 −2175 84 A2 590 2175 42 PD3 602 −2175 85 A1 464 2175 43 PD4 727 −2175 86 A0 337 2175 91C025-6 2007-02-28 TMP91C025 2.3 Pin Names and Functions The names of the input/output pins and their functions are described below. Table 2.3.1 Pin Names and Functions (1/3) Pin Name Number of Pins I/O Functions D0 to D7 8 I/O Data (lower): bits 0 to 7 of data bus P10 to P17 8 I/O Port 1: I/O port that allows I/O to be selected at the bit level (When used to the external 8bit bus) D8 to D15 P20 to P27 I/O 8 A16 to A23 Data (upper): Bits 8 to15 of data bus Output Port 2: Output port Output Address: Bits 16 to 23 of address bus A8 to A15 8 Output Address: Bits 8 to 15 of address bus A0 to A7 8 Output Address: Bits 0 to 7 of address bus RD 1 Output Read: Strobe signal for reading external memory WR 1 Output PZ2 1 I/O Output HWR PZ3 R/ W 1 SRWR P56 1 1 CS0 P61 1 CS1 High Write: Strobe signal for writing data to pins D8 to D15 Port Z3: I/O port (with pull-up resistor) Output Read/Write: 1 represents read or dummy cycle; 0 represents write cycle. Output Write: Strobe signal for writing data to pins D0 to D15 for SRAM I/O Input WAIT P60 I/O Write: Strobe signal for writing data to pins D0 to D7 Port Z2: I/O port (with pull-up resistor) Port 56: I/O port (with pull-up resistor) Wait: Pin used to request CPU bus wait Output Port 60:Output port Output Chip select 0: Outputs 0 when address is within specified address area. Output Port 61:Output port Output Chip select 1: Outputs 0 when address is within specified address area Output Port 62: Output port CS2 Output Chip select 2: Outputs 0 when address is within specified address area CS2A Output Expand chip select: 2A: Outputs 0 when address is within specified address P62 1 area P63 1 Output Port 63:Output port Output Chip select 3: Outputs 0 when address is within specified address area Output Port 64: Output port EA24 Output Chip select 24: Outputs 0 when address is within specified address area CS2B Output Expand chip select: 2B: Outputs 0 when address is within specified address SRLB Output Low byte enable for SRAM CS3 P64 1 area Output Port 65: Output port EA25 Output Chip select 25: Outputs 0 when address is within specified address area CS2C Output Expand chip select: 2C: Outputs 0 when address is within specified address SRUB Output P65 1 area High byte enable for SRAM 91C025-7 2007-02-28 TMP91C025 Table 2.3.2 Pin Names and Functions (2/3) Number of Pins I/O 2 Input Port 80 to 81 port: Pin used to input ports Input Analog input 0 to 1: Pin used to input to AD converter Input Port 82 port: Pin used to input ports AN2 Input Analog input 2: Pin used to input to AD converter MX Input X-Minus: Pin connected to X- for touch screen panel Pin Name P80 to P81 AN0 to AN1 P82 P83 1 Input Port 83 port: Pin used to input ports AN3 Input Analog input 3: Pin used to input to AD converter ADTRG Input AD trigger: Signal used to request AD start MY Input Y-Minus: Pin connected to Y- for touch screen panel Input Port: 90 to 97 port: Pin used to input ports Input Key input 0 to 7: Pin used of key-on wakeup 0 to 7 P90 to P97 1 Functions 8 KI0 to KI7 (Schmitt input, with pull-up resistor) Output Port: A0 port: Pin used to output ports KO0 Output Key output 0: Pin used of key-scan strobe 0 ALARM Output RTC alarm output pin MLDALM Output Melody/alarm output pin (Inverted) Output Port: A1 port: Pin used to output ports KO1 Output Key output 1: Pin used of key-scan strobe 1 TA1OUT Output 8-bit timer 1 output: Timer 0 input or timer 1 output PA0 PA1 PA2 1 1 Output Port: A2 port: Pin used to output ports KO2 Output Key output 2: Pin used of key-scan strobe 2 TA3OUT Output 8-bit timer 3 output: Timer 2 input or timer 3 output Output Port: A3 port: Pin used to output ports KO3 Output Key output 3: Pin used of key-scan strobe 3 SCOUT Output System clock output: Output fFPH clock PA3 PB3 1 1 1 I/O INT0 Input PS Input PB4 1 I/O Port B3: I/O port Interrupt request pin0: Interrupt request with programmable level/rising edge Power save: Pin used as input pin for H/W standby mode Port B4: I/O port INT1 Input Interrupt request pin1: Interrupt request with programmable rising/falling edge TA0IN Input 8-bit timer 0 input: Timer 0 input Input Port B5: Input port Input Interrupt request pin2: Interrupt request with programmable rising/falling edge PB5 1 INT2 PX PB6 Output 1 INT3 PY PC0 TXD0 PC1 RXD0 Port B6: Input port Input Interrupt request pin3: Interrupt request with programmable rising/falling edge Output 1 I/O Output 1 X-Plus: Pin connected to X+ for touch screen panel Input I/O Output Y-Plus: Pin connected to Y+ for touch screen panel Port C0: I/O port Serial 0 send data: Open-drain output pin by programmable Port C1: I/O port Serial 0 receive data Note: After reset, input “1” to PB3 (INT0, PS )-pin, because it is worked as PS input pin. 91C025-8 2007-02-28 TMP91C025 Table 2.3.3 Pin Names and Functions. (3/3) Pin Name PC2 Number of Pins I/O 1 Functions I/O Port C2: I/O port (with pull-up resistor) SCLK0 I/O Serial clock I/O 0 CTS0 Input PC3 1 TXD1 I/O Output Serial data send enable 0 (Clear to send) Port C3: I/O port Serial send data 1 Open-drain output pin by programmable PC4 1 RXD1 PC5 I/O Input 1 SCLK1 CTS1 Port C4: I/O port Serial receive data 1 I/O Port C5: I/O port (with pull-up resistor) I/O Serial clock I/O 1 Input Serial data send enable 1 (Clear to send) Low-frequency oscillator connecting pin XT1 1 Input XT2 1 Output Low-frequency oscillator connecting pin PD0 1 Output Port D0: Output port Output LCD controller output pin 1 Output Port D1: Output port Output LCD controller output pin Output Port D2: Output port Output LCD controller output pin Output Port D3: Output port Output LCD controller output pin Output Port D4: Output port Output LCD controller output pin Output Port D7: Output port D1BSCP PD1 D2BLP PD2 1 D3BFR PD3 1 DLEBCD PD4 1 DOFFB PD7 1 MLDALM AM0 to AM1 Output 2 Input Melody/alarm output pin Operation mode: Fixed to AM1 = 0, AM0 = 1 16-bit external bus or 8-/16-bit dynamic sizing. Fixed to AM1 = 0, AM0 = 0 8-bit external bus fixed. EMU0 1 Output Open pin EMU1 1 Output Open pin RESET 1 Input VREFH 1 Input Pin for reference voltage input to AD converter (H) VREFL 1 Input Pin for reference voltage input to AD converter (L) AVCC 1 AVSS 1 X1, X2 2 DVCC 2 Power supply pins DVSS 2 GND pins (0 V) (All pins should be connected with GND (0 V).) Reset: initializes TMP91C025. (with pull-up resistor) Power supply pin for AD converter GND pin for AD converter (0 V) I/O High-frequency oscillator connection pins (All VCC pins should be connected with the power supply pin.) 91C025-9 2007-02-28 TMP91C025 3. Operation This following describes block by block the functions and operation of the TMP91C025. Notes and restrictions for eatch book are outlined in 6, precautions and restrictions at the end of this manual. 3.1 CPU The TMP91C025 incorporates a high-performance 16-bit CPU (the 900/L1-CPU). For CPU operation, see the TLCS-900/L1 CPU. The following describe the unique function of the CPU used in the TMP91C025; these functions are not covered in the TLCS-900/L1 CPU section. 3.1.1 Reset When resetting the TMP91C025 microcontroller, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input to low level at least for 10 system clocks (9 μs at 36 MHz). Thus, when turn on the switch, be set to the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input to low level at least for 10 system clocks. Clock gear is initialized 1/16 mode by reset operation. It means that the system clock mode fSYS is set to fc/32(= fc/16 × 1/2). When the reset is accept, the CPU: • Sets as follows the program counter (PC) in accordance with the reset vector stored at address FFFF00H to FFFF02H: PC<0:7> ← Value at FFFF00H address PC<15:8> ← Value at FFFF01H address PC<23:16> ← Value at FFFF02H address • Sets the stack pointer (XSP) to 100H. • Sets bits <IFF2:0> of the status register (SR) to 111 (Sets the interrupt level mask register to level 7). • Sets the <MAX> bit of the status register (SR) to 1 (MAX mode). Note: As this product does not support MIN mode, do not write a 0 to the <MAX> • Clears bits <RFP2:0> of the status register(SR) to 000 (Sets the register bank to 0 ). When reset is released,the CPU starts executing instructions in accordance with the program counter settings. CPU internal registers not mentioned above do not change when the reset is released. When the reset is accepted, the CPU sets internal I/O, ports, and other pins as follows. • Initializes the internal I/O registers. • Sets the port pins, including the pins that also act as internal I/O, to general-purpose input or output port mode. Note: The CPU internal register (Except to PC, SR, XSP) do not change by resetting. Figure 3.1.1 is a reset timing chart of the TMP91C025. 91C025-10 2007-02-28 91C025-11 XT1, XT2 HWR Pull-up (Internal) High-Z Data-out Data-in Sampling (PZ2 input mode) Sampling Data-in (After reset released, starting 2 wait read cycle) 0FFFF00H Read WR D0 to D15 RD D0 to D15 CS2 CS0, CS1, CS3 A23 to A0 RESET fFPH TMP91C025 Write Figure 3.1.1 Reset Timing Chart 2007-02-28 TMP91C025 3.2 Memory Map Figure 3.2.1 is a memory map of the TMP91C025. 000000H Internal I/O (4 Kbytes) Direct area (n) 000100H 000FE0H 001000H (Note) 64-Kbyte area (nn) 010000H External memory 16-Mbyte area (R) (−R) (R+) (R + R8/16) (R + d8/16) (nnn) FFFF00H FFFFFFH Vector table (256 bytes) ( = Internal area) Figure 3.2.1 Memory Map Note: Address 000FE0H to 000FEFH is assigned for the external memory area of built-in RAM type LCD driver. Address 000FF0H to 000FFFH is assingned for the external memory area as reserved. 91C025-12 2007-02-28 TMP91C025 3.3 Triple Clock Function and Standby Function TMP91C025 contains a clock gear, clock doubler (DFM), standby controller and noise-reduction circuit. It is used for low-power and low-noise systems. This chapter is organized as follows: 3.3.1 Block Diagram of System Clock 3.3.2 SFRs 3.3.3 System Clock Controller 3.3.4 Prescaler Clock Controller 3.3.5 Clock Doubler (DFM) 3.3.6 Noise reducing Circuit 3.3.7 Standby Controller 91C025-13 2007-02-28 TMP91C025 The clock operating modes are as follows: (a) Single clock mode (X1, X2 pins only), (b) Dual clock mode (X1, X2, XT1 and XT2 pins) and (c) Triple clock mode (the X1, X2, XT1 and XT2 pins and DFM). Figure 3.3.1 shows a transition figure. Reset (fOSCH/32) Release reset Instruction IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) Interrupt Instruction Interrupt (a) NORMAL mode (fOSCH/Gear value/2) Instruction Interrupt STOP mode (Stops all circuits) Single clock mode transition figure Reset (fOSCH/32) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) Instruction Interrupt Instruction Interrupt Release reset NORMAL mode (fOSCH/Gear value/2) Instruction Interrupt Instruction IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) Interrupt Instruction Interrupt (b) STOP mode (Stops all circuits) SLOW mode (fs/2) Dual clock mode transition figure Reset (fOSCH/32) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) Instruction Interrupt Instruction Interrupt Release reset NORMAL mode (fOSCH/Gear value/2) STOP mode (Stops all circuits) Instruction (Note) IDLE2 mode (I/O operate) Instruction Instruction Interrupt IDLE1 mode Instruction (Operate oscillator and DFM) Interrupt NORMAL mode (4 × fOSCH/gear value/2) Instruction (Note) Instruction Interrupt Instruction Instruction Interrupt Using DFM (c) Interrupt SLOW mode (fs/2) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) Triple clock mode trasision figure Note 1: It’s prohibited to control DFM in SLOW mode when shifting from SLOW mode to NORMAL mode with use of DFM. （DFM start up/stop/change write to DFMCR0<ACT1:0> register） Note 2: If you shift from NORMAL mode with use of DFM to NORMAL mode, the instruction should be separated into two procedures as below. Change CPU clock → Stop DFM circuit Note 3: It’s prohibited to shift from NORMAL mode with use of DFM to STOP mode directly. You should set NORMAL mode once, and then shift to STOP mode.(You should stop high frequency oscillator after you stop DFM.) Figure 3.3.1 System Clock Block Diagram The clock frequency input from the X1 and X2 pins is called fc and the clock frequency input from the XT1 and XT2 pins is called fs. The clock frequency selected by SYSCR1<SYSCK> is called the system clock fFPH. The system clock fSYS is defined as the divided clock of fFPH, and one cycle of fSYS is defined to as one state. 91C025-14 2007-02-28 TMP91C025 3.3.1 Block Diagram of System Clock SYSCR0<WUEF> SYSCR2<WUPTM1:0> DFMCR0<ACT1:0, DLUPTM> SYSCR0 <PRCK1:0> Warm-up timer (High/low frequency oscillator), Lock up timer (DFM) φT0 fc/16 fFPH SYSCR0 <XTEN, RXTEN> XT1 XT2 Low-frequency oscillator X2 ÷2 ÷4 fs fs ÷2 fc fc/4 fc/8 Selector Clock Doubler (DFM) SYSCR1<SYSCK> fc/16 ÷2 High-frequency oscillator fOSCH fSYS fc/2 fDFM = fOSCH × 4 SYSCR0 <XEN, RXEN> X1 φT ÷4 ÷8 ÷16 SYSCR1<GEAR2:0> Clock gear DFMCR0<ACT1:0> fSYS CPU TMRA0 to TMRA3 φT0 Interrupt controller Prescaler ADC SIO0 to SIO1 WDT Prescaler I/O ports C/S WAIT controller TSI RTC fs LCDC MLD/ALM Figure 3.3.2 Block Diagram of System Clock 91C025-15 2007-02-28 TMP91C025 3.3.2 SYSCR0 (00E0H) SFRs Bit symbol 7 6 5 4 XEN XTEN RXEN RXTEN Read/Write 2 1 0 RSYSCK WUEF PRCK1 PRCK0 0 0 R/W After reset Function 3 1 1 1 0 0 0 Select prescaler clock High- Low- High- Low- Selects Warm-up frequency frequency frequency frequency clock after timer 00: fFPH 0: Write 01: Reserved oscillator (fc) oscillator (fs) oscillator (fc) oscillator (fs) release of 0: Stop 0: Stop Don’t care 10: fc/16 after release after release STOP mode 1: Oscillation 1: Oscillation of STOP (Note 1) mode of STOP 0: fc mode 1: fs 1: Write 0: Read 0: Stop 0: Stop 11: Reserved start timer end 1: Oscillation 1: Oscillation warm-up 1:Read do not end warm-up 7 SYSCR1 (00E1H) 6 5 4 Bit symbol 3 2 1 0 SYSCK GEAR2 GEAR1 GEAR0 0 1 0 0 Read/Write R/W After reset Function Select Select gear value of high-frequency (fc) system 000: fc clock 001: fc/2 0: fc 010: fc/4 1: fs 011: fc/8 100: fc/16 101: (Reserved) 110: (Reserved) 111: (Reserved) 7 SYSCR2 (00E2H) 6 5 4 3 2 1 0 Bit symbol PSENV WUPTM1 WUPTM0 HALTM1 HALTM0 SELDRV DRVE Read/Write R/W R/W R/W R/W R/W R/W R/W After reset 0 1 0 1 1 0 Function 0 Warm-up timer HALT mode <DRVE> Pin state save 00: Reserved 00: Reserved mode control in mode 01: 28/inputted frequency 01: STOP mode select STOP/IDLE1 enable 10: 214 10: IDLE1 mode 0: IDLE1 mode 11: 216 11: IDLE2 mode 1: STOP 0: I/O off 0: Power 1: Disable (Note 3) 1: Remains (Note 2) the state before halt Note 1: By reset, low-frequency oscillator is enabled. Note 2: When hard ware standby mode is entered, the meaning of SYSCR2<HALTM1:0> = 11 shows IDLE1 mode. Note 3: “0” means IDLE1 and “1” means STOP. Please be carefull because this setting is sometimes different from others. Figure 3.3.3 SFRs for System Clock 91C025-16 2007-02-28 TMP91C025 Symbol Name Address DFM DFMCR0 control E8H 7 6 5 4 ACT1 ACT0 DLUPFG DLUPTM R/W R/W R R/W 0 0 0 0 DFM LUP select fFPH Lock up status Flag 00 STOP STOP fOSCH register 0 01 RUN RUN fOSCH 10 RUN STOP fDFM 3 2 1 0 Lock up Time 0: End 0: 212/fOSCH 1: Not end 1: 210/fOSCH 11 RUN STOP fOSCH DFMCR1 DFM control E9H D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 1 0 0 1 1 DFM revision register 1 Input frequency 4 to 9 MHz (at 3.0 V to 3.6 V): write 0BH Input frequency 4 to 6.75 MHz (at 2.7 V to 3.6 V): write 0BH Figure 3.3.4 SFRs for DFM Limitation point on the use of DFM 1. It’s prohibited to execute DFM enable/disable control in the SLOW mode (fs) (write to DFMCR0<ACT1:0> = “10”). You should control DFM in the NORMAL mode. 2. If you stop DFM operation during using DFM(DFMCR0<ACT1:0> = “10”), you shouldn’t execute that change the clock fDFM to fOSCH and stop the DFM at the same time. Therefore the above execution should be separated into two procedures as showing below. LD (DFMCR0), C0H ; Change the clock fDFM to fOSCH LD (DFMCR0), 00H ; DFM stop 3. If you stop high-frequency oscillator during using DFM (DFMCR0<ACT1:0> = “10”), you should stop DFM before you stop high-frequency oscillator. Please refer to 3.3.5 Clock Doubler (DFM) for the Details. 91C025-17 2007-02-28 TMP91C025 7 EMCCR0 (00E3H) 6 5 4 1 0 AHOLD TA3MLDE − EXTIN DRVOSCH DRVOSCL R R/W R/W R/W R/W R/W R/W R/W After reset 0 0 0 0 0 0 1 1 Protect flag LCDC source Address hold Melody/alarm Always 1: External fc oscillator fs oscillator 0: Off CLK 0: Disable source clock write 0. clock driver ability driver ability 1: On 0: 32 kHz 1: Enable 0: 32 kHz 1: Normal 1: Normal 1: TA3OUT 0: Weak 0: Weak PROTECT TA3LCDE 1: TA3OUT (Note) Bit symbol Read/Write After reset Function EMCCR2 (00E5H) 2 Read/Write Bit symbol Function EMCCR1 (00E4H) 3 Bit symbol Switching the protect ON/OFF by write to following 1st-KEY, 2nd-KEY 1st-KEY: EMCCR1 = 5AH, EMCCR2 = A5H in succession write 2nd-KEY: EMCCR1 = A5H, EMCCR2 = 5AH in succession write Read/Write After reset Function EMCCR3 (00E6H) Bit symbol ENFROM ENDROM ENPROM FFLAG DFLAG PFLAG Read/Write R/W R/W R/W R/W R/W R/W After reset 0 0 0 0 0 0 Function CS1A area CS2B-2C CS2A area CS1A write CS2B-2C write CS2A write detect control area detect detect control operation flag operation 0: Disable control 0: Disable 1: Enable 0: Disable 1: Enable 1: Enable flag operation flag When reading When writing 0: Not written 0: Clear flag 1: Written Note1: When getting access to the logic address 000000H to 000FDFH, A0 to A23 holds the previous address of Note2: In case restarting the oscillator in the stop oscillation state (e.g. Restart the oscillator in STOP mode), set external access. EMCCR0<DRVOSCH>, <DRVOSCL>=”1”. Figure 3.3.5 SFRs for Noise Reduction 91C025-18 2007-02-28 TMP91C025 3.3.3 System Clock Controller The system clock controller generates the system clock signal (fSYS) for the CPU core and internal I/O. It contains two oscillation circuits and a clock gear circuit for high-frequency (fc) operation. The register SYSCR1<SYSCK> changes the system clock to either fc or fs, SYSCR0<XEN> and SYSCR0<XTEN> control enabling and disabling of each oscillator, and SYSCR1<GEAR0:2> sets the high-frequency clock gear to either 1, 2, 4, 8 or 16 (fc, fc/2, fc/4, fc/8 or fc/16). These functions can reduce the power consumption of the equipment in which the device is installed. The combination of settings <XEN> = 1, <XTEN> = 0, <SYSCK> = 0 and <GEAR0:2> = 100 will cause the system clock (fSYS) to be set to fc/32 (fc/16 × 1/2) after a reset. For example, fSYS is set to 1.1 MHz when the 36 MHz oscillator is connected to the X1 and X2 pins. (1) Switching from NORMAL mode to SLOW mode When the resonator is connected to the X1 and X2 pins, or to the XT1 and XT2 pins, the warm-up timer can be used to change the operation frequency after stable oscillation has been attained. The warm-up time can be selected using SYSCR2<WUPTM0:1>. This warm-up timer can be programmed to start and stop as shown in the following examples 1 and 2. Table 3.3.1 shows the warm-up time. Note 1: When using an oscillator (other than a resonator) with stable oscillation, a warm-up timer is not needed. Note 2: The warm-up timer is operated by an oscillation clock. Hence, there may be some variation in warm-up time. Table 3.3.1 Warm-up Times Warm-up Time SYSCR2 <WUPTM1:0> 8 01 (2 /frequency) Change to NORMAL Mode Change to SLOW Mode 7.1 (μs) 7.8 (ms) 14 0.455 (ms) 500 (ms) 16 1.820 (ms) 2000 (ms) 10 (2 /frequency) 11 (2 /frequency) 91C025-19 at fOSCH = 36 MHz, fs = 32.768 kHz 2007-02-28 TMP91C025 (Example 1: Setting the clock) Changing from high-frequency (fc) to low-frequency (fs). SYSCR0 EQU 00E0H SYSCR1 EQU 00E1H SYSCR2 EQU 00E2H LD (SYSCR2), - X11 - - - - B WUP: 16 Sets warm-up time to 2 /fs. ; SET 6, (SYSCR0) ; Enables low-frequency oscillation. SET 2, (SYSCR0) ; Clears and starts warm-up timer. BIT 2, (SYSCR0) ; JR NZ, WUP ; SET 3, (SYSCR1) ; Changes fSYS from fc to fs. RES 7, (SYSCR0) ; Disables high-frequency oscillation. Detects stopping of warm-up timer. x: Don’t care -: No change <XEN> X1, X2 pins <XTEN> XT1, XT2 pins Warm-up timer Counts up by fSYS Counts up by fs End of warm-up timer <SYSCK> fc fs Clears and starts warm-up timer Chages fSYS from fc to fs System clock fSYS Enables low-frequency Disables high-frequency End of warm-up timer 91C025-20 2007-02-28 TMP91C025 (Example 2: Setting the clock) Changing from low-frequency (fs) to high-frequency (fc). SYSCR0 EQU 00E0H SYSCR1 EQU 00E1H SYSCR2 EQU 00E2H LD (SYSCR2), -X10 - - - - B WUP: ; 14 Sets warm-up time to 2 /fc. SET 7, (SYSCR0) ; Enables high-frequency oscillation. SET 2, (SYSCR0) ; Clears and starts warm-up timer. BIT 2, (SYSCR0) ; JR NZ, WUP ; RES 3, (SYSCR1) ; Changes fSYS from fs to fc. RES 6, (SYSCR0) ; Disables low-frequency oscillation. Detects stopping of warm-up timer. x: Don’t care -: No change <XEN> X1, X2 pins <XTEN> XT1, XT2 pins Warm-up timer Counts up by fSYS Counts up by fOSCH End of warm-up timer <SYSCK> fs fc System clock fSYS Enables high-frequency Clears and starts warm-up timer Chages fSYS from fs to fc End of warm-up timer 91C025-21 Disables low-frequency 2007-02-28 TMP91C025 (2) Clock gear controller When the high-frequency clock fc is selected by setting SYSCR1<SYSCK> = 0, fFPH is set according to the contents of the clock gear select register SYSCR1<GEAR2:0> to either fc, fc/2, fc/4, fc/8 or fc/16. Using the clock gear to select a lower value of fFPH reduces power consumption. (Example 3) Changing to a high-frequency gear SYSCR1 EQU 00E1H LD (SYSCR1), XXXX0000B ; Changes fSYS to fc/2. X: Don't care (High-speed clock gear changing) To change the clock gear, write the register value to the SYSCR1<GEAR2:0> register.It is necessary the warm-up time until changing after writing the register value. There is the possibility that the instruction next to the clock gear changing instruction is executed by the clock gear before changing.To execute the instruction next to the clock gear switching instruction by the clock gear after changing,input the dummy instruction as follows (Instruction to execute the write cycle). (Example) SYSCR1 EQU 00E1H LD (SYSCR1), XXXX0001B ; Changes fSYS to fc/4. LD (DUMMY), 00H ; Dummy instruction Instruction to be executed after clock gear has changed (3) Internal clock output pin An internal clock fFPH can be output to the PA3/SCOUT pin. By setting “1” to the PAFC2<PA3F2> register, the PA3 pin functions as the SCOUT pin. 91C025-22 2007-02-28 TMP91C025 3.3.4 Prescaler Clock Controller For the internal I/O (TMRA01 to TMRA23, SIO0 to SIO1) there is a prescaler which can divide the clock. The φT0 clock input to the prescaler is either the clock fFPH divided by 4 or the clock fc/16 divided by 4. The setting of the SYSCR0<PRCK0:1> register determines which clock signal is input. 3.3.5 Clock Doubler (DFM) DFM outputs the fDFM clock signal, which is four times as fast as fOSCH. It can use the low-frequency oscillator, even though the internal clock is high frequency . A reset initializes DFM to stop status, setting to DFMCR0-register is needed before use. Like an oscillator, this circuit requires time to stabilize. This is called the lock up time. The following example shows how DFM is used. DFMCR0 EQU DFMCR1 EQU 00E8H 00E9H LD (DFMCR1), 00001011B LD (DFMCR0), 01X0XXXXB ; BIT 5, (DFMCR0) ; JR NZ, LUP ; LD (DFMCR0), 10X0XXXXB ; DFM parameter setting. 12 Set lock up time to 2 /4 MHz. Enables DFM operation and starts lock up. LUP: Detects end of lock up. Changes fc from 4 MHz to 16 MHz. (Changes fSYS from 2 MHz to 8 MHz.) X: Don't care <ACT1:0> 01 10 DFM output: fDFM Lock up timer Counts up by fOSCH <DLUPFG> During lock up After lock up System clock fSYS Starts DFM operation. Starts lock up. Changes from 4 MHz to 16 MHz. Ends of lock up. Note: Input frequency limitation and correction for DFM Recommend to use Input frequency (High-speed oscillation) for DFM in the following condition. • fOSCH = 4 to 9 MHz (Vcc = 3.0 to 3.6 V): Write 0BH to DFMCR1 • fOSCH = 4 to 6.75 MHz (Vcc = 2.7 to 3.6 V): Write 0BH to DFMCR1 91C025-23 2007-02-28 TMP91C025 Limitation point on the use of DFM 1. It’s prohibited to execute DFM enable/disable control in the SLOW mode (fs) (write to DFMCR0<ACT1:0> = “10”). You should control DFM in the NORMAL mode. 2. If you stop DFM operation during using DFM (DFMCR0<ACT1:0> = “10”), you shouldn’t execute the commands that change the clock fDFM to fOSCH and stop the DFM at the same time. Therefore the above executions should be separated into two procedures as showing below. LD (DFMCR0), C0H ; Change the clock fDFM to fOSCH. LD (DFMCR0), 00H ; DFM stop. 3. If you stop high-frequency oscillator during using DFM (DFMCR0<ACT1:0> = “10”), you should stop DFM before you stop high-frequency oscillator. Examples of settings are below. (1) Start up/change control (OK) Low-frequency oscillator operation mode (fs) (High-frequency oscillator STOP) → High-frequency oscillator start up → High-frequency oscillator operation mode (fOSCH) → DFM start up → DFM use mode (fDFM) LD (SYSCR0), 11 - - - 1 - - B ; High-frequency oscillator start up/warm-up start. WUP: LUP: BIT 2, (SYSCR0) ; JR NZ, WUP ; LD (SYSCR1), - - - - 0 - - - B ; Change the system clock fs to fOSCH. LD (DFMCR0), 01 - 0 - - - - B ; DFM start up/lock up start. BIT 5, (DFMCR0) ; JR NZ, LUP ; LD (DFMCR0), 10 - 0 - - - - B ; Check for the flag of warm-up end. Check for the flag of lock up end. Change the system clock fOSCH to fDFM. (OK) Low-frequency oscillator operation mode (fs) (High-frequency oscillator operate) → High-frequency oscillator operation mode (fOSCH) → DFM start up → DFM use mode (fDFM) LUP: LD (SYSCR1), - - - - 0 - - - B ; Change the system clock fs to fOSCH. LD (DFMCR0), 01 - 0 - - - - B ; DFM start up/lock up start. BIT 5, (DFMCR0) ; JR NZ, LUP ; LD (DFMCR0), 10 - 0 - - - - B ; Check for the flag of lock up end. Change the system clock fOSCH to fDFM. (Error) Low-frequency oscillator operation mode (fs) (High-frequency oscillator STOP) → High-frequency oscillator start up → DFM start up → DFM use mode (fDFM) LD (SYSCR0), 11 - - - 1 - - B ; High-frequency oscillator starts up/warm-up start. WUP: LUP: BIT 2, (SYSCR0) ; JR NZ, WUP ; LD (DFMCR0), 01 - 0 - - - - B ; BIT 5, (DFMCR0) ; JR NZ, LUP ; LD (DFMCR0), 10 - 0 - - - - B ; Change the internal clock fOSCH to fDFM. LD (SYSCR1), - - - - 0 - - - B ; Change the system clock fs to fDFM. 91C025-24 Check for the flag of warm-up end. DFM start up/lock up start. Check for the flag of lock up end. 2007-02-28 TMP91C025 (2) Change/stop control (OK) DFM use mode (fDFM) → High-frequency oscillator operation mode (fOSCH) → DFM stop → Low-frequency oscillator operation mode (fs) → High-frequency oscillator stop LD (DFMCR0), 11 - - - - - - B ; Change the system clock fDFM to fOSCH. LD (DFMCR0), 00 - - - - - - B ; DFM stop. LD (SYSCR1), - - - - 1 - - - B ; Change the system clock fOSCH to fs. LD (SYSCR0), 0 - - - - - - - B ; High-frequency oscillator stop. (Error) DFM use mode (fDFM) → Low-frequency oscillator operation mode (fs) → DFM stop → High-frequency oscillator stop LD (SYSCR1), - - - - 1 - - - B ; Change the system clock fDFM to fs. LD (DFMCR0), 11 - - - - - - B ; Change the internal clock (fc) fDFM to fOSCH. LD (DFMCR0), 00 - - - - - - B ; DFM stop. LD (SYSCR0), 0 - - - - - - - B ; High-frequency oscillator stop. (OK) DFM use mode (fDFM) → Set the STOP mode → High-frequency oscillator operation mode (fOSCH) → DFM stop → HALT (High-frequency oscillator stop) LD (SYSCR2), - - - - 01 - - B ; Set the STOP mode. (This command can execute before use of DFM.) LD (DFMCR0), 11 - - - - - - B ; Change the system clock fDFM to fOSCH. LD (DFMCR0), 00 - - - - - - B ; DFM stop. ; Shift to STOP mode. HALT (Error) DFM use mode (fDFM) → Set the STOP mode → HALT (High-frequency oscillator stop) LD (SYSCR2), - - - - 01 - - B ; Set the STOP mode. (This command can execute before use of DFM.) HALT ; 91C025-25 Shift to STOP mode. 2007-02-28 TMP91C025 3.3.6 Noise Reduction Circuits Noise reduction circuits are built in, allowing implementation of the following features. (1) Reduced drivability for high-frequency oscillator (2) Reduced drivability for low-frequency oscillator (3) Single drive for high-frequency oscillator (4) SFR protection of register contents (5) ROM protection of register contents The above functions are performed by making the appropriate settings in the EMCCR0 to EMCCR3 registers. (1) Reduced drivability for high-frequency oscillator (Purpose) Reduces noise and power for oscillator when a resonator is used. (Block diagram) fOSCH C1 X1 pin Enable oscillation ( STOP + EMCCR0 < EXTIN > ) Resonator EMCCR0<DRVOSCH> C2 X2 pin (Setting method) The drivability of the oscillator is reduced by writing 0 to EMCCR0<DRVOSCH> register. By reset, <DRVOSCH> is initialized to 1 and the oscillator starts oscillation by normal-drivability when the power-supply is on. 91C025-26 2007-02-28 TMP91C025 (2) Reduced drivability for low-frequency oscillator (Purpose) Reduces noise and power for oscillator when a resonator is used. (Block diagram) C1 XT1 pin Enable oscillation Resonator EMCCR0<DRVOSCL> C2 fS XT2 pin (Setting method) The drivability of the oscillator is reduced by writing 0 to EMCCR0<DRVOSCL> register. By reset, <DRVOSCL> is initialized to 1. the (3) Single drive for high-frequency oscillator (Purpose) Not need twin-drive and protect mistake operation by inputted noise to X2 pin when the external-oscillator is used. (Block diagram) fOSCH X1 pin Enable oscillation ( STOP + EMCCR0 < EXTIN > ) EMCCR0<DRVOSCH> X2 pin (Setting method) The oscillator is disabled and starts operation as buffer by writing 1 to EMCCR0<EXTIN> register. X2-pin is always outputted 1. By reset, <EXTIN> is initialized to 0. Note: Do not write EMCCR0<EXTIN> = “1” when using external resonator. 91C025-27 2007-02-28 TMP91C025 (4) Runaway provision with SFR protection register (Purpose) Provision in runaway of program by noise mixing. Write operation to specified SFR is prohibited so that provision program in runaway prevents that it is it in the state which is fetch impossibility by stopping of clock, memory control register (CS/WAIT controller, MMU) is changed. And error handling in runaway becomes easy by INTP0 interruption. Specified SFR list 1. CS/WAIT controller B0CS, B1CS, B2CS, B3CS, BEXCS, MSAR0, MSAR1, MSAR2, MSAR3, MAMR0, MAMR1, MAMR2, MAMR3 2. MMU LOCAL0/1/2/3 3. Clock gear SYSCR0, SYSCR1, SYSCR2, EMCCR0, EMCCR3 4. DFM DFMCR0, DFMCR1 (Operation explanation) Execute and release of protection (write operation to specified SFR) becomes possible by setting up a double key to EMCCR1 and EMCCR2 register. (Double key) 1st-KEY: Succession writes in 5AH at EMCCR1 and A5H at EMCCR2 2nd-KEY: Succession writes in A5H at EMCCR1 and 5AH at EMCCR2 A state of protection can be confirmed by reading EMCCR0<PROTECT>. By reset, protection becomes OFF. And INTP0 interruption occurs when write operation to specified SFR was executed with protection ON state. 91C025-28 2007-02-28 TMP91C025 (5) Runaway provision with ROM protection register (Purpose) Provision in runaway of program by noise mixing. (Operation explanation) When write operation was executed for external three kinds of ROM by runaway of program, INTP1 is occurred and detects runaway function. Three kinds of ROM is fixed as for Flash ROM (Option program ROM), Data ROM, Program ROM are as follows on the logical address memory map. 1. Flash ROM: Address 400000H to 7FFFFFH 2. Data ROM: Address 800000H to BFFFFFH 3. Program ROM: Address C00000H to FFFFFFH For these address, admission/prohibition of detection of write operation sets it up with EMCCR3<ENFROM, ENDROM, ENPROM>. And INTP1 interruption occurred within which ROM area in the case that occurred can confirm each with EMCCR3<FFLAG, DFLAG, PFLAG>. This flag is cleared when write in 0. 91C025-29 2007-02-28 TMP91C025 3.3.7 Standby Controller (1) HALT modes When the HALT instruction is executed, the operating mode switches to IDLE2, IDLE1 or STOP mode, depending on the contents of the SYSCR2<HALTM1:0> register. The subsequent actions performed in each mode are as follows: a. IDLE2: Only the CPU halts. The internal I/O is available to select operation during IDLE2 mode. By setting the following register. Table 3.3.2 Shows the registers of setting operation during IDLE2 mode. Table 3.3.2 SFR Setting Operation during IDLE2 Mode Internal I/O SFR TMRA01 TA01RUN<I2TA01> TMRA23 TA23RUN<I2TA23> SIO0 SC0MOD1<I2S0> SIO1 SC1MOD1<I2S1> AD converter ADMOD1<I2AD> WDT WDMOD<I2WDT> b. IDLE1: Only the oscillator and the RTC (Real-time clock) and MLD continue to operate. c. STOP: All internal circuits stop operating. The operation of each of the different HALT modes is described in Table 3.3.3. Table 3.3.3 I/O Operation during HALT Modes HALT Mode IDLE2 IDLE1 STOP SYSCR2<HALTM1:0> 11 10 01 CPU I/O ports Stop Keep the state when the HALT instruction See Table 3.3.6, Table 3.3.7 was executed. TMRA Block SIO AD converter Available to select operation block WDT Stop LCDC, Interrupt controller Operate RTC, MLD Possible to operate 91C025-30 2007-02-28 TMP91C025 (2) How to release the HALT mode These halt states can be released by resetting or requesting an interrupt. The halt release sources are determined by the combination between the states of interrupt mask register <IFF2:0> and the HALT modes. The details for releasing the halt status are shown in Table 3.3.4. • Released by requesting an interrupt The operating released from the HALT mode depends on the interrupt enabled status. When the interrupt request level set before executing the HALT instruction exceeds the value of interrupt mask register, the interrupt due to the source is processed after releasing the HALT mode, and CPU status executing an instruction that follows the HALT instruction. When the interrupt request level set before executing the HALT instruction is less than the value of the interrupt mask register, releasing the HALT mode is not executed. (In non-maskable interrupts, interrupt processing is processed after releasing the HALT mode regardless of the value of the mask register.) However only for INT0 to INT3, INTKEY, INTRTC and INTALM0 to INTALM4 interrupts, even if the interrupt request level set before executing the HALT instruction is less than the value of the interrupt mask register, releasing the the HALT mode is executed. In this case,interrupt processing, and CPU starts executing the instruction next to the HALT instruction,but the interrupt request flag is held at 1. Note: Usually, interrupts can release all halts status. However, the interrupts (INT0 to INT3, INTRTC, INTALM0 to INTALM4, INTKEY) which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 5 clocks of fFPH) with IDLE1 or STOP mode (IDLE2 is not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficulty. The priority of this interrupt is compared with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt. • Releasing by resetting Releasing all halt status is executed by resetting. When the STOP mode is released by RESET, it is necessry enough resetting time (see Table 3.3.5) to set the operation of the oscillator to be stable. 91C025-31 2007-02-28 TMP91C025 Table 3.3.4 Source of Halt State Clearance and Halt Clearance Operation Status of Received Interrupt Interrupt Enabled Interrupt Disabled (Interrupt level) ≥ (Interrupt mask) (Interrupt level) < (Interrupt mask) Interrupt Source of halt state clearance HALT Mode IDLE2 IDLE1 STOP IDLE2 IDLE1 STOP INTWDT ♦ × × − − − INT0 to INT3 (Note 1) ♦ ♦ *1 ♦ ♦ ○ ○ ○ ○ ○*1 INTALM0 to INTALM4 ♦ × INTTA0 to INTTA3 ♦ × × × × × INTRX0 to INTRX1, TX0 to TX1 ♦ × × × × × INTAD ♦ × × × × × INTKEY ♦ ♦ *1 ♦ ♦ × ○ ○ ○*1 INTRTC ○ ○ INTLCD ♦ × × × × × RESET ♦ × × Initialize LSI ♦: After clearing the HALT mode, CPU starts interrupt processing. ○: After clearing the HALT mode, CPU resumes executing starting from instruction following the HALT instruction. ×: It can not be used to release the HALT mode. −: The priority level (Interrupt request level) of non-maskable interrupts is fixed to 7, the highest priority level. There is not this combination type. *1: Releasing the HALT mode is executed after passing the warm-up time. Note 1: When the HALT mode is cleared by an INT0 interrupt of the level mode in the interrupt enabled status, hold level H until starting interrupt processing. If level L is set before holding level L, interrupt processing is correctly started. (Example) Releasing IDLE1 mode An INT0 interrupt clears the halt state when the device is in IDLE1 mode. Address 8200H LD (PBFC), 00H ; Sets PB3 to INT0. 8203H LD (IIMC), 00H ; Selects INT0 interrupt rising edge. 8206H LD (INTE0AD), 06H ; Sets INT0 interrupt level to 6. 8209H EI 5 ; Sets interrupt level to 5 for CPU. 820BH LD (SYSCR2), 88H 820EH HALT ; Sets HALT mode to IDLE1 Mode. ; Halts CPU. INT0 INT0 interrupt routine RETI 820FH LD XX, XX 91C025-32 2007-02-28 TMP91C025 (3) Operation a. IDLE2 mode In IDLE2 mode only specific internal I/O operations, as designated by the IDLE2 setting register, can take place. Instruction execution by the CPU stops. Figure 3.3.6 illustrates an example of the timing for clearance of the IDLE2 mode halt state by an interrupt. X1 A0 to A23 D0 to D15 Data Data RD WR Interrupt for release IDLE2 mode Figure 3.3.6 Timing Chart for IDLE2 Mode Halt State Cleared by Interrupt b. IDLE1 mode In IDLE1 mode, only the internal oscillator and the RTC, MLD continue to operate. The system clock in the MCU stops. The pin status in the IDLE1 mode is depended on setting the register SYSCR2<SELDRV, DRVE>. Table 3.3.6, Table 3.3.7 summarizes the state of these pins in the IDLE mode1. In the halt state, the interrupt request is sampled asynchronously with the system clock; however, clearance of the halt state (e.g. restart of operation) is synchronous with it. Figure 3.3.7 illustrates the timing for clearance of the IDLE1 mode halt state by an interrupt. X1 A0 to A23 D0 to D15 Data Data RD WR Interrupt for release IDLE1 mode Figure 3.3.7 Timing Chart for IDLE1 Mode Halt State Cleared by Interrupt 91C025-33 2007-02-28 TMP91C025 c. STOP mode When STOP mode is selected, all internal circuits stop, including the internal oscillator pin status in STOP mode depends on the settings in the SYSCR2<DRVE> register. Table 3.3.6, Table 3.3.7 summarizes the state of these pins in STOP mode. After STOP mode has been cleared system clock output starts when the warm-up time has elapsed, in order to allow oscillation to stabilize. After STOP mode has been cleared, either NORMAL mode or SLOW mode can be selected using the SYSCR0<RSYSCK> register. Therefore, <RSYSCK>, <RXEN> and <RXTEN> must be set see the sample warm-up times in Table 3.3.5. Figure 3.3.8 illustrates the timing for clearance of the STOP mode halt state by an interrupt. Warm-up time X1 A0 to A23 D0 to D15 Data Data RD WR Interrupt for release STOP mode Figure 3.3.8 Timing Chart for STOP Mode Halt State Cleared by Interrupt Table 3.3.5 Sample Warm-up Times after Clearance of STOP Mode at fOSCH = 36 MHz, fs =32.768 kHz SYSCR2<WUPTM1:0> SYSCR0 <RSYSCK> 01 (2 ) 0 (fc) 7.1 μs 0.455 ms 1.820 ms 1 (fs) 7.8 ms 500 ms 2000 ms 8 10 (214) 91C025-34 11 (216) 2007-02-28 TMP91C025 (Setting example) The STOP mode is entered when the low-frequency operates, and high-frequency operates after releasing due to INTx. Address SYSCR0 EQU 00E0H SYSCR1 EQU 00E1H SYSCR2 EQU 00E2H 8FFDH LD (SYSCR1), 08H ; fSYS = fs/2. 9000H LD (SYSCR2), - X1001-1B ; Sets warm-up time to 2 /fOSCH. 9002H LD (SYSCR0), 011000 - - B ; Operates high-frequency after released. 9005H HALT 14 − : No change Clears and starts hit warm-up timer. (High-frequency) INTx End INTx interrupt routine 9006H Note: LD XX, XX RETI When different modes are used before and after STOP mode as the above mentioned , there is possible to release the HALT mode without changing the operation mode by acceptance of the halt release interrupt request during execution of HALT instruction (during 6 states). In the system which accepts the interrupts during execution HALT instruction, set the same operation mode before and after the STOP mode. 91C025-35 2007-02-28 TMP91C025 Table 3.3.6 Input Buffer State Table Input Buffer State When the CPU is In HALT operating mode(IDLE2) Input Port Name Function During When Name Reset Used as function Pin D0-7 – ON upon OFF P10-17 D8-15 P56 (*1) WAIT P80-82 (*2) – P83 (*2) ADTRG P90 (*1) KI0 P91 (*1) KI1 P92 (*1) KI2 P93 (*1) KI3 P94 (*1) KI4 P95 (*1) KI5 P96 (*1) KI6 P97 (*1) KI7 PB3 INT0, PS PB4 INT1, TA0IN PB5 INT2 PB6 INT3 PC0 – PC3 (*1) – PC1 RXD0 PC2 SCLK0, CTS0 PC4 RXD1 PC5 (*1) SCLK1, CTS1 PZ2-Z3 – RESET , AM0,AM1 X1,XT1 OFF ON Used as Input Port When Used function Used as as function Input Port Pin Pin – OFF OFF ON ON – When Used as – external read ON When When In HALT mode(IDLE1/STOP) ON ON upon – port read ON Condition A (Note) ON ON Used as Input Port Condition B (Note) When Used as function – OFF OFF OFF OFF – ON When Used as Input Port Pin – ON OFF When ON – ON ON ON OFF ON ON OFF OFF – – OFF – OFF ON ON ON – – OFF ON – – ON OFF ON – – OFF ON – ON – ON – ON – – IDLE1 : ON , STOP : OFF ON: The buffer is always turned on. A current flows *1: Port having a pull-up/pull-down resistor. the input buffer if the input pin is not driven. OFF: The buffer is always turned off. *2:AIN input does not cause a current to flow through the buffer. –: No applicable Note: Condition A/B are as follows. SYSCR2 register setting <DRVE> <SELDRV> 0 0 0 1 1 0 1 1 HALT mode IDLE1 STOP Condition A Condition A Condition B Condition B 91C025-36 2007-02-28 TMP91C025 Table 3.3.7 Output Buffer State Table Output Buffer State When the CPU is Port Name D0-7 Output Function Name During When When When Reset Used as Used as Used as function Output function Pin Port Pin ON upon – – OFF P10-17 D8-15 A0-15 – P20-27 A16-23 P56 (*1) – P60 CS0 P61 CS1 P62 CS2 , CS2A P63 CS3 P64 EA24, CS2B , SRLB P65 EA25, CS2C , SRUB PA0 external write ON ON OFF – ON ON In HALT mode(IDLE1/STOP) Condition A (Note) When Used When Used as Output as function Port Pin – When When Used as Used as Used as Output function Output Port Pin Port – OFF ON ON ON OFF – – ON – OFF ON – Condition B (Note) When OFF – – ON ON ON – – OFF OFF ON ON KO0, ALARM , MLDALM PA1 KO1,TA1OUT PA2 KO2,TA3OUT PA3 KO3,SCOUT PB3-B4 – PB5 PX PB6 PY PC0 TXD0 PC1,C4 – PC2 SCLK0 PC3 (*1) TXD1 PC5 SCLK1 PD0 (*1) D1BSCP PD1 D2BLP PD2 D3BFR PD3 DLEBCD PD4 DOFFB PD7 MLDALM RD , WR – PZ2 (*1) HWR PZ3 (*1) R/W, SRWR X2 – XT2 In HALT mode(IDLE2) operating – – ON – – ON – – – – ON ON – OFF OFF – – ON OFF ON ON – ON ON ON – ON OFF OFF ON ON – – – – ON ON OFF ON – ON – IDLE1 : ON , STOP : Output “H” level IDLE1 : ON , STOP : High-Z ON : The buffer is always turned on. When the bus is *1:Port having a pull-up/pull-down resistor. released , however ,output buffers for some pins are turned off. OFF: The buffer is always turned off. – : No applicable Note: Condition A/B are as follows. SYSCR2 register setting <DRVE> <SELDRV> 0 0 0 1 1 0 1 1 HALT mode IDLE1 STOP Condition A Condition A Condition B Condition B 91C025-37 2007-02-28 TMP91C025 3.4 Interrupts Interrupts are controlled by the CPU interrupt mask register SR<IFF2:0> and by the built-in interrupt controller. The TMP91C025 has a total of 37 interrupts divided into the following three types: • Interrupts generated by CPU: 9 sources (Software interrupts, illegal instruction interrupt) • Internal interrupts: 23 sources • Interrupts on external pins ( INT0 to INT3, INTKEY): 5 sources A (fixed) individual interrupt vector number is assigned to each interrupt. One of six (variable) priority level can be assigned to each maskable interrupt. The priority level of non-maskable interrupts are fixed at 7 as the highest level. When an interrupt is generated, the interrupt controller sends the piority of that interrupt to the CPU.If multiple interrupts are generated simultaneously, the interrupt controller sends the interrupt with the highest priority to the CPU. (The highest priority is level 7 using for non-maskable interrupts.) The CPU compares the priority level of the interrupt with the value of the CPU interrupt mask register <IFF2:0>. If the priority level of the interrupt is higher than the value of the interrupt mask register, the CPU accepts the interrupt. The interrupt mask register <IFF2:0> value can be updated using the value of the EI instruction (EI num sets <IFF2:0> data to num). For example, specifying EI 3 enables the maskable interrupts which priority level set in the interrupt controller is 3 or higher, and also non-maskable interrupts. Operationally, the DI instruction (<IFF2:0> = 7) is identical to the EI 7 instruction. DI instruction is used to disable maskable interrupts because of the priority level of maskable interrupts is 1 to 6. The EI instruction is vaild immediately after execution. In addition to the above general-purpose interrupt processing mode, TLCS-900/L1 has a micro DMA interrupt processing mode as well. The CPU can transfer the data (1/2/4 bytes) automatically in micro DMA mode, therefore this mode is used for speed-up interrupt processing, such as transferring data to the internal or external peripheral I/O. Moreover, TMP91C025 has software start function for micro DMA processing request by the software not by the hardware interrupt. Figure 3.4.1 shows the overall interrupt processing flow. 91C025-38 2007-02-28 TMP91C025 Interrupt processing Micro DMA soft start request Interrupt specified by micro DMA start vector? Yes No Clear interrupt request flag Interrupt vector value V read Interrupt request F/F clear General-purpose interrupt processing PUSH PC PUSH SR SR<IFF2:0> ← Level of accepted interrupt + 1 INTNEST ← INTNEST + 1 Data transfer by micro DMA Count ← Count－1 Count = 0 No Micro DMA processing Yes Clear vector register generating micro DMA trasfer and interrupt (INTTC0 – 3) PC ← (FFFF00H + V) Interrupt processing program RETI instruction POP SR POP PC INTNEST←INTNEST − 1 End Figure 3.4.1 Overall Interrupt Processing Flow 91C025-39 2007-02-28 TMP91C025 3.4.1 General-purpose Interrupt Processing When the CPU accepts an interrupt, it usually performs the following sequence of operations. That is also the same as TLCS-900/L and TLCS-900/H. (1) The CPU reads the interrupt vector from the interrupt controller. If the same level interrupts occur simultaneously, the interrupt controller generates an interrupt vector in accordance with the default priority and clears the interrupt request. (The default priority is already fixed for each interrupt: the smaller vector value has the higher priority level.) (2) The CPU pushes the value of program counter (PC) and status register (SR) onto the stack area (indicated by XSP). (3) The CPU sets the value which is the priority level of the accepted interrupt plus 1 (+1) to the interrupt mask register <IFF2:0>. However, if the priority level of the accepted interrupt is 7, the register’s value is set to 7. (4) The CPU increases the interrupt nesting counter INTNEST by 1 (+1). (5) The CPU jumps to the address indicated by the data at address FFFF00H + interrupt vector and starts the interrupt processing routine. The above processing time is 18 states (1.00 μs at 36 MHz) as the best case (16-bit data bus width and 0 waits). When the CPU compled the interrupt processing, use the RETI instruction to return to the main routine. RETI restores the contents of program counter (PC) and status register (SR) from the stack and decreases the Interrupt Nesting counter INTNEST by 1 (−1). Non-maskable interrupts cannot be disabled by a user program. Maskable interrupts, however, can be enabled or disabled by a user program. A program can set the priority level for each interrupt source. (A priority level setting of 0 or 7 will disable an interrupt request.) If an interrupt request which has a priority level equal to or greater than the value of the CPU interrupt mask register <IFF2:0> comes out, the CPU accepts its interrupt. Then, the CPU interrupt mask register <IFF2:0> is set to the value of the priority level for the accepted interrupt plus 1 (+1). Therefore, if an interrupt is generated with a higher level than the current interrupt during its processing, the CPU accepts the later interrupt and goes to the nesting status of interrupt processing. Moreover, if the CPU receives another interrupt request while performing the said (1) to (5) processing steps of the current interrupt, the latest interrupt request is sampled immediately after execution of the first instruction of the current interrupt processing routine. Specifying DI as the start instruction disables maskable interrupt nesting. A reset initializes the interrupt mask register <IFF2:0> to 111, disabling all maskable interrupts. Table 3.4.1 shows the TMP91C025 interrupt vectors and micro DMA start vectors. The address FFFF00H to FFFFFFH (256 bytes) is assigned for the interrupt vector area. 91C025-40 2007-02-28 TMP91C025 Table 3.4.1 TMP91C025 Interrupt Vectors Table Default Priority Interrupt Source and Source of Micro DMA Request Type Vector Micro Vector Reference DMA Start Value (V) Address Vector 1 Reset or “SWI 0” instruction 0000H FFFF00H − 2 “SWI 1” instruction 0004H FFFF04H − 3 INTUNDEF: illegal instruction or “SWI 2” instruction 0008H FFFF08H − “SWI 3” instruction 000CH FFFF0CH − “SWI 4” instruction 0010H FFFF10H − 6 “SWI 5” instruction 0014H FFFF14H − 7 “SWI 6” instruction 0018H FFFF18H − 8 “SWI 7” instruction 001CH FFFF1CH − 9 INTWD: Watchdog timer 0024H FFFF24H − 4 5 NonMaskable – Micro DMA (MDMA) − − − 10 INT0 pin 0028H FFFF28H 0AH 11 INT1 pin 002CH FFFF2CH 0BH 12 INT2 pin 0030H FFFF30H 0CH 13 INT3 pin 0034H FFFF34H 0DH 14 INTALM0: ALM0 (8192 Hz) 0038H FFFF38H 0EH 15 INTALM1: ALM1 (512 Hz) 003CH FFFF3CH 0FH 16 INTALM2: ALM2 (64 Hz) 0040H FFFF40H 10H 17 INTALM3: ALM3 (2 Hz) 0044H FFFF44H 11H 18 INTALM4: ALM4 (1 Hz) 0048H FFFF48H 12H 19 INTTA0: 8-bit timer0 004CH FFFF4CH 13H 20 INTTA1: 8-bit timer1 0050H FFFF50H 14H 21 INTTA2: 8-bit timer2 0054H FFFF54H 15H 22 INTTA3: 8-bit timer3 0058H FFFF58H 16H 23 INTRX0: Serial reception (Channel 0) 005CH FFFF5CH 17H INTTX0: Serial transmission (Channel 0) 0060H FFFF60H 18H 25 INTRX1: Serial reception (Channel 1) 0064H FFFF64H 19H 26 INTTX1: Serial transmission (Channel 1) 0068H FFFF68H 1AH 24 Maskable 27 INTAD: AD conversion end 006CH FFFF6CH 1BH 28 INTKEY: Key wake up 0070H FFFF70H 1CH 29 INTRTC: RTC (Alarm interrupt) 0074H FFFF74H 1DH 30 INTLCD: LCDC/LP pin 007CH FFFF7CH 1FH 31 INTP0: Protect 0 (WR to special SFR) 0080H FFFF80H 20H 32 INTP1: Protect 1 (WR to ROM) 0084H FFFF84H 21H 33 INTTC0: Micro DMA end (Channel 0) 0088H FFFF88H − 34 INTTC1: Micro DMA end (Channel 1) 008CH FFFF8CH − 35 INTTC2: Micro DMA end (Channel 2) 0090H FFFF90H − 36 INTTC3: Micro DMA end (Channel 3) 0094H FFFF94H − 0098H FFFF98H to to to − to (Reserved) 00FCH FFFFFCH − (Reserved) 91C025-41 2007-02-28 TMP91C025 3.4.2 Micro DMA Processing In addition to general-purpose interrupt processing, the TMP91C025 supprots a micro DMA function. Interrupt requests set by micro DMA perform micro DMA processing at the highest priority level (level 6) among maskable interrupts, regardless of the priority level of the particular interrupt source. The micro DMA has 4 channels and is possible continuous transmission by specifing the say later burst mode. Because the micro DMA function has been implemented with the cooperative operation of CPU, when CPU goes to a standby mode by HALT instruction, the requirement of micro DMA will be ignored (Pending). (1) Micro DMA operation When an interrupt request specified by the micro DMA start vector register is generated, the micro DMA triggers a micro DMA request to the CPU at interrupt priority level 6 and starts processing the request in spite of any interrupt source’s level. The micro DMA is ignored on <IFF2:0> = 7. The 4 micro DMA channels allow micro DMA processing to be set for up to 4 types of interrupts at any one time. When micro DMA is accepted, the interrupt request flip-flop assigned to that channel is cleared. The data are automatically transferred once (1/2/4 bytes) from the transfer source address to the transfer destination address set in the control register, and the transfer counter is decreased by 1 (−1). If the decreased result is 0, the micro DMA transfer end interrupt (INTTC0 to INTTC3) passes from the CPU to the interrupt controller. In addition, the micro DMA start vector register DMAnV is cleared to 0, the next micro DMA is disabled and micro DMA processing completes. If the decreased result is other than 0, the micro DMA processing completes if it isn’t specified the say later burst mode. In this case, the micro DMA transfer end interrupt (INTTC0 to INTTC3) aren’t generated. If an interrupt request is triggered for the interrupt source in use during the interval between the clearing of the micro DMA start vector and the next setting, general-purpose interrupt processing executes at the interrupt level set. Therefore, if only using the interrupt for starting the micro DMA (not using the interrupts as a general-purpose interrupt: level 1 to 6), first set the interrupts level to 0 (Interrupt requests disabled). If using micro DMA and general-purpose interrupts together, first set the level of the interrupt used to start micro DMA processing lower than all the other interrupt levels. (Note) In this case, the cause of general interrupt is limited to the edge interrupt. The priority of the micro DMA transfer end interrupt (INTTC0 to INTTC3) is defined by the interrupt level and the default priority as the same as the other maskable interrupt. Note: If the priority level of micro DMA is set higher than that of other interrupts, CPU operates as follows. In case INTxxx interrupt is generated first and then INTyyy interrupt is generated between checking “Interrupt specified by micro DMA start vector” (in the Figure 3.4.1) and reading interrupt vector with setting below. The vector shifts to that of INTyyy at the time. This is because the priority level of INTyyy is higher than that of INTxxx. In the interrupt routine, CPU reads the vector of INTyyy because cheking of micro DMA has finished. And INTyyy is generated regardless of transfer counter of micro DMA. INTxxx: level 1 without micro DMA INTyyy: level 6 with micro DMA 91C025-42 2007-02-28 TMP91C025 If a micro DMA request is set for more than one channel at the same time, the priority is not based on the interrupt priority level but on the channel number. The smaller channel number has the higher priority (Channel 0 (High) > channel 3 (Low)). While the register for setting the transfer source/transfer destination addresses is a 32-bit control register, this register can only effectively output 24-bit addresses. Accordingly, micro DMA can access 16 Mbytes (the upper eight bits of the 32 bits are not valid). Three micro DMA transfer modes are supported: 1-byte transfer, 2-byte (one word) transfer, and 4-byte transfer. After a transfer in any mode, the transfer source/destination addresses are increased, decreased, or remain unchanged. This simplifies the transfer of data from I/O to memory, from memory to I/O , and from I/O to I/O. For details of the transfer modes, see 3.4.2 (4) Transfer mode register. As the transfer counter is a 16-bit counter, micro DMA processing can be set for up to 65536 times per interrupt source. (The micro DMA processing count is maximized when the transfer counter initial value is set to 0000H.) Micro DMA processing can be started by the 24 interrupts shown in the micro DMA start vectors of Table 3.4.1 and by the micro DMA soft start, making a total of 25 interrupts. Figure 3.4.2 shows the word transfer micro DMA cycle in transfer destination address INC mode (except for counter mode, the same as for other modes). (The conditions for this cycle are based on an external 16-bit bus, 0 waits, trandfer source/transfer destination addresses both even-numberd values). 1 state DM1 Note 1 DM2 DM3 DM4 DM5 Note 2 DM6 DM7 DM8 X1 A0 to A23 Trasfer source address Trasger destination address RD WR / HWR D0 to D15 Input Output Figure 3.4.2 Timing for Micro DMA Cycle States 1 to 3: Instruction fetch cycle (Gets next address code). If 3 bytes and more instruction codes are inserted in the instruction queue buffer, this cycle becomes a dummy cycle. States 4 to 5: Micro DMA read cycle State 6: Dummy cycle (the address bus remains unchanged from state 5) States 7 to 8: Micro DMA write cycle Note 1: If the source address area is an 8-bit bus, it is increased by two states. If the source address area is a 16-bit bus and the address starts from an odd number, it is increased by two states. Note 2: If the destination address area is an 8-bit bus, it is increased by two states. If the destination address area is a 16-bit bus and the address starts from an odd number, it is increased by two states. 91C025-43 2007-02-28 TMP91C025 (2) Soft start function In addition to starting the micro DMA function by interrupts, TMP91C025 includes a micro DMA software start function that starts micro DMA on the generation of the write cycle to the DMAR register. Writing 1 to each bit of DMAR register causes micro DMA once (If write 0 to each bits, micro DMA doesn’t operate). At the end of transfer, the corresponding bit of the DMAR register is automatically cleared to 0. Only one-channel can be set for micro DMA at once. (Do not write 1 to plural bits.) When writing again 1 to the DMAR register, check whether the bit is 0 before writing 1. If read 1, micro DMA transfer isn’t started yet. When a burst is specified by DMAB register, data is continuously transferred until the value in the micro DMA transfer counter is 0 after start up of the micro DMA. If the value in the micro DMA transfer counter is 0 after start up of the micro DMA transfer counter doesn’t change. Don’t use Read-modify-write instruction to avoid writing to other bits by mistake. Symbol DMAR Name Address DMA 89H request (Prohibit register RMW) 7 6 5 4 3 2 DMAR3 DMAR2 1 0 DMAR1 DMAR0 R/W 0 0 0 0 DMA request (3) Transfer control registers The transfer source address and the transfer destination address are set in the following registers in CPU. Data setting for these registers is done by an LDC cr,r instruction. Channel 0 DMAS0 DMA source address register 0: DMAD0 DMA destination address register 0: only use LSB 24 bits. DMAC0 DMAM0 DMA counter register 0: only use LSB 24 bits. 1 to 65536 . DMA mode register 0. Channel 3 DMAS3 DMA source address register 3. DMAD3 DMA destination address register 3. DMAC3 DMAM3 DMA counter register 3. DMA mode register 3. 8 bits 16 bits 32 bits 91C025-44 2007-02-28 TMP91C025 (4) Detailed description of the transfer mode register 8 bits DMAM0 to DMAM3 0 0 0 Mode Note: When setting a value in this register, write 0 to the upper 3 bits. Number of Transfer Bytes 000 000 (fixed) Transfer destination address INC mode 00 Byte transfer ................................................ I/O to memory 01 Word transfer (DMADn+) ← (DMASn) 10 4-bit transfer DMACn ← DMACn − 1 00 Byte transfer ................................................ I/O to memory 01 Word transfer (DMADn−) ← (DMASn) 10 4-bit transfer DMACn ← DMACn − 1 00 Byte transfer ................................................ Memory to I/O 01 Word transfer (DMADn) ← (DMASn+) 10 4-bit transfer DMACn ← DMACn − 1 00 Byte transfer ................................................ Memory to I/O 01 Word transfer (DMADn) ← (DMASn−) 10 4-bit transfer DMACn ← DMACn − 1 00 Byte transfer ........................................................ I/O to I/O 01 Word transfer (DMADn) ← (DMASn−) 10 4-bit transfer DMACn ← DMACn − 1 00 Counter mode 001 444 ns 12 states 667 ns 8 states 444 ns 12 states 667 ns 8 states 444 ns 12 states 667 ns 8 states 444 ns 12 states 667 ns 8 states 444 ns 12 states 667 ns 5 states 278 ns If DMACn = 0, then INTTCn is generated. Transfer source address DEC mode 100 8 states If DMACn = 0, then INTTCn is generated. Transfer source address INC mode 011 Minimum Number of Execution Time Execution States at fc = 36 MHz If DMACn = 0, then INTTCn is generated. Transfer destination address DEC mode 010 101 Mode Description If DMACn = 0, then INTTCn is generated. Fixed address mode If DMACn = 0, then INTTCn is generated. ..................... For counting number of times interrupt is generated DMASn ← DMASn + 1 DMACn ← DMACn − 1 If DMACn = 0, then INTTCn is generated. Note 1: n is the corresponding micro DMA channels 0 to 3 DMADn+/DMASn+: Post-increment (increment register value after transfer) DMADn−/DMASn−: Post-decrement (decrement register value after transfer) The I/Os in the table mean fixed address and the memory means increment (INC) or decrement (DEC) addresses. Note 2: Execution time is under the condition of: 16-bit bus width (both translation and destination address area) /0 waits/ fc = 36 MHz/selected high frequency mode (fc × 1) Note 3: Do not use an undefined code for the transfer mode register except for the defined codes listed in the above table. 91C025-45 2007-02-28 TMP91C025 3.4.3 Interrupt Controller Operation The block diagram in Figure 3.4.3 shows the interrupt circuits. The left-hand side of the diagram shows the interrupt controller circuit. The right-hand side shows the CPU interrupt request signal circuit and the halt release circuit. For each of the 36 interrupt channels there is an interrupt request flag (consisting of a flip-flop), an interrupt priority setting register and a micro DMA start vector register. The interrupt request flag latches interrupt requests from the peripherals. The flag is cleared to 0 in the following cases: • When reset occurs • When the CPU reads the channel vector after accepted its interrupt • When executing an instruction that clears the interrupt (Write DMA start vector to INTCLR register) • When the CPU receives a micro DMA request (When micro DMA is set) • When the micro DMA burst transfer is terminated An interrupt priority can be set independently for each interrupt source by writing the priority to the interrupt priority setting register (e.g. INTE0AD or INTE12). 6 interrupt priorities levels (1 to 6) are provided. Setting an interrupt source’s priority level to 0 (or 7) disables interrupt requests from that source. The priority of non-maskable interrupts (Watchdog timer interrupts) is fixed at 7. If interrupt request with the same level are generated at the same time, the default priority (The interrupt with the lowest priority or, in other words, the interrupt with the lowest vector value) is used to determine which interrupt request is accepted first. The 3rd and 7th bits of the interrupt priority setting register indicate the state of the interrupt request flag and thus whether an interrupt request for a given channel has occurred. The interrupt controller sends the interrupt request with the highest priority among the simulateous interrupts and its vector address to the CPU. The CPU compares the priority value <IFF2:0> in the status register by the interrupt request signal with the priority value set; if the latter is higher, the interrupt is accepted. Then the CPU sets a value higher than the priority value by 1 (+1) in the CPU SR<IFF2:0>. Interrupt request where the priority value equals or is higher than the set value are accepted simultaneously during the previous interrupt routine. When interrupt processing is completed (after execution of the RETI instruction), the CPU restores the priority value saved in the stack before the interrupt was generated to the CPU SR<IFF2:0>. The interrupt controller also has registers (4 channels) used to store the micro DMA start vector. Writing the start vector of the interrupt source for the micro DMA processing (see Table 3.4.1), enables the corresponding interrupt to be processed by micro DMA processing. The values must be set in the micro DMA parameter register (e.g. DMAS and DMAD) prior to the micro DMA processing. 91C025-46 2007-02-28 Micro DMA Counter 0 Interrupt 91C025-47 INTP1 INTTC0 INTTC1 INTTC2 INTTC3 INT1 INT2 INT3 INTALM0 INTALM1 INTALM2 INTALM3 INTALM4 INTTA0 INT0 INTWD RESET D5 D4 D3 D2 D1 D0 Dn + 3 Y1 Y2 Y3 Y4 Y5 Y6 Interrupt request F/F C B A Decoder INTTC0 D Q 6 34 Selector S V = 84H V = 88H V = 8CH V = 90H V = 94H V = 28H V = 2CH V = 30H V = 34H V = 38H V = 3CH V = 40H V = 44H V = 48H V = 4CH 6 V = 20H V = 24H DMA0V DMA1V DMA2V DMA3V Soft start Interrupt vector read Micro DMA acknowledge S Q R Interrupt request F/F D Q CLR Micro DMA start vector setting register Reset Dn + 2 Dn + 1 Dn Q Priority setting register RESET Interrupt vector read S R Interrupt request F/F Interrupt controller 4 1 7 3 2 1 0 B A D2 D3 D4 D5 D6 D7 D0 D1 3 INTRQ2 to 0 2 Interrupt vector read Interrupt vector generator 4 input OR 36 1 A 2 Highest priority B 3 interrupt 4 level select C 5 6 7 Micro DMA channel priority encoder 6 1 Interrupt Priority encoder request signal Interrupt level detect 2 if IFF = 7 then 0 Micro DMA channel specification Micro DMA request INT0, 1, 2, 3, INTKEY, INTRTC, INTALM RESET HALT release During IDLE1 During STOP Interrupt request signal EI 1 to 7 DI RESET if INTRQ2 to 0 ≥ IFF 2 to 0 then 1. 3 3 IFF2:0 Interrupt mask F/F CPU TMP91C025 Figure 3.4.3 Block Diagram of Interrupt Controller 2007-02-28 TMP91C025 (1) Interrupt level setting registers Symbol Name Address INTAD 6 90H enable IADC IADM2 91H enable 92H 0 I2C I2M2 R IA4C INTALM1 INTALM3 93H 0 IA1C IA1M2 R 0 IA3C IA3M2 94H R INTTA1 0 ITA1C ITA1M2 95H INTTA3 0 ITA3C ITA3M2 96H INTKEY enable IA4M0 0 I1M2 0 IKC IKM2 0 R I3C I3M2 I1M0 0 0 IA1M1 IA1M0 IA0C IA0M2 0 I3M1 I3M0 0 0 IA0M1 IA0M0 INTALM0 R R/W 0 0 0 0 IA3M1 IA3M0 IA2C IA2M2 0 0 IA2M1 IA2M0 INTALM2 ITA1M1 ITA3M1 R R/W 0 0 0 0 ITA1M0 ITA0C ITA0M2 0 INTTA0 (TMRA0) ITA0M1 R ITA0M0 R/W 0 0 0 0 ITA3M0 ITA2C ITA2M2 0 INTTA2 (TMRA2) ITA2M1 R ITA2M0 R/W 0 0 0 0 IKM1 IKM0 IRC IRM2 0 0 R/W 0 0 0 IRM1 IRM0 INTRTC R/W 0 I1M1 0 INTKEY 97H 0 R/W 0 R/W 0 0 R 0 R INTRTC INTERTCKEY I1C INTTA3 (TMRA3) enable and IA4M1 R/W 0 I0M0 R/W INT3 0 R INTTA2 INTETA23 0 INTTA1 (TMRA1) enable and 0 R/W 0 I0M1 R R/W 0 INTTA0 INTETA01 I0M2 INTALM3 enable and I2M0 R/W INTALM2 INTEALM23 I0C INTALM1 enable and I2M1 0 0 0 INT1 0 INTALM0 INTEALM01 0 R/W IA4M2 1 R 0 R enable and 2 INTALM4 INT3 and INTALM4 IADM0 R/W 0 INTE3ALM4 3 INT2 INT1 and INT2 4 INT0 IADM1 R 0 INTE12 5 INTAD INT0 and INTE0AD 7 R 0 0 0 R/W 0 0 0 Interrupt request flag lxxM2 lxxM1 lxxM0 Function (Write) 0 0 0 Disables interrupt requests 0 0 1 Sets interrupt priority level to 1 0 1 0 Sets interrupt priority level to 2 0 1 1 Sets interrupt priority level to 3 1 0 0 Sets interrupt priority level to 4 1 0 1 Sets interrupt priority level to 5 1 1 0 Sets interrupt priority level to 6 1 1 1 Disables interrupt requests 91C025-48 2007-02-28 TMP91C025 Symbol Name Address enable 6 ITX0C ITX0M2 5 4 3 2 1 0 ITX0M1 ITX0M0 IRX0C IRX0M2 R R/W IRX0M1 IRX0M0 0 0 0 0 0 IRX1M1 IRX1M0 INTTX0 Interrupt INTES0 7 98H R serial 0 0 INTRX0 R/W 0 0 INTTX1 INTRX1 & INTES1 INTTX1 99H ITXT1C ITX1M2 ITX1M1 R enable 0 INTRX1 ITX1M0 R/W 0 IRX1C IRX1M2 R 0 0 0 R/W 0 INTELCD INTLCD enable 9AH ILCD1C ILCDM2 ILCDM1 R 0 ILCDM0 − 0 − − − R/W 0 0 INTTC0 & 9BH ITC1C ITC1M2 0 ITC1M0 R/W 0 ITC0C ITC0M2 INTTC2 & 9CH ITC3C 0 0 0 9DH IP1C R 0 0 R/W 0 0 ITC2C ITC2M2 ITC2M1 ITC2M0 0 R/W 0 0 0 IP0M1 IP0M0 INTP0 IP1M1 IP1M0 R/W 0 ITC0M0 R 0 IP1M2 ITC0M1 0 INTP1 INTP0 & enable ITC3M0 R/W 0 − INTTC2 ITC3M1 R enable INTEP01 INTP1 ITC3M2 − − R 0 INTTC3 INTETC23 INTTC3 − INTTC0 ITC1M1 R enable 0 − − INTTC1 INTETC01 INTTC1 0 − INTLCD IP0C IP0M2 R 0 0 0 R/W 0 0 0 Interrupt request flag lxxM2 lxxM1 lxxM0 Function (Write) 0 0 0 Disables interrupt requests 0 0 1 Sets interrupt priority level to 1 0 1 0 Sets interrupt priority level to 2 0 1 1 Sets interrupt priority level to 3 1 0 0 Sets interrupt priority level to 4 1 0 1 Sets interrupt priority level to 5 1 1 0 Sets interrupt priority level to 6 1 1 1 Disables interrupt requests 91C025-49 2007-02-28 TMP91C025 (2) External interrupt control Symbol Name Address 7 6 5 4 3 2 1 0 − − I3EDGE I2EDGE I1EDGE I0EDGE I0LE − 0 0 0 0 0 0 0 0 Interrupt IIMC W 8CH input mode control (Prohibit Always Always INT3EDGE INT2EDGE INT1EDGE INT0EDGE INT0 mode Always write 0. write 0. 0: Rising 0: Rising 0: Rising 0: Rising 0: Edge 1: Falling 1: Falling 1: Falling 1: Falling 1: Level RMW) write 0. INT0 level enable 0 edge detect INT 1 High level INT (3) Interrupt request flag clear register The interrupt request flag is cleared by writing the appropriate micro DMA start vector, to the register INTCLR. For example, to clear the interrupt flag INT0, perform the following register operation after execution of the DI instruction. INTCLR ← 0AH: Clears interrupt request flag INT0. Symbol Name Address Interrupt INTCLR clear control 7 6 5 4 3 2 1 0 CLRV5 CLRV4 CLRV3 CLRV2 CLRV1 CLRV0 0 0 0 0 0 0 88H (Prohibit W RMW) Interrupt Vector (4) Micro DMA start vector registers This register assigns micro DMA processing to which interrupt source. The interrupt source with a micro DMA start vector that matches the vector set in this register is assigned as the micro DMA start source. When the micro DMA transfer counter value reaches zero, the micro DMA transfer end interrupt corresponding to the channel is sent to the interrupt controller, the micro DMA start vector register is cleared, and the micro DMA start source for the channel is cleared. Therefore, to continue micro DMA processing, set the micro DMA start vector register again during the processing of the micro DMA transfer end interrupt. If the same vector is set in the micro DMA start vector registers of more than one channel, the channel with the lowest number has a higher priority. Accordingly, if the same vector is set in the micro DMA start vector registers of two channels, the interrupt generated in the channel with the lower number is executed until micro DMA transfer is complete. If the micro DMA start vector for this channel is not set again, the next micro DMA is started for the channel with the higher number. (Micro DMA chaining.) 91C025-50 2007-02-28 TMP91C025 Symbol Name Address 7 6 DMA0 DMA0V start 5 4 3 DMA0V5 DMA0V4 DMA0V3 2 1 0 DMA0V2 DMA0V1 DMA0V0 0 0 DMA1V1 DMA1V0 0 0 DMA2V1 DMA2V0 0 0 DMA3V1 DMA3V0 0 0 R/W 80H 0 vector 0 0 0 DMA0 start vector DMA1 DMA1V start DMA1V5 DMA1V4 DMA1V3 0 0 0 DMA1V2 R/W 81H vector 0 DMA1 start vector DMA2V5 DMA2 DMA2V start DMA2V4 DMA2V3 DMA2V2 R/W 82H 0 0 0 DMA3V5 DMA3V4 DMA3V3 0 0 0 vector 0 DMA2 start vector DMA3 DMA3V start DMA3V2 R/W 83H vector 0 DMA3 start vector (5) Micro DMA burst specification Specifying the micro DMA burst continues the micro DMA transfer until the transfer counter register reaches zero after micro DMA start. Setting a bit which corresponds to the micro DMA channel of the DMAB registers mentioned below to 1 specifies a burst. Symbol Name DMA DMAR software request register Address 7 6 5 89H (Prohibit RMW) burst 3 2 1 0 DMAR3 DMAR2 DMAR1 DMAR0 R/W R/W R/W R/W 0 0 0 0 1: DMA software request DMAB3 DMA DMAB 4 DMAB2 DMAB1 DMAB0 0 0 R/W 8AH 0 register 0 1: DMA burst request 91C025-51 2007-02-28 TMP91C025 (6) Attention point The instruction execution unit and the bus interface unit of this CPU operate independently. Therefore, immediately before an interrupt is generated, if the CPU fetches an instruction that clears the corresponding interrupt request flag, the CPU may execute the instruction that clears the interrupt request flag (Note) between accepting and reading the interrupt vector. In this case, the CPU reads the default vector 0008H and reads the interrupt vector address FFFF08H. To avoid the avobe plogram, place instructions that clear interrupt request flags after a DI instruction. And in the case of setting an interrupt enable again by EI instruction after the execution of clearing instruction, execute EI instruction after clearing and more than 1-instructions (ex. “NOP” × 1 times) In the case of changing the value of the interrupt mask register <IFF2:0> by execution of POP SR instruction, disable an interrupt by DI instruction before execution of POP SR instruction. In addition, take care as the following 2 circuits are exceptional and demand special attention. INT0 level mode In level mode INT0 is not an edge-triggered interrupt. Hence, in level mode the interrupt request flip-flop for INT0 does not function. The peripheral interrupt request passes through the S input of the flip-flop and becomes the Q output. If the interrupt input mode is changed from edge mode to level mode, the interrupt request flag is cleared automatically. If the CPU enters the interrupt response sequence as a result of INT0 going from 0 to 1, INT0 must then be held at 1 until the interrupt response sequence has been completed. If INT0 is set to level mode so as to release a halt state, INT0 must be held at 1 from the time INT0 changes from 0 to 1 until the halt state is released. (Hence, it is necessary to ensure that input noise is not interpreted as a 0, causing INT0 to revert to 0 before the halt state has been released.) When the mode changes from level mode to edge mode, interrupt request flags which were set in level mode will not be cleared. Interrupt request flags must be cleared using the following sequence. DI LD (IIMC), 00H ; Switches interrupt input mode from level mode to edge mode. LD (INTCLR), 0AH ; Clears interrupt request flag. NOP ; Wait EI instruction EI INTRX The interrupt request flip-flop can only be cleared by a reset or by reading the serial channel receive buffer. It cannot be cleared by writing INTCLR register. Note: The following instructions or pin input state changes are equivalent to instructions that clear the interrupt request flag. INT0: Instructions which switch to level mode after an interrupt request has been generated in edge mode. The pin input change from high to low after interrupt request has been generated in level mode. (H → L) INTRX: Instruction which read the receive buffer. 91C025-52 2007-02-28 TMP91C025 3.5 Port Functions The TMP91C025 features 38-bit settings which relate to the various I/O ports. As well as general-purpose I/O port functionality, the port pins also have I/O functions which relate to the built-in CPU and internal I/Os. Table 3.5.1 lists the functions of each port pin. Table 3.5.2, Table 3.5.4 lists I/O registers and their specifications. Table 3.5.1 Port Functions (R: PU = with programmable pull-up resistor/U = with pull-up resistor) Port Name Pin Name Number of Pins Direction R Direction Setting Unit Pin Name for Built-in Function Port 1 P10 to P17 8 I/O − Bit D8 to D15 Port 2 P20 to P27 8 Output A16 to A23 P56 1 I/O − PU (Fixed) Port 5 Port 6 P60 1 Output − (Fixed) CS0 P61 1 Output − (Fixed) CS1 P62 1 Output − (Fixed) CS2 , CS2A P63 1 Output − (Fixed) CS3 Bit WAIT P64 1 Output − (Fixed) EA24, CS2B , SRLB P65 1 Output − (Fixed) EA25, CS2C , SRUB P80 P81 1 1 Input Input − − (Fixed) (Fixed) AN0 AN1 P82 1 Input − (Fixed) P83 1 Input − (Fixed) AN2, MX AN3, ADTRG , MY P90 to P97 8 Input U (Fixed) KI0 to KI7 Port A PA0 1 Output − (Fixed) KO0, ALARM , MLDALM Port B PA1 PA2 PA3 PB3 1 1 1 1 Output Output Output I/O − − − − (Fixed) (Fixed) (Fixed) Bit KO1, TA1OUT KO2, TA3OUT KO3, SCOUT INT0, PS Port 8 Port 9 Port C Port D Port Z PB4 1 I/O − Bit PB5 1 Input − (Fixed) INT2, PX PB6 1 Input − (Fixed) INT3, PY PC0 PC1 1 1 I/O I/O Bit Bit INT1, TA0IN PC2 1 I/O − − PU Bit TXD0 RXD0 SCLK0, CTS0 PC3 1 I/O − Bit TXD1 PC4 1 I/O Bit PC5 1 I/O − PU RXD1 SCLK1, CTS1 PD0 1 Output − (Fixed) D1BSCP PD1 1 Output − (Fixed) D2BLP PD2 1 Output − (Fixed) D3BFR PD3 1 Output − (Fixed) DLEBCD PD4 1 Output − (Fixed) DOFFB PD7 1 Output − (Fixed) MLDALM PZ2 PZ3 1 1 I/O I/O PU PU Bit Bit 91C025-53 Bit HWR R/ W , SRWR 2007-02-28 TMP91C025 Table 3.5.2 I/O Registers and Specifications (1/2) Port Port 1 Pin Name Port 5 Port 6 Port 8 Port 9 Port A PnCR Input port X 0 Output port X 1 D8 to D15 bus X X Output port X None A16 to A23 output X WAIT input (Without PU) 0 0 WAIT input (With PU) 1 0 X 0 0 P60 Output port CS0 output X 1 None P61 CS1 output X 1 P62 CS2 output X 1 P10 to P17 P20 to P27 P56 P60 to P65 PnFC PnFC2 None 0 None 1 None 0 CS2A output X X 1 P63 CS3 output X 1 None P64 SRLB output X 0 1 CS2B output X 1 1 X 1 0 P65 EA24 output SRUB output X 0 1 CS2C output X 1 1 EA25 output X 1 0 None P80 to P83 Input port P83 AN0 to 3 input ADTRG input P90 to P97 Input port X KI0 to 7 input X Output port X 0 0 KO0 to 3 output (CMOS) X 0 0 KO0 to 3 output (Open drain) X 1 0 ALARM output 1 0 1 MLDALM output 0 0 1 PA1 TA1OUT output X 0 1 PA2 TA3OUT output X 0 1 PA3 SCOUT output X 0 1 PB3 to PB4 Input port X PA0 to PA3 PA0 Port B I/O Register Pn (Note 1) Port 2 Specification X: Don’t care X (Note 2) (Note 3) None X None X None None 0 0 1 0 Output port X 1 0 PB3 INT0 input PS input X 0 1 X 0 X PB4 INT1 input X 0 1 TA0IN input X 0 X INT2 input X 0 1 PX output X 0 None INT3 input X 0 1 PY output X 0 None PB5 PB6 91C025-54 None 2007-02-28 TMP91C025 Table 3.5.3 I/O Registers and Specifications (2/2) Port Port C Pin Name Specification Port Z I/O Register Pn PnCR X 0 PnFC PnFC2 PC0 to PC5 Input port X 1 0 PC0 TXD0 output (Note 4) 1 1 1 PC1 RXD0 input (Note 4) 1 0 None PC2 SCLK0 input (Note 4) 1 0 0 SCLK0 output (Note 4) 1 1 1 CTS0 input (Note 4) 1 0 0 Output port Port D X: Don’t care 0 PC3 TXD1 output (Note 4) 1 1 1 PC4 RXD1 input (Note 4) 1 0 None PC5 SCLK1 input (Note 4) 1 0 0 SCLK1 output (Note 4) 1 1 1 CTS1 input (Note 4) 1 0 0 PD0 to PD7 Output port X 0 PD0 D1BSCP output X 1 PD1 D2BLP output X 1 PD2 D3BFR output X PD3 DLEBCD output X None None 1 1 PD4 DOFFB output X 1 PD7 MLDALM output X 1 PZ2 to PZ3 Input port X 0 0 Output port X 1 0 PZ2 HWR output X 1 1 PZ3 R/ W output X 0 1 SRWR output X 1 1 Note 1: Port1 is only use for port or DATA bus (D8 to D15) by setting AM1 and AM0 pins. Note 2: In case using P80 to P83 for analog input ports of AD converter, set to ADMOD1<ADCH2:0>. Note 3: In case using P83 for ADTRG input port, set to ADMOD1<ADTRGE>. Note 4: As for input ports of SIO0 and SIO1: (TXD0, RXD0, SCLK0, CTS0 , TXD1, RXD1, SCLK1, CTS1 ), logical selection for output data or input data is determined by the output latch register Pn of each port. 91C025-55 2007-02-28 TMP91C025 Port 1 (P10 to P17) Port 1 is an 8-bit general-purpose I/O port. Each bit can be set individually for input or output using the control register P1CR. Resetting , the control register P1CR to 0 and sets port 1 to input mode. In addition to functioning as a general-purpose I/O port, port 1 can also function as an address data bus (D8 to 15). Table 3.5.4 Function Setting of AM0/AM1 AM1 AM0 Function Setting after Reset 0 0 Input port 0 1 Data bus (D8 to D15) 1 0 Don’t use this setting 1 1 Don’t use this setting Reset Direction control (on bit basis) P1CR write Output Latch Internal data bus 3.5.1 Output buffer Port 1 P10 to P17 (D8 to D15) P1 write P1 Read Figure 3.5.1 Port 1 91C025-56 2007-02-28 TMP91C025 Port 2 (P20 to P27) Port 2 is an 8-bit output port. In addition to functioning as a output port, port 2 can also function as an address bus (A16 to A23). Each bit can be set individually for address bus using the function register P2FC. Resetting sets all bits of the function register P2FC to 1 and sets port 2 to address bus. Reset S Function control (on bits basis) P2FC write S Output A latch B P2 write selector Internal data bus 3.5.2 Output buffer Port 2 P20 to P27 (A16 to A23) P2 read Internal A16 to A23 Figure 3.5.2 Port 2 91C025-57 2007-02-28 TMP91C025 Port 1 Register P1 P0 (0000H) (0001H) Bit symbol 7 6 5 4 P17 P16 P15 P14 3 2 1 0 P13 P12 P11 P10 Read/Write R/W After reset Data from external port (Output latch register is cleared to 0.) Port 1 Control Register P1CR (0004H) Bit symbol 7 6 5 4 P17C P16C P15C P14C Read/Write After reset (Note2) 3 2 1 0 P13C P12C P11C P10C 0/1 0/1 0/1 0/1 W 0/1 0/1 0/1 Function 0/1 0: Input 1: Output Port 1 I/O setting 0: Input 1: Output Port 2 Register P2 (0006H) Bit symbol 7 6 5 4 3 2 1 0 P27 P26 P25 P24 P23 P22 P21 P20 1 1 1 1 1 1 1 1 3 2 1 0 P23F P22F P21F P20F 1 1 1 1 Read/Write After reset R/W Port 2 Function Register P2FC (0009H) Bit symbol 7 6 5 4 P27F P26F P25F P24F Read/Write After reset Function W 1 1 1 1 0: Port 1: Address bus (A23 to A16) Note1: Read-modify-write is prohibited for P1CR and P2FC. Note2: It is set to “Port” or “Data bus” by AM pins state. Figure 3.5.3 Registers for Ports 1 and 2 91C025-58 2007-02-28 TMP91C025 Port Z (PZ2 to PZ3) Port Z is an 2-bit general-purpose I/O port. I/O is set using control register PZCR and PZFC. Resetting sets all bits of the output latch PZ to 1. In addition to functioning as a general-purpose I/O port, port Z also functions as I/O for the CPU’s control/status signal. Resetting initializes PZ2 and PZ3 pins to input mode with pull-up register. Reset Direction control (on bit basis) PZCR write Function conrtol (on bit basis) PZFC write P-ch (Programmable pull up) S S Output latch A B Selector Internal data bus 3.5.3 PZ2 ( HWR ) Output buffer PZ write HWR PZ read Figure 3.5.4 Port Z2 91C025-59 2007-02-28 TMP91C025 Reset Direction control (on bit basis) PZCR write Function conrtol P-ch (Programmable pull up) PZFC write S S Output latch PZ write A B C PZ3 (R/ W , SRWR ) Selector Internal data bus (on bit basis) Output buffer R/W SRWR PZ read Figure 3.5.5 Port Z3 91C025-60 2007-02-28 TMP91C025 Port Z register 7 PZ (007DH) 6 5 4 3 Bit symbol 2 PZ3 1 0 1 0 1 0 PZ2 Read/Write R/W After reset Data from external port Function 0(Output latch register) (Note 1) : Pull-up resistor OFF 1(Output latch register) : Pull-up resistor ON Port Z control register 7 PZCR (007EH) 6 5 4 Bit symbol 3 2 PZ3C Read/Write PZ2C W After reset 0 Function 0 0: Input 1: Output Port Z function register 7 PZFC (007FH) 6 5 4 Bit symbol 3 2 PZ3F Read/Write PZ2F W After reset 0 Function 0: Port 1: R/ W , 0 0: Port 1: HWR SRWR Note 1: Note 2: Note 3: Output latch register is set to 1. Read-modify-write is prohibited for registers PZCR and PZFC. When port Z is used in Input mode, the PZ register controls the built-in pull-up resistor. Read-modify-write is prohibited in input mode or I/O mode. Setting the built-in pull-up resistor may be depended on the states of the input pin. R/W, SRWR setting <PZ3C> 0 1 0 Input Output 1 R/W SRWR <PZ3F> Figure 3.5.6 Registers for Port Z 91C025-61 2007-02-28 TMP91C025 Port 5 (P56) Port 5 is an 1-bit general-purpose I/O port. I/O is set using control register P5CR and P5FC. Resetting sets all bits of the output latch P5 to 1. In addition to functioning as a general-purpose I/O port, port 5 also functions as I/O for the CPU’s control/status signal. Resetting initializes P56 pins to input mode with pull-up resistor. Reset Direction control (on bit basis) P-ch (Programmable pull up) P5CR write Internal data bus 3.5.4 S Output Latch P56 ( WAIT ) Output buffer P5 write Internal WAIT P5 read Figure 3.5.7 Port 5 (P56) 91C025-62 2007-02-28 TMP91C025 Port 5 register 7 P5 (000DH) 6 5 Bit symbol P56 Read/Write R/W After reset Data from external port (Output latch register is set to 1.) 0(Output latch register) : Pull-up resistor OFF 1(Output latch register) : Pull-up resistor ON Function 4 3 2 1 0 3 2 1 0 Port 5 control register 7 P5CR (0010H) 6 5 Bit symbol P56C Read/Write W After reset 0 Function 4 0: Input 1: Output Note1: Read-modify-write is prohibited for registers P5CR. Note2: When the P56/WAIT pin is to be use as the WAIT pin, P5CR<P56C> must be set to 0 and <BnW2:0> in the chip select/wait control register must be set 010. Figure 3.5.8 Registers for Port 5 91C025-63 2007-02-28 TMP91C025 Port 6 (P60 to P65) Port 60 to 65 are 6-bit output ports. Resetting sets output latch of P62 to “0” and output latches of P60 to P61, P63 to P65 to 1. Port6 also function as chip-select output ( CS0 to CS3 ), extend address output (EA24, EA25) and extend chip-select output ( CS2A , CS2B and CS2C ). Writing 1 in the corresponding bit of P6FC, P6FC2 enables the respective functions. Resetting resets the P6FC, P6FC2 to 0, and sets all bits to output ports. Reset Function control 2 (on bit basis) P6FC2 write Internal data bus 3.5.5 Funtion control (on bit basis) P6FC write S Output lacth P6 write P6 read A B C Selector D P60 ( CS0 ), P61 ( CS1 ), P62 ( CS2 , CS2A ), P63 ( CS3 ), P64 (EA24, CS2B , SRLB ), P65 (EA25, CS2C , SRUB ) 1,1,1,1, SRLB SRUB 1,1, CS2A ,1, CS2B , CS2C CS0 , CS1 , CS2 , CS3 , EA24, EA25 Figure 3.5.9 Port 6 91C025-64 2007-02-28 TMP91C025 Port 6 Register 7 P6 (0012H) 6 Bit symbol 5 4 3 P65 P64 P63 Read/Write 2 1 0 P62 P61 P60 0 1 1 2 1 0 P62F P61F P60F 0 0 0 R/W After reset 1 1 1 Port 6 Function Register 7 P6FC (0015H) 6 Bit symbol 5 4 3 P65F P64F P63F Read/Write W After reset 0 Function 0 0 0: Port 0: Port 1: EA25 1: EA24 0: Port 1: CS3 0: Port 1: CS2 0: Port 1: CS1 0: Port 1: CS0 Port 6 Function Register 2 7 P6FC2 (001BH) 6 Bit symbol 5 4 3 2 1 0 P65F2 P64F2 − P62F2 − − W W W W 0 0 0 0 Read/Write W After reset 0 Function 0 0: <P65F> 0: <P64F> Always 1: SRUB , 1: SRLB , write 0. CS2C , CS2B , EA25 EA24 SRLB , CS2B , EA24 setting SRUB , CS2C , EA25 setting <P65F> <P64F> 0 1 0 1 0 P64 EA24 1 SRLB CS2B 1 <P64F2> <P65F2> 0 Always write 0. 0: <P62F> 1: CS2A P65 SRUB EA25 CS2C Note: Read-modify-write is prohibited for P6FC and P6FC2. Figure 3.5.10 Registers for Port 6 91C025-65 2007-02-28 TMP91C025 3.5.6 Port 8 (P80 to P83) Internal data bus Port 8 is a 4-bit input port and can also be used as the analog input pins for the internal AD converter. P83 can also be used as ADTRG pin for the AD converter. P82, P83 can also be used as MX, MY pin for touch screen interface. Port 8 P80 to P83 (AN0 to AN3) Port 8 read Conversion result register AD Channel converter selector AD Read ADTRG (for P83 only) TSICR0<MXEN, MYEN > (for P82, P83 only) TSICR0<TSI7 > Figure 3.5.11 Port 8 Port 8 Register 7 P8 (0018H) 6 5 4 Bit symbol 3 2 P83 P82 1 0 P81 P80 Read/Write R After reset Data from external port. Note: The input channel selection of AD Converter, the permission of ADTRG input are set by AD Converter mode register ADMOD1. The input channel selection of AD Converter, the permission of MX, MY input are set by touch screen control register TSICR. Figure 3.5.12 Registers for Port 8 91C025-66 2007-02-28 TMP91C025 3.5.7 Port 9 (P90 to P97) Port 90 to 97 are 8-bit input ports with pull-up resistors. In addition to functioning as general-purpose I/O port, port 90 to 97 can also Key-on wakeup function as Key board interface. The various functions can each be enabled by writing 1 to the corresponding bit of the port 9 function register (P9FC). Resetting resets all bits of the register P9FC to 0 and sets all pins to be input port. INTKEY P90 to P97 8-OR Internal data bus Rising edge detection Reset Key-on enable (on bit basis) Pull-up resistor P9FC write P90 to P97 (KI0 to KI7) P9 read Figure 3.5.13 Port 9 When P9FC = 1, if either of input of KI0 to KI7 pins falls down, INTKEY interrupt is generated. INTKEY interrupt can be used to release all HALT mode. Port 9 register P9 (0019H) Bit symbol 7 6 5 4 P97 P96 P95 P94 3 2 1 0 P93 P92 P91 P90 3 2 1 0 P93F P92F P91F P90F 0 0 0 0 Read/Write R After reset Data from external port. Port 9 function register P9FC (001DH) Bit symbol 7 6 5 4 P97F P96F P95F P94F Read/Write After reset Function W 0 0 0 0 0: Key-in disable 1: Key-in enable Key-in of Port 9 Disable 0 Enable 1 Note: Read-modify-write is prohibited for the registers P9FC. Figure 3.5.14 Registers for Port 9 91C025-67 2007-02-28 TMP91C025 Port A (PA0 to PA3) Port A0 to PA3 are 4-bit output ports, and also used Key board interface pin KO0 to KO3 which can set open drain output buffer. Writing 1 to the corresponding bit of the port A function register (PAFC) enable the open drain output. In addition to functioning as output port, port A also function as output pin for internal clock (SCOUT), output pin for RTC alarm ( ALARM ) and output pin for melody/alarm generator (MLDALM, MLDALM ). Above setting is used the function register PAFC2 Resetting reset bits of the registers PA to 1 and PAFC, PAFC2 to 0, and all pin outputs 1. Reset Function control PAFC2 write Internal data bus 3.5.8 Output buffer set PAFC write S Programmable open drain A S Y Selector B Output latch PA write PA0 (KO0, ALARM , MLDALM ) PA read MLDALM ALARM A S Y Selector B Figure 3.5.15 Port A0 91C025-68 2007-02-28 TMP91C025 Reset Function control Internal data bus PAFC2 write Output buffer set PAFC write S A S Programmable open drain PA1 (KO1, TA1OUT) PA2 (KO2, TA3OUT) Y Selector B Output latch PA write PA read TA1OUT TA3OUT Figure 3.5.16 Port A1, 2 Reset Function control Internal data bus PAFC2 write Output buffer set PAFC write S S Output latch A Y Selector B Programmable open drain PA3 (KO3, SCOUT) PA write PA read fFPH clock Figure 3.5.17 Port A3 91C025-69 2007-02-28 TMP91C025 Port A register 7 PA (001EH) 6 5 4 Bit symbol 3 2 1 0 PA3 PA2 PA1 PA0 1 1 1 3 2 1 0 PA3F PA2F PA1F PA0F 0 0 Read/Write R/W After reset 1 Port A function register 7 PAFC (0021H) 6 5 4 Bit symbol Read/Write W After reset 0 Function 0: CMOS output 1: Open drain 7 PAFC2 (0020H) 0 6 5 4 Bit symbol 3 2 PA3F2 PA2F2 Read/Write 1 0 PA1F2 PA0F2 W After reset 0 Function 0 0 0 0: Port 0: Port 0: Port 0: Port 1: SCOUT 1: TA3OUT 1: TA1OUT 1: ALARM at <PA0>=1 1: MLDALM at <PA0>=0 Note: Read-modify-write is prohibited for PAFC and PAFC2. Figure 3.5.18 Registers for Port A 91C025-70 2007-02-28 TMP91C025 3.5.9 Port B (PB3 to PB6) Port B3 to PB6 is a 4-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets port B to be an input port. In addition to functioning as a general-purpose I/O port, port B3 to B6 has each external interruption input facility of INT0 to INT3. Edge selection of external interruption is establishes by IIMC register in the interrupt controller. And also, port B3 has PS input terminal, and port B4 has clock input terminal TA0IN of 8 bits timer 0, and port B5, B6 each has touch screen block listing PX, PY terminal. Timer output function and external interrupt function can be enabled by writing 1 to the corresponding bits in the port B function register (PBFC). Resetting resets all bits of the registers PBCR and PBFC to 0, and sets all bits to be input ports. (1) PB3 (INT0) Reset Direction control (on bits basis) PBCR write Internal data bus Function control (on bits basis) PBFC write S Output latch PB3 (INT0, PS ) PB write S B Selector PB read INT0 A Level/edge select and Rising/falling select IIMC<I0LE, I0EDGE> PS SYSCR2<PSENV> Figure 3.5.19 Port B3 Note: After reset, input 1 to PB3 (INT0, PS ) -pin, because it is worked as PS input pin. 91C025-71 2007-02-28 TMP91C025 (2) PB4 (INT1) Reset Direction control (on bits basis) PBCR write Internal data bus Function control (on bits basis) PBFC write S Output latch PB4 (INT1, TA0IN) PB write S B Selector PB read INT1 A Rising/falling edge detection IIMC<I1EDGE > TA0IN Figure 3.5.20 Port B4 91C025-72 2007-02-28 TMP91C025 (3) PB5 (INT2), PB6(INT3) Internal data bus Reset Function control AVCC (on bits basis) PBFC write TSICR0<PXEN> <PYEN> P-ch TSICR0<TSI7> PB5 (INT2, PX) PB6 (INT3, PY) PB read TSICR1<DBC7> S . INT2 INT3 Rising/falling edge detection IIMC<I2EDGE, I3EDGE > Only for PB5 A Selector Debounce circuit B TSICR0<TWIEN, TSI7> TSICR0<PXEN> TSICR<TSI7> N channel Pull-down resistor Figure 3.5.21 Port B5, B6 91C025-73 2007-02-28 TMP91C025 Port B Register 7 PB (0022H) Bit symbol 6 5 PB6 PB5 4 3 PB4 PB3 Read/Write R/W After reset Data from external port (Note 1). 2 1 0 2 1 0 2 1 0 Port B Control Register 7 PBCR (0024H) 6 5 4 Bit symbol 3 PB4C Read/Write PB3C W After reset 0 Function 0 0: Input 1: Output Port B Function Register 7 PBFC (0025H) Bit symbol 6 5 4 3 PB6F PB5F PB4F PB3F 0 0 Read/Write After reset Function W 0 1 0: Port 0: Port 0: Port 0: Port 1: INT3 1: INT2 1: INT1 1: INT0 Note 1: Output latch register is set to 1. Note 2: Read-modify-write is prohibited for the registers PBCR and PBFC. Note 3: PB4/TA0IN pins do not have a register changing port/function . For example, when it is used as an input port, the input signal is inputted to 8-bit timer 0 as the timer input 0. Figure 3.5.22 Registers for Port B 91C025-74 2007-02-28 TMP91C025 Port C (PC0 to PC5) Port C0 to C5 are 6-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets PC0 to PC5 to be an input ports. It also sets all bits of the output latch register to 1. In addition to functioning as general-purpose I/O port pins, PC0 to PC5 can also function as the I/O for serial channels 0 and 1. A pin can be enabled for I/O by writing 1 to the corresponding bit of the port C function register (PCFC). Resetting resets all bits of the registers PCCR and PCFC to 0 and sets all pins to be input ports . (1) Port C0, C3 (TXD0/TXD1) As well as functioning as I/O port pins, port C0 and C3 can also function as serial channel TXD output pins. In case of use TXD0/TXD1, it is possible to logical invert by setting the register PC<PC0, PC3>. And port C0 to C3 have a programmable open drain function which can be controlled by the register PCODE<ODEPC0, ODEPC3>. Reset Ditection control (on bit basis) PCCR write Function control Internal data bus 3.5.10 (on bit basis) PCFC write S Output latch A S PC0 (TXD0) PC3 (TXD1) Selector PC write Logical invert B S TXD0, TXD1 Open-drain set possible B PCODE<ODEPC0, C3> PC Read Selector A Figure 3.5.23 Port C0 and C3 91C025-75 2007-02-28 TMP91C025 (2) Port C1, C4 (RXD0, RXD1) Port C1 and C4 are I/O port pins and can also is used as RXD input for the serial channels. In case of use RXD0/RXD1, it is possible to logical invert by setting the register PC<PC1, PC4>. Reset Ditection control Internal data bus (on bit basis) PCCR write S PC1 (RXD0) PC4 (RXD1) Output latch S PC write B Selector PC read A RXD0, RXD1 Logical invert Figure 3.5.24 Port C1 and C4 (3) Port C2 ( CTS0 , SCLK0), C5 ( CTS1 , SCLK1) Port C2 and C5 are I/O port pins and can also is used as CTS input or SCLK input/output for the serial channels. In case of use CTS , SCLK, it is possible to logical invert by setting the register PC<PC2, PC5>. Reset Ditection control (on bit basis) Internal data bus PCCR write Function control (Programmable pull-up) (on bit basis) PCFC write S Output latch A Selector PC write SCLK0, 1 output PC2 (SCLK0, CTS0 ) PC5 (SCLK1, CTS1 ) S B Logical invert S B Selector PC read CTS0 , CTS1 SCLK0, SCLK 1 input A Logical invert Figure 3.5.25 Port C2 and C5 91C025-76 2007-02-28 TMP91C025 Port C Register 7 PC (0023H) 6 Bit symbol 5 4 3 PC5 PC4 PC3 2 1 0 PC2 PC1 PC0 Read/Write R/W After reset Data from external port (Output latch register is set to 1). Port C Control Register 7 PCCR (0026H) 6 Bit symbol 5 4 3 PC5C PC4C PC3C Read/Write 2 1 0 PC2C PC1C PC0C 0 0 0 1 0 W After reset 0 0 Function 0 0: Input 1: Output Port C Functon Register 7 PCFC (0027H) 6 5 4 3 2 Bit symbol PC5F PC3F PC2F PC0F Read/Write W W W W After reset 0 0 0 0: Port 0: Port 0: Port 0: Port 1: SCLK1 1: TXD1 1: SCLK0 1: TXD0 Function output 0 output Port C ODE Register 7 PCODE (0028H) 6 5 4 3 2 1 0 Bit symbol ODEPC3 ODEPC0 Read/Write W W After reset 0 0 TXD1 TXD0 0: CMOS 0: CMOS 1: Open 1: Open drain drain Function Note 1: Note 2: Read-modify-write is prohibited for the registers PCCR, PCFC and PCODE. PC1/RXD0, PC4/RXD1 pins do not have a register changing port/function. For example, when it is used as an input port, the input signal is inputted to SIO as the cereal receive data. Figure 3.5.26 Registers for Port C 91C025-77 2007-02-28 TMP91C025 3.5.11 Port D (PD0 to PD4, PD7) Port D is a 6-bit output port. Resetting sets the output latch PD to “1”, and PD0 to PD4, PD7 pin output “1”. In addition to functioning as output port, port D also function as output pin for LCD controller (D1BSCP, D2BLP, D3BFR, DLEBCD and DOFFB) and output pin for melody/alarm generator (MLDALM). Above setting is used the function register PDFC. Reset (on bit basis) PDFC write PD0 (D1BSCP), PD1 (D2BLP), PD2 (D3BFR), PD3 (DLEBCD), PD4 (DOFFB), PD7 (MLDALM) S A Output latch B Selector Internal data bus Function control Output buffer PD write D1BSCP, D2BLP, D3BFR, DLEBCD, DOFFB, MLDALM PD read Figure 3.5.27 Port D Port D register 7 PD (0029H) 6 5 4 3 2 1 0 Bit symbol PD7 PD4 PD3 PD2 PD1 PD0 Read/Write R/W R/W R/W R/W R/W R/W After reset 1 1 1 1 1 1 4 3 2 1 0 Port D function register 7 PDFC (002AH) 6 5 Bit symbol PD7F PD4F PD3F PD2F PD1F PD0F Read/Write W W W W W W After reset Function 0 0 0 0 0 0 0: Port 0: Port 0: Port 0: Port 0: Port 0: Port 1: MLDALM 1: DOFFB 1: DLEBCD 1: D3BFR 1: D2BLP 1: D1BSCP Note: Read-modify-write is prohibited for the registers PDFC. Figure 3.5.28 Registers for Port D 91C025-78 2007-02-28 TMP91C025 3.6 Chip Select/Wait Controller On the TM91C025, four user-specifiable address areas (CS0 to CS3) can be set. The data bus width and the number of waits can be set independently for each address area (CS0 to CS3 and others). The pins CS0 to CS3 (which can also function as port pins P60 to P63) are the respective output pins for the areas CS0 to CS3. When the CPU specifies an address in one of these areas, the corresponding CS0 to CS3 pin outputs the chip select signal for the specified address area (in ROM or SRAM). However, in order for the chip select signal to be output, the port 6 function register P6FC must be set. CS2A to CS2C (CS pin except CS0 to CS3 ) are made by MMU. These pins is CS pin that area and BANK value is fixed without concern in setting of CS/WAIT controller. The areas CS0 to CS3 are defined by the values in the memory start address registers MSAR0 to MSAR3 and the memory address mask registers MAMR0 to MAMR3. The chip select/wait control registers B0CS to B3CS and BEXCS should be used to specify the master enable/disable status the data bus width and the number of waits for each address area. The input pin controlling these states is the bus wait request pin ( WAIT ). 3.6.1 Specifying an Address Area The CS0 to CS3 address areas are specified using the start address registers (MSAR0 to MSAR3) and memory address mask registers (MAMR0 to MAMR3). At each bus cycle, a compare operation is performed to determine if the address on the specified a location in the CS0 to CS3 area. If the result of the comparison is a match, this indicates an access to the corresponding CS area. In this case, the CS0 to CS3 pin outputs the chip select signal and the bus cycle operates in accordance with the settings in chip select/wait control register B0CS to B3CS. (See 3.6.2, Chip Select/Wait Control Registers.) 91C025-79 2007-02-28 TMP91C025 (1) Memory start address registers Figure 3.6.1 shows the memory start address registers. The memory start address registers MSAR0 to MSAR3 set the start addresses for the CS0 to CS3 areas. Set the upper 8 bits (A23 to A16) of the start address in <S23:16>. The lower 16 bits of the start address (A15 to A0) are permanently set to 0. Accordingly, the start address can only be set in 64-Kbyte increments, starting from 000000H. Figure 3.6.2 shows the relationship between the start address and the start address register value. Memory Start Address Registers (for areas CS0 to CS3) MSAR0 (00C8H) MSAR1 (00CAH) Bit symbol MSAR2 (00CCH) MSAR3 (00CEH) After reset 7 6 5 4 S23 S22 S21 S20 Read/Write 3 2 1 0 S19 S18 S17 S16 1 1 1 1 R/W 1 1 1 Function 1 Determines A23 to A16 of start address. Sets start addresses for areas CS0 to CS3. Figure 3.6.1 Memory Start Address Register Start address Address 000000H 64 Kbytes Value in start address register (MSAR0 to MSAR3) 000000H ...................... 00H 010000H ...................... 01H 020000H ...................... 02H 030000H ...................... 03H 040000H ...................... 04H 050000H ...................... 05H 060000H ...................... 06H to to FF0000H ...................... FFH FFFFFFH Figure 3.6.2 Relationship between Start Address and Start Address Register Value 91C025-80 2007-02-28 TMP91C025 (2) Memory address mask registers Figure 3.6.3 shows the memory address mask registers. Memory address mask registers MAMR0 to MAMR3 are used to set the size of the CS0 to CS3 areas by specifying a mask for each bit of the start address set in memory start address registers MAMR0 to MAMR3. The compare operation used to determine if an address is in the CS0 to CS3 areas is only performed for bus address bits corresponding to bits set to 0 in these registers. Also, the address bits that can be masked by MAMR0 to MAMR3 differ between CS0 to CS3 areas. Accordingly, the size that can be each area is different. Memory Address Mask Register (for CS0 area) MAMR0 (00C9H) Bit symbol 7 6 5 4 V20 V19 V18 V17 Read/Write After reset 3 2 1 0 V16 V15 V14 to 9 V8 1 1 1 1 R/W 1 1 1 Function 1 Sets size of CS0 area. 0: Used for address compare Range of possible settings for CS0 area size: 256 bytes to 2 Mbytes Memory Address Mask Register (CS1) MAMR1 (00CBH) Bit symbol 7 6 5 4 V21 V20 V19 V18 Read/Write After reset 3 2 1 0 V17 V16 V15 to 9 V8 1 1 1 1 R/W 1 1 1 Function 1 Sets size of CS1 area. 0: Used for address compare Range of possible settings for CS1 area size: 256 bytes to 4 Mbytes. Memory Address Mask Register (CS2, CS3) MAMR2 (00CDH) MAMR3 (00CFH) Bit symbol 7 6 5 4 V22 V21 V20 V19 Read/Write After reset Function 3 2 1 0 V18 V17 V16 V15 1 1 1 1 R/W 1 1 1 1 Sets size of CS2 or CS3 area. 0: Used for address compare Range of possible settings for CS2 and CS3 area sizes: 32 Kbytes to 8 Mbytes. Figure 3.6.3 Memory Address Mask Registers 91C025-81 2007-02-28 TMP91C025 (3) Setting memory start addresses and address areas Figure 3.6.4 show an example of specifying a 64-Kbyte address area starting from 010000H using the CS0 areas. Set 01H in memory start address register MSAR0<S23:16> (Corresponding to the upper 8-bits of the start address). Next, calculate the difference between the start address and the anticipated end address (01FFFFH). Bits 20 to 8 of the result correspond to the mask value to be set for the CS0 area. Setting this value in memory address mask register MAMR0<V20:8>sets the area size this example sets 07H in MAMR0 to specify a 64-Kbyte area. 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 F 1 1 1 1 F 1 1 1 1 F 1 1 H F S23 S22 S21 S20 S19 S18 S17 S16 MSAR0 0 0 0 0 0 0 0 0 H V14 ∼ V9 V20 V19 V18 V17 V16 V15 MSMR0 0 0 0 0 0 0 0 0 0 1 CSO area size (64 Kbytes) Memory start address 1 1 Memory end address 1 1 1 1 V8 1 1 1 7 1 1 1 1 1 1 1 H 1 Memory address mask register setting Setting of 07H specifies a 64-Kbyte area. Figure 3.6.4 Example Showing How to Set the CS0 Area After a reset, MSAR0 to MSAR3 and MAMR0 to MAMR3 are set to FFH. B0CS<B0E>, B1CS<B1E> and B3CS<B3E> are reset to 0. This disabling the CS0, CS1 and CS3 areas. However, as B2CS<B2M> to 0 and B2CS<B2E> to 1, CS2 is enabled from 000FE0H to 000FFFH and 001000H to FFFFFFH in TMP91C025. Also, the bus width and number of waits specified in BEXCS are used for accessing addresses outside the specified CS0 to CS3 area. (See 3.6.2, Chip Select/Wait Control Registers.) 91C025-82 2007-02-28 TMP91C025 (4) Address area size specification Table 3.6.1 shows the relationship between CS area and area size. Triangle (Δ) indicates areas that cannot be set by memory start address register and address mask register combinations. When setting an area size using a combination indicated by Δ, set the start address mask register in the desired steps starting from 000000H. If the CS2 area is set to 16 Mbytes or if two or more areas overlap, the smaller CS area number has the higher priority. Example: To set the area size for CS0 to 128 Kbytes: (a) Valid start addresses 000000H 020000H 040000H 060000H 128 Kbytes 128 Kbytes Any of these addresses may be set as the start address. 128 Kbytes (b) Invalid start addresses 000000H 010000H 030000H 050000H This is not an integer multiple of the desired area size 64 Kbytes setting. Hence, none of these addresses can be set as the 128 Kbytes start address. 128 Kbytes Table 3.6.1 Valid Area Sizes for Each CS Area Size (Bytes) 256 512 32 K 64 K ○ ○ ○ ○ ○ ○ ○ ○ ○ 128 K 256 K 512 K 1M 2M 4M 8M CS Area CS0 CS1 CS2 CS3 Note: 3.6.2 ○ ○ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ Δ: This symbol indicates areas that cannot be set by memory start address register and address mask register combinations. Chip Select/Wait Control Registers Figure 3.6.5 lists the chip select/wait control registers. The master enable/disable, chip select output waveform, data bus width and number of wait states for each address area (CS0 to CS3 and others) are set in their respective chip select/wait control registers, B0CS to B3CS and BEXCS. 91C025-83 2007-02-28 TMP91C025 7 B0CS (00C0H) Bit symbol B0E Read/Write W After reset Function B1CS (00C1H) B2CS (00C2H) 0 B1E Read/Write W 4 3 B0OM1 B0OM0 B0BUS 0 0 Chip select output waveform selection. 00: For ROM/SRAM 01: 10: Don’t care 11: B1OM1 B3CS (00C3H) 0 0 BEXCS (00C7H) 0 B0W2 B0W1 B0W0 0 0 0 Number of waits 000: 2 waits 001: 1 wait 010: (1 + N) waits 011: 0 waits B1BUS 0 Chip select output waveform selection. 00: For ROM/SRAM 01: 10: Don’t care 11: B2E B2M 1 B2OM1 0 0: Disable 1: Enable B3E Read/Write W B1W2 B1W1 B1W0 0 0 0 0 Data bus width 0: 16 bits 1: 8 bits B2OM0 0 CS2 area selection. 0: 16-Mbyte area 1: CS area 0 Chip select output waveform selection. 00: For ROM/SRAM 01: 10: Don’t care 11: B3OM1 B3OM0 Number of waits 000: 2 waits 001: 1 wait 010: (1 + N) waits 011: 0 waits B2BUS B2W2 B2W1 B2W0 0 0 0 0 Data bus width 0: 16 bits 1: 8 bits Number of waits 000: 2 waits 001: 1 wait 010: (1 + N) waits 011: 0 waits B3BUS 0 0 0: Disable 1: Enable 0 Chip select output waveform selection. 00: For ROM/SRAM 01: 10: Don’t care 11: B3W1 B3W0 0 0 0 0 Data bus width 0: 16 bits 1: 8 bits BEXBUS Number of waits 000: 2 waits 001: 1 wait 010: (1 + N) waits 011: 0 waits BEXW2 0 Data bus width 0: 16 bits 1: 8 bits Master enable bit Enable Chip select output waveform selection BEXW1 BEXW0 0 0 0 Number of waits 000: 2 waits 001: 1 wait 010: (1 + N) waits 011: 0 waits 01 10 Don’t care 11 0 16-Mbyte area 1 Specified address area 100: (0 + N) waits 101: 3 waits 110: 4 waits 111: 8 waits Number of address area waits (See 3.6.2, (3) Wait control.) 00 For ROM/SRAM CS2 area selection Note: 100: (0 + N) waits 101: 3 waits 110: 4 waits 111: 8 waits W After reset Functions 1 100: (0 + N) waits 101: 3 waits 110: 4 waits 111: 8 waits B3W2 Read/Write Disable 100: (0 + N) waits 101: 3 waits 110: 4 waits 111: 8 waits W Bit symbol 0 100: (0 + N) waits 101: 3 waits 110: 4 waits 111: 8 waits W Bit symbol After reset Functions 1 0 Data bus width 0: 16 bits 1: 8 bits B1OM0 Read/Write After reset Functions 2 W 0: Disable 1: Enable Bit symbol 5 W 0: Disable 1: Enable Bit symbol After reset Function 6 Data bus width selection 0 16-bit data bus 1 8-bit data bus Read-modify-write is prohibited for the registers B0CS, B1CS, B2CS, B3CS and BEXCS. Figure 3.6.5 Chip Select/Wait Control Registers 91C025-84 2007-02-28 TMP91C025 (1) Master enable bits Bit 7 (<B0E>, <B1E>, <B2E> or <B3E>) of a chip select/wait control register is the master bit which is used to enable or disable settings for the corresponding address area. Writing 1 to this bit enables the settings. Reset disables (Sets to 0)<B0E>, <B1E>, <B3E>, and enabled (sets to 1) <B2E>. This enables area CS2 only. (2) Data bus width selection Bit 3 (<B0BUS>, <B1BUS>, <B2BUS>, <B3BUS> or <BEXBUS>) of a chip select/wait control register specifies the width of the data bus. This bit should be set to 0 when memory is to be accessed using a 16-bit data bus and to 1 when an 8-bit data bus is to be used. This process of changing the data bus width according to the address being accessed is known as dynamic bus sizing. For details of this bus operation see Table 3.6.2. 91C025-85 2007-02-28 91C025-86 32 bits 16 bits 8 bits 8 bits 2n + 0 number) 2n + 1 (Odd number) (Even 2n + 0 number) 2n + 1 (Odd number) 16 bits 8 bits 16 bits 8 bits 16 bits 8 bits 16 bits 8 bits 2n + 0 (Even 16 bits 8 bits 16 bits number) (Odd 2n + 1 number) (Even Width Address Width Memory Start Data Bus Operand Operand Data Bus XXXX 2n + 4 XXXX 2n + 4 b7-b0 XXXX 2n + 3 b23-b16 XXXX 2n + 2 2n + 2 XXXX 2n + 1 2n + 1 b31-b24 2n + 2 XXXX 2n + 2 XXXX XXXX 2n + 1 b15-b8 XXXX 2n + 0 2n + 0 XXXX 2n + 2 2n + 3 b7-b0 XXXX 2n + 1 XXXX 2n + 2 b15-b8 2n + 1 2n + 0 XXXX XXXX 2n + 0 2n + 1 b7-b0 XXXX XXXX XXXX D15 to D8 b31-b24 b15-b8 XXXX b31-b24 b23-b16 b15-b8 b7-b0 b23-b16 b7-b0 b31-b24 b23-b16 b15-b8 b7-b0 b15-b8 XXXX b15-b8 b7-b0 b7-b0 b15-b8 b7-b0 XXXX b7-b0 b7-b0 b7-b0 D7 to D0 CPU Data 2n + 1 2n + 1 2n + 0 2n + 0 Address CPU H R/W L RD H WR H HWR L L H L L L L H L L L H L L SRLB Control for READ Cycle H L L H L H H L H L H L H H H SRUB SRWR L R/W H RD L L H L L L L H L L L H L L WR H L L H L H H L H L H L H H HWR L L H L L L L H L L L H L L SRLB Control for WRITE Cycle H L L H L H H L H L H L H H L SRUB SRWR TMP91C025 Table 3.6.2 Dynamic Bus Sizing xxxx: Indicates that the input data from these bits are ignored during a read. During a write, indicates that the bus for these bits goes too high-impedance; also, that the write strobe signal for the bus remains inactive. 2007-02-28 TMP91C025 (3) Wait control Bits 0 to 2 (<B0W0:2>, <B1W0:2>, <B2W0:2>, <B3W0:2>, <BEXW0:2>) of a chip select/wait control register specify the number of waits that are to be inserted when the corresponding memory area is accessed. The following types of wait operation can be specified using these bits. Bit settings other than those listed in the table should not be made. Table 3.6.3 Wait Operation Settings <BxW2:0> No. of Waits Wait Operation 000 2 waits Inserts a wait of 2 states, irrespective of the WAIT pin state. 001 1 wait Inserts a wait of 1 state, irrespective of the WAIT pin state. 010 (1 + N) waits Samples the state of the WAIT pin after inserting a wait of one state. If the WAIT pin is low, the waits continue and the bus cycle is extended until the pin goes high. 011 0 waits 100 (0 + N) waits Ends the bus cycle without a wait, regardless of the WAIT pin state. Samples the state of the WAIT pin without inserting a wait. If the WAIT pin is low, the waits continue and the bus cycle is extended until the pin goes high. 101 3 waits Inserts a wait of 3 states, irrespective of the WAIT pin state. 110 4 waits Inserts a wait of 4 states, irrespective of the WAIT pin state. 111 8 waits Inserts a wait of 8 states, irrespective of the WAIT pin state. A Reset sets these bits to 000 (2 waits). (at 16 MHz) 375 ns 62.5 ns T1 T2 TW fFPH CSn R/ W A0 to A23 D0 to D15 Data-in Read RD D0 to D15 Data-out Write HWR , WR WAIT Figure 3.6.6 (0 + N) Waits Read/Write Cycle (N = 1) 91C025-87 2007-02-28 TMP91C025 (4) Bus width and wait control for an area other than CS0 to CS3 The chip select/wait control register BEXCS controls the bus width and number of waits when memory locations which are not in one of the four user-specified address areas (CS0 to CS3) are accessed. The BEXCS register settings are always enabled for areas other than CS0 to CS3. (5) Selecting 16-Mbyte area/specified address area Setting B2CS<B2M> (bit 6 of the chip select/wait control register for CS2) to 0 designates the 16-Mbyte area 000FE0H to 000FFFH, 003000H to FFFFFFH as the CS2 area. Setting B2CS<B2M> to 1 designates the address area specified by the start address register MSAR2 and the address mask register MAMR2 as CS2 (e.g., if B2CS<B2M> = 1, CS2 is specified in the same manner as CS0, CS1 and CS3 are). A reset clears this bit to 0, specifying CS2 as a 16-Mbyte address area. (6) Procedure for setting chip select/wait control When using the chip select/wait control function, set the registers in the following order: • Set the memory start address registers MSAR0 to MSAR3. Set the start addresses for CS0 to CS3. • Set the memory address mask registers MAMR0 to MAMR3. Set the sizes of CS0 to CS3. • Set the chip select/wait control registers B0CS to B3CS. Set the chip select output waveform, data bus width, number of waits and master enable/disable status for CS0 to CS3 . The CS0 to S3 pins can also function as pins P60 to P63. To output a chip select signal using one of these pins, set the corresponding bit in the port 6 function register P6FC to 1. If a CS0 to S3 address is specified which is actually an internal I/O and RAM area address, the CPU accesses the internal address area and no chip select signal is output on any of the CS0 to CS3 pins. (Setting example) In this example CS0 is set to be the 64-Kbyte area 010000H to 01FFFFH. The bus width is set to 16 bits and the number of waits is set to 0. MSAR0 = 01H Start address: 010000H MAMR0 = 07H Address area: 64 Kbytes B0CS = 83H ROM/SRAM, 16-bit data bus, zero waits, CS0 area settings enabled. 91C025-88 2007-02-28 TMP91C025 3.6.3 Connecting External Memory Figure 3.6.7 shows an example of how to connect external memory to the TMP91C025. In this example the ROM is connected using a 16-bit bus. The RAM and I/O are connected using an 8-bit bus. TMP91C025 CS0 CS1 Address bus CS2 A0 to A23 CS Upper byte ROM OE CS Lower byte ROM OE CS 8-bit RAM OE WE CS 8-bit I/O OE WE D8 to D15 D0 to D7 RD WR Figure 3.6.7 Example of External Memory Connection (ROM uses 16-bit bus: RAM and I/O use 8-bit bus.) A reset clears all bits of the port 6 control register P6CR and the port 6 function register P6FC to 0 and disables output of the CS signal. To output the CS signal, the appropriate bit must be set to 1. 91C025-89 2007-02-28 TMP91C025 TMP91C025 16-bit SRAM OE RD SRLB LDS SRUB UDS SRWR R/ W CS0 CE D [15:0] A0 A1 A2 A3 I/O [16:1] Not connect A0 A1 A2 Figure 3.6.8 How to Connect to 16-Bit SRAM for TMP91C025 91C025-90 2007-02-28 TMP91C025 3.7 8-Bit Timers (TMRA) The TMP91C025 features 4 channel (TMRA0 to TMRA3) built-in 8-bit timers. These timers are paired into 2 modules: TMRA01 and TMRA23. Each module consists of 2 channels and can operate in any of the following 4 operating modes. • 8-bit interval timer mode • 16-bit interval timer mode • 8-bit programmable square wave pulse generation output mode (PPG: Variable duty cycle with variable period) • 8-bit pulse width modulation output mode (PWM: Variable duty cycle with constant period) Figure 3.7.1 to Figure 3.7.2 Show block diagrams for TMRA01 and TMRA23. Each channel consists of an 8-bit up counter, an 8-bit comparator and an 8-bit timer register. In addition, a timer flip-flop and a prescaler are provided for each pair of channels. The operation mode and timer flip-flops are controlled by 5 bytes registers SFRs (Special-function registers). Each of the 2 modules (TMRA01 and TMRA23) can be operated independently. All modules operate in the same manner; hence only the operation of TMRA01 is explained here. The contents of this chapter are as follows. 3.7.1 Block Diagrams 3.7.2 Operation of Each Circuit 3.7.3 SFRs 3.7.4 Operation in Each Mode (1) 8-bit timer mode (2) 16-bit timer mode (3) 8-bit PPG (Programmable pulse generation) output mode (4) 8-bit PWM (Pulse width modulation) output mode (5) Setting for each mode Table 3.7.1 Registers and Pins for Each Module Module Input pin for external External pin SFR clock TMRA01 TA0IN (shared with PB4) Output pin for timer TMRA23 None TA1OUT TA3OUT flip-flop (shared with PA1) (shared with PA2) Timer run register TA01RUN (0100H) TA23RUN (0108H) TA0REG (0102H) TA2REG (010AH) Timer register (address) Timer mode register Timer flip-flop control register TA1REG (0103H) TA3REG (010BH) TA01MOD (0104H) TA23MOD (010CH) TA1FFCR (0105H) TA3FFCR (010DH) 91C025-91 2007-02-28 External input clock: TA0IN φT4 8 φT256 91C025-92 <TA0RDE> TA01RUN Internal data bus Register buffer 0 8-bit timer register TA0REG 8-bit compatator (CP0) TA0TR 8-bit timer register TA1REG Match 8-bit comparator detect (CP1) TA1FFCR Timer flip-flop TA1FF TMRA0 Internal data bus TMRA1 match output: interrupt output: TA0TRG INTTA1 TA01MOD <TA01M1:0> TMRA0 interrupt output: INTTA0 Match detect <TA1CLK1:0> TA01MOD TA01MOD 8-bit up counter (UC1) TA01RUN<TA1RUN> <TA0CLK1:0> φT1 φT16 φT256 Selector <TA01PRUN> Run/clear TA01RUN 2 Over flow n 8-bit up counter (UC0) TA01RUN<TA0RUN> φT16 16 32 64 128 256 512 TA01MOD φT4 φT16 φT1 4 Selector φT1 2 Prescaler Timer flip-flop output: TA1OUT 3.7.1 Prescaler clock: φT0 TMP91C025 Block Diagrams Figure 3.7.1 TMRA01 Block Diagram 2007-02-28 Prescaler clock: φT0 φT4 91C025-93 TA23RUN <TA2RDE> φT256 Internal data bus Register buffer 2 8-bit timer register TA2REG TA3FFCR Timer flip-flop TA3FF TMRA2 Internal data bus TMRA3 match output: interrup output: TA2TRG INTTA3 8-bit timer register TA3REG Match 8-bit comparator detect register (CP3) <TA3CLK1:0> 8-bit up counterr (UC3) TA23RUN<TA3RUN> TA23MOD TA23MOD <TA23M1:0> TA2TRG TMRA2 interrupt output: INTTA2 Match 8-bit comparator detect (CP2) n φT1 φT16 φT256 Selector Run/clear TA23RUN <TA23PRUN> 2 Over flow TA23MOD <PWM21:20> 8-bit up counter (UC2) TA23RUN<TA2RUN> φT16 8 16 32 64 128 256 512 TA23MOD <TA2CLK1:0> φT1 φT4 φT16 4 Selector φT1 2 Prescaler Timer flip-flop output: TA3OUT Possible to connect to LCD and MLD circuits TMP91C025 Figure 3.7.2 TMRA23 Block Diagram 2007-02-28 TMP91C025 3.7.2 Operation of Each Circuit (1) Prescalers A 9-bit prescaler generates the input clock to TMRA01. The φT0 as the input clock to prescaler is a clock divided by 4 which selected using the prescaler clock selection register SYSCR0<PRCK1:0>. The prescaler’s operation can be controlled using TA01RUN<TA01PRUN> in the timer control register. Setting <TA01PRUN> to 1 starts the count; setting <TA01PRUN> to 0 clears the prescaler to zero and stops operation. Table 3.7.2 shows the various prescaler output clock resolutions. Table 3.7.2 Prescaler Output Clock Resolution at fc = 36 MHz, fs = 32.768 kHz System Clock Selection SYSCR1 <SYSCK> Prescaler Clock Selection SYSCR0 <PRCK1:0> 1 (fs) 00 (fFPH) 0 (fc) 10 (fc/16 CLOCK) Prescaler Output Clock Resolution Gear Value SYSCR1 <GEAR2:0> φT1 φT4 XXX 2 /fs (244 μs) 2 /fs (977 μs) 2 /fs (3.9 ms) 2 /fs (62.5 ms) 000 (fc) 2 /fc (0.2 μs) 2 /fc (0.9 μs) 2 /fc (3.6 μs) 001 (fc/2) 2 /fc (0.4 μs) 2 /fc (1.8 μs) 2 /fc (7.1 μs) 2 /fc (113.8 μs) 010 (fc/4) 2 /fc (0.9 μs) 2 /fc (3.6 μs) 2 /fc (14.2 μs) 2 /fc (227.6 μs) 011 (fc/8) 2 /fc (1.8 μs) 2 /fc (7.1 μs) 2 /fc (28.4 μs) 2 /fc (455.1 μs) 100 (fc/16) 2 /fc (3.6 μs) 2 /fc (14.2 μs) 2 /fc (56.9 μs) 2 /fc (910.2 μs) XXX 2 /fc (3.6 μs) 2 /fc (14.2 μs) 2 /fc (56.9 μs) 2 /fc (910.2 μs) 3 3 4 5 6 7 7 5 5 6 7 8 9 9 φT16 7 7 8 9 10 11 11 φT256 11 2 /fc (56.9 μs) 11 12 13 14 15 15 xxx: Don't care (2) Up counters (UC0 and UC1) These are 8-bit binary counters which count up the input clock pulses for the clock specified by TA01MOD. The input clock for UC0 is selectable and can be either the external clock input via the TA0IN pin or one of the three internal clocks φT1, φT4 or φT16. The clock setting is specified by the value set in TA01MOD<TA01CLK1:0>. The input clock for UC1 depends on the operation mode. In 16-bit timer mode, the overflow output from UC0 is used as the input clock. In any mode other than 16-bit timer mode, the input clock is selectable and can either be one of the internal clocks φT1, φT16 or φT256, or the comparator output (The match detection signal) from TMRA0. For each interval timer the timer operation control register bits TA01RUN<TA0RUN> and TA01RUN<TA1RUN> can be used to stop and clear the up counters and to control their count. A reset clears both up counters, stopping the timers. 91C025-94 2007-02-28 TMP91C025 (3) Timer registers (TA0REG and TA1REG) These are 8-bit registers which can be used to set a time interval. When the value set in the timer register TA0REG or TA1REG matches the value in the corresponding up counter, the comparator match detect signal goes active. If the value set in the timer register is 00H, the signal goes active when the up counter overflows. The TA0REG are double buffer structure, each of which makes a pair with register buffer. The setting of the bit TA01RUN<TA0RDE> determines whether TA0REG’s double buffer structure is enabled or disabled. It is disabled if <TA0RDE> = 0 and enabled if <TA0RDE> = 1. When the double buffer is enabled, data is transferred from the register buffer to the timer register when a 2n overflow occurs in PWM mode, or at the start of the PPG cycle in PPG mode. Hence the double buffer cannot be used in timer mode. A reset initializes <TA0RDE> to 0, disabling the double buffer. To use the double buffer, write data to the timer register, set <TA0RDE> to 1, and write the following data to the register buffer. Figure 3.7.3 show the configuration of TA0REG. Timer registers 0 (TA0REG) B Matching detection in PPG cycle n 2 overflow of PWM Y Shift trigger Register buffers 0 Selector A Write to TA0REG S Write Internal data bus TA01RUN<TA0RDE> Figure 3.7.3 Configuration of TA0REG Note: The same memory address is allocated to the timer register and the register buffer. When <TA0RDE> = 0, the same value is written to the register buffer and the timer register; when <TA0RDE> = 1, only the register buffer is written to. The address of each timer register is as follows. TA0REG: 000102H TA1REG: 000103H TA2REG: 00010AH TA3REG: 00010BH All these registers are write only and cannot be read. 91C025-95 2007-02-28 TMP91C025 (4) Comparator (CP0) The comparator compares the value in an up counter with the value set in a timer register. If they match, the up counter is cleared to zero and an interrupt signal (INTTA0 or INTTA1) is generated. If timer flip-flop inversion is enabled, the timer flip-flop is inverted at the same time. (5) Timer flip-flop (TA1FF) The timer flip-flop (TA1FF) is a flip-flop inverted by the match detects signal (8-bit comparator output) of each interval timer. Whether inversion is enabled or disabled is determined by the setting of the bit TA1FFCR<TA1FFIE> in the timer flip-flop control register. A Reset clears the value of TA1FF1 to 0. Writing 01 or 10 to TA1FFCR<TA1FFC1:0> sets TA1FF to 0 or 1. Writing 00 to these bits inverts the value of TA1FF (This is known as software inversion). The TA1FF signal is output via the TA1OUT pin (Concurrent with PA1). When this pin is used as the timer output, the timer flip-flop should be set beforehand using the port A function register PAFC2. Note: When the double buffer is enabled for an 8-bit timer in PWM or PPG mode, caution is required as explained below. If new data is written to the register buffer immediately before an overflow occurs by a match between the timer register value and the up-counter value, the timer flip-flop may output an unexpected value. For this reason, make sure that in PWM mode new data is written to the register buffer by six cycles (fSYS × 6) before the next overflow occurs by using an overflow interrupt. In the case of using PPG mode, make sure that new data is written to the register buffer by six cycles before the next cycle compare match occurs by using a cycle compare match interrupt. Example when using PWM mode Match between TA0REG and up-counter n 2 overflow interrupt (INTTA0) TA1OUT tPWM (PWM cycle) Desired PWM cycle change point Write new data to the register buffer before the next overflow occurs by using an overflow interrupt 91C025-96 2007-02-28 TMP91C025 3.7.3 SFRs TMRA01 Run Register 7 TA01RUN (0100H) 6 Bit symbol TA0RDE Read/Write R/W After reset Function 5 4 3 2 I2TA01 TA01PRUN 1 0 TA1RUN TA0RUN R/W 0 0 0 0 0 Double IDLE2 8-bit timer run/stop control buffer 0: Stop 0: Stop and clear 0: Disable 1: Operate 1: Run (Count up) 1: Enable Timer run/stop control TA0REG double buffer control 0 Disable 0 Stop and clear 1 Enable 1 Run (Count up) I2TA01: Operation in IDLE2 mode TA01PRUN: Run prescaler TA1RUN: Run TMRA1 TA0RUN: Run TMRA0 Note: The values of bits 4, 5, 6 of TA01RUN are undefined when read. TMRA23 Run Register 7 TA23RUN (0108H) 6 Bit symbol TA2RDE Read/Write R/W After reset Function 5 4 3 2 I2TA23 TA23PRUN 1 0 TA3RUN TA2RUN R/W 0 0 0 0 0 Double IDLE2 8-bit timer run/stop control buffer 0: Stop 0: Stop and clear 0: Disable 1: Operate 1: Run (Count up) 1: Enable TA2REG double buffer control Timer run/stop control 0 Disable 0 Stop and clear 1 Enable 1 Run (Count up) I2TA23: Operation in IDLE2 mode TA23PRUN: Run prescaler TA3RUN: Run TMRA3 TA2RUN: Run TMRA2 Note: The values of bits 4, 5, 6 of TA23RUN are undefined when read. Figure 3.7.4 TMRA Registers 91C025-97 2007-02-28 TMP91C025 TMRA01 Mode Register TA01MOD (0104H) Bit symbol 7 6 5 4 TA01M1 TA01M0 PWM01 PWM00 Read/Write After reset Function 3 2 1 0 TA1CLK1 TA1CLK0 TA0CLK1 TA0CLK0 0 0 R/W 0 0 0 0 0 0 Operation mode PWM cycle Source clock for TMRA1 Source clock for TMRA0 00: 8-bit timer mode 00: Reserved 00: TA0TRG 00: TA0IN pin 01: 16-bit timer mode 01: 2 10: 8-bit PPG mode 10: 2 11: 8-bit PWM mode 11: 2 6 01: φT1 01: φT1 7 10: φT16 10: φT4 8 11: φT256 11: φT16 TMRA0 source clock selection 00 TA0IN (External input) 01 φT1 (Prescaler) 10 φT4 (Prescaler) 11 φT16 (Prescaler) TMRA1 source clock selection TA01MOD 00 TA01MOD <TA01M1:0> ≠ 01 <TA01M1:0> = 01 Comparator Overflow output from output from TMRA0 TMRA0 01 φT1 10 φT16 11 φT256 (16-bit timer mode) PWM cycle selection 00 Reserved 01 2 × source clock 10 2 × source clock 11 2 × source clock 6 7 8 TMRA01 operation mode selection 00 Two 8-bit timers 01 16-bit timer 10 8-bit PPG 11 8-bit PWM (TMRA0) + 8-bit timer (TMRA1) Figure 3.7.5 TMRA Registers 91C025-98 2007-02-28 TMP91C025 TMRA23 Mode Register TA23MOD (010CH) Bit Symbol 7 6 5 4 TA23M1 TA23M0 PWM21 PWM20 Read/Write After reset Function 3 2 1 0 TA3CLK1 TA3CLK0 TA2CLK1 TA2CLK0 0 0 R/W 0 0 0 0 0 0 Operation mode PWM cycle TMRA3 clock for TMRA3 TMRA2 clock for TMRA2 00: 8-bit timer mode 00: Reserved 00: TA2TRG 00: Reserved 01: 16-bit timer mode 01: 2 10: 8-bit PPG mode 10: 2 11: 8-bit PWM mode 11: 2 6 01: φT1 01: φT1 7 10: φT16 10: φT4 8 11: φT256 11: φT16 TMRA2 source clock selection 00 Do not set 01 φT1 (Prescaler) 10 φT4 (Prescaler) 11 φT16 (Prescaler) TMRA3 source clock selection 00 TA23MOD TA23MOD <TA23M1:0> ≠ 01 <TA23M1:0> = 01 Comparator output Overflow output from from TMRA2 TMRA2 01 φT1 10 φT16 11 φT256 (16-bit timer mode) PWM cycle selection 00 Reserved 01 2 × source clock 10 2 × source clock 11 2 × source clock 6 7 8 TMRA23 operation mode selection 00 Two 8-bit timers 01 16-bit timer 10 8-bit PPG 11 8-bit PWM (TMRA2) + 8-bit timer (TMRA3) Figure 3.7.6 TMRA Registers 91C025-99 2007-02-28 TMP91C025 TMRA1 Flip-Flop Control Register 7 TA1FFCR (0105H) 6 5 4 Bit symbol 3 TA1FFC1 Read/Write 2 1 TA1FFC0 TA1FFIE R/W After reset 1 Function Read-modify -write instructions are prohibited. 0 TA1FFIS R/W 1 0 0 00: Invert TA1FF TA1FF TA1FF 01: Set TA1FF control for inversion 10: Clear TA1FF inversion select 11: Don’t care 0: Disable 0: TMRA0 1: Enable 1: TMRA1 Inverse signal for timer flop-flop 1 (TA1FF) (Don’t care except in 8-bit timer mode) 0 Inversion by TMRA0 1 Inversion by TMRA1 Inversion of TA1FF 0 Disabled 1 Enabled Control of TA1FF 00 Inverts the value of TA1FF 01 Sets TA1FF to 1 10 Clears TA1FF to 0 11 Don’t care Figure 3.7.7 TMRA Registers 91C025-100 2007-02-28 TMP91C025 TMRA3 Flip-Flop Control Register 7 TA3FFCR (010DH) 6 5 4 Bit symbol 3 TA3FFC1 Read/Write 2 1 TA3FFC0 TA3FFIE R/W After reset Read-modify -write instructions are prohibited. TA3FFIS R/W 1 Function 0 1 0 0 00: Invert TA3FF TA3FF TA3FF 01: Set TA3FF control for inversion 10: Clear TA3FF inversion select 11: Don’t care 0: Disable 0: TMRA2 1: Enable 1: TMRA3 Inverse signal for timer flip-flop 3 (TA3FF) (Don’t care except in 8-bit timer mode) 0 Inversion by TMRA2 1 Inversion by TMRA3 Inversion of TA3FF 0 Disabled 1 Enabled Control of TA3FF 00 Inverts the value of TA3FF 01 Sets TA3FF to 1 10 Clears TA3FF to 0 11 Don’t care Figure 3.7.8 TMRA Registers 91C025-101 2007-02-28 TMP91C025 TMRA register 7 6 5 4 3 TA0REG bit Symbol – (0102H) Read/Write W After reset Undefined TA1REG bit Symbol – (0103H) Read/Write W After reset Undefined bit Symbol – TA2REG (010AH) Read/Write W After reset Undefined TA3REG bit Symbol – (010BH) Read/Write W After reset Undefined 2 1 0 Note: The above registers are prohibited read-modify-write instruction. Figure 3.7.9 TMRA Registers 91C025-102 2007-02-28 TMP91C025 3.7.4 Operation in Each Mode (1) 8-bit timer mode Both TMRA0 and TMRA1 can be used independently as 8-bit interval timers. Setting its function or counter data for TMRA0 and TMRA1 after stop these registers. a. Generating interrupts at a fixed interval (Using TMRA1) To generate interrupts at constant intervals using TMRA1 (INTTA1), first stop TMRA1 then set the operation mode, input clock and a cycle to TA01MOD and TA1REG register, respectively. Then, enable the interrupt INTTA1 and start TMRA1 counting. Example: To generate an INTTA1 interrupt every 8.0 μs at fc = 36 MHz, set each register as follows: ∗ Clock state System clock: High-frequency (fc) Prescaler clock: fFPH MSB TA01RUN TA01MOD LSB 7 6 5 4 3 2 1 ← – ← 0 X X X – – 0 0 – Stop TMRA1 and clear it to 0. 0 X X 0 1 X X Select 8-bit timer mode and select φT1 ((2 /fc)s at fc = 36 MHz) as the input clock. 3 Set TA1REG to 8.0 μs ÷ φT1(2 /fc) ≈ 40 = 28H 0 INTETA01 ← 0 ← X 1 0 1 – – – – Enable INTTA1 and set it to level 5. TA01RUN ← – X X X – 1 1 – Start TMRA1 counting. TA1REG 1 0 1 0 0 0 3 X: Don’t care, −: No change Select the input clock using Table 3.7 2. Note: The input clocks for TMRA0 and TMRA1 are different from as follows. TMRA0: TA0IN input, φT1, φT4 or φT16 TMRA1: Match output of TMRA0, φT1, φT16, φT256 91C025-103 2007-02-28 TMP91C025 b. Generating a 50% duty ratio square wave pulse The state of the timer flip-flop (TA1FF) is inverted at constant intervals and its status output via the timer output pin (TA1OUT). Example: To output a 1.2-μs square wave pulse from the TA1OUT pin at fc = 36 MHz, use the following procedure to make the appropriate register settings. This example uses TMRA1; however, either TMRA0 or TMRA1 may be used. ∗ Clock state System clock: High-frequency (fc) Clock gear: 1 (fc) Prescaler clock: fFPH TA01RUN TA01MOD 7 6 5 4 3 2 1 ← – ← 0 X X X – – 0 0 – Stop TMRA1 and clear it to 0. 0 X X 0 1 – – Select 8-bit timer mode and select φT1 ((2 /fc)s at fc = 36 0 0 0 0 0 1 1 Set the timer register to 1.2 μs ÷ φT1(2 /fc) ÷ 2 = 3 X X X 1 0 1 1 Clear TA1FF to 0 and set it to invert on the match detects X X X – – 1 – Set PA1 to function as the TA1OUT pin. X X X – 1 1 – Start TMRA1 counting. 3 MHz) as the input clock. ← 0 ← X TA1REG TA1FFCR 3 signal from TMRA1. ← X ← – PAFC2 TA01RUN X: Don’t care, −: No change φT1 TA01RUN <TA1RUN> Bit7 to 2 Up counter Bit 1 Bit 0 0 1 2 3 0 1 2 3 0 1 2 3 0 Comparator timing Comparator output (match detect) INTTA1 UC1 Clear TA1FF TA1OUT 0.6 μs at fc = 36 MHz Figure 3.7.10 Square Wave Output Timing Chart (50% duty) 91C025-104 2007-02-28 TMP91C025 c. Making TMRA1 count up on the match signal from the TMRA0 comparator Select 8-bit timer mode and set the comparator output from TMRA0 to be the input clock to TMRA1. Comparaot output (TMRA0 match) TMRA0 up counter (when TA0REG = 5) TMRA1 up counter (when TA1REG = 2) 1 2 3 4 5 1 1 2 3 4 5 1 2 2 3 1 TMRA1 match output Figure 3.7.11 TMRA1 Count Up on Signal from TMRA0 91C025-105 2007-02-28 TMP91C025 (2) 16-bit timer mode A 16-bit interval timer is configured by pairing the two 8-bit timers TMRA0 and TMRA1. To make a 16-bit interval timer in which TMRA0 and TMRA1 are cascaded together, set TA01MOD<TA01M1:0> to 01. In 16-bit timer mode, the overflow output from TMRA0 is used as the input clock for TMRA1, regardless of the value set in TA01MOD<TA01CLK1:0>. Table 3.7.2 shows the relationship between the timer (Interrupt) cycle and the input clock selection. LSB 8-bit set to TA0REG and MSB 8-bit is for TA1REG. Please keep setting TA0REG first because setting data for TA0REG inhibit its compare function and setting data for TA1REG permit it. (Setting example) To generate an INTTA1 interrupt every 0.22 s at fc = 36 MHz, set the timer registers TA0REG and TA1REG as follows: ∗ Clock state System clock: High-frequency (fc) Clock gear: 1 (fc) Prescaler clock: fFPH If φT16 ((27/fc)s at 36 MHz) is used as the input clock for counting, set the following value in the registers: 0.22 s/(27/fc) μs ≈ 62500 = F424H (i.e. set TA1REG to F4H and TA0REG to 24H). As a result, INTTA1 interrupt can be generated every 0.23 [s]. The comparator match signal is output from TMRA0 each time the up counter UC0 matches TA0REG, though the up counter UC0 is not be cleared and also INTTA0 is not generated. In the case of the TMRA1 comparator, the match detect signal is output on each comparator pulse on which the values in the up counter UC1 and TA1REG match. When the match detect signal is output simultaneously from both the comparators TMRA0 and TMRA1, the up counters UC0 and UC1 are cleared to 0 and the interrupt INTTA1 is generated. Also, if inversion is enabled, the value of the timer flip-flop TA1FF is inverted. (Example) When TA1REG = 04H and TA0REG = 80H Value of up counter (UC1, UC0) 0080H 0180H 0280H 0380H 0480H 0080H TMRA0 comparator match detect signal TMRA0 comparator match detect signal INTTA0 INTTA1 TA1OUT Inversion Figure 3.7.12 Timer Output by 16-Bit Timer Mode 91C025-106 2007-02-28 TMP91C025 (3) 8-bit PPG (Programmable pulse generation) output mode Square wave pulses can be generated at any frequency and duty ratio by TMRA0. The output pulses may be active low or active high. In this mode TMRA1 cannot be used. TMRA0 outputs pulses on the TA1OUT pin. tH tL When <TA1FFC1:0>=”10” t tL tH When <TA1FFC1:0>=”01” t Example when <TA1FFC1:0>=”01” TA0REG and UC0 match (Interrupt INTTA0) TA1REG and UC0 match (Interruput INTTA1) TA1OUT TA0REG TA1REG Figure 3.7.13 8-Bit PPG Output Waveforms 91C025-107 2007-02-28 TMP91C025 In this mode, a programmable square wave is generated by inverting the timer output each time the 8-bit up counter (UC0) matches the value in one of the timer registers TA0REG or TA1REG. The value set in TA0REG must be smaller than the value set in TA1REG. Although the up counter for TMRA1 (UC1) is not used in this mode, TA01RUN <TA1RUN> should be set to 1, so that UC1 is set for counting. Figure 3.7.14 shows a block diagram representing this mode. TA1OUT TA0IN φT1 φT4 φT16 TA01RUN<TA0RUN> Selector 8-bit up counter (UC 0) TA1FF Inversion TA01MOD<TA0CLK1:0> INTTA0 Comparator Selector TA0REG-WR TA1FFCR<TA1FFIE> Comparator INTTA1 TA0REG Shift trigger Register buffer TA1REG TA01RUN<TA0RDE> Internal data bus Figure 3.7.14 Block Diagram of 8-Bit PPG Output Mode If the TA0REG double buffer is enabled in this mode, the value of the register buffer will be shifted into TA0REG each time TA1REG matches UC0. Use of the double buffer facilitates the handling of low-duty waves (when duty is varied). Match with TA0REG (Up counter = Q1) (Up countner = Q2) Match with TA1REG TA0REG (Value to be compared) Shift from register buffer Q2 Q1 Register buffer Q2 Q3 TA0REG (Register buffer) write Figure 3.7.15 Operation of Register Buffer 91C025-108 2007-02-28 TMP91C025 (Example) To generate 1/4-duty 50 kHz pulses (at fc = 36 MHz): 20 μs ∗ Clock state System clock: High-frequency (fc) Clock gear: 1 (fc) Prescaler clock: fFPH Calculate the value which should be set in the timer register. To obtain a frequency of 50 kHz, the pulse cycle t should be: t = 1/50 kHz = 20 μs φT1 = (23/fc)s (at 36 MHz); 20 μs ÷ (23/fc)s ≈ 90 Therefore set TA1REG to 90 (5AH) The duty is to be set to 1/4: t × 1/4 = 20 μs × 1/4 = 5 μs 5 μs ÷ (23/fc)s ≈ 22 Therefore, set TA0REG = 22 = 16H. TA01RUN TA01MOD TA0REG TA1REG TA1FFCR 7 6 5 4 3 2 1 ← 0 ← 1 X X X – 0 0 0 Stop TMRA0 and TMRA0, 1 and clear it to 0. 0 X X X X 0 1 Set the 8-bit PPG mode, and select φT1 as input clock. ← 0 ← 0 ← X 0 0 0 1 0 1 1 0 Write 16H 1 0 1 1 0 1 0 Write 5AH X X X 0 1 1 X Set TA1FF, enabling both inversion and the double buffer. X X X – – 1 – Set PA1 as the TA1OUT pin. X X X – 1 1 1 Start TMRA0 and TMRA01 counting. Writing 10 provides negative logic pulse. PAFC2 TA01RUN ← X ← 1 X: Don’t care, −: No change 91C025-109 2007-02-28 TMP91C025 (4) 8-bit PWM (Pulse width modulation) output mode This mode is only valid for TMRA0. In this mode, a PWM pulse with the maximum resolution of 8 bits can be output. When TMRA0 is used the PWM pulse is output on the TA1OUT pin (which is also used as P71). TMRA1 can also be used as an 8-bit timer. The timer output is inverted when the up counter (UC0) matches the value set in the timer register TA0REG or when 2n counter overflow occurs (n = 6, 7 or 8 as specified by TA01MOD<PWM01:00>). The up counter UC0 is cleared when 2n counter overflow occurs. The following conditions must be satisfied before this PWM mode can be used. Value set in TA0REG < value set for 2n counter overflow Value set in TA0REG ≠ 0 TA0REG and UC0 match n 2 overflow (INTTA0 interrupt) TA1OUT tPWM (PWM cycle) Figure 3.7.16 8-Bit PWM Waveforms TA01RUN<TA0RUN> TA0IN φT1 φT4 φT16 8-bit up counter (UC0) Selector Clear 2 TAFF1 TA1FFCR <TA1FFIE> Invert n overflow control TA01MOD<TA0CLK1:0> TA1OUT TA01MOD <PWM01:00> Overflow Comparator INTTA0 TA0REG Selector TA0REG-WR Shift trigger Register buffer TA01RUN<TA0RDE> Internal data bus Figure 3.7.17 Block Diagram of 8-Bit PWM Mode 91C025-110 2007-02-28 TMP91C025 In this mode, the value of the register buffer will be shifted into TA0REG if 2n overflow is detected when the TA0REG double buffer is enabled. Use of the double buffer facilitates the handling of low duty ratio waves. Match with TA0REG Up counter = Q1 Up counter = Q2 n 2 overflow Shift into TA0REG Q2 TA0REG (value to be compared) Q1 Register buffer Q2 Q3 TA0REG (Register buffer) write Figure 3.7.18 Register Buffer Operation Example: To output the following PWM waves on the TA1OUT pin at fc = 16 MHz: 16.0 μs 28.4 μs ∗ Clock state System clock: High-frequency (fc) Clock gear: 1 (fc) Prescaler clock: fFPH To achieve a 64.0-μs PWM cycle by setting φT1 to (23/fc)s (at fc = 36 MHz): 28.4 μs ÷ (23/fc)s ≈ 128 = 2n Therefore n should be set to 7. Since the low-level period is 16.0 μsec when φT1 = (23/fc)s, set the following value for TA0REG: 16.0 μs ÷ (23/fc)s ≈ 72 = 48H MSB TA01RUN TA01MOD LSB 7 6 5 4 3 2 1 ← – ← 1 X X X – – – 0 0 Stop TMRA0 and clear it to 0. 1 1 0 – – 0 1 Select 8-bit PWM mode (cycle: 2 ) and select φT1 as the 7 input clock. TA0REG TA1FFCR PAFC2 TA01RUN ← 0 ← X 1 0 0 1 0 0 0 Write 48H. X X X 1 0 1 X Clear TA1FF to 0, enable the inversion and double buffer. ← X ← 1 X X X – – 1 – Set PA1 and the TA1OUT pin. X X X – 1 – 1 Start TMRA0 counting. X: Don’t care, −: No change 91C025-111 2007-02-28 TMP91C025 Table 3.7.3 PWM Cycle at fc = 36 MHz, fs = 32.768 kHz Select System Select Prescaler Clock Clock SYSCR1 SYSCR0 <SYSCK> <PRCK1:0> 1 (fs) 00 (fFPH) 0 (fc) 10 (fc/16 clock) PWM Cycle Gear Value 2 SYSCR1 <GEAR2:0> 6 27 28 φT1 φT4 φT16 φT1 φT4 φT16 φT1 φT4 φT16 1000 ms XXX 15.6 ms 62.5 ms 250 ms 31.3 ms 125 ms 500 ms 62.5 ms 250 ms 000 (fc) 14.2 μs 56.8 μs 227 μs 28.4 μs 113 μs 455 μs 56.8 μs 227 μs 910 μs 001 (fc/2) 28.4 μs 113 μs 455 μs 56.8 μs 227 μs 910 μs 113 μs 455 μs 1820 μs 010 (fc/4) 56.8 μs 227 μs 910 μs 113 μs 455 μs 1820 μs 227 μs 910 μs 3640 μs 011 (fc/8) 113 μs 455 μs 1820 μs 227 μs 910 μs 3640 μs 455 μs 1820 μs 7281 μs 100 (fc/16) 227 μs 910 μs 3640 μs 455 μs 1820 μs 7281 μs 910 μs 3640 μs 14563 μs XXX 227 μs 910 μs 3640 μs 455 μs 1820 μs 7281 μs 910 μs 3640 μs 14563 μs XXX: Don’t care (5) Settings for each mode Table 3.7.4 shows the SFR settings for each mode. Table 3.7.4 Timer Mode Setting Registers Register Name TA01MOD <Bit Symbol> <TA01M1:0> Function Timer Mode PWM Cycle 8-bit timer × 2 channels 00 − TA1FFCR <PWM01:00> <TA1CLK1:0> <TA0CLK1:0> TA1FFIS Upper Timer Input Clock Timer F/F Invert Signal Select Lower Timer Input Clock Lower timer match External clock φT1, φT16, φT256 φT1, φT4, φT16 (00, 01, 10, 11) (00, 01, 10, 11) − φT1, φT4, φT16 0: Lower timer output 1: Upper timer output External clock 16-bit timer mode − 01 − (00, 01, 10, 11) External clock 8-bit PPG × 1 channel − 10 − φT1, φT4, φT16 − (00, 01, 10, 11) 6 8-bit PWM × 1 channel 8-bit timer × 1 channel 11 11 7 External clock 8 2 ,2 ,2 − (01, 10, 11) − φT1, φT4, φT16 − (00, 01, 10, 11) φT1, φT16 , φT256 (01, 10, 11) − Output disabled −: Don’t care 91C025-112 2007-02-28 TMP91C025 (6) LCDC and MELODY/ALARM circuit supply mode This function can operate only TMRA3. It can use LCDC and MELODY/ALARM source clock TA3 clock generated by TMRA3. But this function is special mode, without low clock (XTIN, XTOUT) so keep the rule under below. Operate a. Clock generate by timer 3 b. Clock supply start (EMCCR0 <TA3LCDE> = 1) c. Need setup time d. LCDC or MELODY/ALARM start to operate STOP e. LCDC or MELODY/ALARM stop to operate f. Clock supply cut off (<TA3LCDE> = 0 or <TA3MLDE> = 0) EMCCR0 (00E3H) 7 6 5 4 Bit symbol PROTECT TA3LCDE AHOLD Read/Write R R/W R/W After reset 0 0 0 Function 3 2 1 0 TA3MLDE − EXTIN DRVOSCH DRVOSCL R/W R/W R/W R/W R/W 0 0 0 1 1 fc oscillator fs oscillator Protect flag LCDC source Address hold Melody/Alarm Always write 1: External 0: Off CLK 0: Normal 1: On 0: 32 kHz 1: Enable 1: TA3OUT source clock. 0. clock driver ability. driver ability. 0: 32 kHz 1: Normal 1: Normal 1: TA3OUT 0: Weak 0: Weak 91C025-113 2007-02-28 TMP91C025 3.8 External Memory Extension Function (MMU) This is MMU function which can expand program/data area to 104 Mbytes by having 4 local areas. Address pins to external memory are 2 extended address bus pins (EA24, EA25) or 3 extended chip select pins ( CS2A to CS2C ) in addition to 24 address bus pins (A0 to A23) which are common specification of TLCS-900 and 4 chip select pins ( CS0 to CS3 ) output from CS/WAIT controller. The feature and the recommendation setting method of two types are shown below. In addition, AH in the table is the value which number address 23 to 16 displayed as hex. Purpose Item (A): For Standard Extended Memory 16 Mbytes: BANK (16 Mbytes × 1 pcs) Maximum memory size Program ROM Used local area, BANK number Setting CS/WAIT Used CS pin Maximum memory size Data ROM Used local area, BANK number Setting CS/WAIT Used CS pins Option Program ROM Data RAM LOCAL2 (AH = C0 to DF: 2 Mbytes × 7 BANK) Setup AH = C0 to FF to CS2 Total memory size Setup AH = 80 to FF to CS2 CS2 CS2A 64 Mbytes : BANK 32 Mbytes : BANK (64 Mbytes × 1 pcs) (16 Mbytes × 2 pcs) LOCAL3 LOCAL3 (AH = 80 to BF: 4 Mbytes × 16 BANK) (AH = 80 to BF: 4 Mbytes × 8 BANK) Setup AH = 80 to BF to CS3 CS3 , EA24, EA25 Setup AH = 80 to FF to CS2 CS2B , CS2C Maximum memory size 16 Mbytes: BANK (16 Mbytes × 1 pcs) Used local area, BANK number LOCAL1 (AH = 40 to 5F: 2 Mbytes × 7 BANK) Setting CS/WAIT Used CS pin Setup AH = 40 to 7F to CS1 CS1 Maximum memory size 8 Mbytes: BANK (8 Mbytes × 1 pcs) Used local area, BANK number LOCAL0 (AH = 10 to 1F: 1 Mbyte × 7 BANK) Setting CS/WAIT Used CS pin Setup AH = 00 to 1F to CS0 CS0 Setup AH = 00 to 1F to CS3 CS3 2 Mbytes (2 Mbytes × 1 pcs) Maximum memory size Extended memory 1 (B): For Many Pieces Extended Memory Used local area, BANK number None Setting CS/WAIT Used CS pin Setup AH = 20 to 3F to CS0 CS0 16 M + 64 M + 16 M + 8 M 16 M + 32 M + 16 M + 8 M + 2 M = 104 Mbytes = 74 Mbytes 91C025-114 2007-02-28 TMP91C025 3.8.1 Recommendable Memory Map The recommendation logic address memory map at the time of varieties extension memory correspondence is shown in Figure 3.8.1. And a physical-address map is shown in Figure 3.8.2. However, when memory area is less than 16 Mbytes and is not expanded, please refer to section of CS/WAIT controller. Setting of register in MMU is not necessary. Since it is being fixed, the address of a local-area cannot be changed. BANK Address Size 000000H 1 Mbyte 100000H 1 Mbyte 200000H COMMON0 LOCAL0 400000H CS3 CS0 CS0 CS1 CS1 CS2 CS2B (BANK 0 to 3) 0 1 2 3 4 5 6 7 LOCAL1 COMMON1 800000H 4 Mbytes CS3 0 1 2 3 4 5 6 7 600000H 2 Mbytes CS pin Memory map 2 Mbytes 2 Mbytes CS/WAIT setting 0 1 2 … 6 7 LOCAL3 CS2C (BANK 4 to 7) C00000H 2 Mbytes 0 1 2 3 4 5 6 7 LOCAL2 E00000H 2 Mbytes CS2 COMMON2 FFFF00 256 Bytes CS2A : Internal area Vector area : Overlapped with COMMON area FFFFFF Figure 3.8.1 Logical Address Map 91C025-115 2007-02-28 TMP91C025 LOCAL0 LOCAL1 LOCAL2 CS3 CS1 CS2A for data RAM for option program ROM (16 Mbytes) for program ROM for data ROM (8 Mbytes) 000000H BANK0 BANK1 BANK2 BANK3 BANK4 BANK5 BANK6 BANK7 Internal-I/O LOCAL3 CS2B (16 Mbytes) BANK0 BANK0 BANK1 BANK1 BANK2 BANK2 BANK3 BANK3 BANK4 BANK4 BANK5 BANK5 (16 Mbytes × 2) BANK0 BANK1 800000H BANK6 BANK7 BANK2 BANK6 BANK7 BANK3 1000000H CS2C 000000H Reset and interrupt vector area BANK4 BANK5 BANK6 1000000H BANK7 : Internal area : Overlapped with COMMON area Figure 3.8.2 Physical Address Map 91C025-116 2007-02-28 TMP91C025 3.8.2 Control Registers Set a bank setting value and bank enable/disable in each local register in the common area. At this time, also specify the pin function and mapping by the CS/WAIT controller. When the CPU outputs the logical address of the local area, the MMU outputs its physical address to the external address bus pin according to the value in the bank setting register. This enables access to external memory. LOCAL0 Register 7 LOCAL0 Bit symbol L0E (0350H) Read/Write R/W After reset 0 Function 6 5 4 3 2 1 0 L0EA22 L0EA21 L0EA20 R/W 0 BANK for 0 0 Setting BANK number for LOCAL0 LOCAL0 0: Disable 1: Enable “000” setting is prohibited because it pretend COMMON 0 area LOCAL1 Register 7 LOCAL1 (0351H) Bit symbol L1E Read/Write R/W After reset Function 6 5 4 3 2 1 0 L1EA23 L1EA22 L1EA21 R/W 0 0 BANK for 0 0 Setting BANK number for LOCAL1 LOCAL1 0: Disable “001” setting is prohibited because it 1: Enable pretend COMMON 0 area LOCAL2 Register 7 LOCAL2 (0352H) Bit symbol L2E Read/Write R/W After reset Function 6 5 4 3 2 1 0 L2EA23 L2EA22 L2EA21 R/W 0 0 BANK for 0 0 Setting BANK number for LOCAL2 LOCAL2 0: Disable “111” setting is prohibited because it 1: Enable pretend COMMON 0 area LOCAL3 Register 7 LOCAL3 (0353H) 6 5 4 3 2 1 0 Bit symbol L3E − L3EA25 L3EA24 L3EA23 L3EA22 Read/Write R/W R/W R/W R/W R/W R/W After reset 0 0 0 0 Function BANK for Always 0 0 0000~0011: CS2B LOCAL3 write 0. 0100~0111: CS2C 1000~1111: Set prohibition 0: Disable 1: Enable Figure 3.8.3 Register of MMU 91C025-117 2007-02-28 TMP91C025 Data/Stack RAM CS0 SRAM 8 Mbytes 8 bits CS0 000000H to 1FFFFFH (Logical) 000000H to 7FFFFFH (Physical) Optional ROM CS1 CS1 FLASH 16 Mbytes 16 bits Data 400000H to 7FFFFFH (Logical) 000000H to FFFFFFH (Physical) Address TMP91C025 RD , ( WR , HWR : SRAM) Program ROM CS2 MROM 16 Mbytes 16 bits CS2 EA24, EA25 CS3 MROM 64 Mbytes 16 bits *In case of 16-bit bus memory TMP91C025 A16 : : 000000H to FFFFFFH (Physical) Data ROM CS3 Control signals D [0:15] A0 A1 A2 C00000H to FFFFFFH (Logical) 800000H to BFFFFFH (Logical) 0000000H to 3FFFFFFH (Physical) *In case of 8-bit bus memory Memory TMP91C025 Control signals D [0:15] open A0 A1 Control signals D [0:7] A0 A1 A2 A15 A7 Memory : : Control signals D [0:7] A0 A1 A2 A7 Figure 3.8.4 H/W Setting Example At Figure 3.8.4, it shows example of connection TMP91C025 and some memories: Program ROM: MROM, 16 Mbytes, Data ROM: MROM, 64 Mbytes, Data RAM: SRAM, 8 Mbytes, 8-bit bus, Option ROM: Flash, 16 Mbytes. In case of 16-bit bus memory connection, it need to shift 1-bit address bus from TMP91C025 and 8-bit bus case, direct connection address bus from TMP91C025. In that figure, logical address and physical address are shown. And each memory allot each chip select signal, RAM: CS0 , FLASH_ROM: CS1 , Program MROM: CS2 , Data MROM: CS3 . In case of this example, as data MROM is 64 Mbytes, this MROM connect to EA24 and EA25. Initial condition after reset, because TMP91C025 access from CS2 area, CS2 area allots to program ROM. It can set free setting except program ROM. 91C025-118 2007-02-28 TMP91C025 ;Initial Setting ;CS0 LD LD LD ;CS1 LD LD LD ;CS2 LD LD LD ;CS3 LD LD LD ;CSX LD ;Port LD to (MSAR0), 00H (MAMR0), FFH (B0CS), 89H ; Logical address area: 000000H to 1FFFFFH ; Logical address size: 2 Mbytes ; Condition: 8-bit, 1 waits (8 Mbytes, SRAM) (MSAR1), 40H (MAMR1), FFH (B1CS), 80H ; Logical address area: 400000H to 7FFFFFH ; Logical address size: 4 Mbytes ; Condition: 16-bit, 2 waits (16 Mbytes, Flash ROM) (MSAR2), C0H (MAMR2), 7FH (B2CS), C3H ; Logical address area: C00000H to FFFFFFH ; Logical address size: 4 Mbytes ; Condition: 16-bit, 0 waits (16 Mbytes, MROM) (MSAR3), 80H (MAMR3), 7FH (B3CS), 85H ; Logical address area: 800000H to BFFFFFH ; Logical address size: 4 Mbytes ; Condition: 16-bit, 3 waits (64 Mbytes, MROM) (BEXCS), 00H ; Other: 16-bit, 2 waits (Don’t care) (P6FC), 3FH ; CS0 to CS3 , EA24, EA25: port 6 setting Figure 3.8.5 Bank Operation S/W Example 1 Secondly, Figure 3.8.5 shows example of initial setting at BANK operation S/W example1 of the above. Because CS0 connect to RAM: 8-bit bus, 8 Mbytes, it need to set 8-bit bus. At this example, it set 1-wait setting. In the same way CS1 set to 16-bit bus and 2 waits, CS2 set 16-bit bus and 0 waits, CS3 set 16-bit bus and 3 waits. By CS/WAIT controller, each chip selection signal’s memory size, don’t set actual connect memory size, need to set that logical address size: fitting to each local area. Actual physical address is set by each area’s BANK register setting. CSEX setting of CS/WAIT controller is except above CS0 to CS3’s setting. Finally pin condition is set. Port 60 to 65 set to CS0 , 1, 2, 3, EA24, EA25. 91C025-119 2007-02-28 TMP91C025 ;Bank Operation ;***** /CS2 ***** ORG 000000H ORG 200000H ORG 400000H ORG 600000H ORG 800000H ORG a00000H ORG c00000H ORG to ORG ; Program ROM: Start address at BANK0 of LOCAL2 ; Program ROM: Start address at BANK1 of LOCAL2 ; Program ROM: Start address at BANK2 of LOCAL2 ; Program ROM: Start address at BANK3 of LOCAL2 ; Program ROM: Start address at BANK4 of LOCAL2 ; Program ROM: Start address at BANK5 of LOCAL2 ; Program ROM: Start address at BANK6 of LOCAL2 E00000H LD LDW (LOCAL3), 85H HL,(800000H) LD LDW (LOCAL3), 88H BC,(800000H) FFFFFFH ;***** /CS3 ***** ORG 0000000H ORG 0400000H ORG 0800000H ORG 0C00000H ORG 1000000H ORG 1400000H dw 5555H to ORG 1800000H ORG 1C00000H ORG 2000000H dw AAAAH to ORG 2400000H ORG 2800000H ORG 2C00000H ORG 3000000H ORG 3400000H ORG 3800000H ORG 3C00000H ORG 3FFFFFFH ; Program ROM: Start address at BANK7 (= COMMON2) of LOCAL2 ; Logical address E00000H to FFFFFFH ; Physical address 0E00000H to 0FFFFFFH ; LOCAL3 BANK5 set 14xxxxH ; Load data (5555H) form BANK5 (140000H: Physical address) of LOCAL3 ( CS3 ) ; LOCAL3 BANK8 set 20xxxxH ; Load data (AAAAH) form BANK8 (200000H: Physical address) of LOCAL3 ( CS3 ) ; Program ROM: End address at BANK7 (= COMMON2) of LOCAL2 ; Data ROM: Start address at BANK0 of LOCAL3 ; Data ROM: Start address at BANK1 of LOCAL3 ; Data ROM: Start address at BANK2 of LOCAL3 ; Data ROM: Start address at BANK3 of LOCAL3 ; Data ROM: Start address at BANK4 of LOCAL3 ; Data ROM: Start address at BANK5 of LOCAL3 ; Data ROM: Start address at BANK6 of LOCAL3 ; Data ROM: Start address at BANK7 of LOCAL3 ; Data ROM: Start address at BANK8 of LOCAL3 ; Data ROM: Start address at BANK9 of LOCAL3 ; Data ROM: Start address at BANK10 of LOCAL3 ; Data ROM: Start address at BANK11 of LOCAL3 ; Data ROM: Start address at BANK12 of LOCAL3 ; Data ROM: Start address at BANK13 of LOCAL3 ; Data ROM: Start address at BANK14 of LOCAL3 ; Data ROM: Start address at BANK15 of LOCAL3 ; Data ROM: End address at BANK15 of LOCAL3 Figure 3.8.6 Bank Operation S/W Example 2 Figure 3.8.6 shows example of data access between one BANK and other BANK is one software example. A dot line square area shows one memory and each dot line square shows CS2 ’s program ROM and CS3 ’s data ROM. Program start from E00000H address, firstly, write to BANK register of LOCAL3 area upper 5-bit address of access point. In case of this TMP91C025, because most upper address bit of physical address is EA25, most upper address bit of BANK register is meaningless. 4 bits of upper 5-bit address means 16 BANKs. After setting BANK5, accessing 800000H to BFFFFFH address: Logical local3 address, actually access to physical 1400000H to 1700000H address. 91C025-120 2007-02-28 TMP91C025 ;Bank Operation ;***** /CS2 ***** ORG 000000H ORG 200000H NOP to JP E00100H ORG 400000H ORG 600000H NOP to JP E00200H ORG 800000H ORG a00000H ORG c00000H ; Program ROM: Start address at BANK0 of LOCAL2 ; Program ROM: Start address at BANK1 of LOCAL2 ; Operation at BANK1of LOCAL2 ; Jump to BANK7 (= COMMON2) of LOCAL2 ; Program ROM: Start address at BANK2 of LOCAL2 ; Program ROM: Start address at BANK3 of LOCAL2 ; Operation at BANK3 of LOCAL2 ; Jump to BANK7 (= COMMON2) of LOCAL2 ; Program ROM: Start address at BANK4 of LOCAL2 ; Program ROM: Start address at BANK5 of LOCAL2 ; Program ROM: Start address at BANK6 of LOCAL2 !!!! Program Start !!!! ORG E00000H LD JP to ORG to ORG ORG (LOCAL2), 81H C00000H ; Program ROM: Start address at BANK7 (= COMMON2) of LOCAL2 ; Logical address E00000H to FFFFFFH ; Physical address 0E00000H to 0FFFFFFH ; LOCAL2 BANK1 set 20xxxxH ; Jump to BANK1 (200000H: Physical address) of LOCAL2 E00100H LD (LOCAL2), 83H JP C00000H ; LOCAL2 BANK3 set 60xxxxH ; Jump to BANK3 (600000H: Physical address) of LOCAL2 E00200H LD (LOCAL1),84H JP 400000H FFFFFFH ; LOCAL1 BANK4 set 80xxxxH ; Jump to BANK4 (800000H: Physical address) of LOCAL1 ; Program ROM: End address at BANK7(= COMMON2) of LOCAL2 ;***** /CS1 ***** ORG 000000H ORG 200000H ORG 400000H ORG 600000H LD JP ORG 800000H NOP to JP ORG a00000H ORG c00000H ORG E00000H LD JP (LOCAL1),87H 400000H 600000H (LOCAL1),80H 400000H ; Program ROM: Start address at BANK0 of LOCAL1 ; Program ROM: Start address at BANK1 of LOCAL1 ; Program ROM: Start address at BANK2 of LOCAL1 ; Program ROM: Start address at BANK3 (= COMMON1) of LOCAL1 ; LOCAL1 BANK7 set E0xxxxH ; Jump to BANK7 (E00000H: Physical address) of LOCAL1 ; Program ROM: Start address at BANK4 of LOCAL1 ; Operation at BANK4 of LOCAL1 ; Jump to BANK3 (= COMMON1) of LOCAL1 ; Program ROM: Start address at BANK5 of LOCAL1 ; Program ROM: Start address at BANK6 of LOCAL1 ; Program ROM: Start address at BANK7 of LOCAL1 ; LOCAL1 BANK0 set 00xxxxH ; Jump to BANK0 (000000H: Physical address) of LOCAL1 It’s prohibiting to set other BANK setting in except common area Program run away. ORG FFFFFFH ; Program ROM: End address at BANK7 of LOCAL1 Figure 3.8.7 Bank Operation S/W Example 3 91C025-121 2007-02-28 TMP91C025 At bank operation S/W Example 3 of the above, Figure 3.8.7 shows example of program jump. In the same way with before example, two dot line squares show each CS2 ’s program ROM and CS1 ’s option ROM. Program start from E00000H common address, firstly, write to BANK register of LOCAL2 area upper 3-bit address of jumping point. After setting BANK1, jumping C00000H to DFFFFFH address: logical local2 address, actually jump to physical 2000000H to 3FFFFFH address. When return to common area, it can only jump to E00000H to FFFFFFH without writing to BANK register of LOCAL2 area. By a way of setting of BANK register, the setting that BANK address and common address conflict with is possible. When two kinds or more logical addresses to show common area exist, management of BANK is confused. We recommends not using the BANK setting, BANK address and common address conflict with. When it jumps to one memory from other different memory, it can set same as the last time setting. It needs to write to BANK register of LOCAL1 area upper 3-bit address of jumping point. After setting BANK4, jumping 400000H to 5FFFFFH address: logical local1 address, actually jump to physical 8000000H to 9FFFFFH address. It is a mark paid attention to here, it needs to go by way of common area by all means when moves from a bank to a bank. In other words, it must write to BANK register only in common area and it is prohibit writing the BANK register in BANK area. If it modify the BANK register’s data in BANK area, program runaway. 91C025-122 2007-02-28 TMP91C025 3.9 Serial Channels TMP91C025 includes 2 serial I/O channels. For both channels either UART mode (Asynchronous transmission) or I/O Interface mode (Synchronous transmission) can be selected. • I/O interface mode Mode 0: For transmitting and receiving I/O data using the synchronizing signal SCLK for extending I/O. • UART mode Mode 1: Mode 2: Mode 3: 7-bit data 8-bit data 9-bit data In mode 1 and mode 2 a parity bit can be added. mode 3 has a wakeup function for making the master controller start slave controllers via a serial link (A multi-controller system). Figure 3.9.2, Figure 3.9.3 are block diagrams for each channel. Serial channels 0 and 1 can be used independently. Both channels operate in the same fashion except for the following points; hence only the operation of channel 0 is explained below. Table 3.9.1 Differences between Channels 0 to 1 Channel 0 Pin name Channel 1 TXD0 (PC0) TXD1 (PC3) RXD0 (PC1) CTS0 /SCLK0 (PC2) RXD1 (PC4) CTS1 /SCLK1 (PC5) IrDA mode Yes No This chapter contains the following sections: 3.9.1 Block Diagrams 3.9.2 Operation of Each Circuit 3.9.3 SFRs 3.9.4 Operation in Each Mode 3.9.5 Support for IrDA 91C025-123 2007-02-28 TMP91C025 • Mode 0 (I/O interface mode) Bit0 2 1 3 4 5 6 7 Transfer direction • Mode 1 (7-bit UART mode) No parity Start Bit0 1 2 3 4 5 6 Stop Parity Start Bit0 1 2 3 4 5 6 Parity Stop • Mode 2 (8-bit UART mode) No parity Start Bit0 1 2 3 4 5 6 7 Stop Parity Start Bit0 1 2 3 4 5 6 7 Parity Stop • Mode 3 (9-bit UART mode) Wake up Start Bit0 1 2 3 4 5 6 7 8 Stop Start Bit0 1 2 3 4 5 6 7 Bit8 Stop When bit8 = 1, address (Select code) is denoted. When bit8 = 0, data is denoted. Figure 3.9.1 Data Formats 91C025-124 2007-02-28 TMP91C025 3.9.1 Block Diagrams Figure 3.9.2 is a block diagram representing serial channel 0. Prescaler φT0 2 4 8 16 32 64 φT2 φT8 φT32 Serial clock generation circuit BR0CR <BR0CK1:0> TA0TRG (from TMRA0) ÷2 SCLK0 Concurrent with PC2 SCLK0 Concurrent with PC2 (UART only ÷ 16) SC0MOD0 <SM1:0> I/O interface mode INT request INTRX0 INTTX0 SC0MOD0 <WU> Serial channel interrupt control RXDCLK SC0MOD0 <RXE> SIOCLK SC0CR <IOC> I/O interface mode Receive counter Selector Selector SC0MOD0 <SC1:0> Selector fSYS UART mode BR0CR <BR0ADDE> Baud rate generator Selector φT0 φT2 φT8 φT32 BR0ADD <BR0K3:0> Prescaler BR0CR <BR0S3:0> Transmision counter (UART only ÷ 16) TXDCLK Receive control Transmission control SC0CR <PE> <EVEN> CTS0 SC0MOD0 <CTSE> Parity control Concurrent with PC2 Receive buffer 1 (Shift register) RXD0 Concurrent with PC1 RB8 Receive buffer 2 (SC0BUF) Error flag TB8 Transmission buffer (SC0BUF) SC0CR <OERR><PERR><FERR> TXD0 Concurrent with PC0 Internal data bus Figure 3.9.2 Block Diagram of the Serial Channel 0 (SIO0) 91C025-125 2007-02-28 TMP91C025 Prescaler φT0 2 4 8 16 32 64 φT2 φT8 φT32 Serial clock generation circuit BR1CR <BR1CK1:0> TA0TRG (from TMRA0) Selector SC1MOD0 <SC1:0> Selector Prescaler fSYS ÷2 SCLK1 Concurrent with PC5 SCLK1 Concurrent with PC5 Receive counter (UART only ÷ 16) SIOCLK SC1MOD0 <SM1:0> I/O interface mode SC1CR <IOC> I/O interface mode INT request INTRX1 INTTX1 SC1MOD0 <WU> Serial channel interrupt control RXDCLK SC1MOD0 <RXE> UART mode BR1CR <BR1ADDE> Baud rate generator Selector φT0 φT2 φT8 φT32 Selector BR1CR BR1ADD <BR1S3:0> <BR1K3:0> Transmision counter (UART only ÷ 16) TXDCLK Receive control Transmission control SC1CR <PE> <EVEN> SC1MOD0 <CTSE> Parity control RXD1 Concurrent with PC4 CTS1 Concurrent with PC5 Receive buffer 1 (Shift register) RB8 Receive buffer 2 (SC1BUF) Error flag TB8 Transmission buffer (SC1BUF) SC1CR <OERR><PERR><FERR> TXD1 Concurrent with PC3 Internal data bus Figure 3.9.3 Block Diagram of the Serial Channel 1 (SIO1) 91C025-126 2007-02-28 TMP91C025 3.9.2 Operation of Each Circuit (1) Prescaler There is a 6-bit prescaler for generating a clock to SIO0. The clock selected using SYSCR<PRCK1:0> is divided by 4 and input to the prescaler as φT0. The prescaler can be run by selecting the baud rate generator as the serial transfer clock. Table 3.9.2 shows prescaler clock resolution into the baud rate generator. Table 3.9.2 Prescaler Clock Resolution to Baud Rate Generator Select System Clock <SYSCK> Select Prescaler Clock <PRCK1:0> 1 (fs) 00 (fFPH) 0 (fc) 10 (fc/16 clock) Gear Value <GEAR2:0> Prescaler Output Clock Resolution φT0 φT2 2 2 /fs 2 2 /fc 3 2 /fc 4 2 /fc 5 2 /fc 2 /fc 6 2 /fc − 2 /fc XXX 2 /fs 000 (fc) 2 /fc 001 (fc/2) 2 /fc 010 (fc/4) 2 /fc 011 (fc/8) 2 /fc 100 (fc/16) XXX φT8 4 2 /fs 4 2 /fc 5 2 /fc 6 2 /fc 7 2 /fc 8 2 /fc 8 2 /fc φT32 6 2 /fs 8 6 2 /fc 7 2 /fc 8 2 /fc 9 2 /fc 10 2 /fc 10 2 /fc 8 9 10 11 12 12 X: Don’t care, −: Cannot be used The baud rate generator selects between 4 clock inputs: φT0, φT2, φT8, and φT32 among the prescaler outputs. 91C025-127 2007-02-28 TMP91C025 (2) Baud rate generator The baud rate generator is a circuit which generates transmission and receiving clocks which determine the transfer rate of the serial channels. The input clock to the baud rate generator, φT0, φT2, φT8 or φT32, is generated by the 6-bit prescaler which is shared by the timers. One of these input clocks is selected using the BR0CR<BR0CK1:0> field in the baud rate generator control register. The baud rate generator includes a frequency divider, which divides the frequency by 1 or N + (16 − K)/16 to 16 values, determining the transfer rate. The transfer rate is determined by the settings of BR0CR<BR0ADDE, BR0S3:0> and BR0ADD<BR0K3:0>. • In UART mode (1) When BR0CR<BR0ADDE> = 0 The settings BR0ADD<BR0K3:0> are ignored. The baud rate generator divides the selected prescaler clock by N, which is set in BR0CK<BR0S3:0>. (N = 1, 2, 3 ... 16) (2) When BR0CR<BR0ADDE> = 1 The N + (16 − K)/16 division function is enabled. The baud rate generator divides the selected prescaler clock by N + (16 − K)/16 using the value of N set in BR0CR <BR0S3:0> (N = 2, 3 ... 15) and the value of K set in BR0ADD<BR0K3:0> (K = 1, 2, 3 ... 15) Note: If N = 1 or N = 16, the N + (16 − K)/16 division function is disabled. Set BR0CR <BR0ADDE> to 0. • In I/O interface mode The N + (16 − K)/16 division function is not available in I/O interface mode. Set BR0CR<BR0ADDE> to 0 before dividing by N. The method for calculating the transfer rate when the baud rate generator is used is explained below. • In UART mode Baud rate = • Input clock of baud rate generator ÷ 16 Frequency divider for baud rate generator In I/O interface mode Baud rate = Input clock of baud rate generator Frequency divider for baud rate generator 91C025-128 ÷2 2007-02-28 TMP91C025 • Integer divider (N divider) For example, when the source clock frequency (fc) = 12.288 MHz, the input clock frequency = φT2 (fc/16), the frequency divider N (BR0CR<BR0S3:0>) = 5, and BR0CR<BR0ADDE> = 0, the baud rate in UART mode is as follows: ∗ Clock state System clock: High-frequency (fc) Clock gear: 1 (fc) Prescaler clock: System clock Baud rate = fc/16 ÷ 16 5 = 12.288 × 106 ÷ 16 ÷ 5 ÷ 16 = 9600 (bps) Note: The N + (16 − K)/16 division function is disabled and setting BR0ADD<BR0K3:0> is invalid. • N + (16 − K)/16 divider (UART mode only) Accordingly, when the source clock frequency (fc) = 4.8 MHz, the input clock frequency = φT0, the frequency divider N (BR0CR<BR0S3:0>) = 7, K (BR0ADD<BR0K3:0>) = 3, and BR0CR<BR0ADDE> = 1, the baud rate in UART Mode is as follows: ∗ Clock state System clock: High-frequency (fc) Clock gear: 1 (fc) Prescaler clock: System clock Baud rate = fc/4 ÷ 16 7 + (16 − 3)/16 = 4.8 × 106 ÷ 4 ÷ (7 + 13/16) ÷ 16 = 9600 (bps) Table 3.9.3 show examples of UART mode transfer rates. Additionally, the external clock input is available in the serial clock. (Serial channels 0, 1). The method for calculating the baud rate is explained below: • In UART mode Baud rate = External clock input frequency ÷ 16 It is necessary to satisfy (External clock input cycle) ≥ 4/fc • In I/O interface mode Baud rate = External clock input frequency It is necessary to satisfy (External clock input cycle) ≥ 16/fc 91C025-129 2007-02-28 TMP91C025 Table 3.9.3 Transfer Rate Selection (when baud rate generator is used and BR0CR<BR0ADDE> = 0) Unit (kbps) Input Clock fc [MHz] Frequency Divider N (BR0CR<BR0S3:0>) φT0 φT2 φT8 φT32 9.830400 2 76.800 19.200 4.800 1.200 ↑ 4 38.400 9.600 2.400 0.600 ↑ 8 19.200 4.800 1.200 0.300 ↑ 0 9.600 2.400 0.600 0.150 12.288000 5 38.400 9.600 2.400 0.600 ↑ A 19.200 4.800 1.200 0.300 14.745600 2 115.200 28.800 7.200 1.800 ↑ 3 76.800 19.200 4.800 1.200 ↑ 6 38.400 9.600 2.400 0.600 ↑ C 19.200 4.800 1.200 0.300 19.6608 1 307.200 76.800 19.200 4.800 ↑ 2 153.600 38.400 93.600 2.400 ↑ 4 76.800 19.10 4.800 1.200 ↑ 8 38.400 9.600 2.400 0.600 ↑ 10 19.200 4.800 1.200 0.300 22.1184 3 115.200 28.800 7.200 1.800 24.576 1 384.000 96.000 24.000 6.000 ↑ 2 192.000 48.000 12.000 3.000 ↑ 4 96.000 24.000 6.000 1.500 ↑ 5 76.800 19.200 4.800 1.200 ↑ 8 48.000 12.000 3.000 0.750 ↑ A 38.400 9.600 2.400 0.600 ↑ 10 24.000 6.000 1.500 0.375 27.0336 B 38.400 9.600 2.400 0.600 29.4912 1 460.800 115.200 28.800 7.200 ↑ 3 153.600 38.400 9.600 2.400 ↑ 4 115.200 28.800 7.200 1.800 ↑ 6 76.800 19.200 4.800 1.200 ↑ 9 51.200 12.800 3.200 1.800 ↑ C 38.400 9.600 2.400 1.600 ↑ F 30.720 7.680 1.920 1.480 ↑ 10 28.800 7.200 1.800 0.450 31.9488 D 38.400 9.600 2.400 0.600 34.4064 7 76.800 19.200 4.800 1.200 Note 1: Transfer rates in I/O interface mode are eight times faster than the values given above. Note 2: The values in this table are calculated for when fc is selected as the system clock, the clock gear is set for fc/1 and the system clock is the prescaler clock input fFPH. Timer out clock (TA0TRG) can be used for source clock of UART mode only. Calculation method the frequency of TA0TRG Frequency of TA0TRG = Note: Baud rate × 16 The TMRA0 match detect signal cannot be used as the transfer clock in I/O interface mode. 91C025-130 2007-02-28 TMP91C025 (3) Serial clock generation circuit This circuit generates the basic clock for transmitting and receiving data. • In I/O interface mode In SCLK output mode with the setting SC0CR<IOC> = 0, the basic clock is generated by dividing the output of the baud rate generator by 2, as described previously. In SCLK input mode with the setting SC0CR<IOC> = 1, the rising edge or falling edge will be detected according to the setting of the SC0CR<SCLKS> register to generate the basic clock. • In UART mode The SC0MOD0<SC1:0> setting determines whether the baud rate generator clock, the internal system clock fSYS, the match detect signal from timer TMRA0 or the external clock (SCLK0) is used to generate the basic clock SIOCLK. (4) Receiving counter The receiving counter is a 4-bit binary counter used in UART mode which counts up the pulses of the SIOCLK clock. It takes 16 SIOCLK pulses to receive 1 bit of data; each data bit is sampled three times – on the 7th, 8th and 9th clock cycles. The value of the data bit is determined from these three samples using the majority rule. For example, if the data bit is sampled respectively as 1, 0 and 1 on 7th, 8th and 9th clock cycles, the received data bit is taken to be 1. A data bit sampled as 0, 0 and 1 is taken to be 0. (5) Receiving control • In I/O interface mode In SCLK output mode with the setting SC0CR<IOC> = 0, the RXD0 signal is sampled on the rising or falling edge of the shift clock which is output on the SCLK0 pin, according to the SC0CR<SCLKS> setting. In SCLK input mode with the setting SC0CR<IOC> = 1, the RXD0 signal is sampled on the rising or falling edge of the SCLK0 input, according to the SC0CR<SCLKS> setting. • In UART mode The receiving control block has a circuit which detects a start bit using the majority rule. Received bits are sampled three times; when two or more out of three samples are 0, the bit is recognized as the start bit and the receiving operation commences. The values of the data bits that are received are also determined using the majority rule. 91C025-131 2007-02-28 TMP91C025 (6) The receiving buffers To prevent overrun errors, the receiving buffers are arranged in a double-buffer structure. Received data is stored one bit at a time in receiving buffer 1 (which is a shift register). When 7 or 8 bits of data have been stored in receiving buffer 1, the stored data is transferred to receiving buffer 2 (SC0BUF); this cause an INTRX0 interrupt to be generated. The CPU only reads receiving buffer 2 (SC0BUF). Even before the CPU reads receiving buffer 2 (SC0BUF), the received data can be stored in receiving buffer 1. However, unless receiving buffer 2 (SC0BUF) is read before all bits of the next data are received by receiving buffer 1, an overrun error occurs. If an overrun error occurs, the contents of receiving buffer 1 will be lost, although the contents of receiving buffer 2 and SC0CR<RB8> will be preserved. SC0CR<RB8> is used to store either the parity bit − added in 8-bit UART mode – or the most significant bit (MSB) – in 9-bit UART mode. In 9-bit UART mode the wake-up function for the slave controller is enabled by setting SC0MOD0<WU> to 1; in this mode INTRX0 interrupts occur only when the value of SC0CR<RB8> is 1. (7) Transmission counter The transmission counter is a 4-bit binary counter which is used in UART mode and which, like the receiving counter, counts the SIOCLK clock pulses; a TXDCLK pulse is generated every 16 SIOCLK clock pulses. SIOCLK 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 TXDCLK Figure 3.9.4 Generation of the Transmission Clock (8) Transmission controller • In I/O interface mode In SCLK output mode with the setting SC0CR<IOC> = 0, the data in the transmission buffer is output one bit at a time to the TXD0 pin on the rising or falling edge of the shift clock which is output on the SCLK0 pin, according to the SC0CR<SCLKS> setting. In SCLK input mode with the setting SC0CR<IOC> = 1, the data in the transmission buffer is output one bit at a time on the TXD0 pin on the rising or falling edge of the SCLK0 input, according to the SC0CR<SCLKS> setting. • In UART mode When transmission data sent from the CPU is written to the transmission buffer, transmission starts on the rising edge of the next TXDCLK, generating a transmission shift clock TXDSFT. 91C025-132 2007-02-28 TMP91C025 Handshake function Use of CTS pin allows data can be sent in units of one frame; thus, Overrun errors can be avoided. The handshake functions is enabled or disabled by the SC0MOD<CTSE> setting. When the CTS0 pin foes high on completion of the current data send, data transmission is halted until the CTS0 pin foes low again. However, the INTTX0 interrupt is generated, it requests the next data send to the CPU. The next data is written in the transmission buffer and data sending is halted. Though there is no RTS pin, a handshake function can be easily configured by setting any port assigned to be the RTS function. The RTS should be output high to request send data halt after data receive is completed by software in the RXD interrupt routine. TMP91C025 TMP91C025 TXD RXD CTS RTS (Any port) Sender Receiver Figure 3.9.5 Handshake Function Timing to writing to the transmission buffer CTS Send is suspended during this period [b] [a] 13 14 15 16 1 2 3 14 15 16 1 2 3 SIOCLK TXDCLK Note 1: Bit0 Start bit TXD If the CTS signal goes high during transmission, no more data will be sent after completion of the current transmission. Note 2: Transmission starts on the first falling edge of the TXDCLK clock after the CTS signal has fallen. Figure 3.9.6 CTS (Clear to send) Timing 91C025-133 2007-02-28 TMP91C025 (9) Transmission buffer The transmission buffer (SC0BUF) shifts out and sends the transmission data written from the CPU form the least significant bit (LSB) in order. When all the bits are shifted out, the transmission buffer becomes empty and generates an INTTX0 interrupt. (10) Parity control circuit When SC0CR<PE> in the serial channel control register is set to 1, it is possible to transmit and receive data with parity. However, parity can be added only in 7-bit UART mode or 8-bit UART mode. The SC0CR<EVEN> field in the serial channel control register allows either even or odd parity to be selected. In the case of transmission, parity is automatically generated when data is written to the transmission buffer SC0BUF. The data is transmitted after the parity bit has been stored in SC0BUF<TB7> in 7-bit UART mode or in SC0MOD0<TB8> in 8-bit UART mode. SC0CR<PE> and SC0CR<EVEN> must be set before the transmission data is written to the transmission buffer. In the case of receiving, data is shifted into receiving buffer 1, and the parity is added after the data has been transferred to receiving buffer 2 (SC0BUF), and then compared with SC0BUF<RB7> in 7-bit UART mode or with SC0CR<RB8> in 8-bit UART mode. If they are not equal, a parity error is generated and the SC0CR<PERR> flag is set. (11) Error flags Three error flags are provided to increase the reliability of data reception. 1. Overrun error <OERR> If all the bits of the next data item have been received in receiving buffer 1 while valid data still remains stored in receiving buffer 2 (SC0BUF), an overrun error is generated. The below is a recommended flow when the overrun-error is generated. (INTRX interrupt routine) 1) Read receiving buffer 2) Read error flag 3) If <OERR> = 1 then a) Set to disable receiving (Write 0 to SC0MOD0<RXE>) b) Wait to terminate current frame c) Read receiving buffer d) Read error flag e) Set to enable receiving (Write 1 to SC0MOD0<RXE>) f) Request to transmit again 4) Other 2. Parity error <PERR> The parity generated for the data shifted into receiving buffer 2 (SC0BUF) is compared with the parity bit received via the RXD pin. If they are not equal, a Parity error is generated. 3. Framing error <FERR> The stop bit for the received data is sampled three times around the center. If the majority of the samples are 0, a framing error is generated. 91C025-134 2007-02-28 TMP91C025 (12) Timing generation a. In UART mode Receiving Mode Interrupt Timing Framing Error Timing Center of last bit. Center of last bit. (Bit8) (Parity bit) Center of stop bit. Center of stop bit. Center of last bit. − Parity Error Timing Overrun Error Timing 8 Bits + Parity 9 Bits (Parity bit) Center of last bit. Center of last bit. (Bit8) (Parity bit) 8 Bits, 7 Bits + Parity, 7 Bits Center of stop bit. Center of stop bit. Center of stop bit. Center of stop bit. Note: In 9-Bit and 8-Bit+Parity mode, interrupts coincide with the ninth bit pulse.Thus, when servicing the interrupt, it is necessary to wait for a 1-bit period (to allow the stop bit to be transferred) to allow checking for a framing error. Transmitting Mode Interrupt Timing 9 Bits 8 Bits + Parity 8 Bits, 7 Bits + Parity, 7 Bits Just before stop bit is Just before stop bit is Just before stop bit is transmitted. transmitted. transmitted. b. I/O interface Transmission Interrupt Timing Receiving SCLK output mode SCLK input mode SCLK output mode Interrupt Timing SCLK input mode Immediately after last bit data. (See Figure 3.9.19.) Immediately after rise of last SCLK signal rising mode, or immediately after fall in falling mode. (See Figure 3.9.20.) Timing used to transfer received to data receive buffer 2 (SC0BUF) (e.g. immediately after last SCLK). (See Figure 3.9.21.) Timing used to transfer received data to receive buffer 2 (SC0BUF) (e.g. immediately after last SCLK). (See Figure 3.9.22.) 91C025-135 2007-02-28 TMP91C025 3.9.3 SFRs SC0MOD0 Bit symbol (0202H) Read/Write After reset Function 7 6 5 4 TB8 CTSE RXE WU 3 2 1 0 SM1 SM0 SC1 SC0 0 0 0 0 R/W 0 0 0 0 Transfer Hand shake Receive Wakeup Serial transmission Serial transmission clock. data bit8. 0: CTS function. function. mode. (UART) 0: Receive 0: Disable 00: I/O interface mode 00: TMRA0 trigger disable 1: Enable 01: 7-bit UART mode 01: Baud rate disable 1: CTS enable 1: Receive 10: 8-bit UART mode enable 11: 9-bit UART mode generator 10: Internal clock fSYS 11: External clcok (SCLK0 input) Serial transmission clock source (UART) 00 Timer TMRA0 match detect signal 01 Baud rate generator 10 Internal clock fSYS 11 External clock (SCLK0 input) Note: The clock selection for the I/O interface mode is controlled by the serial bontrol register (SC0CR). Serial transmission mode 00 01 10 11 I/O interface mode 7-bit mode UART mode 8-bit mode 9-bit mode Wakeup function 9-bit UART Other modes Interrupt generated when 0 data is received Don’t care Interrupt generated only 1 when SC0CR<RB8> = 1 Receiving function 0 1 Receive disabled Receive enabled Handshake function ( CTS pin) Enable 0 1 Disabled (Always transferable) Enabled Transmission data bit8 Figure 3.9.7 Serial Mode Control Register (SIO0, SC0MOD0) 91C025-136 2007-02-28 TMP91C025 SC1MOD0 (020AH) Bit symbol 7 6 5 4 TB8 CTSE RXE WU Read/Write After reset Function 3 2 1 0 SM1 SM0 SC1 SC0 0 0 0 0 R/W 0 0 0 0 Transfer Hand shake Receive Wakeup Serial transmission Serial transmission clock. data bit8. 0: CTS function. function. mode. (UART) 0: Receive 0: Disable 00: I/O interface mode 00: TMRA0 trigger 1: Enable 01: 7-bit UART mode 01: Baud rate disable 1: CTS enable disable 1: Receive 10: 8-bit UART mode enable 11: 9-bit UART mode generator 10: Internal clock fSYS 11: External clcok (SCLK1 input) Serial transmission clock source (for UART) 00 Timer TMRA0 match detect signal 01 Baud rate generator 10 Internal clock fSYS 11 External clock (SCLK1 input) Serial transmission mode 00 01 10 11 I/O Interface Mode 7-bit mode UART mode 8-bit mode 9-bit mode Wakeup function 9-bit UART Other modes Interrupt generated when 0 data is received Don’t care Interrupt generated only 1 when SC1CR<RB8> = 1 Receiving function 0 1 Receive disabled Receive enabled Handshake function ( CTS pin) enables 0 1 Disabled (Always transferable) Enabled Transmission data bit8 Figure 3.9.8 Serial Mode Control Register (SIO1, SC1MOD0) 91C025-137 2007-02-28 TMP91C025 SC0CR (0201H) 7 6 Bit symbol RB8 EVEN Read/Write R After reset Undefined Function 5 4 3 2 1 PE OERR PERR FERR SCLKS R/W R (Cleared to 0 when read.) 0 0 0 Received Parity Parity data bit8. 0: Odd addition. 1: Even 0: Disable 0 0 IOC R/W 0 0 0: SCLK0 1: Enable 0 0: Baud rate 1: Error generator Overrun Parity Framing 1: SCLK0 1: SCLK0 pin input I/O interface input clock selection 0 1 Baud rate generator SCLK0 pin input Edge selection for SCLK pin (I/O mode) Transmits and receivers data on rising edge of SCLK0. Transmits and receivers data on falling edge SCLK0. 0 1 Framing error flag Parity error flag Overrun error flag Cleared to 0 when read Parity addition enables 0 1 Disabled Enabled Even parity addition/check 0 1 Odd parity Even parity Received data bit8 Note: As all error flags are cleared after reading do not test only a single bit with a bit testing instruction. Figure 3.9.9 Serial Control Register (SIO0, SC0CR) 91C025-138 2007-02-28 TMP91C025 SC1CR (0209H) 7 6 Bit symbol RB8 EVEN Read/Write R After reset Undefined Function 5 4 3 2 1 PE OERR PERR FERR SCLKS R/W R (Cleared to 0 when read.) 0 0 0 Received Parity Parity data bit8. 0: Odd addition. 1: Even 0: Disable 1: Enable 0 0 IOC R/W 0 0 0 0: SCLK1 0: Baud rate 1: Error generator 1: SCLK1 Overrun Parity Framing 1: SCLK1 pin input I/O interface input clock select 0 1 Baud rate generator SCLK1 pin input Edge selection for SCLK pin (I/O mode) Transmits and receive data on rising edge of SCLK1. Transmits and receive data on falling edge of SCLK1. 0 1 Framing error flag Parity error flag Overrun error flag Cleared to 0 when read Parity addition enables 0 1 Disabled Enabled Even parity addition/check 0 1 Odd parity Even parity Received data bit8 Note: As all error flags are cleared after reading do not test only a single bit with a bit testing instruction. Figure 3.9.10 Serial Control Register (SIO1, SC1CR) 91C025-139 2007-02-28 TMP91C025 Bit symbol BR0CR (0203H) 7 6 5 4 − BR0ADDE BR0CK1 BR0CK0 Read/Write 2 1 0 BR0S3 BR0S2 BR0S1 BR0S0 0 0 0 0 R/W After reset 0 Function 0 0 0 Always +(16 − K)/16 00: φT0 write 0. division. 01: φT2 0: Disable 10: φT8 Setting the divided frequency “N”. 1: Enable 11: φT32 (0 to F) +(16 − K)/16 division enable Setting the input clock of baud rate generator 0 Disable 00 Internal clock φT0 1 Enable 01 Internal clock φT2 10 Internal clock φT8 11 Internal clock φT32 7 BR0ADD (0204H) 3 6 5 4 Bit symbol 3 2 1 0 BR0K3 BR0K2 BR0K1 BR0K0 0 0 0 0 Read/Write R/W After reset Function Sets frequency divisor “K”. (Divided by N + (16 − K)/16) Sets baud rate generator frequency divisor BR0CR<BR0ADDE> = 1 BR0CR <BR0S3:0> BR0ADD BR0CR<BR0ADDE> = 0 0000 (N = 16) 0010 (N = 2) or to 0001 (N = 1) (UART only) to 1111 (N = 15) 0001 (N = 1) 1111 (N = 15) <BR0K3:0> 0000 Disable 0001 (K = 1) Divided by Disable to 0000 (N = 16) Disable Divided by N N + (16 − K)/16 1111 (K = 15) Note1:Availability of +(16-K)/16 division function N UART mode I/O mode 2 to 15 ○ × 1 , 16 × × The baud rate generator can be set “1” in UART mode and disable +(16-K)/16 division function.Don’t use in I/O interface mode. Note2:Set BR0CR <BR0ADDE> to 1 after setting K (K = 1 to 15) to BR0ADD<BR0K3:0> when +(16-K)/16 division function is used. Writes to unused bits in the BR0ADD register do not affext operation, and undefined data is read from these unused bits. Figure 3.9.11 Baud Rate Generator Control (SIO0, BR0CR, BR0ADD) 91C025-140 2007-02-28 TMP91C025 Bit symbol BR1CR (020BH) 7 6 5 4 − BR1ADDE BR1CK1 BR1CK0 Read/Write 2 1 0 BR1S3 BR1S2 BR1S1 BR1S0 0 0 0 0 R/W After reset 0 Function 0 0 0 Always +(16 − K)/16 00: φT0 write 0. division. 01: φT2 0: Disable 10: φT8 Setting the divided frequency “N”. 1: Enable 11: φT32 (0 to F) +(16 − K)/16 division enable Input clock selection for baud rate generator 0 Disabled 00 Internal clock φT0 1 Enabled 01 Internal clock φT2 10 Internal clock φT8 11 Internal clock φT32 7 BR1ADD (020CH) 3 6 5 4 Bit symbol 3 2 1 0 BR1K3 BR1K2 BR1K1 BR1K0 0 0 0 0 Read/Write R/W After reset Function Sets frequency divisor “K”. (Divided by N + (16 − K)/16) Baud rate generator frequency divisor setting BR1CR<BR1ADDE> = 1 BR0CR <BR1S3:0> BR1ADD <BR1K3:0> 0000 0000 (N = 16) 0010 (N = 2) or to 0001 (N = 1) 1111 (N = 15) Disable Disable 0001 (K = 1) Disable to BR1CR<BR1ADDE> = 0 1111 (K = 15) Disabled by 0001 (N = 1) (UART only) to 1111 (N = 15) 0000 (N = 16) Divided by N N + (16 − K)/16 Note1:Availability of +(16-K)/16 division function N UART mode I/O mode 2 to 15 ○ × 1 , 16 × × The baud rate generator can be set “1” in UART mode and disable +(16-K)/16 division function.Don’t use in I/O interface mode. Note2:Set BR1CR <BR1ADDE> to 1 after setting K (K = 1 to 15) to BR10ADD<BR1K3:0> when +(16-K)/16 division function is used. Writes to unused bits in the BR1ADD register do not affext operation, and undefined data is read from these unused bits. Figure 3.9.12 Baud Rate Generator Control (SIO1, BR1CR, BR1ADD) 91C025-141 2007-02-28 TMP91C025 SC0BUF (0200H) 7 6 5 4 3 2 1 0 TB7 TB6 TB5 TB4 TB3 TB2 TB1 TB0 7 6 5 4 3 2 1 0 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 (Transmission) (Receiving) Note: Prohibit read-modify-write for SC0BUF. Figure 3.9.13 Serial Transmission/Receiving Buffer Registers (SIO0, SC0BUF) SC0MOD1 (0205H) 7 6 Bit symbol I2S0 FDPX0 Read/Write R/W R/W After reset 0 Function 5 4 3 2 1 0 0 IDLE2 Duplex 0: Stop 0: Half 1: Run 1: Full Figure 3.9.14 Serial Mode Control Register 1 (SIO0, SC0MOD1) SC1BUF (0208H) 7 6 5 4 3 2 1 0 TB7 TB6 TB5 TB4 TB3 TB2 TB1 TB0 7 6 5 4 3 2 1 0 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 (Transmission) (Receiving) Note: Prohibit read-modify-write for SC1BUF. Figure 3.9.15 Serial Transmission/Receiving Buffer Registers (SIO1, SC1BUF) SC1MOD1 (020DH) 7 6 Bit symbol I2S1 FDPX1 Read/Write R/W R/W After reset 0 Function 5 4 3 2 1 0 0 IDLE2 Duplex 0: Stop 0: Half 1: Run 1: Full Figure 3.9.16 Serial Mode Control Register 1 (SIO1, SC1MOD1) 91C025-142 2007-02-28 TMP91C025 3.9.4 Operation in Each Mode (1) Mode 0 (I/O interface mode) This mode allows an increase in the number of I/O pins available for transmitting data to or receiving data from an external shift register. This mode includes the SCLK output mode to output synchronous clock SCLK and SCLK input mode to input external synchronous clock SCLK. Output extension Input extension Shift register TMP91C025 A TMP91C025 Shift register A QH C B TXD SI C B RXD D SCLK SCK E D SCLK CLOCK E S/ L G F Port RCK G F Port H H TC74HC165 or equivalent TC74HC595 or equivalent Figure 3.9.17 SCLK Output Mode Connection Example Output extension Input extension Shift register TMP91C025 A TMP91C025 Shift register A QH C B TXD SI C B RXD D SCLK SCK E D SCLK CLOCK E S/ L G F Port RCK G F Port H H TC74HC165 or equivalent TC74HC595 or equivalent External clock External clock Figure 3.9.18 SCLK Input Mode Connection Example 91C025-143 2007-02-28 TMP91C025 a. Transmission In SCLK output mode 8-bit data and a synchronous clock are output on the TXD0 and SCLK0 pins respectively each time the CPU writes the data to the transmission buffer. When all data is output, INTES0<ITX0C> will be set to generate the INTTX0 interrupt. Timing to write transmission data SCLK0 output (<SCLKS>=0 Rising edge mode) (Internal clock timing) SCLK0 output (<SCLKS>=1 Falling edge mode) Bit1 Bit0 TXD0 Bit6 Bit7 ITX0C (INTTX0 Interrupt request) Figure 3.9.19 Transmitting Operation in I/O Interface Mode (SCLK0 output mode) In SCLK input mode, 8-bit data is output on the TXD0 pin when the SCLK0 input becomes active after the data has been written to the transmission buffer by the CPU. When all data is output, INTES0<ITX0C> will be set to generate INTTX0 interrupt. SCLK0input (<SCLKS> = 0 Rising edge mode) SCLK0 input (<SCLKS> = 1 Falling edge mode) TXD0 Bit0 Bit1 Bit5 Bit6 Bit7 ITX0C (INTTX0 Interrupt request) Figure 3.9.20 Transmitting Operation in I/O Interface Mode (SCLK0 input mode) 91C025-144 2007-02-28 TMP91C025 b. Receiving In SCLK output mode, the synchronous clock is outputted from SCLK0 pin and the data is shifted to receiving buffer 1. This starts when the receive interrupt flag INTES0<IRX0C> is cleared by reading the received data. When 8-bit data are received, the data will be transferred to receiving buffer 2 (SC0BUF according to the timing shown below) and INTES0<IRX0C> will be set to generate INTRX0 interrupt. The outputting for the first SCLK0 starts by setting SC0MOD0<RXE> to 1. IRX0C (INTRX0 interrupt request) SCLK0 output (<SCLKS>=0 Rising edge mode) SCLK0 output (<SCLKS>=1 Fallingf edge mode) RXD0 Bit1 Bit0 Bit6 Bit7 Figure 3.9.21 Receiving Operation in I/O Interface Mode (SCLK0 output mode) In SCLK input mode, the data is shifted to receiving buffer 1 when the SCLK input becomes active after the receive interrupt flag INTES0<IRX0C> is cleared by reading the received data. When 8-bit data is received, the data will be shifted to receiving buffer 2 (SC0BUF according to the timing shown below) and INTES0<IRX0C> will be set again to be generate INTRX0 interrupt. SCLK0 input (<SCLKS> = 0: Rising edge mode) SCLK0 input (<SCLKS> = 1: Falling edge mode) Bit0 RXD0 Bit1 Bit5 Bit6 Bit7 IRX0C (INTRX0 ) Figure 3.9.22 Receiving Operation in I/O Interface Mode (SCLK0 input mode) Note: The system must be put in the receive enable state (SCMOD0<RXE> = 1) before data can be received. 91C025-145 2007-02-28 TMP91C025 c. Transmission and receiving (Full duplex mode) When the full duplex mode is used, set the level of receive interrupt to 0 and set enable the interrupt level (1 to 6) to the transfer interrupt. In the transfer interrupt program, the receiving operation should be done like the above example before setting the next transfer data. (Example) Channel 0, SCLK output Baud rate = 9600 bps fc = 14.7456 MHz System clock: High-frequency (fc) Clock gear: 1 (fc) Prescaler clock: fFPH Main routine 7 6 5 4 3 2 1 0 INTES0 0 0 0 1 0 0 0 0 Set the INTTX0 level to 1. Set the INTRX0 level to 0. PCCR − − − − − 1 0 1 Set PC0, PC1 and PC2 to function as the TXD0, RXD0 PCFC − − − − − 1 − 1 SC0MOD0 0 0 0 0 0 0 0 0 SC0MOD1 1 1 X X X X X X Select full duplex Mode. SC0CR 0 0 0 0 0 0 0 0 SCLK output, transmit on negative edge, receive on BR0CR 0 0 1 1 0 0 1 1 Baud rate = 9600 bps SC0MOD0 0 0 1 0 0 0 0 0 Enable receiving SC0BUF * * * * * * * * Set the transmit data and start. * * * and SCLK0 pins respectively. Select I/O interface Mode. positive edge INTTX0 interrupt routine Acc SC0BUF SC0BUF Read the receiving buffer. * * * * * Set the next transmit data. X: Don’t care, −: No change 91C025-146 2007-02-28 TMP91C025 (2) Mode 1 (7-bit UART mode) 7-bit UART mode is selected by setting serial channel mode register SC0MOD0 <SM1:0> to 01. In this mode, a parity bit can be added. Use of a parity bit is enabled or disabled by the setting of the serial channel control register SC0CR<PE> bit; whether even parity or odd parity will be used is determined by the SC0CR<EVEN> setting when SC0CR<PE> is set to 1 (Enabled). (Setting example) When transmitting data of the following format, the control registers should be set as described below. This explanation applies to channel 0. Start Bit0 1 2 3 4 5 6 Even parity Stop Transmission direction (transmission rate: 2400 bps at fc = 12.288 MHz) ∗ Clock state System clock: High-frequency (fc) Clock gear: 1 (fc) Prescaler clock: fFPH 7 6 5 4 3 2 1 0 P9CR P9FC SC0MOD SC0CR BR0CR INTES0 SC0BUF ← − − − − − − − 1 ← − − − − − − − 1 Set PC0 to function as the TXD0 pin. ← X 0 − X 0 1 0 1 ← X 1 1 X X X 0 0 Select 7-bit UART mode. Add even parity. ← 0 0 1 0 0 1 0 1 ← 1 1 0 0 − − − − ← * * * * * * * * Set the transfer rate to 2400 bps. Enable the INTTX0 interrupt and set it to interrupt level 4. Set data for transmission. X: Don’t care, −: No change (3) Mode 2 (8-bit UART mode) 8-bit UART mode is selected by setting SC0MOD0<SM1:0> to 10. In this mode, a parity bit can be added (Use of a parity bit is enabled or disabled by the setting of SC0CR<PE>); whether even parity or odd parity will be used is determined by the SC0CR<EVEN> setting when SC0CR<PE> is set to 1 (Enabled). (Setting example) When receiving data of the following format, the control registers should be set as described below. Start Bit0 1 2 3 4 5 6 7 Odd parity Stop Transmission direction (transmission rate: 9600 bps at fc = 12.288 MHz) 91C025-147 2007-02-28 TMP91C025 ∗ Clock state System clock: High-frequency (fc) Clock gear: 1 (fc) Prescaler clock: fFPH Main settings 7 6 5 4 3 2 1 0 ← − − − − − − 0 − SC0MOD ← − 0 1 X 1 0 0 1 PCCR Set PC1 to function as the RXD0 pin. Enable receiving in 8-bit UART mode. Add even parity. BR0CR ← X 0 1 X X X 0 0 ← 0 0 0 1 0 1 0 1 INTES0 ← − − − − 1 1 0 0 Enable the INTRX0 interrupt and set it to interrupt level 4. SC0CR Set the transfer rate to 9600 bps. Interrupt processing if Acc ← SC0CR AND 00011100 ≠ 0 then ERROR Check for errors. Acc ← SC0BUF Read the received data. Acc X: Don’t care, −: No change (4) Mode 3 (9-bit UART mode) 9-bit UART mode is selected by setting SC0MOD0<SM1:0> to 11. In this mode parity bit cannot be added. In the case of transmission the MSB (9th bit) is written to SC0MOD0<TB8>. In the case of receiving it is stored in SC0CR<RB8>. When the buffer is written and read, the MSB is read or written first, before the rest of the SC0BUF data. Wakeup function In 9-bit UART mode, the wakeup function for slave controllers is enabled by setting SC0MOD0<WU> to 1. The interrupt INTRX0 occurs only when<RB8> = 1. TXD RXD Master TXD RXD Slave 1 TXD RXD Slave 2 TXD RXD Slave 3 Note: The TXD pin of each slave controller must be in open-drain output mode. Figure 3.9.23 Serial Link Using Wakeup Function 91C025-148 2007-02-28 TMP91C025 Protocol a. Select 9-bit UART mode on the master and slave controllers. b. Set the SC0MOD0<WU> bit on each slave controller to 1 to enable data receiving. c. The master controller transmits one-frame data including the 8-bit select code for the slave controllers. The MSB (bit8)<TB8> is set to 1. Start Bit0 1 2 3 4 5 6 7 Select code of slave controller 8 Stop 1 d. Each slave controller receives the above frame. Each controller checks the above select code against its own select code. The controller whose code matches clears its WU bit to 0. e. The master controller transmits data to the specified slave controller whose SC0MOD<WU> bit is cleared to 0. The MSB (bit8) <TB8> is cleared to 0. Start Bit0 1 2 3 4 Data f. 5 6 7 Bit8 Stop 0 The other slave controllers (whose <WU> bits remain at 1) ignore the received data because their MSBs (Bit8 or <RB8>) are set to 0, disabling INTRX0 interrupts. The slave controller (WU bit = 0) can transmit data to the master controller, and it is possible to indicate the end of data receiving to the master controller by this transmission. 91C025-149 2007-02-28 TMP91C025 (Setting example) To link two slave controllers serially with the master controller using the internal clock fSYS as the transfer clock. TXD RXD TXD Master RXD TXD RXD Slave 1 Slave 2 Select code 00000001 Select code 00001010 Figure 3.9.24 UART Block Connection Since serial channels 0 and 1 operate in exactly the same way, channel 0 only is used for the purposes of this explanation. • Setting the master controller Main INTES0 ← − − − − − − 0 1 ← X X − X − − X 1 ← 1 1 0 0 1 1 0 1 Enable the INTTX0 interrupt and set it to interrupt level 4. SC0MOD0 ← 1 0 1 0 1 1 1 0 Set fSYS as the transmission clock for 9-bit UART mode. SC0BUF ← 0 0 0 0 0 0 0 1 Set the select code for slave controller 1. PCCR PCFC Set PC0 and PC1 to function as the TXD0 and RXD0 pins respectively. Enable the INTRX0 interrupt and set it to interrupt level 5. INTTX0 interrupt SC0MOD0 SC0BUF • ← 0 − − − − − − − ← * * * * * * * * Set TB8 to 0. Set data for transmission. Setting the slave controller Main INTES0 ← − − − − − − 0 ← X X − X − − X ← X X X X − X X ← 1 1 0 1 1 1 1 SC0MOD0 ← 0 0 1 1 1 1 1 0 PCCR PCFC PCODE 1 1 Set PC1 to RXD and PC0 to TXD0 (Open-drain output). 1 0 Enable INTRX0 and INTTX0. Set <WU> to 1 in 9-bit UART transmission mode using fSYS as the transfer clock. INTRX0 interrupt Acc ← SC0BUF if Acc = Select code Then SC0MOD0 ← − − − 0 − − − − Clear <WU> to 0. 91C025-150 2007-02-28 TMP91C025 3.9.5 Support for IrDA SIO0 includes support for the IrDA 1.0 infrared data communication specification. Figure 3.9.25 shows the block diagram. Transmisison data SIO0 TXD0 IR modulator IR transmitter & LED IR output Modem Receive data RXD0 IR demodulator IR receiver IR input TMP91C025 Figure 3.9.25 IrDA Block Diagram (1) Modulation of the transmission data When the transfer data is 0, the modem outputs 1 to TXD0 pin with either 3/16 or 1/16 times for width of baud-rate. The pulse width is selected by the SIRCR<PLSEL>. When the transfer data is 1, the modem outputs 0. Transmission data Start 0 1 0 0 1 1 0 0 Stop TXD0 pin Figure 3.9.26 Modulation Example of Transfer Data (2) Demodulation of the receive data When the receive data has the effective high-level pulse width (Software selectable), the modem outputs 0 to SIO0. Otherwise the modem outputs 1 to SIO0. The receive pulse logic is also selectable by SIRCR<RXSEL>. Receive pulse <RXSEL> = “0” Receive pulse <RXSEL> = “1” Demodulated data Start 1 0 0 1 0 1 1 0 Stop Figure 3.9.27 Demodulation Example of Receive Data 91C025-151 2007-02-28 TMP91C025 (3) Data format The data format is fixed as follows: • Data length: 8 bits • Parity bits: None • Stop bits: 1 Any other settings don’t guarantee the normal operation. (4) SFR Figure 3.9.28 shows the control register SIRCR. Set the data SIRCR during SIO0 is inhibited (Both TXEN and RXEN of this register should be set to 0). Any changing for this register during transmission or receiving operation doesn’t guarantee the normal operation. The following example describes how to set this register: 1) SIO setting ; Set the SIO to UART mode. ↓ 2) LD (SIRCR), 07H ; Set the receive data pulse width to 16×. 3) LD (SIRCR), 37H ; TXEN, RXEN enable the transmission and receiving of SIO. ↓ 4) Start transmission and receiving for SIO0 ; The modem operates as follows: y SIO0 starts transmitting. y IR receiver starts receiving. (5) Notes 1) Baud rate generator for IrDA To generate baud-rate for IrDA, use baud-rate generator in SIO0 by setting 01 to SC0MOD0<SC1:0>. To use another source (TA0TRG, fSYS and SCLK0 input) are not allowed. 2) As the IrDA 1.0 physical layer specification, the data transfer speed and infra red pulse width is specified. Table 3.9.4 Baud Rate and Pulse Width Specifications Modulation Rate Tolerance (% of rate) Pulse Width (Min) Pulse Width (Typ.) Pulse width (Max) 2.4 kbps RZI ±0.87 1.41 μs 78.13 μs 88.55 μs 9.6 kbps RZI ±0.87 1.41 μs 19.53 μs 22.13 μs 19.2 kbps RZI ±0.87 1.41 μs 9.77 μs 11.07 μs 38.4 kbps RZI ±0.87 1.41 μs 4.88 μs 5.96 μs 57.6 kbps RZI ±0.87 1.41 μs 3.26 μs 4.34 μs 115.2 kbps RZI ±0.87 1.41 μs 1.63 μs 2.23 μs Baud Rate The infra red pulse width is specified either baud rate T x 3/16 or 1.6 μs (1.6 μs is equal to 3/16 pulse width when baud rate is 115.2 kbps). The TMP91C025 has the function selects the pulse width on the transmission either 3/16 or 1/16. But 1/16 pulse width can be selected when the baud rate is equal or less than 38.4 kbps only. When 38.4 kbps and 115.2 kbps, the output pulse width should not be set to T x 1/16. 91C025-152 2007-02-28 TMP91C025 As the same reason, + (16 − K)/16 division functions in the baud rate generator of SIO0 can not be used to generate 115.2 kbps baud-rate. Also when the 38.4 kbps and 1/16 pulse width, + (16 − K)/16 divisions function can not be used. Table 3.9.5 shows “Baud-rate and Pulse Width for (16 − K)/16 Division Function”. Table 3.9.5 Baud-rate and Pulse Width for (16 − K)/16 Division Function Pulse Width Baud-rate 115.2 kbps 57.6 kbps 38.4 kbps 19.2 kbps T × 3/16 × ○ ○ T × 1/16 − − × ○ ○ 9.6 kbps 2.4 kbps ○ ○ ○ ○ ○: Can be used (16 − K)/16 division function ×: Can not be used (16 − K)/16 division function −: Can not be set to 1/16 pulse width 91C025-153 2007-02-28 TMP91C025 SIRCR (0207H) Bit symbol 7 6 5 4 PLSEL RXSEL TXEN RXEN Read/Write After reset Function 3 2 1 0 SIRWD3 SIRWD2 SIRWD1 SIRWD0 0 0 0 R/W 0 0 0 0 0 Select Receive Transmit Receive Select receive pulse width transmit data. 0: Disable 0: Disable Set effective pulse width for equal or more than pulse 0: H pulse 1: Enable 1: Enable 2x × (value + 1) + 100ns width. 1: L pulse Can be set: 1 to 14 Can not be set: 0, 15. 0: 3/16 1: 1/16 Select receive pulse width Formula: Effective pulse width ≥ 2x × (value + 1) + 100ns x = 1/fFPH 0000 Cannot be set 0001 Equal or more than 4x + 100nS to 1110 Equal or more than 30x + 100nS 1111 Can not be set Receive operation 0 Disabled 1 Enabled Transmit operation 0 Disabled 1 Enabled Select transmit pulse width 0 3/16 1 1/16 Figure 3.9.28 IrDA Control Register 91C025-154 2007-02-28 TMP91C025 3.10 Touch Screen Interface (TSI) The TMP91C025 has an interface for 4-terminal resistor network touch-screen. This interface supports two procedures: an X/Y position measurement and touch detection. Each procedure can be performed by setting the TSI control register (TSICR0 and TSICR1) and using an internal AD converter. 3.10.1 Touch Screen Interface Module Internal/External Connection TMP91C025FG YMY X+ Touch screen MX X- PY PX Y+ External capacitors Figure 3.10.1 External Connection of TSI (A) Touch screen control AVCC PXEN AVSS SPY SPX PB6 (PY) Dec. PYEN MXEN INT2 MYEN PTST TSI7 (PX) P83 PXD (typ.200 kΩ) AD Converter (MY) AN3 P82 AN2 (MX) VREFH Internal data bus INT2 PB5/INT2 SMX SMY AVCC AVSS VREFH VREFL VREFL Figure 3.10.2 Internal Block Diagram of TSI (B) 91C025-155 2007-02-28 TMP91C025 3.10.2 Touch Screen Interface (TSI) Control Register TSI Control Register 7 TSICR0 (002BH) 5 4 3 2 1 0 Bit symbol TSI7 PTST TWIEN PYEN PXEN MYEN MXEN Read/Write R/W R R/W R/W R/W R/W R/W After reset 0 0 0 0 0 0 Function 6 0 0: Disable Detection INT2 SPY SPX SMY SMX 1: Enable condition interrupt 0 : OFF 0 : OFF 0 : OFF 0 : OFF 1 : ON 1 : ON 1 : ON 1 : ON 0: no touch control 1: touch 0: Disable 1: Enable PXD (Internal Pull-down resistor) ON/OFF setting Bit5 monitors whether the screen was touched or not. The bit is 1 while the screen has been touched. <PXEN> 0 1 <TSI7> 0 OFF OFF 1 ON OFF De-bounce Time Setting Register TSICR1 (002CH) 7 6 5 4 3 2 1 0 Bit symbol DBC7 DB1024 DB256 DB64 DB8 DB4 DB2 DB1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W After reset 0 0 0 0 0 0 0 0 1024 256 64 8 4 2 1 Function 0: Disable 1: Enable De-bounce time is set by “(N × 64 − 16)/fSYS” – formula. “N” is sum of number which is set to 1 in bit6 to bit0. 91C025-156 2007-02-28 TMP91C025 3.10.3 Touch Detection Procedure A touch detection procedure is a preparing procedure till a pen touches to the screen. When the waiting state, ON only SPY-switch and OFF other 3-switch (SMY, SPX and SMX). During this waiting state, PB5/INT2/PX pin’s level is L because of the internal resistors between X and Y directions in the touch screen are not connected and INT2 isn’t generated. If the pen touches, PB5/INT2/PX pin’s level is H because of the internal pull-down register (PXD) between X and Y direction in the touch screen are connected and INT2 will be generated. And the de-bounce circuit like following diagram is prepared to avoid some number’s interrupt generation though one time touch. This can ignore the pulse under the time which is set to TSICR1 register. TSICR0<TWIEN>, IIMC<I2EDGE>, PBFC<PB5F> TSICR1 Enables INT2 and selects the Rising edge or Falling edge of INT2 De-bounce circuit PB5/INT2 pin F/F INT2 TSICR0 <PTST> Figure 3.10.3 Block Diagram of De-bounce Circuit PB5/INT2 pin Reset counter for de-bounce time Start counter for de-bounce time De-bounce time De-bounce time De-bounce time INT2 INT2 is generated by matching counter and specified de-bounce time. After pen is detouched, INT2 can be issued again. INT2 isn’t generated by matching counter and specified de-bounce time because of it is an edge-type interrupt. Figure 3.10.4 Timing Diagram of De-bounce Circuit 91C025-157 2007-02-28 TMP91C025 3.10.4 X/Y Position Measuring Procedure In the INT2 routine, execute an X/Y position measuring procedure like below. <X position measurement> At first, ON both SPX and SMX-switches and OFF SPY, SMY-switches. By this setting, analog-voltage which shows the X position will be inputted to P83/MY/AN3 pin. The X position can be measured by converting this voltage to digital code with AD converter. <Y position measurement> Next, ON both SPY and SMY-switches and OFF SPX, SMX-switches. By this setting, analog voltage which shows the Y position will be inputted to P82/MX/AN2 pin. The Y position can be measured by converting this voltage to digital code with AD converter. The above analog voltage which is inputted to AN3 or AN2 pin can be calculated. It is a ratio between resistance value in TMP91C025FG and resistance value in touch screen shown in Figure 3.10.5. Therefore, if the pen touches a corner area on touch screen, analog-voltage will not be to 3.3 V or 0.0 V. As a notice, since each resistor has an uneven, consider about it. And it is recommended that an average code among a few times AD conversion will be adopted as a correct code. [Formula to calculate analog voltage (E1) to AN2 or AN3 pin] SPY (SPX) ON resistor: Rpy (Rpx) typ.20 Ω Touch screen resistor: AVCC = 3.3 V E1 = ((R2 + Rmy)/(Rpy + Rty + Rmy)) × AVCC [V] (Example) The case of AVCC = 3.3 V, Rpy = Rmy = 20 Ω, R1 = 400 Ω and R2 = 100 Ω E1 = ((100 + 20)/(20 + 400 + 100 + 20) × 3.3 = 0.733 V R1 Rty (Rtx) AN2 (AN3) pin A value depends on a touch screen. R2 Touch point SMY (SMX) ON resistor: Rmy (Rmx) Note 1: An X position can be calculated in the same way though above formula is for Y position. Note 2: Rty = R1 + R2. typ.20 Ω Figure 3.10.5 Calculation Analog Voltage 91C025-158 2007-02-28 TMP91C025 3.10.5 Flow Chart for TSI (1) Touch detection procedure (2) X/Y position measurement procedure Main routine: INT2 routine: TSICR0 ← 98H TSICR1 ← XXH (Voluntary) (a) Execute main routine <X position measurement> ･TSICR0 ← 85H ･AD conversion for AN3 ･Store the result (b) <Y position measurement> ･TSICR0 ← 8AH ･AD conversion for AN2 ･Store the result (c) Execute an operation By using X/Y position Yes Still touched ? TSICR0<PTST> = 1? No Return to main routine Figure 3.10.6 Flow Chart for TSI It shows the circuit for each statement (a), (b) and (c) in the next page. 91C025-159 2007-02-28 TMP91C025 (a) Main routine : Waiting for INT2 interrupt (pbfc)<PB5F>, <PB6F> = “1” : Set PB5 to int2/PX, set PB6 to PY (inte12) : Set interrupt level of INT2 (tsicr0) = 98h : Pull-down resistor on, SPY on, Interrupt set<TWIEN> ei : Enable interrupt TMP91C025 Touch screen control AVCC PXEN ON SPY SPX Decoder PYEN MXEN (PY/PB6) MYEN Y+ TSI7 X+ X− (MY/P83) PXD (typ. 200 kΩ) AD converter Y− AN3 (MX/P82) Internal data bus INT2 (PX/PB5/INT2) ON Touch screen PTST AN2 SMX SMY AVCC AVSS VREFH VREFH VREFL VREFL AVSS : AVSS : AVCC 91C025-160 2007-02-28 TMP91C025 (b) INT2 routine: X position measurement (AD conversion start) (tsicr0) = 85h : Set SMX, SPX to ON. (admod1) = 83h : Set to AN3. (admod0) = 01h : Start AD conversion. TMP91C025 Touch screen control AVCC PXEN ON SPY SPX Decoder PYEN MXEN (PY/PB6) MYEN Y+ INT2 (PX/PB5/INT2) Touch screen PTST Internal data bus TSI7 X+ X− (MY/P83) PXD (typ. 200 kΩ) AD converter Y− AN3 (MX/P82) ON SMX AN2 SMY AVCC AVSS VREFH VREFH VREFL VREFL AVSS : AVSS : AVCC 91C025-161 2007-02-28 TMP91C025 (c) INT2 routine: Y position measurement (AD conversion start) (tsicr0) = 8ah : Set SMX, SPX to ON. (admod1) = 82h : Set to AN2. (admod0) = 01h : Start AD conversion. TMP91C025 Touch screen control AVCC PXEN ON SPY SPX Decoder PYEN MXEN (PY/PB6) MYEN Y+ (PX/PB5/INT2) Touch screen PTST INT2 Internal data bus TSI7 X+ X− (MY/P83) PXD (typ. 200 kΩ) AD converter Y− AN3 (MX/P82) ON SMX SMY AN2 AVCC AVSS VREFH VREFH VREFL VREFL AVSS : AVSS : AVCC 91C025-162 2007-02-28 TMP91C025 3.11 Analog/Digital Converter The TMP91C025 incorporates a 10-bit successive approximation type analog/digital converter (AD converter) with 4-channel analog input. Figure 3.11.1 is a block diagram of the AD converter. The 4-channel analog input pins (AN0 to AN3) are shared with the input only port 4 and can thus be used as an input port. Note: When IDLE2, IDLE1 or STOP mode is selected, so as to reduce the power, with some timings the system may enter a standby mode even though the internal comparator is still enabled. Therefore be sure to check that AD converter operations are halted before a HALT instruction is executed. Internal data bus AD mode control register 1 ADMOD1 ADMOD1 <ADTRGE> <ADCH2:0> <VREFON> AD mode control register 0 ADMOD0 <EOCF><ADBF><ITM0><REPEAT><SCAN><ADS> Scan Repeat Channel Interrupt selector ADTRG Busy End Start AD converter control Analog input AN3/ ADTRG (P83) AN2 (P82) Multiplexer circuit INTAD interrupt AD conversion result Sample and hold + − register ADREG04L to ADREG37L ADREG04H to ADREG37H AN1 (P81) Comparator AN0 (P80) VREFH DA converter VREFL Figure 3.11.1 Block Diagram of AD Converter 91C025-163 2007-02-28 TMP91C025 3.11.1 Analog/Digital Converter Registers The AD converter is controlled by the two AD mode control registers: ADMOD0 and ADMOD1. The AD conversion results are stored in 8 kinds of AD conversion data upper and lower registers: ADREG04H/L, ADREG15H/L, ADREG26H/L and ADREG37H/L. Figure 3.11.2 shows the registers related to the AD converter. AD Mode Control Register 0 7 ADMOD0 Bit symbol (02B0H) Read/Write After reset Function EOCF 6 5 4 3 ADBF − − ITM0 R 0 AD conversion end flag. 2 1 0 REPEAT SCAN ADS R/W 0 AD conversion busy flag. 0 0 0 0 0 Always write Always write Interrupt Repeat mode Scan mode 0. 0. specification in specification. specification. conversion channel fixed repeat mode. 0: Every conversion 1: Every fourth conversion 0: Conversion 0: Conversion in progress stopped 1: Conversion 1: Conversion complete in progress 0: Single conversion 1: Repeat conversion mode 0 Decoder AD conversion start. 0: Don’t care 1: Start conversion Note: Always 0 when read. 0: Conversion channel fixed mode 1: Conversion channel scan mode AD conversion start 0 Don’t care 1 Start AD conversion Note: Always read as 0. AD scan mode setting 0 AD conversion channel fixed mode 1 AD conversion channel scan mode AD repeat mode setting 0 AD single conversion mode 1 AD repeat conversion mode Specify AD conversion interrupt for channel fixed repeat conversion mode. Channel fixed repeat conversion mode <SCAN> = 0, <REPEAT> = 1 0 Generates interrupt every conversion 1 Generates interrupt every fourth conversion AD conversion busy flag 0 AD conversion stopped 1 AD conversion in progress AD conversion end flag 0 Before or during AD conversion 1 AD conversion complete Figure 3.11.2 AD Converter Related Register 91C025-164 2007-02-28 TMP91C025 AD Mode Control Register 1 ADMOD1 (02B1H) 7 6 Bit symbol VREFON I2AD Read/Write R/W R/W After reset 0 0 VREF IDLE2 Function 5 4 3 2 ADTRGE ADCH2 1 0 ADCH1 ADCH0 0 0 R/W 0 0 AD Analog input channel selection. application 0: Stop external control. trigger start 1: Operate 0: Off control. 1: On 0: Disable 1: Enable Analog input channel selection. <SCAN> 0 1 Channel Channel fixed scanned <ADCH2:0> 000 AN0 AN0 001 AN1 AN0 → AN1 010 AN2 AN0 → AN1 → AN2 011 (Note) AN3 100 to 111 − AN0 → AN1 → AN2 → AN3 Use prohibition AD conversion starts control by external trigger. ( ADTRG input) 0 Disabled 1 Enabled IDLE2 control 0 Stopped 1 In operation Control of application of reference voltage to AD converter. 0 Off 1 On Before starting conversion (Before writing 1 to ADMOD0<ADS>), set the <VREFON> bit to 1. Note: As pin AN3 also functions as the ADTRG input pin, do not set <ADCH2:0> = 011 when using ADTRG with < ADTRGE> = 0. Figure 3.11.3 AD Converter Related Registers 91C025-165 2007-02-28 TMP91C025 AD Conversion Data Lower Register 0/4 7 ADREG04L (02A0H) Bit symbol 6 ADR01 5 4 3 2 1 0 ADR00 ADR0RF Read/Write R R After reset Undefined 0 Function Stores lower 2 bits of AD AD conversion result. conversion data storage flag. 1: Conversion result stored AD Conversion Data Upper Register 0/4 ADREG04H (02A1H) Bit symbol 7 6 5 4 ADR09 ADR08 ADR07 ADR06 Read/Write 3 2 1 0 ADR05 ADR04 ADR03 ADR02 1 0 R After reset Undefined Function Stores upper 8 bits AD conversion result. AD Conversion Data Lower Register 1/5 ADREG15L (02A2H) Bit symbol 7 6 ADR11 ADR10 Read/Write R After reset Undefined Function 5 4 3 2 ADR1RF R 0 Stores lower 2 bits of AD AD conversion result. conversion result flag. 1: Conversion result stored AD Conversion Data Upper Register 1/5 ADREG15H (02A3H) Bit symbol 7 6 5 4 3 2 1 0 ADR19 ADR18 ADR17 ADR16 ADR15 ADR14 ADR13 ADR12 Read/Write R After reset Undefined Function Stores upper 8 bits of AD conversion result. 9 8 7 6 5 4 5 4 3 2 1 0 Channel x conversion result ADREGxH 7 6 ADREGxL 3 2 1 0 7 6 5 4 3 2 1 0 • Bits 5 to 1 are always read as 1. • Bit0 is the AD conversion data storage flag <ADRxRF>. When the AD conversion result is stored, the flag is set to 1. When either of the registers (ADREGxH, ADREGxL) is read, the flag is cleared to 0. Figure 3.11.4 AD Converter Related Registers 91C025-166 2007-02-28 TMP91C025 AD Conversion Result Lower Register 2/6 7 ADREG26L (02A4H) Bit symbol 6 ADR21 5 4 3 2 1 ADR20 0 ADR2RF Read/Write R R After reset Undefined 0 Function Stores lower 2 bits of AD AD conversion result. conversion data storage flag. 1: Conversion result stored AD Conversion Data Upper Register 2/6 ADREG26H (02A5H) Bit symbol 7 6 5 4 ADR29 ADR28 ADR27 ADR26 Read/Write 3 2 1 0 ADR25 ADR24 ADR23 ADR22 1 0 R After reset Undefined Function Stores upper 8 bits of AD conversion result. AD Conversion Data Lower Register 3/7 ADREG37L (02A6H) Bit symbol 7 6 ADR31 ADR30 Read/Write R After reset Undefined Function 5 4 3 2 ADR3RF R 0 Stores lower 2 bits of AD AD conversion result. conversion data storage flag. 1: Conversion result stored AD Conversion Result Upper Register 3/7 ADREG37H (02A7H) Bit symbol 7 6 5 4 ADR39 ADR38 ADR37 ADR36 3 2 1 0 ADR35 ADR34 ADR33 ADR32 Read/Write R After reset Undefined Function Stores upper 8 bits of AD conversion result. 9 8 7 6 ADREGxH 7 6 5 4 5 4 3 2 1 0 Channel x conversion result 3 2 1 0 7 6 5 4 3 2 ADREGxL 1 0 • Bits 5 to1 are always read as 1. • Bit0 is the AD conversion data storage flag <ADRxRF>. When the AD conversion result is stored, the flag is set to 1. When either of the registers (ADREGxH, ADREGxL) is read, the flag is cleared to 0. Figure 3.11.5 AD Converter Related Registers 91C025-167 2007-02-28 TMP91C025 3.11.2 Description of Operation (1) Analog reference voltage A high-level analog reference voltage is applied to the VREFH pin; a low-level analog reference voltage is applied to the VREFL pin. To perform AD conversion, the reference voltage as the difference between VREFH and VREFL, is divided by 1024 using string resistance. The result of the division is then compared with the analog input voltage. To turn off the switch between VREFH and VREFL, write 0 to ADMOD1<VREFON> in AD mode control register 1. To start AD conversion in the off state, first write 1 to ADMOD1<VREFON>, wait 3 μs until the internal reference voltage stabilizes (this is not related to fc), then set ADMOD0<ADS> to 1. (2) Analog input channel selection The analog input channel selection varies depends on the operation mode of the AD converter. • In analog input channel fixed mode (ADMOD0<SCAN> = 0) Setting ADMOD1<ADCH2:0> selects one of the input pins AN0 to AN3 as the input channel. • In analog input channel scan mode (ADMOD0<SCAN> = 1) Setting ADMOD1<ADCH2:0> selects one of the 4 scan modes. Table 3.11.1 illustrates analog input channel selection in each operation mode. After reset, ADMOD0<SCAN> = 0 and ADMOD1<ADCH2:0> = 000. Thus pin AN0 is selected as the fixed input channel. Pins not used as analog input channels can be used as standard input port pins. Table 3.11.1 Analog Input Channel Selection <ADCH2:0> Channel Fixed <SCAN> = 0 000 AN0 AN0 001 AN1 AN0 → AN1 010 AN2 AN0 → AN1 → AN2 011 AN3 AN0 → AN1 → AN2 → AN3 100-111 Use prohibition 91C025-168 Channel Scan <SCAN> = 1 Use prohibition 2007-02-28 TMP91C025 (3) Starting AD conversion To start AD conversion, write 1 to ADMOD0<ADS> in AD mode control register 0, or ADMOD1<ADTRGE> in AD mode control register 1 and input falling edge on ADTRG pin. When AD conversion starts, the AD conversion busy flag ADMOD0<ADBF> will be set to 1, indicating that AD conversion is in progress. Writing 1 to ADMOD0<ADS> during AD conversion restarts conversion. At that time, to determine whether the AD conversion results have been preserved, check the value of the conversion data storage flag ADREGxL<ADRxRF>. During AD conversion, a falling edge input on the ADTRG pin will be ignored. (4) AD conversion modes and the AD conversion end interrupt The 4 AD conversion modes are: • Channel fixed single conversion mode • Channel scan single conversion mode • Channel fixed repeat conversion mode • Channel scan repeat conversion mode The ADMOD0<REPEAT> and ADMOD0<SCAN> settings in AD mode control register 0 determine the AD mode setting. Completion of AD conversion triggers an INTAD AD conversion end interrupt request. Also, ADMOD0<EOCF> will be set to 1 to indicate that AD conversion has been completed. (a) Channel fixed single conversion mode Setting ADMOD0<REPEAT> and ADMOD0<SCAN> to 00 selects channel fixed single conversion mode. In this mode, data on one specified channel is converted once only. When the conversion has been completed, the ADMOD0<EOCF> flag is set to 1, ADMOD0 <ADBF> is cleared to 0, and an INTAD interrupt request is generated. (b) Channel scan single conversion mode Setting ADMOD0<REPEAT> and ADMOD0<SCAN> to 01 selects channel scan single conversion mode. In this mode, data on the specified scan channels is converted once only. When scan conversion has been completed, ADMOD0<EOCF> is set to 1, ADMOD0<ADBF> is cleared to 0, and an INTAD interrupt request is generated. (c) Channel fixed repeat conversion mode Setting ADMOD0<REPEAT> and ADMOD0<SCAN> to 10 selects channel fixed repeat conversion mode. In this mode, data on one specified channel is converted repeatedly. When conversion has been completed, ADMOD0<EOCF> is set to 1 and ADMOD0<ADBF> is not cleared to 0 but held 1. INTAD interrupt request generation timing is determined by the setting of ADMOD0<ITM0>. Setting <ITM0> to 0 generates an interrupt request every time an AD conversion is completed. Setting <ITM0> to 1 generates an interrupt request on completion of every fourth conversion. 91C025-169 2007-02-28 TMP91C025 (d) Channel scan repeat conversion mode Setting ADMOD0<REPEAT> and ADMOD0<SCAN> to 11 selects channel scan repeat conversion mode. In this mode, data on the specified scan channels is converted repeatedly. When each scan conversion has been completed, ADMOD0<EOCF> is set to 1 and an INTAD interrupt request is generated. ADMOD0<ADBF> is not cleared to 0 but held 1. To stop conversion in a repeat conversion mode (e.g., in cases (C) and (d)), write 0 to ADMOD0<REPEAT>. After the current conversion has been completed, the repeat conversion mode terminates and ADMOD0<ADBF> is cleared to 0. Switching to a halt state (IDLE2 mode with ADMOD1<I2AD> cleared to 0, IDLE1 mode or STOP mode) immediately stops operation of the AD converter even when AD conversion is still in progress. In repeat conversion modes (e.g., in cases (C) and (d)), when the halt is released, conversion restarts from the beginning. In single conversion modes (e.g., in cases (a) and (b)), conversion does not restart when the halt is released (the converter remains stopped). Table 3.11.2 shows the relationship between the AD conversion modes and interrupt requests. Table 3.11.2 Relationship between AD Conversion Modes and Interrupt Requests Mode Interrupt Request Generation ADMOD0 <ITM0> <REPEAT> <SCAN> X 0 0 X 0 1 1 0 1 1 Channel fixed single After completion of conversion mode conversion Channel scan single After completion of scan conversion mode conversion Channel fixed repeat Every conversion 0 conversion mode Every forth conversion 1 Channel scan repeat After completion of conversion mode every scan conversion X X: Don’t care 91C025-170 2007-02-28 TMP91C025 (e) AD conversion time 84 states (4.7 μs at fFPH = 36 MHz) are required for the AD conversion for one channel. (f) Storing and reading the results of AD conversion The AD conversion data upper and lower registers (ADREG04H/L to ADREG37H/L) store the AD conversion results. (ADREG04H/L to ADREG37H/L are read-only registers.) In channel fixed repeat conversion mode, the conversion results are stored successively in registers ADREG04H/L to ADREG37H/L. In other modes, the AN0, AN1, AN2 and AN3 conversion results are stored in ADREG04H/L, ADREG15H/L, ADREG26H/L and ADREG37H/L respectively. Table 3.11.3 shows the correspondence between the analog input channels and the registers which are used to hold the results of AD conversion. Table 3.11.3 Correspondence between Analog Input Channels and AD Conversion Result Registers AD Conversion Result Register Analog Input Channel (Port A) Conversion Modes Other than at Right Channel Fixed Repeat Conversion Mode (<ITM0>=1) AN0 ADREG04H/L AN1 ADREG15H/L ADREG15H/L AN2 ADREG26H/L ADREG26H/L AN3 ADREG37H/L ADREG37H/L ADREG04H/L <ADRxRF>, bit0 of the AD conversion data lower register, is used as the AD conversion data storage flag. The storage flag indicates whether the AD conversion result register has been read or not. When a conversion result is stored in the AD conversion result register, the flag is set to 1. When either of the AD conversion result registers (ADREGxH or ADREGxL) is read, the flag is cleared to 0. Reading the AD conversion result also clears the AD conversion end flag ADMOD0<EOCF> to 0. 91C025-171 2007-02-28 TMP91C025 (Setting example) a. Convert the analog input voltage on the AN3 pin and write the result, to memory address 0800H using the AD interrupt (INTAD) processing routine. Main routine: 7 6 5 4 3 2 1 0 ADMOD1 ← X 1 0 0 − − − − ← 1 1 X X 0 0 1 1 Set pin AN3 to be the analog input channel. ADMOD0 ← X X 0 0 0 0 0 1 Start conversion in channel fixed single conversion mode. INTE0AD Enable INTAD and set it to interrupt level 4. Interrupt routine processing example: WA ← ADREG37 Read value of ADREG37L and ADREG37H into 16-bit general-purpose register WA. WA >>6 Shift contents read into WA six times to right and zero-fill upper (0800H) ← WA Write contents of WA to memory address 0800H. bits. b. This example repeatedly converts the analog input voltages on the three pins AN0, AN1 and AN2, using channel scan repeat conversion mode. ADMOD1 ← X 0 0 0 − − − − ← 1 1 X X 0 0 1 0 Set pins AN0 to AN2 to be the analog input channels. ADMOD0 ← X X 0 0 0 1 1 1 Start conversion in channel scan repeat conversion mode. INTE0AD Disable INTAD. X: Don’t care, −: No change 91C025-172 2007-02-28 TMP91C025 3.12 Watchdog Timer (Runaway detection timer) The TMP91C025 features a watchdog timer for detecting runaway. The watchdog timer (WDT) is used to return the CPU to normal state when it detects that the CPU has started to malfunction (Runaway) due to causes such as noise. When the watchdog timer detects a malfunction, it generates a non-maskable interrupt INTWD to notify the CPU. Connecting the watchdog timer output to the Reset pin internally forces a reset. (The level of external RESET pin is not changed.) 3.12.1 Configuration Figure 3.12.1 is a block diagram of he watchdog timer (WDT). WDMOD<RESCR> RESET Internal reset Reset control WDTI interrupt WDMOD <WDTP1:0> Selector 2 fSYS (fFPH/2) 15 2 17 2 19 2 21 Q Binary counter (22 stage) R S Reset Internal reset Write 4EH Write B1H WDMOD<WDTE> WDT control register WDCR Internal data bus Figure 3.12.1 Block Diagram of Watchdog Timer Note: It needs to care designing the total machine set, because Watchdog timer can’t operate completely by external noise. 91C025-173 2007-02-28 TMP91C025 3.12.2 Operation The watchdog timer generates an INTWD interrupt when the detection time set in the WDMOD<WDTP1:0> has elapsed. The watchdog timer must be cleared 0 by software before an INTWD interrupt will be generated. If the CPU malfunctions (e.g. if runaway occurs) due to causes such as noise, but does not execute the instruction used to clear the binary counter, the binary counter will overflow and an INTWD interrupt will be generated. The CPU will detect malfunction (Runaway) due to the INTWD interrupt and in this case it is possible to return to the CPU to normal operation by means of an anti-malfunction program. The watchdog timer works immediately after reset. The watchdog timer does not operate in IDLE1 or STOP mode, as the binary counter continues counting during bus release (When BUSAK goes low). When the device is in IDLE2 mode, the operation of WDT depends on the WDMOD <I2WDT> setting. Ensure that WDMOD<I2WDT> is set before the device enters IDLE2 mode. The watchdog timer consists of a 22-stage binary counter which uses the system clock (fSYS) as the input clock. The binary counter can output fSYS/215, fSYS/217, fSYS/219 and fSYS/221. WDT counter n Over flow 0 WDT interrupt Write clear code WDT clear (Software) Figure 3.12.2 Normal Mode The runaway is detected when an overflow occurs, and the watchdog timer can reset device. In this case, the reset time will be between 22 and 29 states (19.6 to 25.8 μs at fFPH = 36MHz, fOSCH = 2.25 state )is fFPH/2, where fFPH is generated by dividing the high-speed oscillator clock (fOSCH) by sixteen through the clock gear function. Overflow WDT counter n WDT interrupt Internal reset 22 to 29 states (19.6 to 25.8 μs at fOSCH = 36 MHz, fFPH = 2.25 MHz) Figure 3.12.3 Reset Mode 91C025-174 2007-02-28 TMP91C025 3.12.3 Control Registers The watchdog timer WDT is controlled by two control registers WDMOD and WDCR. (1) Watchdog timer mode register (WDMOD) a. Setting the detection time for the watchdog timer in <WDTP1:0> This 2-bit register is used for setting the watchdog timer interrupt time used when detecting runaway. After reset, this register is initialized to WDMOD<WDTP1:0> = 00. The detection times for WDT are shown in Figure 3.12.4. b. Watchdog timer enable/disable control register <WDTE> After reset, WDMOD<WDTE> is initialized to 1, enabling the watchdog timer. To disable the watchdog timer, it is necessary to set this bit to 0 and to write the disable code (B1H) to the watchdog timer control register WDCR. This makes it difficult for the watchdog timer to be disabled by runaway. However, it is possible to return the watchdog timer from the disabled state to the enabled state merely by setting <WDTE> to 1. c. Watchdog timer out reset connection <RESCR> This register is used to connect the output of the watchdog timer with the RESET terminal internally. Since WDMOD<RESCR>is initialized to 0 on reset, a reset by the watchdog timer will not be performed. (2) Watchdog timer control register (WDCR) This register is used to disable and clear the binary counter for the watchdog timer. Disable control the watchdog timer can be disabled by clearing WDMOD<WDTE> to 0 and then writing the disable code (B1H) to the WDCR register. WDCR WDMOD WDCR • ← 0 1 0 0 1 1 1 0 ← 0 − − X X − − 0 ← 1 0 1 1 0 0 0 1 Write the clear code (4EH). Clear WDMOD<WDTE> to 0. Write the disable code (B1H). Enable control Set WDMOD<WDTE> to 1. • Watchdog timer clear control To clear the binary counter and cause counting to resume, write the clear code (4EH) to the WDCR register. WDCR ← 0 1 0 0 1 1 1 0 Write the clear code (4EH). Note1: If it is used disable control, set the disable code (B1H) to WDCR after write the clear code (4EH) once. (Please refer to setting example.) Note2: If it is changed Watchdog timer setting, change setting after set to disable condition once. 91C025-175 2007-02-28 TMP91C025 7 6 Bit symbol WDTE WDTP1 Read/Write R/W After reset 1 WDMOD (0300H) Function 5 4 3 2 WDTP0 1 I2WDT 0 − RESCR R/W R/W 0 0 WDT Select detecting time. control 00: 2 /fSYS 1: Enable 01: 2 /fSYS R/W 0 0 IDLE2 0 1: Internally Always 15 0: Stop connects 17 1: Operate WDT out 19 to the 21 reset pin 10: 2 /fSYS 11: 2 /fSYS write 0. Watchdog timer out control 0 − 1 Connects WDT out to a reset IDLE2 Control 0 Stop 1 Operation at fc = 36 MHz, fs = 32.768 kHz Watchdog timer detection time SYSCR1 System Clock Selection <SYSCK> 1 (fs) 0 (fc) Watchdog Timer Detection Time SYSCR1 Gear Value <GEAR2:0> XXX WDMOD<WDTP1:0> 00 2.0 01 s 8.0 10 s 000 (fc) 1.82 ms 7.28 ms 001 (fc/2) 3.64 ms 010 (fc/4) 7.28 ms 011 (fc/8) 100 (fc/16) 32.0 11 s 128.0 s 29.13 ms 116.51 ms 14.56 ms 58.25 ms 233.02 ms 29.13 ms 116.51 ms 466.03 ms 14.56 ms 58.25 ms 233.02 ms 932.07 ms 29.13 ms 116.51 ms 466.03 ms 1864.14 ms Watchdog timer enable/disable control 0 Disabled 1 Enabled Figure 3.12.4 Watchdog Timer Mode Register 91C025-176 2007-02-28 TMP91C025 7 6 5 4 3 WDCR Bit symbol − (0301H) Read/Write W Function 1 0 − After reset Read-modify -write instructions are prohibited. 2 B1H: WDT disable code 4EH: WDT clear code Disable/clear WDT B1H Disable code 4EH Clear code Others Don’t care Figure 3.12.5 Watchdog Timer Control Register 91C025-177 2007-02-28 TMP91C025 3.13 Real Time Clock (RTC) 3.13.1 Function Description for RTC 1) Clock function (hour, minute, second) 2) Calendar function (month and day, day of the week, and leap year) 3) 24- or 12-hour (AM/PM) clock function 4) ± 30 second adjustment function (by software) 5) Alarm function (Alarm output 6) Alarm interrupt generate 3.13.2 Block Diagram 16 Hz clock Divider 32 kHz Clock: fs 1 Hz clock Alarm register Carry hold (1 s) Alarm select Comparator ALARM INTRTC ALARM Clock Address Bus Internal Data bus Adjust RD Read/Write control WR D0 to D7 Address Figure 3.13.1 Block Diagram Note 1: The Christian era year column: This product has year column toward only lower two columns. Therefore the next year in 99 works as 00 years. In system to use it, please manage upper two columns with the system side when handle year column in the christian era. Note 2: Leap year: A leap year is the year which is divisible with 4, but the year which there is exception, and is divisible with 100 is not a leap year. However, the year which is divisible with 400 is a leap year. But there is not this product for the correspondence to the above exception. Because there are only with the year which is divisible with 4 as a leap year, please cope with the system side if this function is problem. 91C025-179 2007-02-28 TMP91C025 3.13.3 Control Registers Table 3.13.1 PAGE 0 (Clock function) Registers Symbol Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Function Read/Write SECR 0320H 40 s 20 s 10 s 8s 4s 2s 1s Second column R/W MINR 0321H 40 min. 20 min. 10 min. 8 min. 4 min. 2 min. 1 min. Minute column R/W HOURR 0322H 1 hour Hour column R/W DAYR 0323H DATER 0324H MONTHR 0325H YEARR 0326H PAGER 0327H RESTR 0328H 20 /PM/AM Day 20 10 hours 8 hours 4 hours 2 hours W0 Day of the week column R/W Day 8 Day 4 Day 2 Day 1 Day column R/W Oct. Aug. Apr. Feb. Jan. Month column R/W Adjust -ment enable W1 Day 10 Year 80 Year 40 Year 20 Year 10 Interrupt W2 function 1Hz 16Hz Clock Alarm enable enable reset reset Year 8 Year 4 Year 2 Year 1 Clock Alarm PAGE enable enable setting Always write “0” Year column (Lower two columns) R/W PAGE register W, R/W Reset register W only Note: As for SECR, MINR, HOURR, DAYR, MONTHR, YEARR of PAGE0, current state is read when read it. Table 3.13.2 PAGE 1 (Alarm function) Registers Symbol SECR Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Function Read/Write 0320H MINR 0321H HOURR 0322H DAYR 0323H R/W 40 min. 20 min. 20 /PM/AM 10 min. 8 min. 4 min. 2 min. 10 hours 8 hours 4 hours 2 hours 1 min. 1 hour Minute column R/W for alarm Hour column R/W for alarm Day of the week W2 W1 W0 column for R/W alarm DATER 0324H MONTHR 0325H YEARR 0326H PAGER RESTR Note: 0327H 0328H Day 20 Day 10 Day 8 Day 4 Day 2 Day 1 24/12 Day column for R/W alarm 24-hour clock R/W mode Leap-year setting Leap-year mode Adjust Interrupt -ment enable function 1Hz 16Hz Clock Alarm enable enable reset reset Clock Alarm PAGE enable enable setting Always write “0” R/W PAGE register W, R/W Reset register W only As for MINR, HOURR, DAYR, MONTHR, YEARR of PAGE1, current state is read when read it. 91C025-180 2007-02-28 TMP91C025 3.13.4 Detailed Explanation of Control Register RTC is not initialized by reset. Therefore, all registers must be initialized at the beginning of the program. (1) Second column register (for PAGE0 only) 7 SECR Bit symbol (0320H) Read/Write 6 5 4 SE6 SE5 SE4 2 1 0 SE3 SE2 SE1 SE0 R/W After reset Function 3 Undefined "0" is read. 40 sec. 20 sec. 10 sec. 8 sec. 4 sec. 2 sec. 1 sec. column column column column column column column 0 0 0 0 0 0 0 0 sec 0 0 0 0 0 0 1 1 sec 0 0 0 0 0 1 0 2 sec 0 0 0 0 0 1 1 3 sec 0 0 0 0 1 0 0 4 sec 0 0 0 0 1 0 1 5 sec 0 0 0 0 1 1 0 6 sec 0 0 0 0 1 1 1 7 sec 0 0 0 1 0 0 0 8 sec 0 0 0 1 0 0 1 9 sec 0 0 1 0 0 0 0 10 sec 0 0 1 1 0 0 1 19 sec 0 1 0 0 0 0 0 20 sec 0 1 0 1 0 0 1 29 sec 0 1 1 0 0 0 0 30 sec : : : 0 1 1 1 0 0 1 39 sec 1 0 0 0 0 0 0 40 sec 0 0 1 49 sec 0 0 0 50 sec 0 0 1 59 sec : 1 0 0 1 1 0 1 0 : 1 0 1 1 Note: Do not set the data other than showing above. 91C025-181 2007-02-28 TMP91C025 (2) Minute column register (for PAGE0/1) 7 MINR Bit symbol (0321H) Read/Write 6 5 4 MI6 MI5 MI4 2 1 0 MI3 MI2 MI1 MI0 R/W After reset Function 3 Undefined "0" is read. 40 min, 20 min, 10 min, 8 min, 4 min, 2 min, 1 min, column column column column column column column 0 0 0 0 0 0 0 0 min. 0 0 0 0 0 0 1 1 min. 0 0 0 0 0 1 0 2 min. 0 0 0 0 0 1 1 3 min. 0 0 0 0 1 0 0 4 min. 0 0 0 0 1 0 1 5 min. 0 0 0 0 1 1 0 6 min. 0 0 0 0 1 1 1 7 min. 0 0 0 1 0 0 0 8 min. 0 0 0 1 0 0 1 9 min. 0 0 1 0 0 0 0 10 min. 0 0 1 1 0 0 1 19 min. 0 1 0 0 0 0 0 20 min. : : 0 1 0 1 0 0 1 29 min. 0 1 1 0 0 0 0 30 min. : 0 1 1 1 0 0 1 39 min. 1 0 0 0 0 0 0 40 min. 0 0 1 49 min. 0 0 0 50 min. 0 0 1 59 min. : 1 0 0 1 1 0 1 0 : 1 0 1 1 Note: Do not set the data other than showing above. 91C025-182 2007-02-28 TMP91C025 (3) Hour column register (for PAGE0/1) a. In case of 24-hour clock mode (MONTHR<MO0> = 1) of PAGE1 7 6 5 4 3 2 1 0 HO5 HO4 HO3 HO2 HO1 HO0 HOURR Bit symbol (0322H) Read/Write R/W After reset Undefined Function "0" is read. 20 hour 10 hour 8 hour 4 hour 2 hour 1 hour column column column column column column 0 0 0 0 0 0 0 o’clock 0 0 0 0 0 1 1 o’clock 0 0 0 0 1 0 2 o’clock 8 o’clock : 0 0 1 0 0 0 0 0 1 0 0 1 9 o’clock 0 1 0 0 0 0 10 o’clock : 0 1 1 0 0 1 19 o’clock 1 0 0 0 0 0 20 o’clock 0 1 1 23 o’clock 2 1 0 HO2 HO1 HO0 : 1 0 0 Note: Do not set the data other than showing above. b. In case of 12-hour clock mode (MONTHR<MO0> = 0) of PAGE1 7 HOURR Bit symbol (0322H) Read/Write 6 5 4 3 HO5 HO4 HO3 R/W After reset Function Undefined "0" is read. PM/AM 10 hour 8 hour 4 hour 2 hour 1 hour column column column column column 0 o’clock 0 0 0 0 0 0 0 0 0 0 0 1 1 o’clock 0 0 0 0 1 0 2 o’clock (AM) : 0 0 1 0 0 1 9 o’clock 0 1 0 0 0 0 10 o’clock 0 1 0 0 0 1 11 o’clock 1 0 0 0 0 0 0 o’clock 1 0 0 0 0 1 1 o’clock (PM) Note: Do not set the data other than showing above. 91C025-183 2007-02-28 TMP91C025 (4) Day of the week column register (for PAGE0/1) 7 DAYR Bit symbol (0323H) Read/Write 6 5 4 3 2 1 0 WE2 WE1 WE0 R/W After reset Undefined Function "0" is read. W2 W1 W0 0 0 0 Sunday 0 0 1 Monday 0 1 0 Tuesday 0 1 1 Wednesday 1 0 0 Thursday 1 0 1 Friday 1 1 0 Saturday Note: Do not set the data other than showing above. (5) Day column register (for PAGE0/1) 7 DATER Bit symbol (0324H) Read/Write 6 5 4 3 DA5 DA4 DA3 1 0 DA2 DA1 DA0 Day 2 Day 1 R/W After reset Function 2 Undefined "0" is read. Day 20 Day 10 Day 8 Day 4 0 0 0 0 0 0 0 0 0 0 0 0 1 1st day 0 0 0 0 1 0 2nd day 0 0 0 0 1 1 3rd day 0 0 0 1 0 0 4th day : 0 0 1 0 0 1 9th day 0 1 0 0 0 0 10th day 0 1 0 0 0 1 11th day 0 1 1 0 0 1 19th day 1 0 0 0 0 0 20th day : : 1 0 1 0 0 1 29th day 1 1 0 0 0 0 30th day 1 1 0 0 0 1 31st day Note1: Do not set the data other than showing above. th Note2: Do not set the day which is not existed. (ex: 30 Feb) 91C025-184 2007-02-28 TMP91C025 (6) Month column register (for PAGE0 only) 7 MONTHR Bit symbol (0325H) Read/Write 6 5 4 3 2 1 0 MO4 MO4 MO2 MO1 MO0 2 months 1 month R/W After reset Undefined Function "0" is read. 10 months 8 months 4 months 0 0 0 0 1 January 0 0 0 1 0 February 0 0 0 1 1 March 0 0 1 0 0 April 0 0 1 0 1 May 0 0 1 1 0 June 0 0 1 1 1 July 0 1 0 0 0 August 0 1 0 0 1 September 1 0 0 0 0 October 1 0 0 0 1 November 1 0 0 1 0 December Note: Do not set the data other than showing above. (7) Select 24-hour clock or 12-hour clock (for PAGE1 only) 7 MONTHR (0325H) 6 5 4 Bit symbol 3 2 1 0 MO0 Read/Write R/W After reset Undefined Function "0" is read. 91C025-185 0: 12-hour 1: 24-hour 2007-02-28 TMP91C025 (8) Year column register (for PAGE0 only) YEARR Bit symbol (0326H) Read/Write 7 6 5 4 YE7 YE6 YE5 YE4 2 1 0 YE3 YE2 YE1 YE0 4 Years 2 Years 1 Year R/W After reset Function 3 Undefined 80 Years 40 Years 20 Years 10 Years 8 Years 0 0 0 0 0 0 0 0 00 years 0 0 0 0 0 0 0 1 01 years 0 0 0 0 0 0 1 0 02 years 0 0 0 0 0 0 1 1 03 years 0 0 0 0 0 1 0 0 04 years 0 0 0 0 0 1 0 1 05 years 0 0 1 99 years : 1 0 0 1 1 Note: Do not set the data other than showing above. (9) Leap-year register (for PAGE1 only) 7 6 5 4 3 2 1 0 LEAP1 LEAP0 YEARR Bit symbol (0326H) Read/Write R/W After reset 不定 Function 00: Leap-year 01: One year leap year 10: Two years leap year 11: Three years leap year 91C025-186 0 0 0 1 1 0 1 1 Current year is leap year Present is next year of a leap year Present is two years after a leap year Present is three years after leap year 2007-02-28 TMP91C025 (10) PAGE register setting (for PAGE0/1) 7 6 5 4 3 ENATMR PAGER Bit symbol INTENA ADJUST (0327H) Read/Write R/W W Read-modify After reset write Function Undefined Clock ALARM 1:Adjust 1: Enable 1: Enable 0: Disable 0: Disable 0: Disable “0” is read. PAGE R/W 0:Don’t care 1: Enable 0 ENAALM 0 are prohibited 1 R/W INTRTC instruction Note: 2 Undefined Undefined “0” is read. PAGE selection Please keep the setting order below of <ENATMR>, <ENAAML> and <INTENA>. Set different times for Clock/Alarm setting and interrupt setting (Example) Clock setting/Alarm setting ld (pager), 0ch : Clock, Alarm enable ld (pager), 8ch : Interrupt enable PAGE 0 Select Page0 1 Select Page1 0 Don’t care 1 Adjust sec. counter. When set this bit is set to “1” the sec. counter becomes to “0” when the value of the sec. counter is 0 – 29.When the ADJUST value of sec. counter is 30-59, the min. counter is carried and sec. counter becomes "0". Output Adjust signal during 1 cycle of fSYS. After being adjusted once, Adjust is released automatically. (PAGE0 only) (11) Reset register setting (for PAGE0/1) RESTR Bit symbol (1328H) Read/Write Read-modify After reset write Function 7 6 5 4 DIS1Hz DIS16Hz RSTTMR RSTALM 3 2 1 0 RE3 RE2 RE1 RE0 W Undefined 1Hz 16Hz instruction 0: Enable 0: Enable are prohibited 1: Disable 1: Disable RSTALM RSTTMR 1: Clock reset 1: Alarm reset 0 Unused 1 Reset alarm register 0 Unused 1 Reset Counter Always write “0” <DIS1HZ> <DIS1HZ> PAGER<ENAALM> Source signal 1 1 1 Alarm 0 1 0 1Hz 1 0 0 16Hz Others 91C025-187 Output “0” 2007-02-28 TMP91C025 3.13.5 Operational description (1) Reading clock data 1. Using 1Hz interrupt 1Hz interrupt and the count up of internal data synchronize. Therefore, data can read correctly if reading data after 1Hz interrupt occurred. 2. Using two times reading There is a possibility of incorrect clock data reading when the internal counter carries over. To ensure correct data reading, please read twice, as follows: Start PAGER<PAGE> = “0” , Select PAGE0 Read the clock data (1st) Read the clock data (2nd) NO 1st data = 2nd data YES END Figure 3.13.2 Flowchart of clock data read 91C025-188 2007-02-28 TMP91C025 (2) Writing clock data When a carry over occurs during a write operation, the data cannot be written correctly. Please use the following method to ensure data is written correctly. 1. Using 1Hz interrupt 1Hz interrupt and the count up of internal data synchronize. Therefore, data can write correctly if writing data after 1Hz interrupt occurred. 2. Resets counter There are 15-stage counter inside the RTC, which generates a 1Hz clock from 32,768 KHz. The data is written after reset this counter. However, if clearing the counter, it is counted up only first writing at half of the setting time, first writing only. Therefore, if setting the clock counter correctly, after clearing the counter, set the 1Hz-interrupt to enable. And set the time after the first interrupt (occurs at 0.5Hz) is occurred. Start PAGER<PAGE> = “0” , Select PAGE0 RESTR<RSTTMR> = “1” reset counter RESTR<DIS1HZ> = “0” enable 1Hz interrupt First interrupts occur (After 0.5S) NO YES Sets the time END Figure 3.13.3 Flowchart of data write 91C025-189 2007-02-28 TMP91C025 3. Disabling the clock A clock carry over is prohibited when “0” is written to PAGER<ENATMR> in order to prevent malfunction caused by the Carry hold circuit. While the clock is prohibited, the Carry hold circuit holds a one sec. carry signal from a divider. When the clock becomes enabled, the carry signal is output to the clock, the time is revised and operation continues. However, the clock is delayed when clock-disabled state continues for one second or more. Note that at this time system power is down while the clock is disabled. In this case the clock is stopped and clock is delayed. During clock disabling, pay attention with system power is downed. In this case the clock is stopped and time is delayed. Start Disable the clock Read the clock data Enable the clock End Figure 3.13.4 Flowchart of Clock disable 91C025-190 2007-02-28 TMP91C025 3.13.6 Explanation of the interrupt signal and alarm signal The alarm function used by setting the PAGE1 register and outputting either of the following three signals from ALARM pin as follows by write writing “1” to PAGER<PAGE>. INTRTC outputs a 1-shot pulse when the falling edge is detected. RTC is not initializes initialized by RESET. Therefore, when the clock or alarm function is used, clear interrupt request flag in INTC (interrupt controller). (1) When the alarm register and the timer clock correspond, output “0”. (2) 1Hz Output clock of 1Hz. (3) 16Hz Output clock of 16Hz. (1) In accordance with alarm register and a clock, output “0”. When value of a clock of PAGE0 accorded with alarm register of PAGE1 with a state of PAGER<ENAALM>= “1”, output “0” to ALARM pin and occur INTRTC. Follows are ways using alarm. Initialization of alarm is done by writing in “1” at RESTR<RSTALM>, setting value of all alarm becomes don’t care. In this case, always accorded with value of a clock and request INTRTC interrupt if PAGER<ENAALM> is “1”. Setting alarm min., alarm hour, alarm day and alarm the day week are done by writing in data at each register of PAGE1. When all setting contents accorded, RTC generates INTRTC interrupt, if PAGER<INTENA><ENAALM> is “1”. However, contents (don't care state) which does not set it up is considered to always accord. The contents, which set it up once, cannot be returned to don't care state in independence. Initialization of alarm and resetting of alarm register set to “Don’t care”. The following is an example program for outputting alarm from ALARM -pin at noon (PM12:00) every day. LD (PAGER), 09H ; Alarm disable, setting PAGE1 LD (RESTR), D0H ; Alarm initialize LD (DAYR), 01H ; LD (DATAR),01H W0 1 day LD (HOURR), 12H ; Setting 12 o’clock LD (MINR), 00H ; Setting 00 min ; Set up time 31 μs (Note) LD (PAGER), 0CH ; Alarm enable ( LD (PAGER), 8CH ; Interrupt enable ) When CPU is operated by high frequency oscillation, it may take a maximum of one clock at 32 kHz (about 30μs) for the time register setting to become valid. In the above example, it is necessary to set 31μs of set up time between setting the time register and enabling the alarm register. Note: This set up time is unnecessary when you use only internal interruption. 91C025-191 2007-02-28 TMP91C025 (2) With 1Hz output clock RTC outputs clock of 1Hz to ALARM pin by setting up PAGER<ENAALM> = “0”, RESTR<DIS1HZ> = “0”, <DIS16HZ>= “1”. RTC also generates an INTRTC interrupt of the falling edge of the clock. (3) With 16Hz output clock RTC outputs clock of 16Hz to ALARM pin by setting up PAGER<ENAALM> = “0”, RESTR<DIS1HZ> = “1”, <DIS16HZ> = “0”. RTC also generates INTRTC an interrupt on the falling edge of the clock. 91C025-192 2007-02-28 TMP91C025 3.14 LCD Driver Controller (LCDC) The TMP91C025 incorporates two types liquid crystal display driving circuit for controlling LCD driver LSI. One circuit handles a RAM build-in type LCD driver that can store display data in the LCD driver in itself, and the other circuit handles a shift-register type LCD driver that must serially transfer the display data to LCD driver for each display picture. • Shift-register type LCD driver control mode (SR mode) Set the mode of operation, start address of source data save memory and LCD size to control register before setting start register. After set start register LCDC outputs bus release request to CPU and read data from source memory. After that LCDC transmits data of volume of LCD size to external LCD driver through data bus. At this time, control signals (D1BSCP etc.) connected LCD driver output specified waveform synchronizes with data transmission. After finish data transmission, LCDC cancels the bus release request and CPU will restart. • RAM built-in type LCD driver control mode (RAM mode) Data transmission to LCD driver is executed by move instruction of CPU. After setting mode of operation to control register, when move instruction of CPU is executed LCDC outputs chip select signal to LCD driver connected to the outside from control pin. (D1BSCP etc.) Therefore control of data transmission numbers corresponding to LCD size is controlled by instruction of CPU. • Special mode It is assigned <TA3LCDE> at bit6 and <TA3MLDE> at bit4, of EMCCR0 register (00E3hex). These bits are used when you want to operate LCDD and MELODY circuit without low frequency clock (XT1, XT2). After reset these two bits are set to “0” and low clock is supplied each LCDD and MELODY circuit. If you write these bits to 1, TA3OUT (Generate by timer 3) is supplied each LCDD and MELODY circuit. In this case, you should set 32 kHz timer 3 frequency. For detail, look AC specification characteristics. This section is constituted as follows. 3.14.1 Feature of LCDC of Each Mode 3.14.2 Block Diagram 3.14.3 Control Registers 3.14.4 Shift-register Type LCD Driver Control Mode (SR type) 3.14.4.1 Settlement of Frame Frequency Function 3.14.4.2 Timer Out LCDCK 3.14.4.3 Transfer Time by Data Bus Width 3.14.4.4 LCDC Operation in HALT Mode 3.14.5 RAM Built-in Type LCD Driver Control Mode (RAM Type) 91C025-193 2007-02-28 TMP91C025 3.14.1 Feature of LCDC of Each Mode Each feature and operation of pin is as follows. Table 3.14.1 Feature of LCDC of Each Mode Shift-register Type LCD Driver Control Mode Common (row): 64, 68, 80, 100, 120, The number of picture elements can be handled RAM Built-in Type LCD Driver Control Mode 128, 144, 160, 200, 240 Segment (column): 32, 64, 80, 120, 128, There is not a limitation 160, 240, 320, 360 Receiver data bus width 8 bits, 16 bits selectable Transfer data bus width 8 bits, 4 bits selectable Transfer rate 250 ns/1 byte at Byte mode (at fFPH = 16 MHz) 375 ns/1 byte at Nibble mode Data Bus: (D7 to D0) Write Strobe: ( WR ) Data bus: Connect with DI pin of column driver. Upper 7 pins do not use in byte mode and upper 4 pins do not use in nibble mode. 8 bit, 16 bit, selectable (depend on CPU command) 8-bit fixed Equal to memory cycle Data bus: Connect with DB pin of column/row driver. Write strobe: Connect with /WR pin of not used column/row driver. Address 0: Connect with D/I pin of Address Bus: (A0) column driver. When A0 = 1 data bus value means not used display data, when A0 = 0 data bus means instruction data. Shift Clock Shift clock pulse: Connect with SCP pin of External Pulse: column driver. LCD driver latches data bus pins (D1BSCP) value by falling edge of this pin. Chip enable for column driver 1: Connect with CE pin of column driver 1. Latch pulse output: Connect with LP/EIO1 pin Latch Pulse: of column/row driver. Display data is latched in (D2BLP) output buffer in LCD driver by rising edge of Chip enable for column driver 2: Connect with CE pin of column driver 2. this pin. Frame: LCD frame output: Connect with FR pin of (D3BFR) column/row driver. Cascade Pulse: (DLEBCD) Display Off: ( DOFF ) Cascade pulse output: Connect with DIO1 pin of row driver. This pin outputs 1 shot pulse by every D3BFR pin changes. Chip enable for column driver 3: Connect with/ CE pin of column driver 3. Chip enable for row driver: Connect with LE pin of row driver. Display off output: Connect with /DSPOF terminal of column/row driver. L means display off and H means display on. 91C025-194 2007-02-28 TMP91C025 3.14.2 Block Diagram Selector CPU address bus: A0 to A23 A0 to A23 MMU LCDSAH/L Lower address Register (10 bits) Increment (14 bits) Clear Internal data bus Latch, shifter D0 to D7 SCPEN & RD RD, <BUS1:0> SCP generate System clock CPU BUSAK Output D1BSCP SEG Counter (9 bits) SR,<BUS1:0> SEGEND SEG register Comparator Internal Data bus S <BUS1:0> SCPEN <START> To interrupt circuit (Rising edge) 32 kHz clock Timer out TA3OUT BUSRQ R Q Shift register Inc. (14 bits) EMCCR0 <TA3LCDE> COM register LP generate LP modify D2BLP <BUS1:0> Internal data bus FP register BCD generate DLEBCD COM counter FR generate D3BFR Figure 3.14.1 LCDC Block Diagram 91C025-195 2007-02-28 TMP91C025 3.14.3 Control Registers LCDSAL Register LCDSAL (0360H) 7 6 5 4 Bit symbol SAL15 SAL14 SAL13 SAL12 Read/Write R/W R/W R/W R/W After reset 0 0 0 0 Function 3 2 1 0 − − MODE R/W R/W R/W 0 0 0 SR mode Always Always Mode Display memory address. (Low: A15 to A12) write 0. write 0. select 0: RAM 1: SR LCDSAH Register LCDSAH (0361H) 7 6 5 4 3 2 1 0 Bit symbol SAL23 SAL22 SAL21 SAL20 SAL19 SAL18 SAL17 SAL16 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W After reset 0 0 0 0 0 0 0 0 Function SR mode Display memory address. (High: A23 to A16) LCDSIZE Register LCDSIZE (0362H) 7 6 5 4 3 2 1 0 Bit symbol COM3 COM2 COM1 COM0 SEG3 SEG2 SEG1 SEG0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W After reset 0 0 0 0 0 0 0 0 Function LCD common number. (SR mode) LCD segment number. (SR mode) 0000: 64 0101: 128 0000: 32 0101: 160 0001: 68 0110: 144 0001: 64 0110: 240 0010: 80 0111: 160 0010: 80 0111: 320 0011: 100 1000: 200 0011: 120 1000: 360 0100: 120 1001: 240 Other: Reserved 0100: 128 Other: Reserved LCDCTL Register LCDCTL (0363H) 7 6 5 4 3 2 1 0 Bit symbol LCDON − − BUS1 BUS0 MMULCD FP8 START Read/Write R/W R/W R/W R/W R/W R/W R/W R/W After reset 0 0 0 0 0 0 0 0 Function DOFF Always Always Data bus width. Type Setting bit8 Start (SR,RAM write 0. write 0. (SR mode) selection for fFP. 00: 8 bits (Byte mode) LCDD (build 01: 4 bits (Nibble mode) in RAM). 0: Off 10: Reserved 0: Sequential 0: Stop 1: On 11: Reserved 1: Random 1: Start mode) control. (SR mode) Note 1: There is a limitation about to set LCDSAH and LCDSAL start address. It prohibit to set A13 carry to A14 by all 1-frame data transmitting. e.g. In case 240 (Row) × 360 (Column): 2a30 bytes Start address of LCDC: SAL15 to SAL12 = 0000 or 0001; Note 2: Initial incrementer’s address (LSB 14 bits) for LCDC DMA is 0000 (hex). 91C025-196 2007-02-28 TMP91C025 LCDFFP Register LCDFFP (0364H) Bit symbol 7 6 5 4 FP7 FP6 FP5 FP4 Read/Write After reset 3 2 1 0 FP3 FP2 FP1 FP0 0 0 0 0 2 1 0 R/W 0 0 0 Function 0 Setting bit7 to bit0 for fFP. LCDCTR2 Register 7 LCDCTL2 (0366H) 6 5 4 3 Bit symbol − − − RAMBUS AC1 AC0 Read/Write R/W R/W R/W R/W R/W R/W 0 0 0 0 0 After reset Function 0 Always write to “111”. 0: Byte 00: Type A 1: Word 01: Type B 10: Type C 11: Reserved Note: Please write bit7:5 to “111”, even if you use <RAMBUS>, <AC1> and <AC0> as initial setting. LCDC1L/LCDC1H/LCDC2L/LCDC2H/LCDC3L/LCDC3H/LCDR1L/LCDR1H Register Bit symbol 7 6 D7 D6 5 4 3 2 1 0 D5 D4 D3 D2 D1 D0 Read/Write Depend on the specification of external LCD driver. After reset Depend on the specification of external LCD driver. Function Depend on the specification of external LCD driver. These registers do not exist on TMP91C025. These are image for instruction registers and display registers of external RAM built-in sequential access type (Note) LCD driver. Address as Table 3.14.2 is assigned to these registers, and the following chip enable pin becomes active when accesses corresponding address. And, the area of these address is external area, so RD , WR terminal becomes active by external access. Table 3.14.3 shows the address map in the case of controlling RAM built-in random access type (Note) LCD driver. The explanation part of MMU circuit also explains this. This setup is performed by LCDCTL<MMULCD>. 91C025-197 2007-02-28 TMP91C025 Table 3.14.2 Memory Mapping for Direct Addressed Built-in RAM Type Register Purpose Address Sequential Access Type LCDC1L 0FE0H RAM built-in type Instruction LCDC1H 0FE1H column driver 1 Display data LCDC2L 0FE2H RAM built-in type Instruction LCDC2H 0FE3H column driver 2 Display data LCDC3L 0FE4H RAM built-in type Instruction LCDC3H 0FE5H column driver 3 Display data LCDR1L 0FE6H RAM built-in type row Instruction LCDR1H 0FE7H driver Display data Chip Enable A0 Terminal Terminal D1BSCP 0 D2BLP 0 D3BFR 0 DLEBCD 0 1 1 1 1 Table 3.14.3 Memory Mapping for Built-in RAM Random Access Type Address Purpose Random Access Type 3C0000H to RAM built-in type driver 1 Chip Enable Terminal D1BSCP 3CFFFFH 3D0000H to RAM built-in type driver 2 D2BLP 3DFFFFH 3E0000H to RAM built-in type driver 3 D3BFR 3EFFFFH 3F0000H to RAM built-in type driver 4 DLEBCD 3FFFFFH Note: We call built-in RAM sequential access type LCD driver that use register to access to display-ram without address. (e.g., T6B65A,T6C84 etc: mar/2000) We call built-in RAM random access type LCD driver that is same method to access to SRAM. (e.g., T6C23, T6K01 etc: mar/2000) 91C025-198 2007-02-28 TMP91C025 3.14.4 Shift-register Type LCD Driver Control Mode (SR type) Set the mode of operation, start address of source data save memory and LCD size to control registers before setting start register. After set start register LCDC outputs bus release request to CPU and read data from source memory. After that LCDC transmits data of volume of LCD size to external LCD driver through data bus. At this time, control signals (D1BSCP etc.) connected LCD driver output specified waveform synchronizes with data transmission. After finish data transmission, LCDC cancels the bus release request and CPU will re-start. LCDC timing figure in the case of 240 seg × 120 com and BYTE mode is shown in Figure 3.14.2, Figure 3.14.3. The table of tLP (D2BLP pin cycle) by the number of segments and the common number and CPU stop time/stop ratio are shown in Table 3.14.4. And, fFP (Frame frequency) by the common number is shown in Table 3.14.5. Moreover, the example of a 240 seg × 120 com LCD driver connection circuit is shown in Figure 3.14.5. 91C025-199 2007-02-28 TMP91C025 3.14.4.1 Settlement of Frame Frequency Function TMP91C025 defines so-called frame period (Refresh interval for LCD panel) by the value set in fFP [8:0]. DLEBCD pin outputs pulse every frame period. DLEBFR pin usually outputs the signal inverts polarity every frame period. Basic frame period: DLEBCD signal, is made according to the resister fFP [8:0] setting mentioned before. However this fFP [8:0] setting is generally equal to common number, frame period can be corrected by increasing fFP [8:0] with ease. The equation can calculate frame period. Frame period = LCDCK/ (D x fFP) [Hz] D: Constant for each common (Table 3.14.5) fFP: Setting of fFP [8:0] resister LCDCK: Source clock of LCD (Low clock is usually selected ) Please select the value of fFP [8:0] as the frame period you want to set in the Table 3.14.5. Note: Please make the value set to fFP [8:0] into the following range. COM (Common number) ≤ FR ≤ 320 Example: In the case where frame period is set to 72.10 Hz by 240 coms. fFP = 240 (COM) + 63 = 303 = 12FH (by Table 3.14.5) Therefore, LCDCTL<FP8> = 1 and LCDFFP<FP7:0> = 2FH are setup. LCDCTL Register 7 LCDCTL (0363H) 6 5 4 3 2 1 0 Bit symbol LCDON − − BUS1 BUS0 MMULCD FP8 START Read/Write R/W R/W R/W R/W R/W R/W R/W R/W After reset 0 0 0 0 0 0 0 0 Function DOFF Always Always Data bus width. TYPE (SR, RAM write 0. write 0. (SR mode) selection 00: 8 bits (Byte mode) LCDD (Build mode) Setting bit Start 8 for fFP. control. (SR mode) 01: 4 bits (Nibble mode) in RAM). 0: Off 10: Reserve 0:Sequential 0: Stop 1: On 11: Reserve 1:Random 1: Start LCDFFP Register LCDFFP (0364H) Bit symbol 7 6 5 4 FP7 FP6 FP5 FP4 Read/Write After reset Function 3 2 1 0 FP3 FP2 FP1 FP0 0 0 0 0 R/W 0 0 0 0 Setting bit7 to bit0 for fFP. 91C025-200 2007-02-28 TMP91C025 3.14.4.2 Timer Out LCDCK LCD source clock (LCDCK) can select low frequency (XT1, XT2: 32.768 [kHz]) or timer out (TA3OUT) outputs from internal TMRA23. Example: Here indicates the method that frame period is set 70 [Hz] by selecting TA3OUT for source clock of LCD (fc = 6 [MHz], 120 COM). The next equation calculates frame period. tLP: The period of D2BLP Frame period = 1/(tLP × fFP) [Hz] Source clock for LCDC defines as XT [Hz] and then this tLP represents D: The value is 3.5 at 120 COM tLP = D/XT Therefore if you set the frame period at 70 [Hz] under 120 COM, XT = 120 × 3.5 × 70 = 29400 [Hz] XT should be above value. In order to make XT = 29400 [Hz] under fc = 6 [MHz] with φT1 of timer3, 1/XT = T3 × 2 × 8/fc [s] T3: the value of timer resister (TA3REG) in short, XT = fc/(T3 × 2 × 8) [Hz] However T3 = (TA3REG) is 12.75 after calculate, it’s impossible to set the value under a decimal point. So if (TA3REG) is set 0CH, XT = 31250 [Hz]. And because of D = 3.5, Frame period = 31250/(120 ×3.5) = 74.404 [Hz] Further if fFP is 127 (COM + 7) with correction, Frame period = 31250/(127 × 3.5) = 70.30 ... [Hz] Reference: To maintain quality for display, please refer to following value for each gray scale. (You have to use settlement of frame frequency function, frame invert adjustment function and timer out LCDCK.) Monochrome: Frame period = 70 [Hz] 91C025-201 2007-02-28 TMP91C025 fFP = 78.02 Hz (at <FP8:0> = 120) D3BFR 1 picture (120 com) display time DLEBCD 1 2 3 1 120 2 3 120 1 2 D2BLP D1BSCP D7 to D0 Data transmission (240 seg = 30 byte) of volume of 1com Figure 3.14.2 Timing Diagram for SR Mode D3BFR tLP: LP period DLEBCD tSTOP: Stop time tOPR: CPU operating time D2BLP tLPH = 0.5XT BUSRQ (Internal) tSCP = 2 states D1BSCP D7 to D0 N N+1 N+28 N+29 Note: XT = 1/32768 [s] 1 state = 1/fSYS [s] Figure 3.14.3 Timing Diagram for SR Mode (Detail) 91C025-202 2007-02-28 TMP91C025 Table 3.14.4 Performance Listing for Each Segment and Common Number 64 com 68 com 80 com 100 com 120 com 128 com 144 com 160 com 200 com 240 com Unit 6.5 6 5 4 3.5 3 2.5 2.5 2 1.5 --- 198.4 183.1 152.6 122.1 106.8 91.6 76.3 76.3 61.0 45.8 μs XT number of counts for tLP making: D tLP 32 seg 64 seg 80 seg 120 seg 128 seg 160 seg 240 seg 320 seg 360 seg tSTOP CPU stop rate 0.2 0.2 0.3 0.4 0.4 tSTOP CPU stop rate 0.4 0.5 0.6 0.7 0.8 0.6 0.6 0.7 0.9 0.8 0.9 1.1 1.4 0.9 1.0 1.2 1.5 % 1.2 1.5 1.9 % μs 1.5 1.5 1.8 2.4 % μs 1.8 1.7 2.2 2.2 2.7 3.6 % μs 1.9 2.3 2.3 2.9 3.9 % μs 2.2 1.1 1.2 1.5 1.8 2.1 2.4 2.9 2.9 3.6 4.9 % μs 3.3 1.7 1.8 2.2 2.7 3.1 3.6 4.4 4.4 5.5 7.3 % μs 4.4 2.2 2.4 2.9 3.6 4.2 tSTOP CPU stop rate 1.0 1.8 tSTOP CPU stop rate 1.2 1.2 1.6 tSTOP CPU stop rate 0.7 1.7 tSTOP CPU stop rate 0.6 μs 1.0 1.0 tSTOP CPU stop rate 0.6 1.1 tSTOP CPU stop rate 0.5 0.9 tSTOP CPU stop rate μs 0.4 4.9 5.8 5.8 7.3 9.7 % μs 5.0 2.5 2.7 3.3 4.1 4.7 5.5 6.6 6.6 8.2 10.9 % Note 1: The above value is at fFPH = 36 [MHz]. Note 2: CPU stop time tSTOP: A value is value when reading a transmitting memory by 0 waits in the BYTE write/BYTE read mode. The value becomes x1.5 in NIBBLE write mode. Details, see the “state/cycle” is each type timing table. The time required to the transmission start accompanied by bus opening demand is not included in the above-mentioned numerical value. Note 3: The following equation can calculate tLP listed below. tLP = D/32768 [s] (e.g.) If the row is 240 and D = 1.5 by the above table tLP = 1.5/32768 = 45.8 [μs] D3BFR pin DLEBCD pin 1 2 3 120 1 2 3 120 1 2 D2BLP pin D1BSCP pin D7 to D0 pin tLP BUS occupation time of CPU tSTOP * BUS occupation rate of CPU = tSTOP/tLP Figure 3.14.4 Stop Time and BUS Occupation Rate of CPU 91C025-203 2007-02-28 TMP91C025 Table 3.14.5 fFP Table for Each Common Number (1/2) D 6.5 6 5 4 3.5 3 2.5 2.5 2 1.5 COM 64 68 80 100 120 128 144 160 200 240 COM+0 78.77 80.31 81.92 81.92 78.02 85.33 91.02 81.92 81.92 91.02 COM+1 77.56 79.15 80.91 81.11 77.37 84.67 90.39 81.41 81.51 90.64 COM 76.38 78.02 79.92 80.31 76.74 84.02 89.78 80.91 81.11 90.27 COM 75.24 76.92 78.96 79.53 76.12 83.38 89.16 80.41 80.71 89.90 COM 74.14 75.85 78.02 78.77 75.50 82.75 88.56 79.92 80.31 89.53 COM 73.06 74.81 77.10 78.02 74.90 82.13 87.97 79.44 79.92 89.16 COM 72.02 73.80 76.20 77.28 74.30 81.51 87.38 78.96 79.53 88.80 COM 71.00 72.82 75.33 76.56 73.72 80.91 86.80 78.49 79.15 88.44 COM 70.02 71.86 74.47 75.85 73.14 80.31 86.23 78.02 78.77 88.09 COM 69.06 70.93 73.64 75.16 72.58 79.73 85.67 77.56 78.39 87.73 COM + 10 68.12 70.02 72.82 74.47 72.02 79.15 85.11 77.10 78.02 87.38 COM 67.22 69.13 72.02 73.80 71.47 78.58 84.56 76.65 77.65 87.03 COM 66.33 68.27 71.23 73.14 70.93 78.02 84.02 76.20 77.28 86.69 COM 65.47 67.42 70.47 72.50 70.39 77.47 83.49 75.76 76.92 86.35 COM 64.63 66.60 69.72 71.86 69.87 76.92 82.96 75.33 76.56 86.01 COM 63.81 65.80 68.99 71.23 69.35 76.38 82.44 74.90 76.20 85.67 COM 63.02 65.02 68.27 70.62 68.84 75.85 81.92 74.47 75.85 85.33 COM 62.24 64.25 67.56 70.02 68.34 75.33 81.41 74.05 75.50 85.00 COM 61.48 63.50 66.87 69.42 67.84 74.81 80.91 73.64 75.16 84.67 COM 60.74 62.77 66.20 68.84 67.35 74.30 80.41 73.22 74.81 84.34 COM + 20 60.01 62.06 65.54 68.27 66.87 73.80 79.92 72.82 74.47 84.02 COM 59.31 61.36 64.89 67.70 66.40 73.31 79.44 72.42 74.14 83.70 COM 58.62 60.68 64.25 67.15 65.93 72.82 78.96 72.02 73.80 83.38 COM 57.95 60.01 63.63 66.60 65.47 72.34 78.49 71.62 73.47 83.06 COM 57.29 59.36 63.02 66.06 65.02 71.86 78.02 71.23 73.14 82.75 COM 56.64 58.72 62.42 65.54 64.57 71.39 77.56 70.85 72.82 82.44 COM 56.01 58.10 61.83 65.02 64.13 70.93 77.10 70.47 72.50 82.13 COM 55.40 57.49 61.25 64.50 63.69 70.47 76.65 70.09 72.18 81.82 COM 54.80 56.89 60.68 64.00 63.26 70.02 76.20 69.72 71.86 81.51 COM 54.21 56.30 60.12 63.50 62.83 69.57 75.76 69.35 71.55 81.21 COM + 30 53.63 55.73 59.58 63.02 62.42 69.13 75.33 68.99 71.23 80.91 COM 53.07 55.16 59.04 62.53 62.00 68.70 74.90 68.62 70.93 80.61 COM 52.51 54.61 58.51 62.06 61.59 68.27 74.47 68.27 70.62 80.31 COM 51.97 54.07 58.00 61.59 61.19 67.84 74.05 67.91 70.32 80.02 COM 51.44 53.54 57.49 61.13 60.79 67.42 73.64 67.56 70.02 79.73 COM 50.92 53.02 56.99 60.68 60.40 67.01 73.22 67.22 69.72 79.44 COM 50.41 52.51 56.50 60.24 60.01 66.60 72.82 66.87 69.42 79.15 COM 49.91 52.01 56.01 59.80 59.63 66.20 72.42 66.53 69.13 78.86 COM 49.42 51.52 55.54 59.36 59.25 65.80 72.02 66.20 68.84 78.58 COM + 39 48.94 51.04 55.07 58.94 58.88 65.41 71.62 65.87 68.55 78.30 Note 1: fFP can be calculated in the following formulas. fFP = 32768/(D × FP) [Hz] Example: In case of 120 com, <FP8:0> = 131, fFP = 32768/(3.5 × 131) = 71.5 [Hz] Note 2: The above is at fs = 32 [kHz]. 91C025-204 2007-02-28 TMP91C025 Table 3.14.6 fFP Table for Each Common Number (2/2) D 6.5 6 5 4 3.5 3 2.5 2.5 2 1.5 COM 64 68 80 100 120 128 144 160 200 240 COM + 40 48.47 50.57 54.61 58.51 58.51 65.02 71.23 65.54 68.27 78.02 COM 48.01 50.10 54.16 58.10 58.15 64.63 70.85 65.21 67.98 77.74 COM 47.56 49.65 53.72 57.69 57.79 64.25 70.47 64.89 67.70 77.47 COM 47.11 49.20 53.28 57.29 57.44 63.88 70.09 64.57 67.42 77.19 COM 46.68 48.76 52.85 56.89 57.09 63.50 69.72 64.25 67.15 76.92 COM 46.25 48.33 52.43 56.50 56.74 63.14 69.35 63.94 66.87 76.65 COM 45.83 47.91 52.01 56.11 56.40 62.77 68.99 63.63 66.60 76.38 COM 45.42 47.49 51.60 55.73 56.06 62.42 68.62 63.32 66.33 76.12 COM 45.01 47.08 51.20 55.35 55.73 62.06 68.27 63.02 66.06 75.85 COM 44.61 46.68 50.80 54.98 55.40 61.71 67.91 62.71 65.80 75.59 COM + 50 44.22 46.28 50.41 54.61 55.07 61.36 67.56 62.42 65.54 75.33 COM 43.84 45.89 50.03 54.25 54.75 61.02 67.22 62.12 65.27 75.07 COM 43.46 45.51 49.65 53.89 54.43 60.68 66.87 61.83 65.02 74.81 COM 43.09 45.13 49.28 53.54 54.12 60.35 66.53 61.54 64.76 74.56 COM 42.72 44.77 48.91 53.19 53.81 60.01 66.20 61.25 64.50 74.30 COM 42.36 44.40 48.55 52.85 53.50 59.69 65.87 60.96 64.25 74.05 COM 42.01 44.04 48.19 52.51 53.19 59.36 65.54 60.68 64.00 73.80 COM 41.66 43.69 47.84 52.18 52.89 59.04 65.21 60.40 63.75 73.55 COM 41.32 43.34 47.49 51.85 52.60 58.72 64.89 60.12 63.50 73.31 COM 40.99 43.00 47.15 51.52 52.30 58.41 64.57 59.85 63.26 73.06 COM + 60 40.66 42.67 46.81 51.20 52.01 58.10 64.25 59.58 63.02 72.82 COM 40.33 42.34 46.48 50.88 51.73 57.79 63.94 59.31 62.77 72.58 COM 40.01 42.01 46.15 50.57 51.44 57.49 63.63 59.04 62.53 72.34 COM 39.69 41.69 45.83 50.26 51.16 57.19 63.32 58.78 62.30 72.10 COM 39.38 41.37 45.51 49.95 50.88 56.89 63.02 58.51 62.06 71.86 COM 39.08 41.06 45.20 49.65 50.61 56.59 62.71 58.25 61.83 71.62 COM 38.78 40.76 44.89 49.35 50.33 56.30 62.42 58.00 61.59 71.39 COM 38.48 40.45 44.58 49.05 50.07 56.01 62.12 57.74 61.36 71.16 COM 38.19 40.16 44.28 48.76 49.80 55.73 61.83 57.49 61.13 70.93 COM 37.90 39.86 43.98 48.47 49.54 55.45 61.54 57.24 60.91 70.70 COM + 70 37.62 39.57 43.69 48.19 49.28 55.16 61.25 56.99 60.68 70.47 COM 37.34 39.29 43.40 47.91 49.02 54.89 60.96 56.74 60.46 70.24 COM 37.07 39.01 43.12 47.63 48.76 54.61 60.68 56.50 60.24 70.02 COM 36.80 38.73 42.83 47.35 48.51 54.34 60.40 56.25 60.01 69.79 COM 36.53 38.46 42.56 47.08 48.26 54.07 60.12 56.01 59.80 69.57 COM 36.27 38.19 42.28 46.81 48.01 53.81 59.85 55.78 59.58 69.35 COM 36.01 37.93 42.01 46.55 47.77 53.54 59.58 55.54 59.36 69.13 COM 35.75 37.66 41.74 46.28 47.52 53.28 59.31 55.30 59.15 68.91 COM 35.50 37.41 41.48 46.02 47.28 53.02 59.04 55.07 58.94 68.70 COM 35.25 37.15 41.22 45.77 47.05 52.77 58.78 54.84 58.72 68.48 COM + 80 35.01 36.90 40.96 45.51 46.81 52.51 58.51 54.61 58.51 68.27 91C025-205 2007-02-28 TMP91C025 T6C13B (240-row driver selection) VDD VSS DIR TEST Di7-Di0 DUAL SCP S/C Open O240 SCP LP FR DSPOF DI7 to DI0 EIO1 EIO2 VCCLR ,V0LR,V2LR, VSSLR,V3LR ,V5LR DLEBCD D1BSCP D2BLP D3BFR DOFF D7 to D0 VSS TEST DUAL DSPOF COM240 FR LP EIO2 EIO1 O240 SEG240 240 COM × 240 SEG LCD VCCL/R, V0L/R, V1L/R, V4L/R, V5L/R Open COM001 SEG001 VSS O001 O001 VDD DIR VDD S/C TMP91C025 VSS VDD VSS T6C13B (240-column driver selection) Note: Other circuit is necessary for LCD drive power supply for LCD driver display. Figure 3.14.5 Interface Example for Shift Register Type LCD Driver (Setting example) In case of use 240 SEG × 240 COM, 8bit bus width LCD driver. In case of store 7200 bytes transfer data to LCD driver in built-in RAM (1000H to 2c1FH). LD LD LD LD LD (PDCR), 1FH (LCDSAL), 11H (LCDSAH), 00H (LCDSIZE), 96H (LCDFFP), 308 ; Setting control terminal ; Select SR mode ; Source start address = 1000H ; 240SEG × 240COM ; fFP = 70.93 Hz LD (LCDCTL), 81H ; BYTE mode fFP = 70.93 Hz, ; LCDON, Transfer start D0 D1 D2 D3 D4 D5 D6 D7 1 1 2 2 3 4 5 6 1000H 101eH 7 8 Segment 9 10 11 … 1001H 239 240 101dH 3 119 2c1fH 240 Common Relation Display Panel and Display Memory (In case of above setting) 91C025-206 2007-02-28 TMP91C025 3.14.4.3 Transfer Time by Data Bus Width Data bus width of LCD driver can be selected either of BYTE/NIBBLE by LCDCTL<BUS1:0>. And that cycle is selectable, type A, type B and type C. Each type has each timing, for detail, look for timing table. Readout bus width of source is selectable 8 bits or 16 bits, without concern to bus width of LCD driver. WAIT number of the read cycle is 0 waits in case of built-in RAM and works by setting value of CS/WAIT controller in case of external RAM 3.14.4.4 LCDC Operation in HALT Mode When LCDC is working, CPU executes HALT instruction and changes in HALT mode, LCDC continue operation if CPU in IDLE2 mode. But LCDC stops in case of IDLE1, STOP mode. Note: It need to set the same bus width setting of display RAM, CS/WAIT controller and LCDCTL2<RAMBUS> fFPH Address n+1 n n+2 n+3 n+4 RD D7 to D0 12H 12H 34H 34H 56H 56H 78H 78H 9aH D1SCP 2states/1byte Byte mode n+1 n Address n+2 RD D7 to D0 12H x2H x1H 34H x4H x3H 56H x6H x5H D1SCP 3 states/1 byte Nibble mode Figure 3.14.6 Bus Width Timing (No-wait external RAM) 91C025-207 2007-02-28 TMP91C025 Table 3.14.7 Each Type Timing Table Read Bus Width Byte Type A B C Word A B C Write Mode Setup Time Hold Time D1BSCP Pulse Width D1BSCP Cycle State/ Cycle 4.0x Byte 0.5x 1.0x 1.5x 4.0x Nibble 0.5x 1.0x 1.0x 2.0x 6.0x Byte 1.0x 0.5x 2.0x 4.0x 4.0x Nibble 1.0x 0.5x 1.0x 2.0x 6.0x Byte 1.0x 2.5x 1.5x 6.0x 6.0x Nibble 1.0x 1.5x 2.5x 5.0x 10.0x Byte 0.5x 1.0x 1.0x 2.0x 6.0x Nibble 0.5x 1.0x 1.0x 2.0x 10.0x Byte 1.0x 0.5x 1.0x 2.0x 6.0x Nibble 1.0x 0.5x 1.0x 2.0x 10.0x Byte 1.0x 1.5x 1.5x 3.0x 8.0x Nibble 1.0x 1.5x 2.5x 5.0x 20.0x Note: Number in above Table shows fFPH clock cycle, for example, in case of 27 MHz frequency Xin-Xout, 1.00 equal 37 ns. Above table don’t show to guarantee the time, it shows outline. For details, look for AC timing at after page. A23 to A0 pin N+1 N RD pin State/cycle D7 to D0 pin Data setup time Data hold time D1BSCP pulse width D1SCP cycle D1BSCP pin Figure 3.14.7 Definition of Specification 91C025-208 2007-02-28 TMP91C025 Type Read Trance RAM A 8 bits 8 bits SRAM fFPH Address (n + 1) (n) (n + 2) (n + 3) RD WR 12H D7 to D0 12H 34H 34H 56H 56H 78H D1SCP Type Read Trance RAM B 8 bits 8 bits SRAM fFPH Address (n + 1) (n) (n + 2) (n + 3) RD WR D7 to D0 12H 12H 34H 34H 56H 56H 78H D1SCP Type Read Trance RAM C 8 bits 8 bits SRAM fFPH Address Pc (n) (n + 1) (n + 2) Pc RD WR D7 to D0 12H 12H 34H 34H 56H D1SCP Figure 3.14.8 Byte Read and Byte Write Timing 91C025-209 2007-02-28 TMP91C025 Type Read Trance RAM A 8 bits 4 bits SRAM fFPH Address (n) (n + 1) Pc (n + 2) Pc RD WR 12H D7 to D0 x1H x2H x3H x4H 34H 56H D1SCP Type Read Trance RAM B 8 bits 4 bits SRAM fFPH Address (n) (n + 1) Pc (n + 2) Pc RD WR D7 to D0 12H x2H 34H x1H x4H x3H 56H D1SCP Type Read Trance RAM C 8 bits 4 bits SRAM fFPH Address (n) (n + 1) Pc Pc RD WR D7 to D0 12H x2H x1H 34H D1SCP Figure 3.14.9 Byte Read and Nibble Write Timing 91C025-210 2007-02-28 TMP91C025 Type Read Trance RAM A 8 bits 4 bits SRAM fFPH Address (n) (n + 1) Pc (n + 2) Pc RD WR D15 to D8 34H D7 to D0 12H 78H 12H 34H BCH 56H 56H 78H 9AH D1SCP Type Read Trance RAM B 16 bits 8 bits SRAM fFPH Address (n) (n + 1) Pc (n + 2) Pc RD WR D15 to D8 34H D7 to D0 12H 78H 12H 34H BCH 56H 56H 78H 9AH D1SCP Type Read Trance RAM C 16 bits 8 bits SRAM fFPH Address (n) (n + 1) Pc pc RD WR D15 to D8 34H D7 to D0 12H 78H 12H 34H 56H 56H D1SCP Figure 3.14.10 Word Read and Byte Write Timing 91C025-211 2007-02-28 TMP91C025 Type Read Trance RAM A 16 bits 4 bits SRAM fFPH Address (n) (n + 1) Pc Pc RD WR D15 to D8 34H D7 to D0 12H 78H x2H x1H x4H x3H 56H x6H x5H x8H x7H D1SCP Type Read Trance RAM B 16 bits 4 bits SRAM fFPH Address (n) (n + 1) Pc Pc RD WR D15 to D8 34H D7 to D0 12H 78H x2H x1H x4H x3H 56H x6H x5H x8H Type Read Trance RAM C 16 bits 4 bits SRAM x7H D1SCP fFPH Address (n) Pc RD WR D15 to D8 34H D7 to D0 12H x2H x1H x4H x3H D1SCP Figure 3.14.11 Word Read and Nibble Write Timing 91C025-212 2007-02-28 TMP91C025 3.14.5 RAM Built-in Type LCD Driver Control Mode (RAM Type) Data transmission to LCD driver is executed by move instruction of CPU. After setting mode of operation to control register, when move instruction of CPU is executed LCDC outputs chip select signal to LCD driver connected to the outside from control pin. (D1BSCP etc.) Therefore control of data transmission numbers corresponding to LCD size is controlled by instruction of CPU. There are 2 kinds of addresses of LCD driver in this case, and which is chosen determines by LCDCTL<MMULCD> register. It corresponds to LCD driver which has every 1 byte of instruction register and display data register in LCD driver at the time of <MMULCD> = 0. Please make the transmission place address at this time into either of FE0H to FE7H. (Table 3.14.2 references) It corresponds to address direct writing type LCD driver at the time of <MMULCD> = 1. The transmission place address at this time can also assign the memory area of 3C0000H to 3FFFFFH to four areas for every 64 Kbytes. (Table 3.14.3 references) The example of a setting is shown as follows and connection example is shown in Figure 3.14.12 at the time below. [<MMULCD> = 0] (Setting example) In case of use 80 SEG × 65 COM LCD driver. Assign external column driver to LCDC0 and row driver to LCDR0. This example used LD instruction in setting of instruction and used burst function of micro DMA by soft start in setting of display data. In case of store 650 bytes transfer data to LCD driver in built-in RAM (1000H to 1289H). ; Setting external terminal LD (PDCR), 19H ; Setting for LCDC LD (LCDSAL), 00H LD (LCDCTL), 80H ; CE for LCDC1: D1BSCP, ; LE for LCDR1: DLEBCD, ; Setting for/DOFF ; Select RAM mode ; LCDON ; Setting for mode of LCDC1/LCDR1 LD (LCDC1L), XX ; Setting instruction for LCDC1 LD (LCDR1L), XX ; Setting instruction for LCDR1 ; Setting for micro DMA and INTTC (ch0) LD A, 08H ; Source address INC mode LDC DMAM0, A ; LD WA, 650 ; count = 650 LDC DMAC0, WA ; LD XWA, 1000H ; Source address = 1000H LDC DMAS0, XWA ; LD XWA, 0FE1H ; Destination address = FE1H (LCDC0H) LDC DMAD0, XWA ; LD (INTETC01), 06H ; INTTC0 level = 6 EI 6 ; LD (DMAB), 01H ; Burst mode LD (DMAR), 01H ; Soft start 91C025-213 2007-02-28 TMP91C025 T6B66A (65-row driver) VSS Power supply circuit VLC1,VLC2, VLC3,VLC4, VLC5 LE DB5 to 0 DSPOF COM001 65 COM × 80 SEG LCD COM065 COM065 CE WR D/I DSPOF DB7 to DB0 EIO1 EIO2 SEG080 VSS COM001 SEG001 VDD SEG001 VDD WR TMP91C025 VSS VLC2,VLC3, VLC5 Open VDD D1BSCP WR A0 DOFF D7 to D0 SEG080 DLEBCD VDD VSS T6B65A (80-column driver) Note: Other circuit is necessary for LCD drive power supply for LCD driver display. Figure 3.14.12 Interface Example for RAM Built-in Type LCD Driver [Write cycle] [Read cycle] System clock: fSYS A23 to A0 R/ W D1BSCP, D2BLP, D3BFR, DLEBCD D7 to D0 Data-out Data-in Figure 3.14.13 Example of Access Timing for RAM Built-in Type LCD Driver (Wait = 0) 91C025-214 2007-02-28 TMP91C025 3.15 Melody/Alarm Generator TMP91C025 incorporates melody function and alarm function, both of which are output from the MLDALM pin. 5 kinds of fixed cycle interrupts are generated by the 15-bit free-run counter which is used for alarm generator. Features are as follows. • Melody generator The melody function generates signals of any frequency (4 Hz to 5461 Hz) based on low-speed clock (32.768 kHz) and outputs several signals from the MLDALM pin. By connecting a loud speaker outside, melody tone can sound easily. • Alarm generator The alarm function generates 8 kinds of alarm waveform having a modulation frequency (4096 Hz) determined by the low-speed clock (32.768 kHz). And this waveform is able to invert by setting a value to a register. By connecting a loud speaker outside, Alarm tone can sound easily. And also 5 kinds of fixed cycle (1 Hz, 2 Hz, 64 Hz, 512 Hz, and 8192 Hz) interrupts are generated by the free-run counter which is used for alarm generator. • Special mode It is assigned <TA3LCDE> at bit0 and <TA3MLDE> at bit1, of EMCCR0 register (00E3hex). These bits are used when you want to operate LCDD and MELODY circuit without low-frequency clock (XTIN, XTOUT). After reset these two bits set to “0” and low clock is supplied each LCDD and MELODY circuit. If you write these bits to “1”, TA3 (Generate by timer3) is supplied each LCDD and MELODY circuit. In this case, you should set 32 kHz timer3 frequency. For detail, look AC specification characteristics. This section is constituted as follows. 3.15.1 Block Diagram 3.15.2 Control Registers 3.15.3 Operational Description 3.15.3.1 Melody Generator 3.15.3.2 Alarm Generator 91C025-215 2007-02-28 TMP91C025 3.15.1 Block Diagram Internal data bus [Melody generator] Reset MELFH, MELFL resistor MELFH <MELON> MELOUT Invert EMCCR0 <TA3MLDE> F/F Comparator (CP0) Stop & clear Low-speed clock (32 kHz) Clear Selector 12-bit counter (UC0) TA3OUT INTALM0 (8192 Hz) INTALM1 (512 Hz) INTALM2 (64 Hz) INTALM3 (2 Hz) INTALM4 (1 Hz) Edge detect 15-bit counter (UC1) 4096 Hz MELALMC<FC1:0> MELOUT 8-bit counter (UC2) Selector ALM resistor MLDALM pin invert Alarm wave form generator [Alarm generator] INTALMH (Halt release) ALMINT <IALME4:0> ALMOUT MELALMC <ALMINV> MELALMC <MELALM> Internal data bus Reset Figure 3.15.1 MLD Block Diagram 91C025-216 2007-02-28 TMP91C025 3.15.2 Control Registers ALM Register ALM (0330H) Bit symbol 7 6 5 4 AL8 AL7 AL6 AL5 Read/Write After reset 3 2 1 0 AL4 AL3 AL2 AL1 0 0 0 0 2 1 0 − − MELALM 0 0 R/W 0 0 0 Function 0 Setting alarm pattern. MELALMC Register 7 MELALMC Bit symbol (0331H) Read/Write After reset Function FC1 6 5 4 3 FC0 ALMINV − − R/W 0 R/W 0 0 0 0 Free-run counter control. Alarm Always write 0. 0 Output 00: Hold waveform waveform 01: Restart invert. select. 10: Clear 1: INVERT 0: Alarm 1: Melody 11: Clear & start Note 1: MELALMEC<FC1> is read always 0. Note 2: When setting MELALMC register except <FC1:0> during the free-run counter is running, <FC1:0> is kept 01. MELFL Register MELFL (0332H) Bit symbol 7 6 5 4 3 2 1 0 ML7 ML6 ML5 ML4 ML3 ML2 ML1 ML0 0 0 0 0 0 0 0 0 Read/Write After reset R/W Function Setting melody frequency (Lower 8 bits). MELFH Register 7 MELFH (0333H) Bit symbol MELON Read/Write R/W After reset Function 6 5 4 3 2 1 0 ML11 ML10 ML9 ML8 0 0 R/W 0 0 Control 0 Setting melody frequency (Upper 4 bits). melody counter. 0: Stop & clear 1: Start ALMINT Register 7 ALMINT (0334H) Bit symbol 6 5 4 3 2 1 0 − IALM4E IALM3E IALM2E IALM1E IALM0E 0 0 0 0 0 0 Read/Write After reset Function R/W Always 1: Interrupt enable for INTALM4 to INTALM0. write 0. 91C025-217 2007-02-28 TMP91C025 3.15.3 Operational Description 3.15.3.1 Melody Generator The melody function generates signals of any frequency (4 Hz to 5461 Hz) based on low-speed clock (32.768 kHz) and outputs the signals from the MLDALM pin. By connecting a loud speaker outside, melody tone can sound easily. (Operation) At first, MELALMC<MELALM> have to be set as 1 in order to select melody waveform as output waveform from MLDALM. Then melody output frequency has to be set to 12-bit register MELFH, MELFL. Followings are setting example and calculation of melody output frequency. (Formula for calculating of melody waveform frequency) melody output waveform at fs = 32.768 [kHz] fMLD [Hz] = 32768/(2 × N + 4) setting value for melody N = (16384/fMLD) – 2 (Note: N = 1 to 4095 (001H to FFFH), 0 is not acceptable ) (Example program) In case of outputting La musical scale (440 Hz) LD (MELALMC), 11X00001B ; Select melody waveform LD (MELFL), 23H ; N = 16384/440 – 2 = 35.2 = 023H LD (MELFH), 80H ; Start to generate waveform (Refer to basic musical scale setting table) Scale Frequency [Hz] Register Value: N C 264 03CH D 297 035H E 330 030H F 352 02DH G 396 027H A 440 023H B 495 01FH C 528 01DH 91C025-218 2007-02-28 TMP91C025 3.15.3.2 Alarm Generator The Alarm function generates 8 kinds of alarm waveform having a modulation frequency 4096 Hz determined by the low-speed clock (32.768 kHz). And this waveform is reversible by setting a value to a register. By connecting a loud speaker outside, Alarm tone can sound easily. 5 kinds of fixed cycle (1 Hz, 2 Hz, 64 Hz, 512 Hz, 8192 Hz) interrupts are generate by the free-run counter which is used for alarm generator. (Operation) At first, MELALMC<MELALM> have to be set as 0 in order to select alarm waveform as output waveform from MLDALM. Then “10” be set on MELALMC<FC1:0> register, and clear internal counter. Finally alarm pattern has to be set on 8-bit register of ALM. If it is inverted output-data, set <ALMINV> as invert. Followings are example program, setting value of alarm pattern and waveform of each setting value. (Setting value of alarm pattern) Setting Value for ALM Register Alarm Waveform 00H 0 fixed 01H AL1 pattern 02H AL2 pattern 04H AL3 pattern 08H AL4 pattern 10H AL5 pattern 20H AL6pattern 40H AL7 pattern 80H AL8 pattern Other Undefined (do not set) (Example program) In case of outputting AL2 pattern (31.25 ms/8 times/1 s) LD (MELALMC), C0H ; Set output alarm waveform ; Free-run counter start LD (ALM), 02H ; Set AL2 pattern, start 91C025-219 2007-02-28 TMP91C025 (Example) Waveform of alarm pattern for each setting value: Not invert AL1 pattern (Continuous output) Modulation frequency (4096 Hz) 1 8 2 1 AL2 pattern (8 times/1 s) 1s 31.25 ms 1 AL3 pattern (once) 500 ms 1 2 1 AL4 pattern (Twice/1 s) 1s 62.5 ms 1 2 3 1 AL5 pattern (3 times/1 s) 1s 62.5 ms 1 AL6 pattern (once) 62.5 ms 1 2 AL7 pattern (Twice) 62.5 ms AL8 pattern (once) 250 ms 91C025-220 2007-02-28 TMP91C025 3.16 Hardware Standby Function TMP91C025 have hardware standby circuit that is able to save the power consumption and protect from program runaway by supplying power voltage down. Especially, it’s useful in case of battery using. It can be shifted to “PS condition” by fixing PS pin to “Low” level. Figure 3.16.1 shows timing diagram of transition of PS condition below. PS mode can be released only by external RESET. fSYS RESET PS (Note1) Keep to PS pin Shifting time (Note 2 Power save condition Reset condition (Release PS mode) More than 10 clock Figure 3.16.1 Hardware Standby Timing Diagram Note 1: PS pin is effective after RESET because SYSCR2<PSENV> to 0. If you use as INT0 pin, please write SYSCR2<PSENV> to 1. Note 2: Shifting time is 2 to 10 clock times of fSYS. Table 3.16.1 Power Save Conditions of Each HALT Mode HALT Mode Setting PS condition IDLE2 IDLE1 IDLE1 mode IDLE1 mode + High-frequency stop + High-frequency stop STOP STOP mode Note: Settings of SYSCR2<DRVE> and <SELDRV> at HALT mode are effective as well as PS condition. 91C025-221 2007-02-28 TMP91C025 4. 4.1 Electrical Characteristics Absolute Maximum Ratings Parameter Symbol Rating Unit Power supply voltage Vcc −0.5 to 4.0 V Input voltage VIN −0.5 to Vcc + 0.5 V Output current IOL 2 mA Output Current (MX, MY pin) IOL 15 mA Output current IOH −2 mA Output Current (PX, PY pin) IOH −15 mA Output current (Total) ΣIOL 80 mA Output current (Total) ΣIOH −80 mA PD 600 mW Power dissipation (Ta = 85°C) Soldering temperature (10 s) TSOLDER 260 °C Storage temperature TSTG −65 to 150 °C Operating temperature TOPR −40 to 85 °C Note: The absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, the device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no absolute maximum rating value will ever be exceeded. Solderability of lead lead-free products Test parameter Solderability Test condition (1) Note Use of Sn-637Pb solder Bath Pass: Solder bath temperature =230°C, Dipping time = 5 seconds solderability rate until forming ≥ 95% The number of times = one, Use of R-type flux (2) Use of Sn-3.0Ag-0.5Cu solder bath Solder bath temperature =245°C, Dipping time = 5 seconds The number of times = one, Use of R-type flux (use of lead lead-free) 91C025-222 2007-02-28 TMP91C025 4.2 DC Characteristics (1/2) Parameter Symbol fc = 4 to 36 MHz Power supply voltage (AVCC = DVCC) VCC (AVSS = DVSS = 0 V) D0 to D15 Condition fc = 4 to 27 MHz 2.7 Input low voltage PB3, PB5, PB6, P9) RESET , PB3, PB5, PB6, P9 AM0 to AM1 VIL1 VIL2 VIL3 Vcc ≥ 2.7 V VIL4 Unit − 3.6 V − 0.6 − 0.2 Vcc 0.25 Vcc −0.3 Vcc < 2.7 V Vcc ≥ 2.7 V − − Vcc ≥ 2.7 V − Vcc < 2.7 V Input high voltage PZ2 to PD7 (Except RESET , PB3, PB5, PB6, P9) RESET , PB3, PB5, PB6, P9 VIH VIH1 VIH2 AM0 to AM1 VIH3 X1 VIH4 Output low voltage Output high voltage VOL1 VOH2 0.3 Vcc Vcc < 2.7 V 0.15 Vcc 0.3 0.3 0.2 Vcc 0.1 Vcc 3.6 V ≥ Vcc ≥ 2.7 V D0 to D15 0.2 Vcc Vcc ≥ 2.7 V Vcc < 2.7 V X1 Max 2.4 Vcc ≥ 2.7 V Vcc < 2.7 V PZ2 to PD7 (Except RESET , Typ. 3.0 fs = 30 to 34 kHz fc = 4 to 16 MHz VIL Min 3.3 V > Vcc ≥ 2.7 V 2.0 0.7 < Vcc 0.7 Vcc Vcc ≥ 2.7 V 0.7 Vcc Vcc < 2.7 V 0.8 Vcc Vcc ≥ 2.7 V 0.75 Vcc Vcc < 2.7 V 0.85 Vcc Vcc ≥ 2.7 V Vcc − 0.3 Vcc < 2.7 V Vcc − 0.3 Vcc ≥ 2.7 V 0.8 Vcc Vcc < 2.7 V 0.9 Vcc IOL = 1.6 mA V 2.4 Vcc ≥ 2.7 V − IOL = 0.4 mA Vcc < 2.7 V IOH = −400 μA Vcc ≥ 2.7 V Vcc − 0.3 IOH = 200 μA Vcc < 2.7 V 0.8 Vcc − − − Vcc + 0.3 − − − 0.45 0.15 Vcc − V − Note: Typical values are for when Ta = 25°C and Vcc = 3.3 V uncles otherwise noted. 91C025-223 2007-02-28 TMP91C025 DC Characteristics (2/2) Parameter Internal resistor (ON) MX, MY pins Internal resistor (ON) PX, PY pins Symbol IMon IMon Condition Min Typ.(Note 1) Max VOL = 0.2V Vcc ≥ 2.7 V 30 VOL = 0.07 Vcc Vcc < 2.7 V 25 VOH = Vcc − 0.2V Vcc ≥ 2.7 V 30 VOH = 0.94 Vcc Vcc < 2.7 V Unit Ω 25 Input leak current ILI 0.0 ≤ VIN ≤ Vcc − 0.02 ±5 Output leak current RESET pull-up resistor ILO 0.2 ≤ VIN ≤ Vcc − 0.2 − 0.05 ±10 RRST 3.6 V ≥ Vcc ≥ 2.7 V 80 400 kΩ Pin capacitance CIO fc = 1 MHz − − 10 pF Schmitt width RESET , INT0, KI0 to KI7, Vcc ≥ 2.7 V 0.4 1.0 − VTH Vcc < 2.7 V 0.3 0.8 3.6 V ≥ Vcc ≥ 2.7 V 80 − 400 − 16 21 − 5.0 7 − 1.5 3.2 − 12 30 − 8 25 − 4 20 − 0.2 15 INT2, INT3 Programmable pull-up resistor RKH NORMAL (Note 2) fc = 36 MHz IDLE1 SLOW (Note 2) IDLE2 IDLE1 STOP V 3.6 V ≥ Vcc ≥ 3.0 V IDLE2 Icc μA 3.6 V ≥ Vcc ≥ 2.7 V fs = 32.768 kHz 3.6 V ≥ Vcc ≥ 2.7 V kΩ mA μA Note 1: Typical values are for when Ta = 25°C and Vcc = 3.3 V unless otherwise noted. Note 2: Icc measurement conditions (NORMAL, SLOW): All functions are operational; output pins are open and input pins are fixed. Data and address bus CL = 30 pF loaded. 91C025-224 2007-02-28 TMP91C025 4.3 AC Characteristics Vcc = 2.7 to 3.6 V case of fFPH = 27 MHz Vcc = 3.0 to 3.6 V case of fFPH = 36 MHz (1) Vcc = 2.7 V to 3.6 V No. Variable Parameter Symbol 1 tFPH fFPH period ( = x) 2 tAC A0 to 23 valid → RD / WR fall 3 tCAR 4 5 27 MHz Min Max Min 27.7 31250 Max 36 MHz Min Max Unit 37.0 27.7 ns x – 23 14 4 ns RD rise → A0 to A23 hold 0.5x – 13 5 0 ns tCAW WR rise → A0 to A23 hold x – 13 tAD A0 to A23 valid → D0 to D15 input 3.5x – 24 105 73 ns 6 tRD RD fall → D0 to D15 input 2.5x – 24 68 45 ns 7 tRR RD low width 8 tHR RD rise → D0 to A15 hold 9 tWW 10 11 24 14 ns 2.5x – 15 77 54 ns 0 0 0 ns WR low width 2.0x – 15 59 40 ns tDW D0 to D15 valid → WR rise 1.5x – 35 20 6 ns tWD WR rise → D0 to D15 hold x – 25 12 2 12 tSBA Data byte control access time for SRAM 13 tSWP Write pulse width for SRAM 2x – 15 59 40 ns 14 tSBW Data byte control to end of write for SRAM 3x – 15 96 68 ns 15 tSAS Address setup time for SRAM 1.5x – 35 20 6 ns 16 tSWR Write recovery time for SRAM 0.5x – 13 5 0 ns 17 tSDS Data setup time for SRAM 2x – 35 39 20 ns 18 tSDH Data hold time for SRAM 19 tAW A0 to A23 valid → WAIT input (1 + N) waits mode 20 tCW RD / WR fall → WAIT hold (1 + N) waits mode 21 tAPH A0 to A23 valid → Port input 22 tAPH2 A0 to A23 valid → Port hold 23 tAPO A0 to A23 valid → Port valid 3x – 24 0.5x – 13 87 3 3.5x – 60 2.5x + 0 0 69 92 3.5x – 89 3.5x 40 ns ns 8 96 209 ns ns 37 69 129 3.5x + 80 ns 59 ns ns 176 ns AC measuring conditions • Output level: High = 0.7 Vcc, Low = 0.3 Vcc, CL = 50 pF • Input level: High = 0.9 Vcc, Low = 0.1 Vcc Note: Symbol “x” in the above table means the period of clock “fFPH”, it’s half period of the system clock “fSYS” for CPU core. The period of fFPH depends on the clock gear setting or selection of high/low oscillator frequency. 91C025-225 2007-02-28 TMP91C025 (2) Vcc = 2.4 V to 3.6 V No. Variable Parameter Symbol 16 MHz Max Min 62.5 31250 62.5 ns 39 ns ns 1 tFPH fFPH period ( = x) 2 tAC A0 to 23 valid → RD / WR fall 3 tCAR RD rise → A0 to A23 hold 0.5x − 23 8 4 tCAW WR rise → A0 to A23 hold x − 13 49 5 tAD A0 to A23 valid → D0 to D15 input 6 tRD RD fall → D0 to D15 input 7 tRR RD low width 8 tHR RD rise → D0 to A15 hold x − 23 3.5x − 38 2.5x − 30 Max Unit Min ns 180 ns 126 ns 2.5x − 15 141 ns 0 0 ns 9 tWW WR low width 2.0x − 15 110 ns 10 tDW D0 to D15 valid → WR rise 1.5x − 35 58 ns 11 tWD WR rise → D0 to D15 hold x − 25 37 ns 12 tSBA Data byte control access time for SRAM 13 tSWP Write pulse width for SRAM 2x − 15 110 ns 14 tSBW Data byte control to end of write for SRAM 3x − 25 162 ns 15 tSAS Address setup time for SRAM 1.5x − 35 58 ns 16 tSWR Write recovery time for SRAM 0.5x − 22 9 ns 17 tSDS Data setup time for SRAM 2x − 35 90 ns 18 tSDH Data hold time for SRAM 19 tAW A0 to A23 valid → WAIT input (1 + N) waits mode 20 tCW RD / WR fall → WAIT hold (1 + N) waits mode 21 tAPH A0 to A23 valid → Port input 22 tAPH2 A0 to A23 valid → Port hold 23 tAPO A0 to A23 valid → Port valid 3x − 39 0.5x − 18 148 13 3.5x − 60 2.5x + 0 ns 158 156 3.5x − 89 3.5x ns ns 129 218 3.5x + 80 ns ns ns 298 ns AC measuring conditions • Output level: High = 0.7 Vcc, Low = 0.3 Vcc, CL = 50 pF • Input level: High = 0.9 Vcc, Low = 0.1 Vcc Note: Symbol “x” in the above table means the period of clock “fFPH”, it’s half period of the system clock “fSYS” for CPU core. The period of fFPH depends on the clock gear setting or selection of high/low oscillator frequency. 91C025-226 2007-02-28 TMP91C025 (3) Read cycle tFPH fFPH EA24 to EA25, A23 to A0 CSn R/ W tAW tCW WAIT tAP tAPH2 Port input (Note) tAD RD tCAR tRR tAC tRD D0 to D15 SRLB tHR D0 to D15 tSBA SRUB SRWR Note: Since the CPU accesses the internal area to read data from a port, the control signals of external pins such as RD and CS are not enabled. Therefore, the above waveform diagram should be regarded as depicting internal operation. Please also note that the timing and AC characteristics of port input/output shown above are typical representation. For details, contact your local Toshiba sales representative. 91C025-227 2007-02-28 TMP91C025 (4) Write cycle SRLB SRUB fFPH EA24 to EA25, A23 to A0 CSn R/ W WAIT tAPO Port output (Note) tCAW WR , HWR tWW tSWR tDW D0 to D15 tWD D0 to D15 tSDH tSBW SRLB SRUB tSDS tSAS tSWP SRWR Note: Since the CPU accesses the internal area to write data to a port, the control signals of external pins such as WR and CS are not enabled. Therefore, the above waveform diagram should be regarded as depicting internal operation. Please also note that the timing and AC characteristics of port input/output shown above are typical representation. For details, contact your local Toshiba sales representative. 91C025-228 2007-02-28 TMP91C025 4.4 AD Conversion Characteristics AVcc = Vcc, AVss = Vss Symbol VREFH VREFL VAIN IREF (VREFL = 0 V) ⎯ Parameter Analog reference voltage (+) Analog reference voltage (−) Condition Min Typ. Max Vcc Unit 3.6 V ≥ Vcc ≥ 2.7 V Vcc − 0.2 V Vcc 2.7 V ≥ Vcc ≥ 2.4 V Vcc Vcc Vcc 3.6 V ≥ Vcc ≥ 2.7 V Vss Vss Vss + 0.2 V 2.7 V ≥ Vcc ≥ 2.4 V Vss Vss Vss Analog input voltage range VREFL V VREFH Analog current for analog reference 3.6 V ≥ Vcc ≥ 2.7 V 1.04 1.2 voltage<VREFON> = 1 2.7 V ≥ Vcc ≥ 2.4 V 0.75 0.90 <VREFON> = 0 3.6 V ≥ Vcc ≥ 2.4 V 0.03 10.0 μA Error (Not including quantizing errors) 3.6 V ≥ Vcc ≥ 2.4 V ±1.0 ±4.0 LSB mA Note 1: 1 LSB = (VREFH − VREFL)/1024 [V] Note 2: The operation above is guaranteed for fFPH ≥ 4 MHz. Note 3: The value of ICC includes the current which flows through the AVCC pin. 91C025-229 2007-02-28 TMP91C025 4.5 Serial Channel Timing (I/O internal mode) Vcc = 2.7 to 3.6 V case of fFPH = 27 MHz Vcc = 3.0 to 3.6 V case of fFPH = 36 MHz (1) SCLK input mode Symbol Variable Parameter tSCY SCLK period tOSS Output data → SCLK rising /Falling edge* tOHS SCLK rising /Falling edge*→ Output data hold tHSR SCLK rising /Falling edge*→ Input data hold tSRD SCLK rising /Falling edge*→ Valid data input tRDS SCLK rising /Falling edge*→ Valid data input 27 MHz Min Max Min Max 36 MHz Min Max Unit 16X 0.59 0.44 μs tSCY/2 − 4X − 110 38 0 ns tSCY/2 + 2X + 0 370 277 ns 3X + 10 121 93 ns tSCY − 0 0 592 0 443 0 ns ns (2) SCLK output mode Symbol Variable Parameter 27 MHz 36 MHz Min Max Min Max Min Max 16X 8192X 0.59 303 0.44 227 Unit μs tSCY SCLK period tOSS Output data → SCLK rising /Falling edge* tSCY/2 − 40 256 181 ns tOHS SCLK rising /Falling edge*→ Output data hold tSCY/2 − 40 256 181 ns tHSR SCLK rising /Falling edge*→ Input data Hold 0 0 0 ns tSRD SCLK rising /Falling edge*→ Valid data input tRDS SCLK rising /Falling edge*→ Valid data input tSCY − 1X − 180 1X + 180 375 217 235 207 ns ns *) SCLK rising/Falling edge: The rising edge is used in SCLK Rising mode. The Falling edge is used in SCLK Falling mode. Note: Above table’s data values at 27 MHz and 36 MHz, are caliculated from tSCY = 16x base. tSCY SCLK (Rising up mode) SCLK (Falling down mode) tOSS Output data TXD tOHS 0 1 tSRD Input data RXD tRDS 2 3 tHSR 0 1 2 3 Valid Valid Valid Valid 91C025-230 2007-02-28 TMP91C025 4.6 Event Counter (TA0IN) Symbol Parameter Variable Min 4.7 Max 36 MHz 27 MHz (Vcc = 2.7 to 3.6 V) (Vcc = 3.0 to 3.6 V) Unit Min Max Min Max tVCK Clock period 8X + 100 396 321 ns tVCKL Clock low level width 4X + 40 188 151 ns tVCKH Clock high level width 4X + 40 188 151 ns Interrupt, Capture (1) NMI , INT0 to INT3 interrupts Symbol Parameter Variable Min 4.8 tINTAL tINTAH Max 27 MHz 36 MHz (Vcc = 2.7 to 3.6 V) (Vcc = 3.0 to 3.6 V) Unit Min Max Min Max NMI , INT0 to INT3 low level width 4X + 40 188 151 ns NMI , INT0 to INT3 high level width 4X + 40 188 151 ns SCOUT pin AC Characteristics Symbol Parameter Variable Min Max 27 MHz Min Max 36 MHz Min Max Unit tSCH Clock low level width 0.5T − 10 8 3 ns tSCL Clock high level width 0.5T − 10 8 3 ns Note: T = Period of SCOUT Measuring condition • Output level: High 0.7Vcc/Low 0.3 Vcc, CL = 10 pF 91C025-231 2007-02-28 TMP91C025 4.9 LCD Controller (SR mode) fSYS EA24 to EA25, A23 to A0, CSn tC tCWH tCWL D1BSCP tDSU D0 to D7 Read Bus Width TYPE Byte A B C Word A B C Note: tDHD Data Write Mode Setup Time (tDSU) Hold Time (tDHD) Clock High Width (tCWH) Cycle (tc) State/ Cycle Byte 0.5x − α 1.0x − β 1.5x − γ 4.0x 4.0x Nibble 0.5x − α 1.0x − β 1.0x − γ 2.0x 6.0x Byte 1.0x − α 0.5x − β 2.0x − γ 4.0x 4.0x Nibble 1.0x − α 0.5x − β 1.0x − γ 2.0x 6.0x Byte 1.0x − α 2.5x − β 1.5x − γ 6.0x 6.0x Nibble 1.0x − α 1.5x − β 2.5x − γ 5.0x 10.0x Byte 0.5x − α 1.0x − β 1.0x − γ 2.0x 6.0x Nibble 0.5x − α 1.0x − β 1.0x − γ 2.0x 10.0x Byte 1.0x − α 0.5x − β 1.0x − γ 2.0x 6.0x Nibble 1.0x − α 0.5x − β 1.0x − γ 2.0x 10.0x Byte 1.0x − α 1.5x − β 1.5x − γ 3.0x 8.0x Nibble 1.0x − α 1.5x − β 2.5x − γ 5.0x 20.0x Value of alpha, beta and gamma are showed next page. 91C025-232 2007-02-28 TMP91C025 No. Symbol 1 2 3 4 tDSU tDHD tCWH tC Parameter Variable Min 27 MHz 36 MHz Max Min Max Min Max D1BSCP rising → Data setup time 0.5x − 8 10 5 1.0x − 8 29 19 D1BSCP falling → Data hold time 0.5x − 8 10 5 1.0x − 8 29 19 1.5x − 8 47 33 2.5x − 8 84 61 D1BSCP 1.0x − 12 25 15 high width 1.5x − 12 43 29 2.0x − 12 62 43 2.5x − 12 80 57 D1BSCP 2.0x 74 55 clock cycle 3.0x 111 83 4.0x 148 110 5.0x 185 138 6.0x 222 166 Condition Unit 3.6 V ≥ Vcc ≥ 2.7 V ns Note: The reading characteristics of display data from the memory which does not define above table, is same as 4.3 AC electrical 91C025-233 2007-02-28 TMP91C025 4.10 Recommended Crystal Oscillation Circuit TMP91C025 is evaluated by below oscillator vender. When selecting external parts, make use of this information. Note: Total loads value of oscillator is sum of external loads (C1 and C2) and floating loads of actual assemble board. There is a possibility of miss-operating using C1 and C2 value in below table. When designing board, it should design minimum length pattern around oscillator. And we recommend that oscillator evaluation try on your actual using board. (1) Connection example X1 X2 XT1 Rf XT2 Rf Rd Rd C2 C1 C1 C2 Low-Frequency Oscillator High-Frequency Oscillator (2) TMP91C025 recommended ceramic oscillator: Murata Manufacturing Co., LTD; JAPAN MCU TMP91C025FG Parameter of Elements Running Condition Frequency Item of Oscillator Voltage of [MHz] C1 [pF] C2 [pF] Rf [Ω] Rd [Ω] Power TC [°C] [V] 9.0 CSTLS9M00G56-B0 (47) (47) Open 0 2.7~3.6 −20~80 • The values enclosed in blackest in the C1 and C2 columns apply to the condenser built-in type. • The product numbers and specifications of the resonators by Murata Manufacturing Co., Ltd. are subject to change. For up-to-date information, please refer to the following URL: http://www.murata.co.jp/search/index.html 91C025-234 2007-02-28 TMP91C025 5. Table of SFR The SFRs (Special function registers) include the I/O ports and peripheral control registers allocated to the 4-Kbyte address space from 000000H to 000FFFH. (1) I/O port (2) I/O port control (3) Interrupt control (4) Chip select/wait control (5) Clock gear (6) DFM (Clock doubler) (7) 8-bit timer (8) UART/serial channel (9) AD converter (10) Watchdog timer (11) Real-time clock (12) Melody/alarm generator (13) MMU (14) LCD control (15) Touch screen interface Table layout Symbol Name Address 7 6 1 0 Bit symbol Read/Write Initial value after reset Remarks Note: Prohibit RMW in the table means that you cannot use RMW instructions on these register. Example: When setting bit0 only of the register PxCR, the instruction SET 0, (PxCR) cannot be used. The LD (transfer) instruction must be used to write all eight bits. Read/Write R/W: Both read and write are possible. R: Only read is possible. W: Only write is possible. W*: Both read and write are possible (when this bit is read as1) Prohibit RMW: Read-modify-write instructions are prohibited. (The EX, ADD, ADC, BUS, SBC, INC, DEC, AND, OR, XOR, STCF, RES, SET, CHG, TSET, RLC, RRC, RL, RR, SLA, SRA, SLL, SRL, RLD and RRD instruction are read-modify-write instructions.) R/W*: Read-modify-write instructions are prohibited when controlling the pull-up resistor. 91C025-234 2007-02-28 TMP91C025 Table 5.1 Address Map SFRs [1], [2] Port Address Name 0000H Address Name Address 0010H P5CR Name 0020H PAFC2 Address Name 0070H 1H P1 1H 1H PAFC 1H 2H 2H P6 2H PB 2H 3H 3H 3H PC 3H 4H P1CR 4H 4H PBCR 4H 5H 5H P6FC 5H PBFC 5H 6H P2 6H 6H PCCR 6H 7H 7H 7H PCFC 7H 8H 8H P8 8H PCODE 8H 9H P2FC 9H P9 9H PD 9H AH AH AH PDFC AH BH BH P6FC2 BH TSICR0 BH CH CH CH TSICR1 CH DH P5 DH P9FC DH DH PZ EH EH PA EH EH PZCR FH FH FH FH PZFC [3] INTC [4] CS/WAIT Address Name 0080H DMA0V Address Name Address 0090H INTE0AD [5], [6] CGEAR, DFM Name Address Name 00C0H B0CS 00E0H SYSCR0 1H DMA1V 1H INTE12 1H B1CS 1H SYSCR1 2H DMA2V 2H INTE3ALM4 2H B2CS 2H SYSCR2 3H DMA3V 3H INTEALM01 3H B3CS 3H EMCCR0 4H 4H INTEALM23 4H 4H EMCCR1 5H 5H INTETA01 5H 5H EMCCR2 6H 6H INTETA23 6H 6H EMCCR3 7H 7H INTERTCKEY 7H BEXCS 7H 8H INTCLR 8H INTES0 8H MSAR0 8H DFMCR0 9H DMAR 9H INTES1 9H MAMR0 9H DFMCR1 AH DMAB AH INTELCD AH MSAR1 AH BH BH INTETC01 BH MAMR1 BH CH IIMC CH INTETC23 CH MSAR2 CH DH DH INTEP01 DH MAMR2 DH EH EH EH MSAR3 EH FH FH FH MAMR3 FH [7] TMRA [8] UART/serial channel Address Name 0100H TA01RUN Address Name [9] 10-bit ADC Address 0200H SC0BUF Name Address Name 02A0H ADREG04L 02B0H ADMOD0 1H 1H SC0CR 1H ADREG04H 1H ADMOD1 2H TA0REG 2H SC0MOD0 2H ADREG15L 2H 3H TA1REG 3H BR0CR 3H ADREG15H 3H 4H TA01MOD 4H BR0ADD 4H ADREG26L 4H 5H TA1FFCR 5H SCMOD1 5H ADREG26H 5H 6H 6H 6H ADREG37L 6H 7H 7H SIRCR 7H ADREG37H 7H 8H TA23RUN 8H SC1BUF 8H 8H 9H 9H SC1CR 9H 9H AH TA2REG AH SC1MOD0 AH AH BH TA3REG BH BR1CR BH BH CH TA23MOD CH BR1ADD CH CH DH TA3FFCR DH SC1MOD1 DH DH EH EH EH EH FH FH FH FH Note: Do not access to the unnamed addresses, e.g., addresses to which no register has been allocated. 91C025-235 2007-02-28 TMP91C025 [10] WDT [11] RTC Address Name 0300H WDMOD [12] MLD Address Name Address 0320H SECR [13] MMU Name 0330H ALM Address Name 0350H LOCAL0 1H WDCR 1H MINR 1H MELALMC 2H 2H HOURR 2H MELFL 1H LOCAL1 2H LOCAL2 3H 3H DAYR 3H MELFH 3H LOCAL3 4H 4H DATER 4H ALMINT 4H 5H 5H MONTHR 5H 5H 6H 6H YEARR 6H 6H 7H 7H PAGER 7H 7H 8H 8H RESTR 8H 8H 9H 9H 9H 9H AH AH AH AH BH BH BH BH CH CH CH CH DH DH DH DH EH EH EH EH FH FH FH FH [14] LCD controller Address Name 0360H LCDSAL 1H LCDSAH 2H LCDSIZE 3H LCDCTL 4H LCDFFP 5H 6H LCDCTL2 7H 8H 9H AH BH CH DH EH FH Note: Do not access to the unnamed addresses, e.g., addresses to which no register has been allocated. 91C025-236 2007-02-28 TMP91C025 (1) I/O ports Symbol P1 Name Port 1 Address 7 6 5 4 P17 P16 P15 P14 01H 3 2 1 0 P13 P12 P11 P10 R/W Data from external port (Output latch register is cleared to 0). P27 P2 Port 2 P26 P25 P24 06H P23 P22 P21 P20 1 1 1 P62 P61 P60 R/W 1 1 1 1 1 P65 P64 P63 P56 R/W P5 Port 5 0DH P6 Port 6 12H Data from external port (Output latch register is set to 1). 0 (Output latch register) : Pull-up resistor OFF 1(Output latch register) : Pull-up resistor ON R/W 1 P8 Port 8 1 1 0 1 1 P83 P82 P81 P80 18H R Data from external port. P97 P9 Port 9 P96 P95 P94 19H P93 P92 P91 P90 PA1 PA0 1 1 1 PC2 PC1 PC0 R Data from external port. PA3 PA Port A PA2 1EH R/W 1 PB6 PB5 PB4 PB3 1 1 R/W PB Port B 22H 1 1 Data from external port (Output latch register is set to 1). PC5 PC Port C PC4 PC3 23H R/W Data from external port (Output latch register is set to 1). PD7 PD Port D 29H PD4 PD3 PD2 1 1 1 PZ3 PZ2 R/W PD1 PD0 1 1 R/W 1 R/W Data from external port (Output latch register is PZ Port Z 7DH set to 1” 0 (Output latch register) : Pull-up resistor OFF 1(Output latch register) : Pull-up resistor ON 91C025-237 2007-02-28 TMP91C025 (2) I/O ports control (1/2) Symbol P1CR Name Port 1 control Address 04H (Prohibit RMW) 7 6 5 4 P17C P16C P15C P14C 3 2 1 0 P13C P12C P11C P10C 0/1 0/1 0/1 0/1 P23F P22F P21F P20F 1 1 1 1 P61F P60F W 0/1 0/1 0/1 0/1 0: Input 1: Output P2FC Port 2 function 09H (Prohibit RMW) P27F P26F P25F P24F W 1 1 1 1 0: Port, 1:Address bus (A23 to A16) PZCR Port Z control PZ3C 7EH PZ2C W (Prohibit 0 RMW) 0 0: Input 1: Output PZ3F PZFC Port Z function PZ2F W 7FH 0 (Prohibit 0 0: Port 1: R / W , 1: HWR SRWR 0: Port RMW) P56C P5CR Port 5 control 10H (Prohibit RMW) W 0 0: Input 1: Output P65F P6FC Port 6 function P64F 0 0: Port 1: EA25 0 0: Port 1: EA24 P65F2 P6FC2 P9FC Port 6 function2 Port 9 function 0 0: Port 1: CS3 P64F2 W 1BH (Prohibit RMW) 1DH (Prohibit RMW) P63F P62F W 15H (Prohibit RMW) 0 0 0: <P65F> 0: <P64F> 1: CS2C 1: CS2B P97F P96F P95F P94F 0 0: Port 1: CS2 0 0 0: Port 1: CS1 0: Port 1: CS0 – P62F2 – – W W W W 0 0 0 0 Always write 0. 0: <P62F> 1: CS2A P93F P92F P91F P90F 0 0 0 0 PA1F PA0F 0 0 Always write 0. W 0 0 0 0 0: KEY-IN DISABLE , 1: KEY-IN ENABLE PAFC Port A function 21H (Prohibit RMW) PA3F PA2F 0 0 W 0: CMOS output , 1: Open-drain output PA3F2 PA2F2 0 0 PA1F2 PA0F2 0 0 W PAFC2 Port A function 2 20H (Prohibit RMW) 0: Port 0: Port 0: Port 0: Port 1: SCOUT 1: TA3OUT 1: TA1OUT 1: ALARM at <PA0>=1 1: MLDALM at <PA0>=0 91C025-238 2007-02-28 TMP91C025 I/O ports control (2/2) Symbol Name PBCR Port B control Address 7 6 5 4 3 PB4C 24H 2 1 0 PC2C PC1C PC0C 0 0 0 PB3C W (Prohibit 0 RMW) 0 0: Input 1: Output PB6F PBFC PCCR Port B function Port C control PB5F 25H PB4F PB3F W (Prohibit 0 RMW) 0: Port 1: INT3 0 0: Port 1: INT2 0 0: Port 1: INT1 PC5C 26H PC4C 0 0: Port 1: INT0 PC3C W (Prohibit 0 RMW) 0 0 0: Input 1: Output PCFC PCODE Port C function PC5F PC3F PC2F PC0F 27H W W W W (Prohibit 0 0 0 RMW) 0: Port 1: SCLK1 0: Port 1: TXD1 28H (Prohibit open-drain RMW) Port C Port D function 0: Port 1: TXD0 ODEPC3 ODEPC0 W W 0 0 0: CMOS 1: Opendrain PD7F PDFC 0 0: Port 1: SCLK0 2AH W (Prohibit 0 RMW) 0: Port 1: MLDALM 0: CMOS 1: Opendrain PD4F PD3F PD2F PD1F PD0F W W W W W 0 0 0 0 0 0: Port 0: Port 0: Port 0: Port 0: Port 1: D2BLP 1: D1BSCP 1: DOFFB 1: DLEBCD 1:D3BFR 91C025-239 2007-02-28 TMP91C025 (3) Interrupt control (1/2) Symbol Name Address 7 6 IADC IADM2 5 4 3 2 IADM1 IADM0 I0C I0M2 INTAD INT0 and INTE0AD INTAD 90H enable 0 R/W 0 0 R INT1 and INT2 I2C 91H 0 Interrupt level enable I2M2 0 0 0 0 1: INT0 INTE3ALM4 INTALM4 IA4C I2M1 I2M0 R/W 0 0 I1C I1M2 92H 0 0 enable 0 0 1: INT1 0 0 and INTALM1 IA1C 0 I3C I3M2 93H 0 0 0 enable 0 0 INTEALM23 INTALM3 enable IA3C IA1M0 0 IA0C IA0M2 94H 0 0 0 0 0 IA3M0 0 IA2C INTETA01 INTTA1 enable ITA1C 95H 0 Interrupt level ITA1M2 0 0 0 INTETA23 0 INTTA3 enable ITA3C ITA3M2 INTERTCKEY 0 0 INTES0 0 INTES1 0 97H IKM2 0 ITA0C ITA0M2 0 0 ITA3M0 98H 0 0 0 Interrupt level ITA2C ITA2M2 0 0 ITX1C IKM0 0 ITX1M2 0 1: INTTX1 0 IRC IRM2 0 IRM1 0 IRM0 R/W 0 0 1: INTRTC ITX0M0 0 Interrupt level IRX0C IRX0M2 R 0 0 IRX0M1 IRX0M0 R/W 0 0 1: INTRX0 0 Interrupt level INTRX1 ITX1M1 ITX1M0 R/W 0 0 R Interrupt level R ITA2M0 Interrupt level INTTX1 99H ITA2M1 R/W 1: INTTA2 R/W 0 0 INTRX0 ITX0M1 R 0 R Interrupt level ITX0M2 ITA0M0 INTTA2 (TMRA2) INTTX0 ITX0C ITA0M1 R/W 1: INTTA0 R/W 0 0 INTRTC IKM1 R 0 Interrupt level INTKEY IKC 1: INTTX0 INTRX1 and INTTX1 enable 0 Interrupt level 1: INTKEY INTRX0 and INTTX0 enable ITA3M1 IA2M0 R/W R R/W 1: INTTA3 INTRTC0 and INTKEY enable ITA1M0 Interrupt level R IA2M1 INTTA0 (TMRA0) INTTA3 (TMRA3) 96H IA2M2 1: INTALM2 R/W 1: INTTA1 INTTA2 and ITA1M1 R 0 Interrupt level R INTTA1 (TMRA1) INTTA0 and 0 1: INTALM0 R/W 1: INTALM3 IA0M0 R/W INTALM2 IA3M1 R IA0M1 R Interrupt level IA3M2 0 Interrupt level INTALM3 INTALM2 and 0 1: INT3 R/W 1: INTALM1 I3M0 R/W INTALM0 IA1M1 R I3M1 R Interrupt level IA1M2 0 Interrupt level INTALM1 INTALM0 INTEALM01 IA4M0 R/W 1: INTALM4 I1M0 R/W INT3 IA4M1 R I1M1 R Interrupt level IA4M2 0 Interrupt level INTALM4 INT3 and I0M0 INT1 R 1: INT2 I0M1 R/W INT2 INTE12 0 INT0 R 1: INTAD 1 0 Interrupt level 91C025-240 IRX1C IRX1M2 R 0 0 1: INTRX1 IRX1M1 IRX1M0 R/W 0 0 0 Interrupt level 2007-02-28 TMP91C025 Interrupt control (2/2) Symbol Name Address 7 6 ILCD2C ILCDM2 5 4 3 2 ILCDM1 ILCDM0 – – INTLCD enable 9AH R 0 0 0 enable ITC1C ITC1M2 0 and INTTC3 9CH ITC3C ITC3M2 ITC1M0 ITC0C ITC0M2 9DH IP1C R 0 ITC3M0 0 0 DMA 0 0 0 0 ITC2C ITC2M2 ITC2M1 ITC2M0 R 0 R/W 0 0 0 0 IP0M1 IP0M0 INTP0 IP1M1 IP1M0 R/W 0 ITC0M0 R/W INTTC0 R/W IP1M2 – ITC0M1 R 0 ITC3M1 0 – INTP1 enable request vector 0 R 0 INTP0 and DMA0V – INTTC3 enable INTEP01 INTP1 – Always write 0 R/W 0 – INTTC0 ITC1M1 R INTTC2 INTETC23 0 INTTC1 9BH – – Interrupt level INTTC0 and INTETC01 INTTC1 – R/W 1: INTLCD 0 – INTLCD INTLCD 1 IP0C IP0M2 R R/W 0 0 0 0 0 0 DMA0V5 DMA0V4 DMA0V3 DMA0V2 DMA0V1 DMA0V0 0 0 DMA1V1 DMA1V0 0 0 DMA2V1 DMA2V0 0 0 DMA3V1 DMA3V0 0 0 CLRV2 CLRV1 CLRV0 0 0 0 R/W 80H 0 0 0 0 DMA0 Start vector. DMA1V DMA 1 request vector DMA1V5 DMA1V4 DMA1V3 DMA1V2 R/W 81H 0 0 0 0 DMA1 Start vector. DMA2V DMA 2 request vector DMA2V5 DMA2V4 DMA2V3 DMA2V2 R/W 82H 0 0 0 0 DMA3V5 DMA3V4 DMA3V3 DMA2 Start vector. DMA3V DMA 3 request vector DMA3V2 R/W 83H 0 0 0 0 CLRV5 CLRV4 CLRV3 DMA3 Start vector. INTCLR Interrupt clear control DMAR DMA software request register 88H (Prohibit RMW) W 0 0 0 Clears interrupt request flag by writing to DMA start vector. DMAB IIMC DMA burst request register Interrupt input mode control 89H (Prohibit RMW) DMAR3 DMAR2 DMAR1 DMAR0 R/W R/W R/W R/W 0 0 0 0 1: DMA request in software 8AH DMAB3 DMAB2 DMAB1 DMAB0 R/W R/W R/W R/W 0 0 0 0 1 : DMA request on Burst Mode 8CH − − I3EDGE I2EDGE I1EDGE I0EDGE I0LE – W W W W W W W W 0 0 0 0 0 0 (Prohibit RMW) Always write 0. 0 Always write 0. INT3 edge INT2 edge INT1 edge INT0 edge INT0 0: Rising 0: Rising 0: Rising 0: Rising 0: edge 1: Falling 1: Falling 1: Falling 1: Falling 1:level 91C025-241 0 Always write 0. 2007-02-28 TMP91C025 (4) Chip select/wait control (1/2) Symbol Name Block 0 B0CS CS/WAIT control register Address C0H (Prohibit RMW) 7 6 5 4 3 2 1 0 B0E B0OM1 B0OM0 B0BUS B0W2 B0W1 B0W0 W W W W W W W 0 0 0 0 0 0 0 0: Disable 1: Enable Data bus width. 10: 0: 16 bits 001: 1 wait 101: 3 waits 010: (1 + N) waits 110: 4 waits 1: 8 bits 011: 0 waits Reserved 11: Block 1 B1CS CS/WAIT control register C1H (Prohibit RMW) B2CS CS/WAIT control register B3CS BEXCS MSAR0 Block 3 CS/WAIT control register External CS/WAIT control register Memory start address register 0 Memory address MAMR0 mask register 0 MSAR1 Memory start address register 1 Memory address MAMR1 mask register 1 C2H (Prohibit RMW) C3H (Prohibit RMW) 000: 2 waits 111: 8 waits B1E B1OM1 B1OM0 B1BUS B1W2 B1W1 B1W0 W W W W W W W 0 0 0 0 0 0 0 0: Disable 1: Enable 100: (0 + N) waits 00: ROM/SRAM 01: Data bus width. 10: 0: 16 bits 001: 1 wait 101: 3 waits 010: (1 + N) waits 110: 4 waits 1: 8 bits 011: 0 waits Reserved 11: Block 2 100: (0 + N) waits 00: ROM/SRAM 01: 000: 2 waits 111: 8 waits B2E B2M B2OM1 B2OM0 B2BUS B2W2 B2W1 B2W0 W W W W W W W W 1 0 0 0 0 0 0 0 0: Disable 0: 16 M 1: Enable area 00: ROM/SRAM 01: 10: Reserved 1: Area set 11: Data bus width. 0: 16 bits 1: 8 bits 000: 2 waits 100: (0 + N) waits 001: 1 wait 101: 3 waits 010: (1 + N) waits 110: 4 waits 011: 0 waits 111: 8 waits B3E B3OM1 B3OM0 B3BUS B3W2 B3W1 B3W0 W W W W W W W 0 0 0 0 0 0 0 0: Disable 00: ROM/SRAM Data bus 000: 2 waits 100: (0 + N) waits 1: Enable 01: 10: 11: width. 0: 16 bits 1: 8 bits 001: 1 wait 101: 3 waits Reserved BEXBUS BEXW2 BEXW1 BEXW0 W W W W 0 0 0 0 C7H Data bus width. 0: 16 bits 1: 8 bits (Prohibit RMW) S23 S22 S21 010: (1 + N) waits 110: 4 waits 011: 0 waits 111: 8 waits S20 000: 2 waits 100: (0 + N) waits 001: 1 wait 101: 3 waits 010: (1 + N) waits 110: 4 waits 011: 0 waits 111: 8 waits S19 S18 S17 S16 1 1 1 1 V16 V15 V14 to 9 V8 1 1 1 1 R/W C8H 1 1 1 V20 V19 V18 1 Start address A23 to A16. C9H V17 R/W 1 1 1 1 CS0 area size S23 CAH S22 S21 0: Enable to address comparison S20 S19 S18 S17 S16 1 1 1 1 V17 V16 V15 to 9 V8 1 1 1 R/W 1 1 1 V21 V20 V19 1 Start address A23 to A16. CBH V18 R/W 1 1 1 CS1 area size 91C025-242 1 0: Enable to address comparison 2007-02-28 TMP91C025 Interrupt control (2/2) Symbol Name Address Memory MSAR2 start address CCH 7 6 5 4 S23 S22 S21 S20 1 1 V22 CDH V21 1 V20 1 1 mask register 3 V19 1 S23 CEH S22 1 S21 S19 S18 S17 S16 1 1 1 1 V18 V17 V16 V15 1 1 1 1 0: Enable to address comparison S20 S19 S18 S17 S16 1 1 1 1 V18 V17 V16 V15 1 1 1 1 R/W 1 1 1 register 3 MAMR3 1 CS2 area size Memory Memory address 0 R/W register 2 MSAR3 1 Start address A23 to A16. Memory start address 2 R/W register 2 address MAMR2 mask 3 1 Start address A23 to A16. V22 CFH V21 V20 V19 R/W 1 1 1 CS3 area size 91C025-243 1 0: Enable to address comparison 2007-02-28 TMP91C025 (5) Clock gear (1/2) Symbol Name Address 7 6 5 4 XEN XTEN RXEN RXTEN 3 2 1 0 RSYSCK WUEF PRCK1 PRCK0 0 0 0 R/W 1 Highfrequency System SYSCR0 clock control E0H oscillator. (fc) 0: Stopped register 0 1 1 0 HighLowLowfrequency frequency frequency oscillator. oscillator oscillator 0 Select Warm-up Select prescaler clock. clock after timer release of 0 write: 00: fFPH (fs) (fc) after (fs) after STOP 0: Stopped release release of STOP Mode. 0: fc 01: reserved Don’t care 10: fc/16 1 write: 11: Reserved start timer Mode. Mode. 1: fs 0 read: end 0: Stopped 0: Stopped 1: Oscillation 1: Oscillation of STOP warm-up 1 read: 1: Oscillation 1: Oscillation not end warm up SYSCK GEAR2 0 1 GEAR1 GEAR0 0 0 R/W SYSCR1 System clock control register 1 E1H System clock High-frequency gear value selection. (fc) selection 0: fc 000: fc 001: fc/2 1: fs 010: fc/4 011: fc/8 100: fc/16 101: (Reserved) 110: (Reserved) 111: (Reserved) SYSCR2 System clock control register 2 E2H PSENV WUPTM1 WUPTM0 HALTM1 HALTM0 SELDRV DRVE R/W R/W R/W R/W R/W R/W R/W 0 1 0 1 1 0 0 0: Power save mode enable Warm-up time 00: Reserved 8 01: 2 /input frequency 1: Disable 10: 2 14 16 11: 2 91C025-244 00: Reserved 01: STOP mode 10: IDLE1 mode 11: IDLE2 mode <Drive> mode select 0: IDLE1 1: STOP 1: Drive the pin in STOP/ IDLE1mode 2007-02-28 TMP91C025 Clock gear (1/2) Symbol Name Address 7 6 EMCCR0 control E3H register 0 4 3 2 1 0 AHOLD TA3MLDE − EXTIN R R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 1 1 PROTECT TA3LCDE EMC 5 Protection Address MLD Always hold 0: Normal source clock write 0. flag LCDC Source 0: Off clock 1: On 0: 32 kHz 1: Hold 1: TA3OUT 1: fc is DRVOSCH DRVOSCL fc oscillator fs oscillator external drivability clock. 1: Normal 0: 32 kHz 0: Weak drivebility 1: Normal 0: Weak 1: TA3OUT EMC EMCCR1 control E4H Switching the protect ON/OFF by write to following 1st-KEY, 2nd-KEY register 1 1st-KEY: EMCCR1 = 5AH, EMCCR2 = A5H in succession write EMC EMCCR2 control 2nd-KEY: EMCCR1 = A5H, EMCCR2 = 5AH in succession write E5H register 2 ENFROM E6H FFLAG DFLAG PFLAG R/W R/W R/W R/W R/W R/W 0 0 0 0 0 CS1A CS1A CS2B-2C CS2A area detect area detect area detect EMC EMCCR3 control register 3 ENDROM ENPROM 0 CS2B-2C write write operation operation flag flag enable enable enable 0: Disable 0: Disable 0: Disable 1: Enable 1: Enable 1: Enable CS2A write operation flag When reading When writing 0: Not written 1: Written 0: Clear flag (6) DFM (clock doubler) Symbol Name DFM DFMCR0 control register 0 DFM DFMCR1 control register 1 Address E8H 7 6 5 4 ACT1 ACT0 DLUPFG DLUPTM R/W R/W R R/W 0 0 0 0 DFM LUP fFPH Lockup 00 STOP STOP fOSCH falg 3 2 1 0 Lockup time 12 01 RUN RUN fOSCH 0: End LUP 0: 2 /fOSCH 10 10 RUN STOP fDFM 1: Not end 1: 2 /fOSCH 11 RUN STOP fOSCH E9H D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 1 0 0 1 1 DFM correction Input frequency 4 to 9 MHz (at 3.0 to 3.6 V): Write 0BH Input frequency 4 to 6.75 MHz (at 2.7 to 3.6 V): Write 0BH 91C025-245 2007-02-28 TMP91C025 (7) 8-bit timer (7−1) TMRA01 Symbol Name Address 8-bit timer TA01RUN RUN 100H register 7 6 5 4 3 TA0RDE I2TA01 R/W R/W 0 Double Buffer 0: Disable 1: Enable 102H − W register 0 RMW) Undefined 8-bit 103H − TA1REG timer register 1 (Prohibit W RMW) Undefined TA01M1 TA01M0 PWM01 PWM00 timer source CLK and 104H MODE TA1FFCR 8-bit timer flip-flop control 0 TA01PRUN TA1RUN R/W TA0RUN R/W R/W TA1CLK1 TA1CLK0 TA0CLK1 0 TA0CLK0 R/W 8-bit TA01MOD 1 0 0 0 IDLE2 8-bit timer run/stop control 0: Stop 0: Stop and clear 1: Operate 1: Run (Count up) (Prohibit 8-bit TA0REG timer 2 0 00: 8-bit timer 01: 16-bit timer 10: 8-bit PPG 11: 8-bit PWM 0 0 0 00: Reserved 6 01: 2 PWM cycle 7 10: 2 8 11: 2 0 00: TA0TRG 01: φT1 10: φT16 11: φT256 0 TA1FFC1 TA1FFC0 0 00: TA0IN pin 01: φT1 10: φT4 11: φT16 TA1FFIE R/W 105H RMW) TA1FFIS R/W 1 1 00: Invert TA1FF 01: Set TA1FF 10: Clear TA1FF 11: Don’t care (Prohibit 0 0 0 1: TA1FF 0: TMRA0 1: TMRA1 invert inversion enable (7−2) TMRA23 Symbol Name 8-bit timer TA23RUN RUN register Address 108H TA2REG 8-bit timer register 0 10AH (Prohibit RMW) TA3REG 8-bit timer register 1 10BH (Prohibit RMW) 7 8-bit timer TA3FFCR flip-flop control 5 4 3 TA2RDE I2TA23 R/W R/W 0 Double buffer 0: Disable 1: Enable 2 1 0 TA23PRUN TA3RUN R/W TA2RUN R/W R/W 0 0 0 8-bit timer run/stop control IDLE2 0: Stop and clear 0: Stop 1: Operate 1: Run (Count up) 0 − W Undefined − W Undefined TA23M1 8-bit timer TA23MOD source CLK and MODE 6 TA23M0 PWM21 PWM20 TA3CLK1 TA3CLK0 TA2CLK1 TA2CLK0 R/W 10CH 0 0 00: 8-bit timer 01: 16-bit timer 10: 8-bit PPG 11: 8-bit PWM 0 0 00: Reserved 6 01: 2 PWM cycle 7 10: 2 8 11: 2 0 00: TA2TRG 01: φT1 10: φT16 11: φT256 0 TA3FFC1 TA3FFC0 0 00: Reserved 01: φT1 10: φT4 11: φT16 TA3FFIE R/W 10DH 1 1 00: Invert TA3FF 01: Set TA3FF 10: Clear TA3FF 11: Don’t care (Prohibit RMW) 91C025-246 0 TA3FFIS R/W 0 1: TA3FF invert enable 0 0: TMRA2 1: TMRA3 inversion 2007-02-28 TMP91C025 (8) UART/serial channel (1/2) (8-1) UART/SIO channel 0 Symbol Name Serial SC0BUF channel 0 buffer Address 7 6 5 200H RB7/TB7 RB6/TB6 RB5/TB5 (Prohibit 3 2 1 0 RB4/TB4 RB3/TB3 RB2/TB2 RB1/TB1 RB0/TB0 SCLKS IOC R (Receiving)/W (Transmission) RMW) Undefined RB8 EVEN R Serial SC0CR channel 0 4 201H control PE R/W Undefined 0 Receiving Parity data bit8. 0: Odd 1: Even TB8 PERR FERR R (Cleared to 0 by reading.) 0 Parity enable. CTSE OERR RXE 0 0 R/W 0 1: Error 0 0 0:SCLK0↑ 1: Input Framing 1:SCLK0↓ SCLK0 pin Over Run Parity WU SM1 SM0 SC1 SC0 0 0 0 0 R/W Serial SC0MOD0 channel 0 202H 0 Transfer data bit8. mode0 0 0 1: CTS enable 0 1: Receive 1: Wakeup 00: I/O Interface enable enable 01: UART 7 bits 00: TA0TRG 01: Baud rate generator 10: UART 8 bits 10: Internal clock fSYS 11: UART 9 bits 11: External clock SCLK0 − BR0ADDE BR0CK1 BR0CK0 BR0S3 BR0S2 BR0S1 BR0S0 0 0 0 0 R/W BR0CR BR0ADD Baud rate control Serial channel0 K setting register Serial SC0MOD1 channel 0 mode1 0 203H Always write 0. 0 0 0 1: (16-K)/16 00: φT0 divided 01: φT2 enable 10: φT8 11: φT32 Setting the divided frequency “N” (0 to F) BR0K3 BR0K2 BR0K1 BR0K0 R/W 204H 205H 0 I2S0 FDPX0 R/W R/W 0 0 0 0 Sets frequency divisor “K” (Divided by N+(16-K)/16) 0 IDLE2 Duplex 0: Stop 0: Half 1: Operate 1: Full (8-2) IrDA Symbol Name IrDA SIRCR control register Address 207H 7 6 5 4 3 2 PLSEL RXSEL TXEN RXEN SIRWD3 SIRWD2 R/W R/W R/W R/W 0 0 0 0 1 0 SIRWD1 SIRWD0 R/W 0 0 0 0 Set the effective SIRRxD pulse width 0: Disable 0: Disable Pulse width more than 2x × (set value + 1) + pulse width. data. 0: 3/16 0: H pulse 1: Enable 1: Enable 100ns 1: 1/16 1: L pulse Possible: 1 to 14 Not possible: 0, 15 Transmission Receiving Transmission Receiving 91C025-247 2007-02-28 TMP91C025 Clock gear (2/2) (8-3) UART/SIO channel 0 Symbol Name Serial SC1BUF channel 1 buffer Address 7 6 5 208H RB7/TB7 RB6/TB6 RB5/TB5 (Prohibit EVEN R 209H control 2 1 0 RB4/TB4 RB3/TB3 RB2/TB2 RB1/TB1 RB0/TB0 SCLKS IOC Undefined RB8 SC1CR channel 1 3 R (Receiving)/W (Transmission) RMW) Serial 4 Undefined PE R/W 0 Receiving Parity data bit8. 0: Odd OERR PERR FERR R (Cleared to 0 by reading.) 0 0 0 1:Parity R/W 0 0 0 0: SCLK1↑ 1: Input 1: Error Framing 1: SCLK1↓ SCLK1 pin enable Over run Parity SM1 SM0 0 0 1: Even TB8 CTSE RXE WU 0 0 0 0 SC1 SC0 0 0 R/W Serial SC1MOD0 channel 1 Trans20AH mode mission 1: CTS 1: Receive 1: Wakeup 00: I/O interface enable enable enable data bit8. 00: TA0TRG 01: UART 7 bits 01: Baud rate 10: UART 8 bits 11: UART 9 bits generater 10: Internal clock fSYS 11: External clock SCLK1 − BR1ADDE BR1CK1 BR1CK0 BR1S3 BR1S2 BR1S1 BR1S0 0 0 0 0 R/W BR1CR Baud rate control 0 20BH Always write 0. 0 0 0 1: (16 − K)/16 00: φT0 divided enable Setting the divided frequency “N” (0 to F) 01: φT2 10: φT8 11: φT32 BR1ADD Serial channel 1 K setting register Serial SC1MOD1 channel 1 mode1 BR1K3 BR1K2 BR1K1 BR1K0 R/W 20CH 0 0 0 Sets frequency divisor “K” 0 (Divided by N+(16-K)/16) 20DH I2S1 FDPX1 R/W R/W 0 0 IDLE2 Duplex 0: Stop 0: Half 1: Operate 1: Full 91C025-248 2007-02-28 TMP91C025 (9) AD converter Symbol Name Address 7 6 EOCF 5 ADBF R AD ADMOD0 MODE 0 2B0H register 0 AD ADMOD1 MODE 2B1H 0 4 3 2 1 0 − − ITM0 REPEAT SCAN ADS R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 AD Always Always write Interrupt in Repeat Scan mode conversion conversion write 0. 0. Repeat mode specification conversion end flag end flag Mode. specification 1: Scan start 1: End 1: busy 1: Repeat 1: Start VREFON I2AD ADTRGE R/W R/W R/W 0 0 0 VREF IDLE2 AD control Input channel control 0: Abort 1: Enable ADCH2 ADCH1 ADCH0 R/W 0 0 0 000: AN0 AN0 for 001: AN1 AN0 → AN1 external 010: AN2 AN0 → AN1 → AN2 start 011: AN3 AN0 → AN1 → AN2 → 1: VREF on 1: Operate register 1 AD AD AN3 100-111: Reserved ADR01 AD result ADREG04L register 0/4 2A0H low AD result ADREG04H register 0/4 ADR00 ADR0RF R R Undefined 0 ADR09 ADR08 ADR07 AD result register 1/5 ADR11 2A2H ADR10 R Undefined 0 ADR18 ADR17 ADR15 ADR14 ADR13 ADR12 R Undefined ADR21 2A4H low ADR20 ADR2RF R R Undefined ADR29 0 ADR28 ADR27 ADR26 2A5H ADR25 ADR24 ADR23 ADR22 R high AD result ADREG37H register 3/7 high ADR16 2A3H AD result AD result ADREG37L register 3/7 low ADR02 ADR1RF high AD result ADREG26H register 2/6 ADR03 R ADR19 AD result ADREG26L register 2/6 ADR04 Undefined low ADREG15H register 1/5 ADR05 R high ADREG15L ADR06 2A1H Undefined ADR31 2A6H ADR30 ADR3RF R R Undefined ADR39 0 ADR38 ADR37 2A7H ADR36 ADR35 ADR34 ADR33 ADR32 R Undefined 91C025-249 2007-02-28 TMP91C025 (10) Watchdog timer Symbol Name Address WDT WDMOD MODE 7 6 5 WDTE WDTP1 R/W R/W 1 0 1: WDT 300H register enable 4 3 2 1 WDTP0 I2WDT RESCR − R/W R/W R/W R/W 0 0 0 0 15 00: 2 /fsys 17 01: 2 /fsys IDLE2 0: Abort 1: Operate 19 10: 2 /fsys 21 11: 2 /fsys 0 1: RESET Always connect write 0. internally WDT out to reset pin − 301H WDT WDCR control W − (Prohibit RMW) B1H: WDT disable 91C025-250 4EH: WDT clear 2007-02-28 TMP91C025 (11) RTC (Real-time clock) Symbol SECR Name Second register Address 7 Minute register Hour register 4 SE6 SE5 SE4 320H 3 2 1 0 SE3 SE2 SE1 SE0 Undefined 40 s 20 s 10 s 8s 4s 2s 1s MI6 MI5 MI4 MI3 MI2 MI1 MI0 4 min 2 min 1min HO2 HO1 HO0 4 hour 2 hour 1 hour W2 W1 W0 R/W 321H Undefined 0 is read. HOURR 5 R/W 0 is read. MINR 6 40 min 20 min 10 min 8 min HO5 HO4 HO3 R/W 322H Undefined 0 is read. 20 hour 10 hour 8 hour (PM/AM) DAYR Day register R/W 323H Undefined 0 is read DA5 DATER Date register DA4 DA3 W2 W1 W0 DA2 DA1 DA0 R/W 324H Undefined 0 is read. 20 day 10 day 8 day 4 day 2 day 1 day MO4 MO3 MO2 MO1 MO0 325H R/W Undefined MONTHR Month Page0 0 is read. 10 month 4 month 2 month 0 is read. YE7 YE6 YE5 YE4 326H YE2 YE1 YE0 4 year 2 year 1 year Undefined Page0 80 year 40 year 20 year Page1 10 year 327H (Prohibit RMW) 8 year 0 is read. INTRTC Leap year setting. ADJUST ENATMR ENAALM PAGE R/W W R/W R/W 0 Undefined Undefined Undefined INTRTC 0: Disable 1: Enable DIS1HZ Reset RESTR register YE3 R/W Year register Page PAGER register 1 month 0: Indicator for 12 hours 1: Indicator for 24 hours register Page1 YEARR 8 month 0 is read. DIS16HZ 0: Clock Alarm Don’t care 0: Disable 0: Disable 1: Adjust 1: Enable 1: Enable 0 is read. PAGE setting − − − RSTTMR RSTALM − W 328H Undefined (Prohibit RMW) 1Hz 16Hz 1: Clock 0: Enable 0: Enable reset 1: Disable 1: Disable 1: Alarm reset 91C025-251 Always write 0. 2007-02-28 TMP91C025 (12) Melody/alarm generator Symbol Name Address AlarmALM pattern 330H register 7 6 5 4 AL8 AL7 AL6 AL5 3 2 1 0 AL4 AL3 AL2 AL1 0 0 0 0 R/W 0 0 0 0 Alarm-pattern set. FC1 FC0 R/W Melody/ MELALMC 331H alarm control register 0 0 ALMINV – – – – MELALM R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Free-run counter Alarm Always write 0. Output Control. frequency frequency 00: Hold 01: Restart invert. 1: Invert 0: Alarm 1: Melody 10: Clear 11: Clear and start ML7 Melody MELFL frequency 332H L- register ML6 ML5 ML4 ML3 ML2 ML1 ML0 0 0 0 0 ML9 ML8 0 0 R/W 0 0 0 0 Melody frequency set. (Low 8 bits) MELON ML11 ML10 R/W R/W 0 Melody MELFH frequency H- register 0 Melody 333H 0 Melody frequency set. (High 4 bits) counter control. 0: Stop and clear 1: Start ALMINT Alarm interrupt enable register – IALM4E IALM3E 0 0 R/W 334H 0 Always write 0. 91C025-252 IALM2E IALM1E IALM0E 0 0 R/W 0 INTALM4 to INTALM0 alarm interrupt enable. 2007-02-28 TMP91C025 (13) MMU Symbol Name Address 7 6 5 4 3 L0E 2 1 0 L0EA22 L0EA21 L0EA20 R/W LOCAL0 LOCAL0 control 350H register R/W 0 BANK for LOCAL0 0: Disable 1: Enable 0 0 “000” setting is prohibited because it pretend COMMON0 area L1E L1EA23 L1EA22 R/W LOCAL1 LOCAL1 control 351H register 0 BANK for LOCAL1 0: Disable 1: Enable 0 0 352H register LOCAL3 LOCAL3 control register 353H 0 LOCAL1 area BANK set. “001” setting is prohibited because it pretend COMMON0 area L2EA23 L2EA22 R/W LOCAL2 L1EA21 R/W L2E LOCAL2 control 0 LOCAL0 area BANK set. L2EA21 R/W 0 BANK for LOCAL2 0: Disable 1: Enable 0 0 0 LOCAL2 area BANK set. “111” setting is prohibited because it pretend COMMON0 area L3E – R/W R/W 0 BANK for LOCAL3 0: Disable 1: Enable Always write 0. 0 L3EA25 L3EA24 L3EA23 L3EA22 R/W 0 0 0000~0011: CS2B 0100~0111: CS2C 0 0 1000~1111: Set prohibition 91C025-253 2007-02-28 TMP91C025 (14) LCD controllers Symbol Name Address address register 6 SAL15 SAL14 5 4 SAL13 SAL12 3 R/W LCD start LCDSAL 7 0 360H 0 0 0 SR mode: Start address A15 to A12. low 2 1 0 − − MODE R/W R/W R/W 0 0 Always write 0. Always write 0. 0 Mode select 0: RAM 1: SR SAL23 LCD start address LCDSAH register 361H SAL22 SAL21 SAL20 SAL19 SAL18 SAL17 SAL16 0 0 0 R/W 0 0 0 high 0 0 SR mode: Start Address A23 to A16. COM3 COM2 COM1 COM0 SEG3 SEG2 SEG1 SEG0 0 0 0 0 FP8 START 0 0 R/W 0 LCDSIZE LCD size register 362H 0 0 0 SR mode :LCD common SR mode LCD Segment 0000: 64, 0101: 128 0001: 68, 0110: 144 0000: 32, 0101: 160 0001: 64, 0110: 240 0010: 80, 0111: 320 0010: 80, 0111: 160 0011: 100, 1000: 200 0100: 120, 1001: 240 LCDON − Other: Reserved − 0011: 120, 1000: 360 0100: 128, Other: Reserved BUS1 BUS0 MMULCD 0 0 R/W LCDCTL LCD control register 363H 0 0 0 DOFF pin Always write 0. Always write 0. 0: Off 1: On 0 SR mode: Type Data-bus width select. selection 00: 8 bits Byte LCDD 01: 4 bits Nibble 10: Reserved 11: Reserved Set bit8 for SR mode: fFP Start address. (build in RAM) 0: 1: START Sequential 1: Random LCDFFP LCDCTL2 LCD frame frequency register LCD control register 2 364H FP7 FP6 FP5 FP4 0 0 0 0 FP3 FP2 FP1 FP0 0 0 0 0 R/W Set bit7 to bit0 for fFP 366H − − − RAMBUS AC1 AC0 R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Always write to “111”. 91C025-254 0: Byte 1: Word 00: Type A 01: Type B 10: Type C 11: Reserved 2007-02-28 TMP91C025 (15) Touch screen interface Symbol Name Address Touchscreen TSICR0 control 2BH 5 4 3 2 1 0 TSI7 7 6 PTST TWIEN PYEN PXEN MYEN MXEN R/W R R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 SPY 0: OFF SPX 0: OFF SMY 0: OFF SMX 0: OFF 1: ON 1: ON 1: ON 1: ON 0: Disable Detection 1: Enable condition register 0: No touch control 1: touch TSICR1 Debouncecircuit control register INT2 interrupt 2CH 0: Disable 1: Enable DBC7 DB1024 DB256 DB64 DB8 DB4 DB2 DB1 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 1024 256 64 8 4 2 1 0: Disable 1: Enable De-bounce time is set by “(N × 64 – 16)/fSYS” – formula “N” is sum of number which is set to 1 in bit6 to bit0 91C025-255 2007-02-28 TMP91C025 6. Points of Note and Restrictions (1) Notation a. The notation for built-in I/O registers is as follows register symbol <Bit symbol> e.g.) b. TA01RUN<TA0RUN> denotes bit TA0RUN of register TA01RUN. Read-modify-write instructions An instruction in which the CPU reads data from memory and writes the data to the same memory location in one instruction. • Example 1: SET 3, (TA01RUN) ... Set bit 3 of TA01RUN. Example 2: INC 1, (100H) ... Increment the data at 100H. Examples of read-modify-write instructions on the TLCS-900 Exchange instruction EX (mem), R Arithmetic operations ADD (mem), R/# ADC (mem), R/# SUB (mem), R/# SBC (mem), R/# INC #3, (mem) DEC #3, (mem) OR (mem), R/# Logic operations AND (mem), R/# XOR (mem), R/# Bit manipulation operations STCF #3/A, (mem) RES #3, (mem) SET #3, (mem) CHG #3, (mem) TSET #3, (mem) Rotate and shift operations c. RLC (mem) RRC (mem) RL (mem) RR (mem) SLA (mem) SRA (mem) SLL (mem) SRL (mem) RLD (mem) RRD (mem) fc, fs, fFPH, fSYS and one state The clock frequency input on pins X1 and 2 is called fOSCH. The clock selected by DFMCR0<ACT1:0> is called fc. The clock selected by SYSCR1<SYSCK> is called fFPH. The clock frequency give by fFPH divided by 2 is called fSYS. One cycle of fSYS is referred to as one state. 91C025-256 2007-02-28 TMP91C025 (2) Points to note a. AM0 and AM1 pins This pin is connected to the VCC or the VSS pin. Do not alter the level when the pin is active. b. EMU0 and EMU1 Open pins. c. Warm-up counter The warm-up counter operates when STOP mode is released, even if the system is using an external oscillator. As a result a time equivalent to the warm-up time elapses between input of the release request and output of the system clock. d. Programmable pull-up resistance The programmable pull-up resistor can be turned on/off by a program when the ports are set for use as input ports. When the ports are set for use as output ports, they cannot be turned on/off by a program. The data registers (e.g., Px) are used to turn the pull-up/pull-down resistors on/off. Consequently Read-Modify-write instructions are prohibited. e. Watchdog timer The watchdog timer starts operation immediately after a Reset is released. When the watchdog timer is not to be used, disable it. f. AD converter The string resistor between the VREFH and VREFL pins can be cut by a program so as to reduce power consumption. When STOP mode is used, disable the resistor using the program before the HALT instruction is executed. g. CPU (micro DMA) Only the LDC cr, r and LDC r, cr instructions can be used to access the control registers in the CPU (e.g., The transfer source address register (DMASn)). h. Undefined SFR The value of an undefined bit in an SFR is undefined when read. i. POP SR instruction Please execute the POP SR instruction during DI condition. j. Releasing the HALT mode by requesting an interruption Usually, interrupts can release all halts status. However, the interrupts (INT0 to INT3, INTKEY, INTRTC, INTALM0 to INTALM4) which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 5 clocks of fFPH) with IDLE1 or STOP mode (IDLE2 is not applicable to this case). (In this case, an interrupt request is kept on hold internally) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficulty. The priority of this interrupt is compared with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt. 91C025-257 2007-02-28 TMP91C025 7. Package Dimensions P-LQFP100-1414-0.50F Unit: mm 91C025-258 2007-02-28