T6B65AFG TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC T6B65AFG Column Driver LSI for Dot Matrix Graphic LCD’s Manufactured using the CMOS process, the T6B65AFG is a column (segment) driver for small-to-medium-sized dot matrix graphic LCDs. Use of the T6B65AFG enables power dissipation to be reduced. It is designed to connect directly to an 8-bit microprocessor unit. The MPU can program all operating modes for the T6B65AFG asynchronously. The T6B65AFG stores display data transferred from an MPU in its internal display RAM. The contents of the internal display RAM correspond to the image on the LCD screen and are used to generate the LCD drive signal. Three T6B65AFGs can be combined with a Toshiba T6B66BFG row (common) driver to drive a 240-dot by 65-dot LCD screen. The T6B65AFG is lead (Pb)-free product. QFP100-P-1420-0.65Q Weight: 1.6 g (typ.) Features Dot matrix graphic LCD column driver with display RAM Display RAM capacity : 64 lines × 10 pages × 8 bits = 5120 bits (display area) 1 line × 10 pages × 8 bits = 80 bits (flag area) Total = 5200 bits LCD drive outputs : 80 Interface : 80-family MPU (8-bit) RAM data directly echoed to LCD (1) RAM bit data = 1 …………… ON (2) RAM bit data = 0 …………… OFF Duty: Can be controlled by the T6B66BFG. Display OFF functions Various functions X/Y-counter selection, Up/Down mode selection, X-address setting, Y-address setting, Display Start Line setting, “Status Read”, display data read/write Low power consumption Logic power supply : 2.7 to 5.5 V CMOS Si-Gate process 100-pin-plastic flat package 1 2005-06-01 T6B65AFG Block Diagram 2 2005-06-01 T6B65AFG Pin Assignment 3 2005-06-01 T6B65AFG Pin Functions Pin Name Pin No . I/O Function SEG1 to SEG80 1 to 80 Output CL 96 Input Shift clock pulse PM 95 Input Pre-frame signal input /φ 94 Input Clock signal DB0 to DB7 81 to 88 I/O Data bus Column driver outputs D/I 93 Input Data/instruction select signal input (Note 1) / WR 92 Input Write select signal input (Note 2) / CE 91 Input Chip enable signal input (Note 3) Reset signal input: / RST = L ......... Reset state / RST 89 Input VDD, VSS 90, 97 ― Power supply VLC2, 3, 5 98, 99, 100 ― Power supply for LCD drive Note 1: D / I = H ……………… Indicates that the data on DB0 to DB7 is display data. D / I = L ……………… Indicates that the data on DB0 to DB7 is control data. Note 2: / WR = H ………..…… Read is selected. / WR = L ………..…… Write is selected. Note 3: When writing………… Data on DB0 to DB7 is latched on the rising edge of / CE. When reading…..…… Data appears at DB0 to DB7 while / CE is LOW. Function of Each Block ● Interface The T6B65AFG is equipped with interface logic enabling interfacing to an 8-bit (80-family) MPU. ● Input register This register holds 8-bit data from the MPU. Instruction and display data are distinguished by the D / I signal and the 8-bit data. ● Output register This register holds 8-bit data from the display RAM. When display data is read, the display data in the address is copied to this register. The address is then automatically incremented or decremented. When an address is set, therefore, the correct data does not appear on the first data reading. The data at the specified address appears on the second data reading. ● X, Y (Page)-address counter The X, Y (Page)-address counter holds a display RAM address. Reading or writing to the display RAM causes the X / Y-address to increment or decrement automatically. 4 2005-06-01 T6B65AFG ● Z-address counter The Z-address counter holds the 6-bit datum that indicates the display start line. This value is preset by the PM signal. The value indicates the address of the display start line, which is the line that appears at the top of the screen. ● Counter Up / Down register This register determines the counter and Up / Down mode. When the X-counter / Up mode is selected, reading or writing to the RAM causes the X-counter to increment automatically. When the X-counter / Down mode is selected, reading or writing to the RAM causes the X-counter to decrement automatically. When the Y-counter / Up mode is selected, reading or writing to the RAM causes the Y-counter to increment automatically. When the Y-counter / Down mode is selected, reading or writing to the RAM causes the Y-counter to decrement automatically. ● Display ON / OFF register This 1-bit register holds the ON / OFF state. In the OFF state, the output is ignored. In the ON state, the data in the display RAM is displayed. The data in the display RAM is independent of the value of the display ON / OFF setting. ● Busy flag The Busy flag is set when an instruction other than the Status Read instruction is executed. Using Status Read, you can find out whether the Busy flag has been set or not. While the Busy flag is set, the T6B65A cannot accept any instruction other than Status Read. Ensure, therefore, that the Busy flag is reset before an instruction is issued. The Busy state time (T) is always as follows: 1 / F ≤ T ≤ 2 / F [seconds] F: φ frequency (one half of the T6B66BFG's oscillation frequency) ● Latch The rising edge of CL latches data from the display RAM. ● Column driver circuit and LCD voltage generation circuit The column driver circuit consists of 80 driver circuits. The combination of display data from latches and the M signal selects one of the four LCD levels. Details of the voltage generation circuit and column driver circuit are shown in the diagram below: 5 2005-06-01 T6B65AFG Command Definitions / WR D/I DB7 DB6 DB5 DB4 DB3 Code DB2 DB1 DB0 0 0 0 0 0 0 0 0 1 1/0 Display ON (1) / OFF (0) Y (1) / X (0) Counter Select UP (1) / Down (0) Mode Select Function 0 0 0 0 0 0 0 1 Y/X U/D 0 0 0 0 0 0 1 * * * 0 0 0 1 0 0 1 0 0 0 1 1 * F / DR 1 0 B 0 D R 0 1 Write Data Write Display Data 1 1 Read Data Read Display Data Test Mode Select Z-Address (0 to 63) Set Z-Address X-Address (0 to 63) Set X-Address Y (Page) −Address (0 to 9) Set Y (Page) −Address 0 Status Read (Note) F / DR Y/X U/D *: INVALID Note: B : D : R : Y/X : U/D : F / DR : Busy flag Display ON (1) / OFF (0) Reset Counter Select 1: Y-Counter Up / Down Select 1: Up Flag Mode 1: Flag Mode 0: X-Counter 0: Down 0: Display RAM Mode ● Display ON / OFF / WR D / I DB7 Code ················································ DB0 0 0 0 0 0 0 0 0 1 1 Display ON 0 0 0 0 0 0 0 0 1 0 Display OFF This command controls the display ON / OFF setting. Display ON / OFF does not change the display RAM data. When / RST = L, Display = OFF (all the segment outputs are at the VDD level when Display = OFF). The T6B65A is in display OFF mode after a reset operation. ● Counter UP / DOWN select / WR D / I DB7 Code ················································ DB0 0 0 0 0 0 0 0 1 0 0 X-Counter / Down Mode 0 0 0 0 0 0 0 1 0 1 X-Counter / Up Mode 0 0 0 0 0 0 0 1 1 0 Y-Counter / Down Mode 0 0 0 0 0 0 0 1 1 1 Y-Counter / Up Mode This command selects the counter and Up / Down mode. When / RST = L, Y-Counter / Up mode is selected. 6 2005-06-01 T6B65AFG ● Test mode select / WR D / I DB7 Code 0 0 0 ················································ 0 0 0 1 * DB0 * * *: INVALID This command selects the Test mode. Do not use this command. ● Set Z-address (Display Start Line) / WR D / I DB7 Code 0 0 0 ················································ 1 A A A A DB0 A A This command specifies which RAM line (0 to 63) is displayed at the top of the screen. When the display duty is more than 1 / 64 (e.g., 1 / 33, 1 / 49), display begins at a line within the range 1 to 33 or 1 to 49. This command only applied to display RAM. The line following the last line of the display RAM is the flag RAM. ● Set X-address / WR D / I DB7 Code 0 0 1 ················································ 0 A A A A DB0 A A This command sets the X-address (0 to 63). When the Counter Up / Down Select command selects this address counter, reading or writing to the RAM causes the X-address to increment or decrement automatically. In X-Counter / Up mode, if the previous X-address is 63, the new X-address after the increment will be 0 and the Y (page)-address will be incremented. In Y-Counter / Down mode, if the previous X-address is 0, the new X-address after the decrement will be 63 and the Y (page)-address will be decremented. ● Set Y (Page)-address / WR D / I DB7 Code ················································ DB0 0 0 1 1 * 1 A A A A Flag mode 0 0 1 1 * 0 A A A A Display RAM mode *: INVALID This command sets the Y (page) -address and also selects Flag mode or Display RAM mode. In Flag mode, you can read data from or write data to Flag RAM only but cannot access the Display RAM. In Display RAM mode, you can read data from or write data to the Display RAM only but cannot access the Flag RAM. When the Counter Up / Down Select command selects this address counter, reading from or writing to the RAM causes the Y-address to increment or decrement automatically. In Y-Counter / Up mode, if the previous Y-address is 9, the new Y-address after the increment will be 0 and the X-address will be incremented. In Y-Counter / Down mode, if the previous Y-address is 0, the new Y-address after the decrement will be 9 and the X-address will be decremented. In Flag mode, only Y-Counter / Up or Down mode is permitted. 7 2005-06-01 T6B65AFG ● Status Read / WR D / I DB7 Code 0 0 B ················································ 0 D R 0 DB0 F / DR Y / X U / D B (Busy) : When B = 1, an instruction is being executed and no other instructions may be accepted. When B = 0, instructions can be accepted. D (Display) : When D = 1, display is ON. When D = 0, display is OFF. R (Reset) : When R = 1, the T6B65A is in the Reset state. When R = 0, the T6B65A is in the Operating state. Y / X (Counter) : When Y / X = 1, Y-Counter is selected. When Y / X = 0, X-Counter is selected. U (Up) / D (Down) : When U / D = 1, Up mode is selected. When U / D = 0, Down mode is selected. F (Flag) / DR (Display RAM) : When F / DR = 1, Flag mode is selected. When F / DR = 0, Display RAM is selected. ● Read / Write display data / WR D / I DB7 Code ················································ DB0 0 1 D D D D D D D D Write Data 1 1 D D D D D D D D Read Data This command sends data to or receives data from the LCD RAM address that was specified. However, the correct data does not appear on the first read of the display data. Refer to the description of the Output Register in the section FUNCTION OF EACH BLOCK. 8 2005-06-01 T6B65AFG LCD Drive Waveform LCD driver timing chart (1 / 65 duty) Absolute Maximum Ratings (Ta = 25°C) Item Symbol Rating Unit Supply Voltage (1) VDD (Note 1) −0.3 to 7.0 V Supply Voltage (2) VLC2, 3, 5 (Note 3) VDD − 18.0 to VDD + 0.3 V Input Voltage VIN (Note 1, 2) −0.3 to VDD + 0.3 V Operating Temperature Topr −20 to 75 °C Storage Temperature Tstg −55 to 125 °C Note 1: Referenced to VSS Note 2: Applies to all data bus pins and input pins except VLC2, VLC3 and VLC5 Note 3: Ensure that the following condition is always maintained: VDD ≥ VLC2 ≥ VLC3 ≥ VLC5 9 2005-06-01 T6B65AFG Electrical Characteristics DC Characteristics Test Conditions (1) (Unless otherwise specified, VSS = 0, VDD = 3.0 V ± 10%, VLC5 = VDD − 16 V, Ta = −20 to 75°C) Item Symbol Test Circuit Test Condition Operating Supply (1) VDD ― Min Typ. Max Unit ― 2.7 Pin Name ― 3.3 V VDD ― VDD −4.0 V VLC5 CL, PM, / φ DB0 to DB7, D / I, / WR, / CE, / RST VLC5 ― ― VDD −16.0 H Level VIH ― ― 0.8 VDD ― VDD V L Level VIL ― ― 0 ― 0.2 VDD V H Level VOH ― IOH = −400 µA VDD −0.2 ― ― V L Level VOL ― IOL = 400 µA ― ― 0.2 V Rcol ― VDD − VLC5 = 11.0 V Load current = ±100 µA ― ― 7.5 KΩ SEG1 to SEG80 Input Leakage IIL ― VIN = VDD to GND −1 ― 1 µA DB0 to DB7, D / I, / WR, / CE, / RST, CL, PM, / φ Operating Frequency fφ ― 10 ― 250 kHz /φ Current Consumption (1) IDD1 ― (Note 1) ― 100 140 µA VDD Current Consumption (2) IDD2 ― (Note 2) ― 20 30 µA VDD Current Consumption (3) IDD3 ― (Note 3) −1 ― 1 µA VDD Operating Supply (2) Input Voltage Output Voltage Column Driver Output Resistance ― DB0 to DB7 Note 1: Current consumption while the internal data receiver is operating: VDD = 2.7 to 3.3 V, VLC5 = VDD − 16 V, Ta = 25°C 1/9 bias, 1/65 duty, no load, fPM = 35 Hz, fCE = 1 MHz Note 2: Current consumption while the internal data receiver is inactive: VDD = 2.7 to 3.3 V, VLC5 = VDD −16 V, Ta = 25°C 1/9 bias, 1/65 duty, no load Note 3: Current consumption in low power mode ( / STB pin of T6B66BFG = L): VDD = 3.0V, VLC5 = 0 V, Ta = 25°C, no load 10 2005-06-01 T6B65AFG Test Conditions (2) (Unless otherwise noted, VSS = 0, VDD = 5.0 V ± 10%, VLC5 = VDD − 16 V, Ta = −20 to 75°C) Item Symbol Test Circuit Test Condition Min Typ. Max Unit Operating Supply (1) VDD ― ― 4.5 ― 5.5 V VDD Operating Supply (2) VLC5 ― ― VDD −16.0 ― VDD −4.0 V VLC5 H Level VIH ― ― 0.7 VDD ― VDD V L Level VIL ― ― 0 ― 0.3 VDD V CL, PM, /φ DB0 to DB7, D / I, / WR, / CE, / RST H Level VOH ― IOH = −400 µA VDD −0.4 ― ― V L Level VOL ― IOL = 400 µA ― ― 0.4 V Column Output Resistance Rcol ― VDD − VLC5 = 11.0 V Load current = ±100 µA ― ― 7.5 kΩ SEG1 to SEG80 Input Leakage IIL ― VIN = VDD to GND −1 ― 1 µA DB0 to DB7, D / I, / WR, / CE, / RST, CL, PM, /φ Operating Frequency fφ ― 10 ― 250 kHz /φ Current Consumption (1) IDD1 ― (Note 1) ― 220 330 µA VDD Current Consumption (2) IDD2 ― (Note 2) ― 35 50 µA VDD Current Consumption (3) IDD3 ― (Note 3) −1 ― 1 µA VDD Input Voltage Output Voltage ― Pin Name DB0 to DB7 Note 1: Current consumption while the internal data receiver is operating: VDD = 4.0 to 5.5 V, VLC5 = VDD − 16 V, Ta = 25°C 1/9 bias, 1/65 duty, no load, fPM = 35 Hz, fCE = 1 MHz Note 2: Current consumption while the internal data receiver is inactive: VDD = 4.0 to 5.5 V, VLC5 = VDD − 16 V, Ta = 25°C 1/9 bias, 1/65 duty, no load Note 3: Current consumption in Low Power mode ( / STB pin of T6B66BFG = L): VDD = 5.0 V, VLC5 = 0 V, Ta = 25°C, no load 11 2005-06-01 T6B65AFG AC Characteristics Test Conditions (1) (VSS = 0 V , VDD = 3.0 V ± 10%, VLC5 = 0 V , Ta = −20 to 75°C) Item Symbol Min Enable Cycle Time tcycE 1000 ― ns Enable Pulse Width PWEH 450 ― ns Enable Rise / Fall Time tEr, tEf ― 25 ns Address Set-up Time tAS 40 ― ns Address Hold Time tAH 10 ― ns Data Set-up Time tDS 280 ― ns tDHW 10 ― ns Data Hold Time Max Load Circuit Unit Data Delay Time tDD (Note) ― 300 ns Data Hold Time tDHR (Note) 20 ― ns Test Conditions (2) (VSS = 0 V, VDD = 5.0 V ± 10%, VLC5 = 0 V, Ta = −20 to 75°C) Item Symbol Min Max Unit Enable Cycle Time tcycE 500 ― ns Enable Pulse Width PWEH 220 ― ns Enable Rise / Fall Time tEr, tEf ― 20 ns Address Set-up Time tAS 40 ― ns Address Hold Time tAH 0 ― ns Data Set-up Time tDS 60 ― ns tDHW 10 ― ns Data Hold Time Data Delay Time tDD (Note) ― 120 ns Data Hold Time tDHR (Note) 20 ― ns Note: With load circuit connected 12 2005-06-01 T6B65AFG Application Circuit 13 2005-06-01 T6B65AFG Package Dimensions QFP100-P-1420-0.65Q Weight :1.6g (Typ.) 14 2005-06-01 T6B65AFG 15 2005-06-01