TC58NVG1S3BFT00/TC58NVG1S8BFT00
TENTATIVE
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
2
2 GBIT (256M × 8 BIT/128M × 16 BIT) CMOS NAND E PROM
DESCRIPTION
The TC58NVG1SxB is a single 3.3 V 2 Gbit (2,214,592,512 bits) NAND Electrically Erasable and Programmable
Read-Only Memory (NAND E2PROM) organized as (2048 + 64) bytes/(1024 + 32) words × 64 pages × 2048 blocks.
The device has a 2112-byte/1056-word static register which allow program and read data to be transferred between
the register and the memory cell array in 2112-byte increments. The Erase operation is implemented in a single
block unit (128 Kbytes + 4 Kbytes: 2112 bytes × 64 pages).
The TC58NVG1SxB is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed making
the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still
cameras and other systems which require high-density non-volatile memory data storage.
FEATURES
•
Organization
Memory cell array
Register
Page size
Block size
TC58NVG1S3B
2112 × 128K × 8
2112 × 8
2112 bytes
(128K + 4K) bytes
TC58NVG1S8B
1056 × 128K × 16
1056 × 16
1056 words
(64K + 2K) words
•
Modes
Read, Reset, Auto Page Program, Auto Block Erase，Status Read
•
Mode control
Serial input/output
Command control
•
Number of valid blocks
Max 2048 blocks
Min 2008 blocks
•
Power supply
VCC = 2.7 V to 3.6 V
•
Program/Erase Cycles
100000 Cycles (With ECC)
•
Access time
Cell array to register
Serial Read Cycle
25 µs max
50 ns min
•
Program/Erase time
Auto Page Program
Auto Block Erase
200 µs/page typ.
1.5 ms/block typ.
Operating current
Read (50 ns cycle)
Program (avg.)
Erase (avg.)
Standby
10 mA typ.
10 mA typ.
10 mA typ.
50 µA max
•
•
Package
TC58NVG1S3BFT00 TSOP I 48-P-1220-0.50
TC58NVG1S8BFT00 TSOP I 48-P-1220-0.50
(Weight: 0.53 g typ.)
1
2003-10-30A
TC58NVG1S3BFT00/TC58NVG1S8BFT00
PIN ASSIGNMENT (TOP VIEW)
TC58NVG1S8BFT00
TC58NVG1S3BFT00
×16
×8
NC
NC
NC
NC
NC
GND
NC
NC
NC
NC
NC
GND
RY / BY
RY / BY
RE
CE
NC
NC
VCC
VSS
NC
NC
CLE
ALE
WE
WP
NC
NC
NC
NC
NC
RE
CE
NC
NC
VCC
VSS
NC
NC
CLE
ALE
WE
WP
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
×8
×16
NC
NC
NC
NC
I/O8
I/O7
I/O6
I/O5
NC
PSL
NC
VCC
VSS
NC
NC
NC
I/O4
I/O3
I/O2
I/O1
NC
NC
NC
NC
VSS
I/O16
I/O8
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
PSL
NC
VCC
NC
NC
NC
I/O12
I/O4
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
VSS
PINNAMES
I/O1 to I/O8
I/O port
I/O9 to I/O16
I/O port (×16)
CE
Chip enable
WE
Write enable
RE
Read enable
CLE
Command latch enable
ALE
Address latch enable
PSL
Power on select
WP
Write protect
RY/BY
Ready/Busy
GND
Ground
VCC
Power supply
VSS
Ground
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2003-10-30A
TC58NVG1S3BFT00/TC58NVG1S8BFT00
BLOCK DIAGRAM
VCC VSS
Status register
Address register
I/O1
Column buffer
I/O
Control circuit
to
Column decoder
I/O8
or
I/O16
Command register
Data register
Row address buffer
decoder
CE
CLE
ALE
WE
Logic control
Control circuit
RE
WP
Row address decoder
Sense amp
Memory cell array
PSL
RY / BY
RY / BY
HV generator
ABSOLUTE MAXIMUM RATINGS
SYMBOL
RATING
VALUE
UNIT
VCC
Power Supply Voltage
−0.6 to 4.6
V
VIN
Input Voltage
−0.6 to 4.6
V
VI/O
Input /Output Voltage
−0.6 V to VCC + 0.3 V (≤ 4.6 V)
V
PD
Power Dissipation
0.3
W
TSOLDER
Soldering Temperature (10 s)
260
°C
TSTG
Storage Temperature
−55 to 150
°C
TOPR
Operating Temperature
0 to 70
°C
CAPACITANCE *(Ta = 25°C, f = 1 MHz)
SYMB0L
PARAMETER
CONDITION
MIN
MAX
UNIT
CIN
Input
VIN = 0 V
10
pF
COUT
Output
VOUT = 0 V
10
pF
*
This parameter is periodically sampled and is not tested for every device.
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2003-10-30A
TC58NVG1S3BFT00/TC58NVG1S8BFT00
VALID BLOCKS
SYMBOL
NVB
NOTE:
PARAMETER
Number of Valid Blocks
MIN
TYP.
MAX
UNIT
2008
2048
Blocks
The device occasionally contains unusable blocks. Refer to Application Note (13) toward the end of this document.
The first block (Block 0) is guaranteed to be a valid block at the time of shipment.
The minimum number of valid blocks is guaranteed over the lifetime.
RECOMMENDED DC OPERATING CONDITIONS
SYMBOL
PARAMETER
MIN
TYP.
MAX
UNIT
2.7 V
3.6 V
V
VCC
Power Supply Voltage
VIH
High Level input Voltage
2.7 V ≤ VCC ≤ 3.6 V
2.0
VCC + 0.3
V
VIL
Low Level Input Voltage
2.7 V ≤ VCC ≤ 3.6 V
−0.3*
0.8
V
−2 V (pulse width lower than 20 ns)
*
DC CHARACTERISTICS (Ta = 0 to 70℃, VCC = 2.7 V to 3.6 V)
SYMBOL
PARAMETER
CONDITION
MIN
TYP.
MAX
UNIT
IIL
Input Leakage Current
VIN = 0 V to VCC
±10
µA
ILO
Output Leakage Current
VOUT = 0 V to VCC
±10
µA
PSL = GND or NC
10
30
ICCO0*
Power On Reset Current
PSL = VCC, FFh command input after
Power On
10
30
CE = VIL, IOUT = 0 mA, tcycle = 50 ns
10
30
mA
mA
ICCO1
Serial Read Current
ICCO2
Programming Current
10
30
mA
ICCO3
Erasing Current
10
30
mA
ICCS1
Standby Current
CE = VIH, WP = 0 V/VCC
1
mA
ICCS2
Standby Current
CE = VCC − 0.2 V, WP = 0 V/VCC
10
50
µA
VOH
High Level Output Voltage
IOH = −0.4 mA (2.7 V ≤ VCC ≤ 3.6 V)
2.4
V
VOL
Low Level Output Voltage
IOL = 2.1 mA (2.7 V ≤ VCC ≤ 3.6 V)
0.4
V
IOL
( RY / BY )
Output current of RY / BY
VOL = 0.4 V (2.7 V ≤ VCC ≤ 3.6 V)
pin
8
mA
*
Refer to application note (2) for detail
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2003-10-30A
TC58NVG1S3BFT00/TC58NVG1S8BFT00
AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(Ta = 0 to 70℃, VCC = 2.7 V to 3.6 V)
SYMBOL
PARAMETER
MIN
MAX
UNIT
tCLS
CLE Setup Time
0
ns
tCLH
CLE Hold Time
10
ns
tCS
CE Setup Time
0
ns
tCH
CE Hold Time
10
ns
tWP
Write Pulse Width
25
ns
tALS
ALE Setup Time
0
ns
tALH
ALE Hold Time
10
ns
tDS
Data Setup Time
20
ns
tDH
Data Hold Time
10
ns
tWC
Write Cycle Time
50
ns
tWH
WE High Hold Time
15
ns
tWW
WP High to WE Low
100
ns
tRR
Ready to RE Falling Edge
20
ns
tRW
Ready to WE Falling Edge
20
ns
tRP
Read Pulse Width
35
ns
tRC
Read Cycle Time
50
ns
tREA
RE Access Time
35
ns
tCEA
CE Access Time
45
ns
tCLEA
CLE Access Time
45
ns
tALEA
ALE Access Time
45
ns
tOH
Data Output Hold Time
10
ns
tRHZ
RE High to Output High Impedance
30
ns
tCHZ
CE High to Output High Impedance
20
ns
tREH
RE High Hold Time
15
ns
tIR
Output-High-impedance-to- RE Falling Edge
0
ns
tRHW
RE High to WE Low
30
ns
tWHC
WE High to CE Low
30
ns
tWHR
WE High to RE Low
30
ns
tR
Memory Cell Array to Starting Address
25
µs
tWB
WE High to Busy
200
ns
tRST
Device Reset Time (Ready/Read/Program/Erase)
6/6/10/500
µs
5
NOTES
2003-10-30A
TC58NVG1S3BFT00/TC58NVG1S8BFT00
AC TEST CONDITIONS
CONDITION
PARAMETER
2.7 V ≤ VCC ≤ 3.6 V
Input level
2.4 V, 0.4 V
Input pulse rise and fall time
3ns
Input comparison level
1.5 V, 1.5 V
Output data comparison level
1.5 V, 1.5 V
CL (100 pF) + 1 TTL
Output load
Note:
Busy to ready time depends on the pull-up resistor tied to the RY / BY pin.
(Refer to Application Note (9) toward the end of this document.)
PROGRAMMING AND ERASING CHARACTERISTICS
(Ta = 0 to 70℃, VCC = 2.7 V to 3.6 V)
SYMBOL
PARAMETER
MIN
TYP.
MAX
UNIT
µs
tPROG
Average Programming Time
200
500
N
Number of Partial Program Cycles in the Same Page
8
tBERASE
Block Erasing Time
1.5
3
NOTES
(1)
ms
(1) Refer to Application Note (12) toward the end of this document.
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TC58NVG1S3BFT00/TC58NVG1S8BFT00
TIMING DIAGRAMS
Latch Timing Diagram for Command/Address/Data
CLE
ALE
CE
RE
Setup Time
Hold Time
WE
tDS
tDH
I/O
: VIH or VIL
Command Input Cycle Timing Diagram
CLE
tCLS
tCLH
tCS
tCH
CE
tWP
WE
tALS
tALH
ALE
tDS
tDH
I/O
: VIH or VIL
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2003-10-30A
TC58NVG1S3BFT00/TC58NVG1S8BFT00
Address Input Cycle Timing Diagram
tCLS
CLE
tCS
tWC
tWC
tWC
tWC
CE
tWP
tWH
tWP
tWH
tWP
tWH
tWP
tWH
tWP
WE
tALS
tALH
ALE
tDS
tDH
tDS
CA0 to 7
I/O
tDH
tDS
CA8 to 11
tDH
tDS
PA0 to 7
tDH
tDS
PA8 to 15
tDH
PA16
: VIH or VIL
Data Input Cycle Timing Diagram
tCLH
CLE
tCH
CE
tALS
tWC
ALE
tWP
tWH
tWP
tWP
WE
tDS
tDH
tDS
DIN0
I/O
tDH
DIN1
*) ×16: 1055
tDS
tDH
DIN2111*
: VIH or VIL
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TC58NVG1S3BFT00/TC58NVG1S8BFT00
Serial Read Cycle Timing Diagram
tRC
tCEA
CE
tRP
tREH
RE
tRP
tRP
tOH
tREA
tRHZ
tCHZ
tOH
tREA
tOH
tRHZ
tREA
tRHZ
I/O
tRR
RY / BY
Status Read Cycle Timing Diagram
tCLEA
CLE
tCLS
tCLH
tCS
CE
tWP
tCH
WE
tWHC
tCEA
tCHZ
tWHR
RE
tOH
tDS
I/O
tIR
tDH
tREA
tRHZ
Status
output
70h*
RY / BY
*: 70h represents the hexadecimal number
: VIH or VIL
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2003-10-30A
TC58NVG1S3BFT00/TC58NVG1S8BFT00
Read Cycle Timing Diagram
tCLEA
CLE
tCLS
tCLH
tCS
tCH
tCLS
tCS
tCLH
tCH
tCEA
CE
tWC
WE
tALH tALS
tALH tALS
ALE
tR
tRC
tWB
RE
tDS tDH
I/O
00h
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
CA0
to 7
CA8
to 11
PA0
to 7
PA8
to 15
tDS tDH
PA16
tRR
tREA
DOUT
N
30h
DOUT
N+1
Data out from
Col. Add. N
Col. Add. N
RY / BY
Read Cycle Timing Diagram: When Interrupted by CE
tCLEA
CLE
tCLS
tCLH
tCS
tCH
tCLS
tCS
tCLH
tCH
tCEA
CE
tWC
WE
tALH tALS
tALH tALS
tCHZ
ALE
tR
tRHZ
tREA
tOH
DOUT
N
DOUT
N+1
tWB
RE
tDS tDH
I/O
tRC
00h
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
CA0
to 7
CA8
to 11
PA0
to 7
PA8
to 15
Col. Add. N
PA16
tDS tDH
30h
tRR
Col. Add. N
RY / BY
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2003-10-30A
TC58NVG1S3BFT00/TC58NVG1S8BFT00
Column Address Change in Read Cycle Timing Diagram (1/2)
tCLEA
CLE
tCLS
tCLH
tCS
tCH
tCLS tCLH
tCS
tCH
CE
tWC
tCEA
WE
tALH
tALS
tALH
tALS
ALE
tRC
tR
tWB
RE
I/O
tDS tDH
tDS tDH
tDS tDH
tDS tDH
tDS tDH
tDS tDH
tDS tDH
00h
CA0
to 7
CA8
to 11
PA0
to 7
PA8
to 15
PA16
30h
Column address
A
Page address
P
tRR
tREA
DOUT DOUT
A
A+1
DOUT
A+N
Page address
P
RY / BY
Column address
A
1
Continues from 1
11
of next page
2003-10-30A
TC58NVG1S3BFT00/TC58NVG1S8BFT00
Column Address Change in Read Cycle Timing Diagram (2/2)
tCLEA
CLE
tCLS
tCLH
tCS
tCH
tCLS
tCS
tCLH
tCH
CE
tRHW
tCEA
tWC
WE
tALH tALS
tALH tALS
ALE
tRC
RE
tDS tDH
tDS tDH
tDS tDH
tDS tDH
tREA
tIR
DOUT
A+N
I/O
05h
CA0
to 7
CA8
to 11
Column address
B
E0h
DOUT
B
DOUT
B+1
DOUT
B + N’
Page address
P
RY / BY
Column address
B
1
Continues from 1
of next page
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TC58NVG1S3BFT00/TC58NVG1S8BFT00
Auto-Program Operation Timing Diagram
tCLS
CLE
tCLS tCLH
tCS
tCS
CE
tCH
WE
tALH
tALH
tALS
tPRPG
tALS
tWB
ALE
RE
I/O
tDS
tDS
tDS tDH
tDS tDH
80h
CA0
to 7
tDH
tDH
CA8
to 11
PA0
to 7
PA8
PA16
to 15
DINN
DIN
DINM*
10h
70h
Status
output
Column address
N
RY / BY
: Do not input data while data is being output.
: VIH or VIL
*) M: up to 2112 (byte input data for ×8 device).
M: up to 1056 (word input data for ×16 device).
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TC58NVG1S3BFT00/TC58NVG1S8BFT00
Auto Block Erase Timing Diagram
CLE
tCLS
tCLH
tCS
tCLS
CE
WE
tALH
tALS
tWB
tBERASE
ALE
RE
tDS tDH
I/O
RY / BY
60h
Auto Block
Erase Setup
command
: VIH or VIL
PA0
to 7
PA8
to 15
PA16
D0h
Erase Start
command
Status
output
70h
Busy
Status Read
command
: Do not input data while data is being output.
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TC58NVG1S3BFT00/TC58NVG1S8BFT00
ID Read Operation Timing Diagram
tCLS
CLE
tCLS
tCS
tCS
tCH
tCEA
CE
tCH
WE
tALS
tALH
tALH
tALEA
ALE
RE
tDH
tDH
I/O
tREA
tREA
tREA
90h
00h
98h
DAh
ID Read
command
Address
00
Maker code
Device code
tREA
See
Table 5
tREA
See
Table 5
See
Table 5
: VIH or VIL
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2003-10-30A
TC58NVG1S3BFT00/TC58NVG1S8BFT00
PIN FUNCTIONS
The device is a serial access memory which utilizes time-sharing input of address information.
Command Latch Enable: CLE
The CLE input signal is used to control loading of the operation mode command into the internal command
register. The command is latched into the command register from the I/O port on the rising edge of the WE
signal while CLE is High.
Address Latch Enable: ALE
The ALE signal is used to control loading address information into the internal address register. Address
information is latched into the address register from the I/O port on the rising edge of WE while ALE is High.
Chip Enable: CE
The device goes into a low-power Standby mode when CE goes High during the device is in Ready state. The
CE signal is ignored when device is in Busy state ( RY / BY = L), such as during a Program or Erase or Read
operation, and will not enter Standby mode even if the CE input goes High.
Write Enable: WE
The WE signal is used to control the acquisition of data from the I/O port.
Read Enable: RE
The RE signal controls serial data output. Data is available tREA after the falling edge of RE .
The internal column address counter is also incremented (Address = Address + l) on this falling edge.
I/O Port: I/O1 to 8
The I/O1 to 8 pins are used as a port for transferring address, command and input/output data to and from
the device.
I/O Port: I/O9 to 16 (×16 device)
The I/O9 to 16 pins are used as a port for transferring input/output data to and from the device. I/O9 to 16
pins must be low level (VIL) when address and command are input.
Write Protect: WP
The WP signal is used to protect the device from accidental programming or erasing. The internal voltage
regulator is reset when WP is Low. This signal is usually used for protecting the data during the power-on/off
sequence when input signals are invalid.
Ready/Busy: RY / BY
The RY / BY output signal is used to indicate the operating condition of the device. The RY / BY signal is
in Busy state ( RY / BY = L) during the Program, Erase and Read operations and will return to Ready state
( RY / BY = H) after completion of the operation. The output buffer for this signal is an open drain and has to be
pulled-up to Vccq with an appropriate resister.
Power on Select: PSL
The PSL signal is used to select whether the device initialization should take place during the device power
on or during the first Reset. Please refer to the application note (2) for details.
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2003-10-30A
TC58NVG1S3BFT00/TC58NVG1S8BFT00
Schematic Cell Layout and Address Assignment
The Program operation works on page units while the Erase operation works on block units.
I/O1
Page Buffer
2048
I/O8
64
A page consists of 2112 bytes in which 2048 bytes are
used for main memory storage and 64 bytes are for
redundancy or for other uses.
64 Pages = 1 block
1 page = 2112 bytes
1 block = 2112 bytes × 64 pages = (128K + 4K) bytes
Capacity = 2112 bytes × 64pages x 2048blocks
131072
pages
2048 blocks
8I/O
2112
I/O1
Page Buffer
1024
I/O16
32
A page consists of 1056 words in which 1024 words are
used for main memory storage and 32 words are for
redundancy or for other uses.
64 Pages = 1 block
1 page = 1056 words
1 block = 1056 words × 64 pages = (64K + 2K) words
Capacity = 1056 words × 64 pages × 2048 blocks
131072
pages
2048 blocks
An address is read in via the I/O port over three
consecutive clock cycles, as shown in Table 1.
16I/O
1056
Table 1. Addressing
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
CA7
CA6
CA5
CA4
CA3
CA2
CA1
CA0
L
L
L
L
CA11
CA10
CA9
CA8
Third cycle
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Fourth cycle
PA15
PA14
PA13
PA12
PA11
PA10
PA9
PA8
L
L
L
L
L
L
L
PA16
First cycle
Second cycle
Fifth cycle
CA0 to CA11: Column address
PA0 to PA16: Page address
PA6 to PA16: Block address
PA0 to PA5: NAND address in block
Note) I/O9 − 16 must be held low when address is input (×16 device).
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2003-10-30A
TC58NVG1S3BFT00/TC58NVG1S8BFT00
Operation Mode: Logic and Command Tables
The operation modes such as Program, Erase, Read and Reset are controlled by command operations shown
in Table 3. Address input, command input and data input/output are controlled by the CLE, ALE, CE , WE ,
RE and WP signals, as shown in Table 2.
Table 2. Logic Table
CLE
ALE
CE
Command Input
H
L
Data Input
L
Address input
WE
*1
RE
WP
L
H
*
L
L
H
H
L
H
L
H
*
Serial Data Output
L
L
L
H
During Program (Busy)
*
*
*
*
*
H
During Erase (Busy)
*
*
*
*
*
H
*
*
H
*
*
*
*
*
L
H (*2)
H (*2)
*
Program, Erase Inhibit
*
*
*
*
*
L
Standby
*
*
H
*
*
0 V/VCC
*
During Read (Busy)
H: VIH, L: VIL, *: VIH or VIL
*1: Refer to Application Note (10) toward the end of this document regarding the WP signal when Program or Erase Inhibit
*2: If CE is low during read busy, WE and RE must be held High to avoid unintended command/address input to the device or
read to device. Reset or Status Read command can be input during Read Busy.
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2003-10-30A
TC58NVG1S3BFT00/TC58NVG1S8BFT00
Table 3. Command table (HEX)
First Cycle
Second Cycle
Acceptable while Busy
Serial Data Input
80
Read
00
30
Column Address Change in Serial Data Output
05
E0
Auto Page Program
80
10
Column Address Change in Serial Data Input
85
Auto Block Erase
60
D0
ID Read
90
Status Read
70
{
Reset
FF
{
Table 4 shows the operation states for Read mode.
Table 4. Read mode operation states
CLE
ALE
CE
WE
RE
I/O1 to I/O8 (I/O16)
Power
Output select
L
L
L
H
L
Data output
Active
Output Deselect
L
L
L
H
H
High impedance
Active
H: VIH, L: VIL, *: VIH or VIL
HEX data bit assignment
(Example)
0
0
0
0
0
0
Serial Data Input: 80h
0
0
1
0
0
0
0
0
0
I/O16 15 14 13 12 11 10
9
8
7
6
5
4
3
2 I/O1
19
0
2003-10-30A
TC58NVG1S3BFT00/TC58NVG1S8BFT00
DEVICE OPERATION
Read Mode
Read mode is set when the "00h" and “30h” commands are issued to the Command register. Between the two
commands, a start address for the Read mode needs to be issued. Refer to the figures below for the sequence and
the block diagram (Refer to the detailed timing chart.).
CLE
CE
WE
ALE
RE
RY / BY
Column Address M
Busy
Page Address N
00h
I/O
tR
30h
M+1
M
M+2
Page Address N
Start-address input
M
m
Select page
N
Cell array
A data transfer operation from the cell array to the register
starts on the rising edge of WE in the 30h command input
cycle (after the address information has been latched). The
device will be in the Busy state during this transfer period.
After the transfer period, the device returns to Ready state.
Serial data can be output synchronously with the RE clock
from the start address designated in the address input cycle.
I/O1 to 8: m = 2111
I/O1 to 16: m = 1055
Random Column Address Change in Read Cycle
CLE
CE
WE
ALE
RE
RY / BY
Busy
tR
Col. M
I/O
30h
00h
Col. M
Page N
Start-address input
M
Select page
N
M
M+1 M+2 M+3
Page N
Start from Col. M
M’
Cell array
20
E0h
05h
Col. M’
M’ M’+1 M’+2 M’+3 M’+4
Page N
Start from Col. M’
During the serial data output from the register the column
address can be changed by inputting a new column address
using the 05h and E0h commands. The data is read out in serial
starting at the new column address. Random Column Address
Change operation can be done multiple times within the same
page.
2003-10-30A
TC58NVG1S3BFT00/TC58NVG1S8BFT00
Auto Page Program Operation
The device carries out an Automatic Page Program operation when it receives a "10h" Program command
after the address and data have been input. The sequence of command, address and data input is shown below.
(Refer to the detailed timing chart.)
CLE
CE
WE
ALE
RE
RY/BY
I/O
Din Din Din
80h
Col. M
Page P
70h
10h
Data
The data is transferred (programmed) from the register to the
selected page on the rising edge of WE following input of the “10h”
command. After programming, the programmed data is transferred
back to the register to be automatically verified by the device. If the
programming does not succeed, the Program/Verify operation is
repeated by the device until success is achieved or until the
maximum loop number set in the device is reached.
Data input
Program
Din
Read& verification
Random Column Address Change in Auto Page Program Operation
The column address can be changed by the 85h command during the data input sequence of the Auto Page
Program operation.
Two address input cycles after the 85h command are recognized as a new column address for the data input.
After the new data is input to the new column address, the 10h command initiates the actual data program into the
selected page automatically. The Random Column Address Change operation can be repeated multiple times within
the same page.
80h
Din
Col. M
Din
Din
Din
85h
Din
Col. M’
Page N
Col. M
Din
10h
Status
Busy
Col. M’
Data input
Program
Reading & verification
Selected
page
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2003-10-30A
TC58NVG1S3BFT00/TC58NVG1S8BFT00
Auto Block Erase
The Auto Block Erase operation starts on the rising edge of WE after the Erase Start command “D0h” which
follows the Erase Setup command “60h”. This two-cycle process for Erase operations acts as an extra layer of
protection from accidental erasure of data due to external noise. The device automatically executes the Erase
and Verify operations.
60
D0
Block Address
input: 3 cycles
RY / BY
70
Status Read
command
Erase Start
command
I/O
Pass
Fail
Busy
22
2003-10-30A
TC58NVG1S3BFT00/TC58NVG1S8BFT00
ID Read
The device contains ID codes which can be used to identify the device type, the manufacturer, and features of
the device. The ID codes can be read out under the following timing conditions:
CLE
tCEA
CE
WE
tALEA
ALE
RE
tREA
I/O
90h
00h
98h
DAh
ID Read
command
Address 00
Maker code
Device code
See
table 5
See
table 5
See
table 5
For the specifications of the access times tREAI, tCEA and tALEA refer to the AC Characteristics.
Table 5. Code table
Description
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
Hex Data
1st Data
Maker Code
1
0
0
1
1
0
0
0
98h
2nd Data
Device Code
1
1
0
1
1
0
1
0
DAh
3rd Data
Chip Number, Cell Type, PGM
Page
0 or 1
0
0
0
0
0
0
0
00h or 80h
4th Data
Page Size, Block Size,
Redundant Size, Organization
0 or 1 0 or 1
0
1
0
1
0
1
×8) 15h or 95h
×16) 55h or D5h
5th Data
Plane Number, Plane Size
0 or 1
0
0
0
1
0
0
44h or C4h
1
3rd Data
Description
Internal Chip Number
Cell Type
Number of simultaneously
programmed pages
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
1
2
4
8
2 level cell
4 level cell
8 level cell
16 level cell
0
0
1
1
1
2
4
8
0
0
1
1
I/O2
I/O1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Reserved
0 or 1
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2003-10-30A
TC58NVG1S3BFT00/TC58NVG1S8BFT00
4th Data
Description
Page Size
(without redundant area)
1 KB
2 KB
4K KB
8 KB
Block Size
(without redundant area)
64 KB
128 KB
256 KB
512 KB
Redundant area size
(byte/512byte)
Organization
I/O8
I/O7
I/O6
0
0
1
1
I/O5
I/O3
I/O2
I/O1
0
0
1
1
0
1
0
1
I/O2
I/O1
0
1
0
1
8
16
Reserved
Reserved
×8
×16
I/O4
0
0
1
1
0
1
0
1
I/O4
I/O3
0
0
1
1
0
1
0
1
0
1
Reserved
0 or 1
5th Data
Description
Plane Number
Plane Size
Power Supply
I/O8
I/O7
I/O6
I/O5
1
2
4
8
64 Mbit
128 Mbit
256 Mbit
512 Mbit
1 Gbit
2 Gbit
4 Gbit
8 Gbit
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
3 V only
1.8 V & 3.3 V dual
0
1
Reserved
0 or 1
24
0
2003-10-30A
TC58NVG1S3BFT00/TC58NVG1S8BFT00
Status Read
The device automatically implements the execution and verification of the Program and Erase operations.
The Status Read function is used to monitor the Ready/Busy status of the device, determine the result (pass
/fail) of a Program or Erase operation, and determine whether the device is in Protect mode. The device status is
output via the I/O port using RE after a “70h” command input. The Status Read can also be used during a
Read operation to find out the Ready/Busy status.
The resulting information is outlined in Table 6.
Table 6. Status output table
Page Program
Block Erase
Definition
I/O1
Chip Status1
Pass: 0
I/O2
Read
Pass/Fail
Invalid
Not Used
Invalid
Invalid
I/O3
Not Used
0
0
I/O4
Not Used
0
0
I/O5
Not Used
0
0
I/O6
Ready/Busy
Ready: 1
Busy: 0
Ready/Busy
Ready/Busy
I/O7
Ready/Busy
Ready: 1
Busy: 0
Ready/Busy
Ready/Busy
I/O8
Write Protect
Not Protected :0
Protected: 1
Write Protect
Write Protect
Not used
Not used
I/O9 to 16 Not used
Fail: 1
The Pass/Fail status on I/O1 is only valid during a Program/Erase operation when the device is in the Ready state.
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2003-10-30A
TC58NVG1S3BFT00/TC58NVG1S8BFT00
An application example with multiple devices is shown in the figure below.
CE1
CE2
CE3
CEN
CEN + 1
CLE
ALE
Device
1
WE
Device
2
Device
3
Device
N
Device
N+1
RE
I/O1
to I/O8
RY / BY
RY / BY
Busy
CLE
ALE
WE
CE1
CEN
RE
70h
I/O
70h
Status on Device N
Status on Device 1
System Design Note: If the RY / BY pin signals from multiple devices are wired together as shown in the
diagram, the Status Read function can be used to determine the status of each individual device.
Reset
The Reset mode stops all operations. For example, in case of a Program or Erase operation, the internally
generated voltage is discharged to 0 volt and the device enters the Wait state.
The response to a “FFh” Reset command input during the various device operations is as follows:
When a Reset (FFh) command is input during programming
80
10
FF
00
Internal VPP
RY / BY
tRST (max 10 µs)
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2003-10-30A
TC58NVG1S3BFT00/TC58NVG1S8BFT00
When a Reset (FFh) command is input during erasing
D0
FF
00
Internal erase
voltage
RY / BY
tRST (max 500 µs)
When a Reset (FFh) command is input during Read operation
00
30
FF
00
RY / BY
tRST (max 6 µs)
When a Reset (FFh) command is input during Ready
FF
00
RY / BY
tRST (max 6 µs)
When a Status Read command (70h) is input after a Reset
FF
70
I/O status: Pass/Fail → Pass
: Ready/Busy → Ready
RY / BY
When two or more Reset commands are input in succession
10
(1)
(2)
(3)
FF
FF
FF
RY / BY
The second
FF
command is invalid, but the third
27
FF
command is valid.
2003-10-30A
TC58NVG1S3BFT00/TC58NVG1S8BFT00
APPLICATION NOTES AND COMMENTS
(1)
Power-on/off sequence:
The timing sequence shown in the figure below is necessary for the power-on/off sequence.
The device internal initialization starts after the power supply reaches an appropriate level in the power
on sequence. During the initialization the device Ready/Busy signal indicates the Busy state as shown in the
figure below. In this time period, the acceptable commands are FFh or 70h.
The WP signal is useful for protecting against data corruption at power-on/off.
2.7 V
2.5 V
0 V
VCC
Don’t
care
Don’t
care
CE , WE , RE
CLE, ALE
WP
VIH
VIL
VIL
1 ms max
Operation
100 µs max
Don’t
care
Invalid
Ready/Busy
(2)
Power-on Reset
The device goes into automatic self initialization during power on if PSL is tied either to GND or NC.
During the initialization process, the device consumes a maximum current of 30 mA (ICCO0). If PSL is tied
to VCC, the device will not complete its self initialization during power on and will not consume ICCO0, and
completes the initialization process with the first Reset command input after power on. During the first FFh
reset Busy period, the device consumes a maximum current of 30 mA (ICCO0). In either case (PSL = GND/
NC or VCC), the following sequence is necessary because some input signals may not be stable at power-on.
Power on
FF
Reset
(3)
Prohibition of unspecified commands
The operation commands are listed in Table 3. Input of a command other than those specified in Table 3 is
prohibited. Stored data may be corrupted if an unknown command is entered during the command cycle.
(4)
Restriction of commands while in the Busy state
During the Busy state, do not input any command except 70h and FFh.
28
2003-10-30A
TC58NVG1S3BFT00/TC58NVG1S8BFT00
(5)
Acceptable commands after Serial Input command “80h”
Once the Serial Input command “80h” has been input, do not input any command other than the Column
Address Change in Serial Data Input command “85h”, Auto Program command “10h”, or the Reset command
“FFh”.
80
FF
WE
Address input
RY / BY
If a command other than “85h”, “10h” or “FFh” is input, the Program operation is not performed and the
device operation is set to the mode which the input command specifies.
80
XX
10
Mode specified by the command.
Programming cannot be executed.
Command other than
“85h”, “10h” or “FFh”
(6)
Addressing for program operation
Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of
the block to MSB (most significant bit) page of the block. Random page address programming is prohibited.
From the LSB page to MSB page
DATA IN: Data (1)
Ex.) Random page program (Prohibition)
DATA IN: Data (1)
Data (64)
Data register
Data (64)
Data register
Page 0
(1)
Page 0
(2)
Page 1
Page 2
(2)
(32)
(3)
Page 1
Page 2
Page 31
(32)
Page 31
(1)
Page 63
(64)
Page 63
(64)
29
(3)
2003-10-30A
TC58NVG1S3BFT00/TC58NVG1S8BFT00
(7)
Status Read during a Read operation
00
Command
00
30
[A]
70
CE
WE
RY/BY
RE
Address N
Status Read
command input
Status output
Status Read
.
The device status can be read out by inputting the Status Read command “70h” in Read mode. Once the
device has been set to Status Read mode by a “70h” command, the device will not return to Read mode
unless the Read command “00h” is input during [A]. In this case, data output starts automatically from
address N and address input is unnecessary
(8)
Auto programming failure
Fail
80
10
70
I/O
80
Address Data
M
input
10
Address Data
N
input
80
If the programming result for page address M is Fail, do not try to program the
page to address N in another block without the data input sequence.
Because the previous input data has been lost, the same input sequence of 80h
command, address and data is necessary.
10
M
N
(9)
RY / BY : termination for the Ready/Busy pin ( RY / BY )
A pull-up resistor needs to be used for termination because the RY / BY buffer consists of an open drain
circuit.
VCC
Ready
VCC
VCC
3.0 V
R
1.0 V
Device
Busy
1.0 V
RY / BY
tr
tf
CL
VSS
1.5 µs
tr
This data may vary from device to device.
We recommend that you use this data as a
reference when selecting a resistor value.
tf
1.0 µs
15 ns
10 ns
tf
tr
0.5 µs
0
VCC = 3.3 V
Ta = 25°C
CL = 100 pF
5 ns
1 KΩ
2 KΩ
3 KΩ
4 KΩ
R
30
2003-10-30A
TC58NVG1S3BFT00/TC58NVG1S8BFT00
(10)
Note regarding the WP signal
The Erase and Program operations are automatically reset when WP goes Low. The operations are
enabled and disabled as follows:
Enable Programming
WE
DIN
80
10
WP
RY / BY
tWW (100 ns MIN)
Disable Programming
WE
DIN
80
10
WP
RY / BY
tWW (100 ns MIN)
Enable Erasing
WE
DIN
60
D0
WP
RY / BY
tWW (100 ns MIN)
Disable Erasing
WE
DIN
60
D0
WP
RY / BY
tWW (100 ns MIN)
31
2003-10-30A
TC58NVG1S3BFT00/TC58NVG1S8BFT00
(11)
When six address cycles are input
Although the device may read in a sixth address, it is ignored inside the chip.
Read operation
CLE
CE
WE
ALE
I/O
00h
30h
Ignored
Address input
RY / BY
Program operation
CLE
CE
WE
ALE
I/O
80h
Ignored
Address input
32
Data input
2003-10-30A
TC58NVG1S3BFT00/TC58NVG1S8BFT00
(12)
Several programming cycles on the same page (Partial Page Program)
A page can be divided into up to 8 segments as follows:
Data area (column address 0 to 2047)
: 512 bytes × 4 segments
1st segment: column address 0 to 511
2nd segment: column address 512 to 1023
3rd segment: column address 1024 to 1535
4th segment: column address 1536 to 2047
Redundant area (column address 2048 to 2111) : 16 bytes × 4 segments
1st segment: column address 2048 to 2063
2nd segment: column address 2064 to 2079
3rd segment: column address 2080 to 2095
4th segment: column address 2096 to 2111
Each segment can be programmed individually as follows:
1st programming
2nd programming
All 1 s
8th programming
Result
All 1 s
Data Pattern 1
Data Pattern 2
All 1 s
Data Pattern 1
Data Pattern 2
33
All 1 s
Data Pattern 8
Data Pattern 8
2003-10-30A
TC58NVG1S3BFT00/TC58NVG1S8BFT00
(13)
Invalid blocks (bad blocks)
The device occasionally contains unusable blocks. Therefore, the following issues must be recognized:
Bad Block
Bad Block
At the time of shipment, all data bytes in a valid block are FFh. For bad
blocks, all bytes are not in the FFh state. Please do not perform an erase
operation to bad blocks. It may be impossible to recover the bad block
information if the information is erased.
Check if the device has any bad blocks after installation into the system.
Refer to the test flow for bad block detection. Bad blocks which are
detected by the test flow must be managed as unusable blocks by the
system.
A bad block does not affect the performance of good blocks because it is
isolated from the bit lines by select gates.
The number of valid blocks at the time of shipment is as follows:
Valid (Good) Block Number
MIN
TYP.
MAX
UNIT
2008
2048
Block
Bad Block Test Flow
Read Check: Read either column 0 or 2048 of the
1st page or the 2nd page of each
block. If the data of the column is
not FF (Hex), define the block as a
bad block.
Start
Block No = 1
Fail
Read Check
Pass
Block No. = Block No. + 1
No
Bad Block *1
Block No. = 2048
Yes
End
*1: No erase operation is allowed to detected bad blocks
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2003-10-30A
TC58NVG1S3BFT00/TC58NVG1S8BFT00
(14)
Failure phenomena for Program and Erase operations
The device may fail during a Program or Erase operation.
The following possible failure modes should be considered when implementing a highly reliable system.
FAILURE MODE
DETECTION AND COUNTERMEASURE SEQUENCE
Block
Erase Failure
Status Read after Erase → Block Replacement
Page
Programming Failure
Status Read after Program → Block Replacement
Single Bit
Programming Failure
“1 to 0”
ECC
•
•
ECC: Error Correction Code. 2 bits per page is necessary.
In case the 2 Kbyte page is divided into segments of 512 bytes, 1 bit correction per segment is
necessary.
Block Replacement
Program
Error occurs
Buffer
memory
Block A
When an error happens in Block A, try to reprogram the
data into another Block (Block B) by loading from an
external buffer. Then, prevent further system accesses
to Block A ( by creating a bad block table or by using
another appropriate scheme).
Block B
Erase
When an error occurs during an Erase operation, prevent future accesses to this bad block
(again by creating a table within the system or by using another appropriate scheme).
(15)
Do not turn off the power before write/erase operation is complete. Avoid using the device when the battery
is low. Power shortage and/or power failure before write/erase operation is complete will cause loss of data
and/or damage to data.
35
2003-10-30A
TC58NVG1S3BFT00/TC58NVG1S8BFT00
Package Dimensions
Weight: 0.53 g (typ.)
36
2003-10-30A
TC58NVG1S3BFT00/TC58NVG1S8BFT00
RESTRICTIONS ON PRODUCT USE
•
030619EBA
The information contained herein is subject to change without notice.
•
The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of
TOSHIBA or others.
•
TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc..
•
The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer’s own risk.
•
•
The products described in this document are subject to the foreign exchange and foreign trade laws.
TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced
and sold, under any law and regulations.
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2003-10-30A