NSC MM74HC4511 Bcd-to-7 segment latch/decoder/driver Datasheet

MM54HC4511/MM74HC4511
BCD-to-7 Segment Latch/Decoder/Driver
General Description
Features
This high speed latch/decoder/driver utilizes advanced silicon-gate CMOS technology. It has the high noise immunity
and low power consumption of standard CMOS integrated
circuits, as well as the ability to drive 10 LS-TTL loads. The
circuit provides the functions of a 4-bit storage latch, an
8421 BCD-to-seven segment decoder, and an output drive
capability. Lamp test (LT), blanking (Bl), and latch enable
(LE) inputs are used to test the display, to turn-off or pulse
modulate the brightness of the display, and to store a BCD
code, respectively. It can be used with seven-segment light
emitting diodes (LED), incandescent, fluorescent, gas discharge, or liquid crystal readouts either directly or indirectly.
Applications include instrument (e.g., counter, DVM, etc.)
display driver, computer/calculator display driver, cockpit
display driver, and various clock, watch, and timer uses.
The 54HC/74HC logic family is speed, function, and pinout
compatible with the standard 54LS/74LS logic family. All
inputs are protected from damage due to static discharge by
internal diode clamps to VCC and ground.
Y
Connection Diagram
Truth Table
Y
Y
Y
Y
Y
Y
Latch storage of input data
Blanking input
Lamp test input
Low power consumption characteristics of CMOS
devices
Wide operating voltage range: 2 to 6 volts
Low input current: 1 mA maximum
Low quiescent current: 80 mA maximum over full temperature range (74 Series)
Dual-In-Line Package
INPUTS
OUTPUTS
LE BI LT D C B A a b c d e f g DISPLAY
TL/F/5373 – 1
Order Number MM54HC4511 or MM74HC4511
x
x
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
x
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
x
x
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
x
x
x
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
x
x
x
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
x
x
x
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
x
H
L
H
L
H
H
L
H
L
H
H
H
L
L
L
L
L
L
H
L
H
H
H
H
H
L
L
H
H
H
L
L
L
L
L
L
H
L
H
H
L
H
H
H
H
H
H
H
L
L
L
L
L
L
H
L
H
L
H
H
L
H
H
L
H
L
L
L
L
L
L
L
*
H
L
H
L
H
L
L
L
H
L
H
L
L
L
L
L
L
L
H
L
H
L
L
L
H
H
H
L
H
H
L
L
L
L
L
L
H
L
L
L
H
H
H
H
H
L
H
H
L
L
L
L
L
L
8
0
1
2
3
4
5
6
7
8
9
*
x e Don’t care
* e Depends upon the BCD code applied during the 0 to 1 transition of LE.
C1995 National Semiconductor Corporation
TL/F/5373
RRD-B30M105/Printed in U. S. A.
MM54HC4511/MM74HC4511 BCD-to-7 Segment Latch/Decoder/Driver
January 1988
Absolute Maximum Ratings (Notes 1 and 2)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (VCC)
DC Input or Output Voltage
(VIN, VOUT)
b 0.5 to a 7.0V
Supply Voltage (VCC)
b 1.5 to VCC a 1.5V
DC Input Voltage (VIN)
b 0.5 to VCC a 0.5V
DC Output Voltage (VOUT)
g 20 mA
Clamp Diode Current (IIK, IOK)
g 25 mA
DC Output Current, per pin (IOUT)
g 50 mA
DC VCC or GND Current, per pin (ICC)
b 65§ C to a 150§ C
Storage Temperature Range (TSTG)
Power Dissipation (PD)
(Note 3)
600 mW
S.O. Package only
500 mW
Lead Temp. (TL) (Soldering 10 seconds)
260§ C
Operating Temp. Range (TA)
MM74HC
MM54HC
Min
2
Max
6
0
VCC
Units
V
V
b 40
b 55
a 85
a 125
§C
§C
1000
500
400
ns
ns
ns
Input Rise or Fall Times
VCC e 2.0V
(tr, tf)
VCC e 4.5V
VCC e 6.0V
DC Electrical Characteristics (Note 4)
Symbol
Parameter
Conditions
TA e 25§ C
VCC
74HC
TA eb40 to 85§ C
Typ
54HC
TA eb55 to 125§ C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage**
2.0V
4.5V
6.0V
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
V
V
VOH
Minimum High Level
Output Voltage
VIN e VIH or VIL
lIOUTl s20 mA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN e VIH or VIL
lIOUTl s4.0 mA
lIOUTl s5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN e VIH or VIL
lIOUTl s6.0 mA
lIOUTl s7.8 mA
VOL
Maximum Low Level
Output Voltage
VIN e VIH or VIL
lIOUTl s20 mA
IIN
Maximum Input
Current
VIN e VCC or GND
6.0V
g 0.1
g 1.0
g 1.0
mA
ICC
Maximum Quiescent
Supply Current
VIN e VCC or GND
IOUT e 0 mA
6.0V
8.0
80
160
mA
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: b 12 mW/§ C from 65§ C to 85§ C; ceramic ‘‘J’’ package: b 12 mW/§ C from 100§ C to 125§ C.
Note 4: For a power supply of 5V g 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case VIH and VIL occur at VCC e 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN,
ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
**VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY’89.
2
AC Electrical Characteristics VCC e 5V, TA e 25§ C, CL e 15 pF, tr e tf e 6 ns
Typ
Guaranteed
Limit
Units
Maximum Propagation
Delay from Inputs A thru D to any Output
60
120
ns
tPHL, tPLH
Maximum Propagation
Delay from BI to any Output
60
120
ns
tPHL, tPLH
Maximum Propagation
Delay from LT to any Output
60
120
ns
tS
Minimum Setup Time
Inputs A thru D to LE
10
20
ns
tH
Minimum Hold Time
Inputs A thru D to LE
b3
0
ns
tW
Minimum Pulse Width
for LE
16
ns
Symbol
Parameter
tPHL, tPLH
Conditions
AC Electrical Characteristics CL e 50 pF, tr e tf e 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
VCC
TA e 25§ C
Typ
74HC
TA eb40 to 85§ C
54HC
TA eb55 to 125§ C
Units
Guaranteed Limits
tPHL, tPLH
Maximum Propagation
Delay from Inputs
A thru D to any Output
LE e 0V
LT e VCC
BI e VCC
2.0V
4.5V
6.0V
300
60
51
600
120
102
756
151
129
894
179
152
ns
ns
ns
tPHL, tPLH
Maximum Propagation
Delay from BI to
any Output
LT e VCC
2.0V
4.5V
6.0V
300
60
51
600
120
102
756
151
129
894
179
152
ns
ns
ns
tPHL, tPLH
Maximum Propagation
Delay from LT to
any Output
BI e 0V
2.0V
4.5V
6.0V
300
60
51
600
120
102
756
151
129
894
179
152
ns
ns
ns
tS
Minimum Setup Time
Inputs A thru D to LE
2.0V
4.5V
6.0V
100
20
17
126
25
21
149
30
25
ns
ns
ns
tH
Minimum Hold Time
Inputs A thru D to LE
2.0V
4.5V
6.0V
0
0
0
0
0
0
0
0
0
ns
ns
ns
tW
Minimum Pulse Width
for LE
2.0V
4.5V
6.0V
80
16
14
100
20
17
120
24
20
ns
ns
ns
tr, tf
Maximum Input Rise and
Fall Time
2.0V
4.5V
6.0V
1000
500
400
1000
500
400
1000
500
400
ns
ns
ns
CPD
Power Dissipation
Capacitance (Note 5)
CIN
Maximum Input
Capacitance
pF
5
10
10
10
pF
Note 5: CPD determines the no load dynamic power consumption, PD e CPD VCC2 f a ICC VCC, and the no load dynamic current consumption, IS e CPD VCC f a ICC.
3
INPUTS
CONTROLS
A, B, C, D (Pins 7, 1, 2, 6)ÐBCD data inputs. A (pin 7) is the
least-significant data bit and D (pin 6) is the most significant
bit. Hexadecimal data A–F at these inputs will cause the
outputs to assume a logic low, offering an alternate method
of blanking the display.
BI (Pin 4)ÐActive-low display blanking input. A logic low on
this input will cause all outputs to be held at a logic low,
thereby blanking the display. LT is the only input that will
override the Bl input.
LT (Pin 3)ÐActive-low lamp test. A low logic level on this
input causes all outputs to assume a logic high. This input
allows the user to test all segments of a display, with a
single control input. This input is independent of all other
inputs.
LE (Pin 5)ÐLatch enable input. This input controls the 4-bit
transparent latch. A logic high on this input latches the data
present at the A, B, C and D inputs; a logic low allows the
data to be transmitted through the latch to the decoder.
OUTPUTS
a – gÐDecoded, buffered outputs. These outputs, unlike the
4511, have CMOS drivers, which will produce typical CMOS
output voltage levels.
Output Characteristics (VCC e 5V)
TL/F/5373 – 2
TL/F/5373 – 3
*The expected minimum curves are not guarantees, but are design aids.
Typical Applications
TL/F/5373 – 4
TL/F/5373 – 5
Typical Common Cathode LED Connection
Incandescent Bulb Driving Circuit
4
Logic Diagram
TL/F/5373 – 6
Display
TL/F/5373 – 7
Segment Identification
TL/F/5373 – 8
5
MM54HC4511/MM74HC4511 BCD-to-7 Segment Latch/Decoder/Driver
Physical Dimensions inches (millimeters)
Dual-In-Line Package
Order Number MM54HC4511J or MM74HC4511J
NS Package J16A
Dual-In-Line Package
Order Number MM74HC4511N
NS Package N16E
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