ON MC33272AP Single supply, high slew rate, low input offset voltage operational amplifier Datasheet

MC33272A, MC33274A,
NCV33274A
Single Supply,
High Slew Rate,
Low Input Offset Voltage
Operational Amplifiers
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MARKING
DIAGRAMS
The MC33272/74 series of monolithic operational amplifiers are
quality fabricated with innovative Bipolar design concepts. This dual
and quad operational amplifier series incorporates Bipolar inputs
along with a patented Zip−R−Trim element for input offset voltage
reduction. The MC33272/74 series of operational amplifiers exhibits
low input offset voltage and high gain bandwidth product.
Dual−doublet frequency compensation is used to increase the slew rate
while maintaining low input noise characteristics. Its all NPN output
stage exhibits no deadband crossover distortion, large output voltage
swing, and an excellent phase and gain margin. It also provides a low
open loop high frequency output impedance with symmetrical source
and sink AC frequency performance.
The MC33272/74 series is specified over −40° to +85°C and are
available in plastic DIP and SOIC surface mount packages.
DUAL
8
1
1
8
•
•
SOIC−8
D SUFFIX
CASE 751
8
1
33272
ALYWA
1
QUAD
Pb−Free Packages are Available
Input Offset Voltage Trimmed to 100 V (Typ)
Low Input Bias Current: 300 nA
Low Input Offset Current: 3.0 nA
High Input Resistance: 16 M
Low Noise: 18 nV/ √ Hz @ 1.0 kHz
High Gain Bandwidth Product: 24 MHz @ 100 kHz
High Slew Rate: 10 V/s
Power Bandwidth: 160 kHz
Excellent Frequency Stability
Unity Gain Stable: w/Capacitance Loads to 500 pF
Large Output Voltage Swing: +14.1 V/ −14.6 V
Low Total Harmonic Distortion: 0.003%
Power Supply Drain Current: 2.15 mA per Amplifier
Single or Split Supply Operation: +3.0 V to +36 V or
±1.5 V to ±18 V
ESD Diodes Provide Added Protection to the Inputs
NCV Prefix for Automotive and Other Applications Requiring Site
and Control Changes
MC33272AP
AWL
YYWW
PDIP−8
P SUFFIX
CASE 626
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
8
14
PDIP−14
P SUFFIX
CASE 646
MC33274AP
AWLYYWW
14
1
1
SOIC−14
D SUFFIX
CASE 751A
14
1
14
14
MC33274AD
AWLYWW
1
NCV33274A
AWLYWW
1
A
WL, L
YY, Y
WW, W
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
 Semiconductor Components Industries, LLC, 2004
December, 2004 − Rev. 7
1
Publication Order Number:
MC33272A/D
MC33272A, MC33274A, NCV33274A
PIN CONNECTIONS
DUAL
QUAD
CASE 626/751
CASE 646/751A
Output 1
2
Inputs 1
VEE
8
1
3
7
−
+
−
+
4
6
VCC
Output 2
Output 1
1
14
2
13
Inputs 1
Inputs 2
3
5
VCC
(Top View)
1
4
−
+
Inputs 4
12
4
11
5
10
Inputs 2
6
Output 2
−
+
+
−
2
3
7
+
−
Output 4
9
8
VEE
Inputs 3
Output 3
(Top View)
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VCC to VEE
+36
V
Input Differential Voltage Range
VIDR
Note 1
V
Input Voltage Range
VIR
Note 1
V
Output Short Circuit Duration (Note 2)
tSC
Indefinite
sec
Maximum Junction Temperature
TJ
+150
°C
Storage Temperature
Tstg
−60 to +150
°C
Supply Voltage
ESD Protection at Any Pin
Vesd
− Human Body Model
− Machine Model
Maximum Power Dissipation
Operating Temperature Range
MC33272A, MC33274A
NCV33274A
V
2000
200
PD
Note 2
mW
TA
−40 to +85
−40 to +125
°C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. Either or both input voltages should not exceed VCC or VEE.
2. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded (see Figure 2).
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2
MC33272A, MC33274A, NCV33274A
DC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, TA = 25°C, unless otherwise noted.)
Characteristics
Figure
Symbol
Input Offset Voltage (RS = 10 , VCM = 0 V, VO = 0 V)
(VCC = +15 V, VEE = −15 V)
TA = +25°C
TA = −40° to +85°C
TA = −40° to +125°C (NCV33274A)
(VCC = 5.0 V, VEE = 0)
TA = +25°C
3
|VIO|
Average Temperature Coefficient of Input Offset Voltage
RS = 10 , VCM = 0 V, VO = 0 V, TA = −40° to +125°C
3
Input Bias Current (VCM = 0 V, VO = 0 V)
TA = +25°C
TA = Tlow to Thigh
4, 5
Input Offset Current (VCM = 0 V, VO = 0 V)
TA = +25°C
TA = Tlow to Thigh
6
Large Signal Voltage Gain (VO = 0 V to 10 V, RL = 2.0 k)
TA = +25°C
TA = Tlow to Thigh
7
Max
Unit
mV
−
−
−
0.1
−
−
1.0
1.8
3.5
−
−
2.0
−
2.0
−
−
−
300
−
650
800
−
−
3.0
−
65
80
VIO/T
V/°C
IIB
nA
nA
VICR
V
VEE to (VCC −1.8)
AVOL
dB
90
86
Output Voltage Swing (VID = ±1.0 V)
(VCC = +15 V, VEE = −15 V)
RL = 2.0 k
RL = 2.0 k
RL = 10 k
RL = 10 k
(VCC = 5.0 V, VEE = 0 V)
RL = 2.0 k
RL = 2.0 k
100
−
−
−
8, 9, 12
V
VO +
VO −
VO +
VO −
10, 11
Common Mode Rejection (Vin = +13.2 V to −15 V)
Power Supply Rejection
VCC/VEE = +15 V/ −15 V, +5.0 V/ −15 V, +15 V/ −5.0 V
CMR
14, 15
PSR
16
Power Supply Current Per Amplifier (VO = 0 V)
(VCC = +15 V, VEE = −15 V)
TA = +25°C
TA = Tlow to Thigh
(VCC = 5.0 V, VEE = 0 V)
TA = +25°C
17
Thigh = +85°C
Thigh = +125°C
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3
VOL
VOH
13
Output Short Circuit Current (VID = 1.0 V, Output to Ground)
Source
Sink
Tlow = −40°C
Tlow = −40°C
Typ
|IIO|
Common Mode Input Voltage Range (VIO = 5.0 mV, VO = 0 V)
TA = +25°C
3. MC33272A, MC33274A
NCV33274A
Min
13.4
−
13.4
−
13.9
−13.9
14
−14.7
−
−13.5
−
−14.1
−
3.7
−
−
0.2
5.0
80
100
−
80
105
−
+25
−25
+37
−37
−
−
dB
dB
ISC
mA
ICC
mA
−
−
2.15
−
2.75
3.0
−
−
2.75
MC33272A, MC33274A, NCV33274A
AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = −15 V, TA = 25°C, unless otherwise noted.)
Characteristics
Figure
Symbol
Slew Rate
(Vin = −10 V to +10 V, RL = 2.0 k, CL = 100 pF, AV = +1.0 V)
18, 33
SR
Gain Bandwidth Product (f = 100 kHz)
AC Voltage Gain (RL = 2.0 k, VO = 0 V, f = 20 kHz)
Min
Typ
Max
Unit
V/s
8.0
10
−
19
GBW
17
24
−
MHz
20, 21, 22
AVO
−
65
−
dB
Unity Gain Bandwidth (Open Loop)
BW
−
5.5
−
MHz
Gain Margin (RL = 2.0 k, CL = 0 pF)
23, 24, 26
Am
−
12
−
dB
Phase Margin (RL = 2.0 k, CL = 0 pF)
23, 25, 26
m
−
55
−
Deg
27
CS
−
−120
−
dB
BWP
−
160
−
kHz
−
0.003
−
|ZO|
−
35
−
Differential Input Resistance (VCM = 0 V)
Rin
−
16
−
M
Differential Input Capacitance (VCM = 0 V)
Cin
−
3.0
−
pF
Channel Separation (f = 20 Hz to 20 kHz)
Power Bandwidth (VO = 20 Vpp, RL = 2.0 k, THD ≤ 1.0%)
Total Harmonic Distortion
(RL = 2.0 k, f = 20 Hz to 20 kHz, VO = 3.0 Vrms, AV = +1.0)
28
Open Loop Output Impedance (VO = 0 V, f = 6.0 MHz)
29
THD
%
Equivalent Input Noise Voltage (RS = 100 , f = 1.0 kHz)
30
en
−
18
−
nV/ √ Hz
Equivalent Input Noise Current (f = 1.0 kHz)
31
in
−
0.5
−
pA/ √ Hz
VCC
Vin
+
−
Vin
+
Sections
B
C
D
VO
+
VEE
Figure 1. Equivalent Circuit Schematic
(Each Amplifier)
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2400
5.0
V,
IO INPUT OFFSET VOLTAGE (mV)
P(MAX),
MAXIMUM POWER DISSIPATION (mW)
D
MC33272A, MC33274A, NCV33274A
2000
MC33272P & MC33274P
1600
MC33274D
1200
800
MC33272D
400
0
−60 −40 −20
0
20
40
60
1.0
2
50
75
100
125
600
I
IB, INPUT BIAS CURRENT (nA)
150
VCC = +15 V
VEE = −15 V
TA = 25°C
−12
−8.0
−4.0
0
4.0
8.0
12
500
VCC = +15 V
VEE = −15 V
VCM = 0 V
400
300
200
100
0
−55
16
−25
0
25
50
75
VCM, COMMON MODE VOLTAGE (V)
TA, AMBIENT TEMPERATURE (°C)
Figure 4. Input Bias Current versus
Common Mode Voltage
Figure 5. Input Bias Current
versus Temperature
VCC
VCC
VCC −0.5
VCC −1.0
VCC −1.5
VCC −2.0
VCC = +5.0 V to +18 V
VEE = −5.0 V to −18 V
VIO = 5.0 mV
VO = 0 V
VEE +1.0
VEE
−25
0
25
50
75
100
125
A,
VOL OPEN LOOP VOLTAGE GAIN (X 1.0 kV/V)
I
IB, INPUT BIAS CURRENT (nA)
V,
ICR INPUT COMMON MODE VOLTAGE RANGE (V)
25
Figure 3. Input Offset Voltage versus
Temperature for Typical Units
200
VEE
−55
0
Figure 2. Maximum Power Dissipation
versus Temperature
250
VEE +0.5
−25
TA, AMBIENT TEMPERATURE (°C)
300
0
−16
1. VIO > 0 @ 25°C
2. VIO = 0 @ 25°C
3. VIO < 0 @ 25°C
TA, AMBIENT TEMPERATURE (°C)
350
50
2
1
3
−3.0
−5.0
−55
80 100 120 140 160 180
3
1
−1.0
400
100
VCC = +15 V
VEE = −15 V
VCM = 0 V
3.0
100
125
100
125
180
160
140
120
100
−55
VCC = +15 V
VEE = −15 V
RL = 2.0 k
f = 10 Hz
VO = −10 V to +10 V
−25
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
TA, AMBIENT TEMPERATURE (°C)
Figure 6. Input Common Mode Voltage
Range versus Temperature
Figure 7. Open Loop Voltage Gain
versus Temperature
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V sat , OUTPUT SATURATION VOLTAGE (V)
MC33272A, MC33274A, NCV33274A
TA = 25°C
30
RL = 10 k
20
10
0
V sat , OUTPUT SATURATION VOLTAGE (V)
RL = 2.0 k
0
5.0
10
15
Source
VCC −1.0
TA = −55°C
TA = 125°C
VCC −2.0
TA = 25°C
VEE +2.0
Sink
VEE +1.0
TA = 125°C
TA = 25°C
TA = −55°C
VCC = +5.0 V to +18 V
VEE = −5.0 V to −18 V
VEE
20
0
5.0
10
15
20
VCC, VEE SUPPLY VOLTAGE (V)
IL, LOAD CURRENT (±mA)
Figure 8. Split Supply Output Voltage Swing
versus Supply Voltage
Figure 9. Split Supply Output Saturation
Voltage versus Load Current
VCC
TA = 125°C
VCC
VCC −4.0
VCC = +5.0 V to +18 V
RL to Gnd
VEE = Gnd
TA = 55°C
VCC −8.0
VCC −12
+0.2
TA = 125°C
TA = +25°C
TA = −55°C
+0.1
Gnd
0
100
1.0 k
10 k
100 k
TA = 55°C
8.0
TA = 25°C
4.0
TA = −55°C
TA = 125°C
VCC = +15 V
RL to VCC
VEE = Gnd
RFdbk = 100 k
0
10
100
1.0 k
10 k
100 k
Figure 11. Single Supply Output Saturation
Voltage versus Load Resistance to VCC
CMR, COMMON MODE REJECTION (dB)
VCC = +15 V
VEE = −15 V
RL = 2.0 k
AV = +1.0
THD = ≤1.0%
TA = 25°C
0
1.0 k
14.2
Figure 10. Single Supply Output Saturation
Voltage versus Load Resistance to Ground
16
4
TA = 25°C
RL, LOAD RESISTANCE TO VCC ()
20
8
TA = 125°C
14.6
RL , LOAD RESISTANCE TO GROUND (k)
24
12
15
1.0 M
28
VO, OUTPUT VOLTAGE (Vpp )
VCC
V sat , OUTPUT SATURATION VOLTAGE (V)
VO, OUTPUT VOLTAGE (Vpp )
40
120
100
TA = −55°C
TA = 125°C
80
60
VCC = +15 V
VEE = −15 V
VCM = 0 V
VCM = ±1.5 V
−
ADM
VCM
40
VO
+
20
CMR = 20Log
VCM
VO
X ADM
0
10 k
100 k
1.0 M
1 0M
10
100
1.0 k
10 k
100 k
f, FREQUENCY (Hz)
f, FREQUENCY (Hz)
Figure 12. Output Voltage versus Frequency
Figure 13. Common Mode Rejection
versus Frequency
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1.0 M
MC33272A, MC33274A, NCV33274A
100
80
TA = −55°C
60
VCC
−
ADM
+
40
VO
VEE
20
VO/ADM
VCC
+PSR = 20Log
|I|,
SC OUTPUT SHORT CIRCUIT CURRENT (mA)
0
−PSR, POWER SUPPLY REJECTION (dB)
VCC = +15 V
VEE = −15 V
VCC = ±1.5 V
TA = 125°C
10
100
1.0 k
10 k
100 k
VCC = ±1.5 V
VCC = +15 V
VEE = −15 V
100
TA = −55°C
80
60
VCC
−
ADM
+
40
VO
TA = 125°C
VEE
20
−PSR = 20Log
10
VO/ADM
VEE
100
1.0 k
10 k
100 k
1.0 M
f, FREQUENCY (Hz)
f, FREQUENCY (Hz)
Figure 14. Positive Power Supply Rejection
versus Frequency
Figure 15. Negative Power Supply Rejection
versus Frequency
11
60
VCC = +15 V
VEE = −15 V
VID = ±1.0 V
RL < 100 50
Sink
40
Source
Sink
30
Source
20
10
0
−55
−25
0
25
50
75
100
9.0
TA = +25°C
8.0
TA = −55°C
7.0
6.0
5.0
3.0
125
0
2.0
4.0
6.0
8.0
10
12
14
16
18
TA, AMBIENT TEMPERATURE (°C)
VCC, |VEE| , SUPPLY VOLTAGE (V)
Figure 17. Supply Current versus
Supply Voltage
GBW, GAIN BANDWIDTH PRODUCT (MHz)
−
Vin
+
VO
2.0k
100 pF
1.0
VCC = +15 V
VEE = −15 V
Vin = 20 V
0.95
0.9
0.85
−55
TA = +125°C
Figure 16. Output Short Circuit Current
versus Temperature
1.1
1.05
10
4.0
1.15
SR, SLEW RATE (NORMALIZED)
120
0
1 .0 M
I,
CC SUPPLY CURRENT (mA)
+PSR, POWER SUPPLY REJECTION (dB)
120
−25
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
100
125
50
VCC = +15 V
VEE = −15 V
f = 100 kHz
RL = 2.0 k
CL = 0 pF
40
30
20
10
0
−55
Figure 18. Normalized Slew Rate
versus Temperature
−25
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
100
Figure 19. Gain Bandwidth Product
versus Temperature
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20
125
100
20
100
120
140
Phase
5.0
160
0
180
−5.0
200
−15
VCC = +15 V
VEE = −15 V
RL = 2.0 k
TA = 25°C
220
240
260
−20
1.0 M
280
100 M
10 M
2B
240
10 M
100 M
Figure 21. Gain and Phase
versus Frequency
12
100
120
140
160
2A
0
180
VCC = +15 V
VEE = −15 V
−10 Vout = 0 V
TA = 25°C
1A − Phase (RL = 2.0 k)
−20 2A − Phase (RL = 2.0 k, CL = 300 pF)
1B − Gain (RL = 2.0 k)
2B − Gain (RL = 2.0 k, CL = 300 pF)
−30
3.0
4.0
6.0
8.0 10
200
1B
220
2B
240
260
280
20
0
Gain Margin
10
10
VCC = +15 V
VEE = −15 V
VO = 0 V
8.0
6.0
20
30
−
Vin
VO
+
2.0 k
4.0
CL
40
2.0
50
Phase Margin
0
1.0
30
10
100
1000
f, FREQUENCY (MHz)
CL, OUTPUT LOAD CAPACITANCE (pF)
Figure 22. Open Loop Voltage Gain and
Phase versus Frequency
Figure 23. Open Loop Gain Margin and Phase
Margin versus Output Load Capacitance
12
60
CL = 10 pF
10
8.0
CL = 100 pF
6.0
CL = 300 pF
CL = 500 pF
4.0
2.0
0
−55
220
Figure 20. Voltage Gain and Phase
versus Frequency
1A
200
1B
−10 1A − Phase V = 18 V, V = −18 V
CC
EE
−15 2A − Phase VCC = 1.5 V, VEE = −1.5 V
1B − Gain VCC = 18 V, VEE = −18 V
−20 2B − Gain V = 1.5 V, V = −1.5 V
CC
EE
−25
100 k
1.0 M
f, FREQUENCY (Hz)
10
180
2A
f, FREQUENCY (Hz)
20
140
160
0
φ m, PHASE MARGIN (DEGREES)
A,
m OPEN LOOP GAIN MARGIN (dB)
A,
VOL OPEN LOOP VOLTAGE GAIN (dB)
−25
100 k
5.0
120
1A
TA = 25°C
CL = 0 pF
10
−5.0
A,
m OPEN LOOP GAIN MARGIN (dB)
−10
15
φ EXCESS PHASE (DEGREES)
A V , VOLTAGE GAIN (dB)
10
80
VCC = +15 V
VEE = −15 V
−25
0
25
50
75
100
CL = 10 pF
50
CL = 100 pF
CL = 300 pF
40
30
CL = 500 pF
20
VCC = +15 V
VEE = −15 V
10
0
−55
125
φ m, PHASE MARGIN (DEGREES)
Gain
15
25
A V , VOLTAGE GAIN (dB)
20
80
φ, EXCESS PHASE (DEGREES)
25
−25
0
25
50
75
100
TA, AMBIENT TEMPERATURE (°C)
TA, AMBIENT TEMPERATURE (°C)
Figure 24. Open Loop Gain Margin
versus Temperature
Figure 25. Phase Margin versus Temperature
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φ, PHASE (DEGREES)
MC33272A, MC33274A, NCV33274A
125
MC33272A, MC33274A, NCV33274A
40
VCC = +15 V
VEE = −15 V
RT = R1+R2
VO = 0 V
TA = 25°C
3.0
0
Vin
−
+
R2
10
10
VO
100
0
10 k
1.0 k
e,
nV/ √ Hz )
n INPUT REFERRED NOISE VOLTAGE (
1.0 k
10 k
100 k
1.0 M
50
AV = +1000
AV = +1.0
100
1.0 k
VCC = +15 V
VEE = −15 V
10 k
VCC = +15 V
VEE = −15 V
VO = 0 V
TA = 25°C
40
30
AV = 1000
20
AV = 100
10
AV = 1.0
AV = 10
0
10 k
100 k
100 k
1.0 M
10 M
f, FREQUENCY (Hz)
f, FREQUENCY (Hz)
Figure 28. Total Harmonic Distortion
versus Frequency
Figure 29. Output Impedance versus Frequency
50
+
40
−
30
VO
Input Noise Voltage
Test Circuit
20
VCC = +15 V
VEE = −15 V
TA = 25°C
10
110
Figure 27. Channel Separation
versus Frequency
VO = 2.0 Vpp
TA = 25°C
0
120
Figure 26. Phase Margin and Gain Margin
versus Differential Source Resistance
AV = +10
10
130
f, FREQUENCY (Hz)
0.1
0.001
10
140
RT, DIFFERENTIAL SOURCE RESISTANCE ()
AV = +100
0.01
Driver Channel
VCC = +15 V
VEE = −15 V
RL = 2.0 k
VOD = 20 Vpp
TA = 25°C
150
100
100
pA/ √ Hz )
i,
n INPUT REFERRED NOISE CURRENT (
THD, TOTAL HARMONIC DISTORTION (%)
20
R1
1.0
1.0
30
|Z|,
Ω
O OUTPUT IMPEDANCE ()
A,
m GAIN MARGIN (dB)
Phase Margin
9.0
CS, CHANNEL SEPERATION (dB)
50
12
6.0
160
60
Gain Margin
φ m , PHASE MARGIN (DEGREES)
15
100
1.0 k
f, FREQUENCY (Hz)
10 k
100 k
2.0
Input Noise Current Circuit
1.8
1.6
RS
1.4
+
−
1.2
(RS = 10 k
1.0
0.8
0.6
0.4
0.2
0
10
Figure 30. Input Referred Noise Voltage
versus Frequency
VCC = +15 V
VEE = −15 V
TA = 25°C
100
1.0 k
f, FREQUENCY (Hz)
10 k
Figure 31. Input Referred Noise Current
versus Frequency
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9
VO
100 k
MC33272A, MC33274A, NCV33274A
PERCENT OVERSHOOT (%)
60
VCC = +15 V
VEE = −15 V
RL = 2.0 k
TA = 25°C
50
40
30
20
10
0
10
100
CL, LOAD CAPACITANCE (pF)
1000
V,
O OUTPUT VOLTAGE (5.0 V/DIV)
V,
O OUTPUT VOLTAGE (5.0 V/DIV)
Figure 32. Percent Overshoot versus
Load Capacitance
VCC = +15 V
VEE = −15 V
AV = +1.0
RL = 2.0 k
CL = 100 pF
TA = 25°C
t, TIME (2.0 s/DIV)
VCC = +15 V
VEE = −15 V
AV = +1.0
RL = 2.0 k
TA = 25°C
CL = t, TIME (2.0 ns/DIV)
Figure 33. Non−inverting Amplifier Slew Rate
for the MC33274
Figure 34. Non−inverting Amplifier Overshoot
for the MC33274
VCC = +15 V
VEE = −15 V
AV = +1.0
RL = 2.0 k
CL = 300 pF
TA = 25°C
VCC = +15 V
VEE = −15 V
AV = +1.0
RL = 2.0 k
CL = 300 pF
TA = 25°C
V,
O OUTPUT VOLTAGE (5.0 V/DIV)
V,
O OUTPUT VOLTAGE (50 mV/DIV)
CL = 100 pF
t, TIME (2.0 s/DIV)
t, TIME (1.0 s/DIV)
Figure 35. Small Signal Transient Response
for MC33274
Figure 36. Large Signal Transient Response
for MC33274
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10
MC33272A, MC33274A, NCV33274A
ORDERING INFORMATION
Package
Shipping†
SOIC−8
98 Units / Rail
MC33272ADG
SOIC−8
(Pb−Free)
98 Units / Rail
MC33272ADR2
SOIC−8
2500 Tape & Reel
SOIC−8
(Pb−Free)
2500 Tape & Reel
PDIP−8
50 Units / Rail
MC33272APG
PDIP−8
(Pb−Free)
50 Units / Rail
MC33274AD
SOIC−14
55 Units / Rail
MC33274AD
SOIC−14
55 Units / Rail
MC33274ADR2
SOIC−14
2500 Tape & Reel
MC33274ADR2G
SOIC−14
(Pb−Free)
2500 Tape & Reel
MC33274AP
PDIP−14
25 Units / Rail
NCV33274ADG*
SOIC−14
(Pb−Free)
2500 Tape & Reel
NCV33274ADR2*
SOIC−14
2500 Tape & Reel
Device
MC33272AD
MC33272ADR2G
MC33272AP
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV devices are automotive qualified.
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11
MC33272A, MC33274A, NCV33274A
PACKAGE DIMENSIONS
SOIC−8
D SUFFIX
CASE 751−07
ISSUE AD
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
−X−
A
8
5
S
B
1
0.25 (0.010)
M
Y
M
4
K
−Y−
G
C
N
X 45 DIM
A
B
C
D
G
H
J
K
M
N
S
SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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12
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0
8
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 8 0.010
0.020
0.228
0.244
MC33272A, MC33274A, NCV33274A
PACKAGE DIMENSIONS
PDIP−14
P SUFFIX
CASE 646−06
ISSUE M
14
8
1
7
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
A
F
DIM
A
B
C
D
F
G
H
J
K
L
M
N
L
N
C
−T−
SEATING
PLANE
J
K
H
D 14 PL
G
M
0.13 (0.005)
INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.290
0.310
−−−
10
0.015
0.039
MILLIMETERS
MIN
MAX
18.16
18.80
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.37
7.87
−−−
10
0.38
1.01
M
SOIC−14
D SUFFIX
CASE 751A−03
ISSUE G
−A−
14
8
−B−
P 7 PL
0.25 (0.010)
M
B
M
7
1
G
F
R X 45 C
−T−
SEATING
PLANE
D 14 PL
0.25 (0.010)
T B
J
M
K
M
S
A
S
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13
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0
7
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0
7
0.228 0.244
0.010 0.019
MC33272A, MC33274A, NCV33274A
PACKAGE DIMENSIONS
PDIP−8
P SUFFIX
CASE 626−05
ISSUE L
8
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5
−B−
1
4
F
−A−
NOTE 2
L
C
J
−T−
MILLIMETERS
MIN
MAX
9.40
10.16
6.10
6.60
3.94
4.45
0.38
0.51
1.02
1.78
2.54 BSC
0.76
1.27
0.20
0.30
2.92
3.43
7.62 BSC
−−−
10
0.76
1.01
INCHES
MIN
MAX
0.370
0.400
0.240
0.260
0.155
0.175
0.015
0.020
0.040
0.070
0.100 BSC
0.030
0.050
0.008
0.012
0.115
0.135
0.300 BSC
−−−
10
0.030
0.040
N
SEATING
PLANE
D
H
DIM
A
B
C
D
F
G
H
J
K
L
M
N
M
K
G
0.13 (0.005)
M
T A
M
B
M
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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Phone: 81−3−5773−3850
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14
For additional information, please contact your
local Sales Representative.
MC33272A/D
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