Cypress CY62127DV20LL-55ZI 1m (64k x 16) static ram Datasheet

CY62127DV20
MoBL2®
ADVANCE
INFORMATION
1M (64K x 16) Static RAM
Features
• Very high speed: 55 ns
• Wide voltage range: 1.65V to 2.2V
• Ultra-low active power
— Typical active current: 0.5 mA @ f = 1 MHz
— Typical active current: 3.75 mA @ f = fMAX
• Ultra-low standby power
• Easy memory expansion with CE1, CE2, and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Packages offered in a 48-ball FBGA and a 44-pin TSOP
Type II
Functional Description[1]
The CY62127DV20 is a high-performance CMOS static RAM
organized as 64K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life (MoBL®) in portable
applications such as cellular telephones. The device also has
an automatic power-down feature that significantly reduces
power consumption by 99% when addresses are not toggling.
The device can be put into standby mode reducing power con-
Reading from the device is accomplished by taking Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH.
If Byte Low Enable (BLE) is low, then data from the memory
location specified by the address pins will appear on I/O0 to
I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back
of this data sheet for a complete description of read and write
modes.
64K × 16
RAM ARRAY
2048 x 32 x 16
SENSE AMPS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Writing to the device is accomplished by taking Chip Enable 1
(CE1) LOW and Chip Enable 2 (CE2) HIGH and Write Enable
(WE) input LOW. If Byte Low Enable (BLE) is LOW, then das
pins (A0 through A15). If Byte High Enable (BHE) is LOW, then
data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A15).
DATA IN DRIVERS
ROW DECODER
Logic Block Diagram
sumption by more than 99% when deselected Chip Enable 1
(CE1) HIGH or Chip Enable 2 (CE2) LOW or both BHE and
BLE are HIGH. The input/output pins (I/O0 through I/O15) are
placed in a high-impedance state when: deselected Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW, outputs are
disabled (OE HIGH), both Byte High Enable and Byte Low
Enable are disabled (BHE, BLE HIGH) or during a write operation (Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2)
HIGH and WE LOW).
I/O0 –I/O7
I/O8 –I/O15
BHE
WE
A15
A14
A13
A12
A11
COLUMN DECODER
CE2
CE1
OE
BLE
Power-down
Circuit
CE2
BHE
BLE
CE1
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05301 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised September 30, 2002
CY62127DV20
MoBL2®
ADVANCE
INFORMATION
Pin Configuration[2]
TSOP II (Forward)
Top View
A4
A3
A2
A1
A0
CE 1
I/O1
I/O2
I/O3
I/O4
VCC
VSS
I/O5
I/O6
I/O7
I/O8
WE
A15
A14
A13
A12
NU
1
44
2
3
43
42
4
41
40
39
38
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BH E
BLE
I/O16
I/O15
I/O14
I/O13
VSS
VCC
I/O12
I/O11
I/O10
I/O9
CE2
A8
A9
A10
A11
DNU
FBGA (Top View)
3
4
5
1
2
BLE
OE
A0
A1
A2
CE 2
A
I/O8
B HE
A3
A4
CE 1
I/O0
B
I/O9
I/O10
A5
A6
I/O1
I/O2
C
VS S
I/O11 DNU
A7
I/O3
VCC
D
VCC
I/O12 DNU DNU
I/O4
VS S
E
I/O14
I/O13
A14
A15
I/O5
I/O6
F
I/O15 DNU
A12
A13
WE
I/O7
G
A9
A10
A11
DNU
H
DNU
A8
6
Note:
2. DNU pins are to be connected to VSS or left open.
Document #: 38-05301 Rev. **
Page 2 of 12
CY62127DV20
MoBL2®
ADVANCE
INFORMATION
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage to Ground Potential
DC Input Voltage[3] ................................ −0.2V to VCC + 0.2V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current .................................................... > 200 mA
Operating Range
.........................................................−0.2V to VCCMAX + 0.2V
DC Voltage Applied to Outputs
Range
in High-Z State[3] ....................................−0.2V to VCC + 0.2V
Industrial
Ambient
Temperature (TA)
−40°C to
+85oC
VCC
1.65V to 2.2V
Product Portfolio
Power Dissipation
Operating, Icc (mA)
VCC Range(V)
Product
CY62127DV20L
Min.
Typ.[4]
Max.
1.65
1.8
2.2
CY62127DV20LL
f = 1 MHz
Speed
(ns)
Typ.[4]
Max.
55
0.5
1
55
f = fMAX
Typ.[4]
Max.
Standby, ISB2 (µA)
Typ.[4]
Max.
3.75
7.5
0.5
4
3.75
7.5
0.5
2.5
Notes:
3. VIL(min.) = −2.0V for pulse durations less than 20 ns.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C.
Document #: 38-05301 Rev. **
Page 3 of 12
CY62127DV20
MoBL2®
ADVANCE
INFORMATION
DC Electrical Characteristics (Over the Operating
Range)
CY62127DV20-55
Parameter
Description
Test Conditions
Min.
Typ.[4]
Max.
Unit
VOH
Output HIGH Voltage
IOH = −0.1 mA
VCC = 1.65V
VOL
Output LOW Voltage
IOL = 0.1 mA
VCC = 1.65V
0.2
V
VIH
Input HIGH Voltage
1.4
VCC +
0.2
V
VIL
Input LOW Voltage
–0.2
0.4
V
1.4
V
IIX
Input Leakage Current
GND < VI < VCC
–1
+1
µA
IOZ
Output Leakage Current
GND < VO < VCC, Output Disabled
–1
+1
µA
ICC
VCC Operating Supply Cur- f = fMAX = 1/tRC
rent
f = 1 MHz
3.75
7.5
mA
0.5
1
L
0.5
4
LL
0.5
2.5
L
0.5
4
LL
0.5
2.5
ISB1
ISB2
Vcc = 2.2V, IOUT
= 0mA, CMOS
level
Automatic CE Power-down
Current − CMOS Inputs
CE1 > VCC − 0.2V, CE2 < 0.2V,
VIN > VCC − 0.2V, VIN < 0.2V, f =
fMAX (Address and Data Only), f
= 0 (OE, WE, BHE and BLE)
Automatic CE Power-down
Current − CMOS Inputs
CE1 > VCC − 0.2V, CE2 < 0.2V,
VIN > VCC − 0.2V or VIN < 0.2V, f
= 0, VCC=2.2V
µA
µA
Capacitance [5]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz
VCC = VCC(typ)
Max.
Unit
6
pF
8
pF
Test Conditions
BGA
Unit
Still Air, soldered on a 3 x 4.5 inch, two-layer
printed circuit board
55
C/W
16
C/W
Thermal Resistance
Parameter
Description
θJA
Thermal Resistance (Junction to
Ambient)[5]
θJC
Thermal Resistance (Junction to
Case)[5]
Note:
5. Tested initially and after any design or proces changes that may affect these parameters.
Document #: 38-05301 Rev. **
Page 4 of 12
CY62127DV20
MoBL2®
ADVANCE
INFORMATION
AC Test Loads and Waveforms
R1
ALL INPUT PULSES
VCC
VCC Typ
UTPUT
10%
90%
10%
90%
GND
R2
CL = 30 pF
Rise Time:
1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
Fall Time:
1 V/ns
THÉVENIN EQUIVALENT
OUTPUT
RTH
V
Parameters
1.8V
UNIT
R1
1350 0
Ω
R2
1080 0
Ω
R TH
6000
Ω
VT H
0.80
V
Data Retention Characteristics
Parameter
Description
Conditions
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR[5]
Chip Deselect to Data Retention Time
tR[6]
Operation Recovery Time
Min.
Typ.[4]
Max.
Unit
2.2
V
L
1
µA
LL
TBD
1
VCC = 1V, CE1 > VCC − 0.2V, CE2 <
0.2V, VIN > VCC − 0.2V or VIN < 0.2V
0
ns
tRC
ns
Data Retention Waveform[7]
VCC
VCC(min.)
tCDR
DATA RETENTION MODE
VDR > 1.0V
VCC(min.)
tR
CE1 or
BHE . BLE
or
CE2
Notes:
6. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 µs or stable at VCC(min.) > 100 µs.
.
7. BHE BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both.
Document #: 38-05301 Rev. **
Page 5 of 12
CY62127DV20
MoBL2®
ADVANCE
INFORMATION
Switching Characteristics (Over the Operating Range)[8]
CY62127DV20-55
Parameter
Description
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE1 LOW or CE2 HIGH to Data Valid
55
ns
tDOE
OE LOW to Data Valid
25
ns
tLZOE
OE LOW to Low Z[9]
tHZOE
OE HIGH to High Z[9,11]
55
55
10
tLZCE
CE1 LOW or CE2 HIGH to Low Z
CE1 HIGH or CE2 LOW to High Z[9,11]
tPU
CE1 LOW or CE2 HIGH to Power-up
tPD
CE1 HIGH or CE2 LOW to Power-down
tDBE
BLE/BHE LOW to Data Valid
tLZBE[10]
BLE/BHE LOW to Low Z[9]
BLE/BHE HIGH to High-Z
ns
20
[9]
10
ns
ns
20
ns
55
ns
55
ns
0
ns
5
[9,11]
ns
ns
5
tHZCE
tHZBE
ns
ns
20
ns
Write Cycle[12]
tWC
Write Cycle Time
55
ns
tSCE
CE1 LOW or CE2 HIGH to Write End
45
ns
tAW
Address Set-up to Write End
45
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Set-up to Write Start
0
ns
tPWE
WE Pulse Width
40
ns
tBW
BLE/BHE LOW to Write End
45
ns
tSD
Data Set-up to Write End
25
ns
tHD
Data Hold from Write End
0
tHZWE
WE LOW to High Z[9,11]
tLZWE
WE HIGH to Low Z[9]
ns
20
10
ns
ns
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[13, 14]
tRC
ADDRESS
tAA
tOHA
ATA OUT
PREVIOUS DATA VALID
DATA VALID
Notes:
8. Test conditions assume signal transition time of 3 ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the
specified IOL
9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than t
10. If both byte enables are toggled together, this value is 10 ns.
11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
12. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL
Document #: 38-05301 Rev. **
Page 6 of 12
CY62127DV20
MoBL2®
ADVANCE
INFORMATION
Switching Waveforms (continued)
Read Cycle No. 2 (OE Controlled)[14, 15]
ADDRESS
t RC
CE 1
t PD
t HZCE
CE2
tACE
BHE /BLE
t DBE
t HZBE
t LZBE
OE
t HZOE
t DOE
DATA OUT
tLZOE
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA VALID
t LZCE
tPU
VCC
SUPPLY
CURRENT
50%
50%
I CC
I SB
Write Cycle No. 1 (WE Controlled) [12, 16, 17, 18]
t WC
ADDRESS
tSCE
CE1
CE2
tAW
t HA
t SA
t PWE
WE
tBW
BHE /BLE
OE
tSD
ATA I/O
t HD
DATAIN VALID
DON’T CARE
t HZOE
Notes:
13. Device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, CE2<Def>
14. WE is HIGH for Read cycle.
15. Address valid prior to or coincident with CE1, BHE, BLE transition LOW and CE2 transition HIGH.
Document #: 38-05301 Rev. **
Page 7 of 12
CY62127DV20
MoBL2®
ADVANCE
INFORMATION
Switching Waveforms (continued)
Write Cycle No. 2 (CE1 or CE2 Controlled) [12, 16, 17, 18]
t WC
ADDRESS
t SCE
CE 1
CE 2
t SA
t AW
t HA
t PWE
WE
t BW
BHE /BLE
OE
t SD
DATA I/O
t HD
DATA IN VALID
DON’T CARE
t HZOE
Write Cycle No. 3 (WE Controlled, OE LOW)[17, 18]
tWC
ADDRESS
tSCE
CE1
CE2
tAW
tSA
tHA
tPWE
WE
tSD
DATA I/O
tHD
DATAIN VALID
DON’T CARE
tHZWE
tLZWE
Notes:
16. Data I/O is high-impedance if OE = VIH.
17. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state.
18. During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
Document #: 38-05301 Rev. **
Page 8 of 12
CY62127DV20
MoBL2®
ADVANCE
INFORMATION
Switching Waveforms (continued)
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[17]
t WC
ADDRESS
CE 1
CE 2
t SCE
t AW
t HA
t BW
BHE /BLE
t SA
t PWE
WE
t SD
DATA I/O
t HD
DATAIN VALID
DON’T CARE
Truth Table
CE 1
CE 2
WE
OE
BHE
BLE
H
X
X
X
X
X
High Z
Deselect/Power-down
Standby(I SB )
X
L
X
X
X
X
High Z
Deselect/Power-down
Standby(I SB )
X
X
X
X
H
H
High Z
Deselect/Power-down
Standby(I SB )
L
H
H
L
L
L
Data Out(I/O0– I/O15)
Read
Active(I CC)
L
H
H
L
H
L
Data Out(I/O0– I/O7);
High Z (I/O8– I/O15)
Read
Active(I CC)
L
H
H
L
L
H
High Z (I/O0– I/O7);
Data Out(I/O8– I/O15)
Read
Active(I CC)
L
H
H
H
L
H
High Z
Output Disabled
Active(I CC)
L
H
H
H
H
L
High Z
Output Disabled
Active(I CC)
L
H
H
H
L
L
High Z
Output Disabled
Active(I CC)
L
H
L
X
L
L
Data In (I/O0– I/O15)
Write
Active(I CC)
L
H
L
X
H
L
Data In (I/O0– I/O7);
High Z (I/O8– I/O15)
Write
Active(I CC)
L
H
L
X
L
H
High Z (I/O0– I/O7);
Data In (I/O8– I/O15)
Write
Active(I CC)
Document #: 38-05301 Rev. **
Input / Outputs
Mode
Power
Page 9 of 12
CY62127DV20
MoBL2®
ADVANCE
INFORMATION
Ordering Information
Speed
(ns)
55
Ordering Code
Package
Name
Operating
Range
Package Type
CY62127DV20L-55BVI
BV48A
48-ball Fine Pitch BGA (6mm x 8mm x 1mm)
CY62127DV20LL-55BVI
BV48A
48-ball Fine Pitch BGA (6mm x 8mm x 1mm)
CY62127DV20L-55ZI
Z44
44-lead TSOP Type II
CY62127DV20LL-55ZI
Z44
44-lead TSOP Type II
Industrial
Package Diagrams
48-ball VFBGA (6 x 8 x 1 mm) BV48A
51-85150-*A
Document #: 38-05301 Rev. **
Page 10 of 12
ADVANCE
INFORMATION
CY62127DV20
MoBL2®
Package Diagrams (continued)
44-pin TSOP II Z44
51-85087-A
MoBL is a registered trademark, and MoBL2 and More Battery Life are trademarks of Cypress Semiconductor. All product and
company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05301 Rev. **
Page 11 of 12
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
ADVANCE
INFORMATION
CY62127DV20
MoBL2®
Document History Page
Document Title: CY62127DV20 MoBL2® 1M (64K x 16) Static RAM
Document Number: 38-05301
REV.
ECN NO.
Issue
Date
Orig. of
Change
**
116568
10/01/02
CDY
Document #: 38-05301 Rev. **
Description of Change
New Data Sheet
Page 12 of 12
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