Revised November 1999 74AC174 • 74ACT174 Hex D-Type Flip-Flop with Master Reset General Description Features The AC/ACT174 is a high-speed hex D-type flip-flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the LOW-to-HIGH clock transition. The device has a Master Reset to simultaneously clear all flipflops. ■ ICC reduced by 50% ■ Outputs source/sink 24 mA ■ ACT174 has TTL-compatible inputs Ordering Code: Order Number Package Number Package Description 74AC174SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body 74AC174SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74AC174PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide 74ACT174SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACT174SJ 74ACT174MTC MTC16 74ACT174PC N16E 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names Description D0–D5 Data Inputs CP Clock Pulse Input MR Master Reset Input Q0–Q5 Outputs FACT is a trademark of Fairchild Semiconductor Corporation. © 1999 Fairchild Semiconductor Corporation DS009935 www.fairchildsemi.com 74AC174 • 74ACT174 Hex D-Type Flip-Flop with Master Reset November 1988 74AC174 • 74ACT174 Functional Description Truth Table The AC/ACT174 consists of six edge-triggered D-type flipflops with individual D inputs and Q outputs. The Clock (CP) and Master Reset (MR) are common to all flip-flops. Each D input’s state is transferred to the corresponding flipflop’s output following the LOW-to-HIGH Clock (CP) transition. A LOW input to the Master Reset (MR) will force all outputs LOW independent of Clock or Data inputs. The AC/ ACT174 is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. Inputs Output MR CP L X L H H L L L X Q H H H X D H = HIGH Voltage Level L = LOW Voltage Level = LOW-to-HIGH Transition X = Immaterial Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Q Recommended Operating Conditions −0.5V to +7.0V Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V −20 mA VI = VCC + 0.5V +20 mA DC Input Voltage (VI) Supply Voltage (VCC) −0.5V to VCC + 0.5V V = VCC + 0.5V +20 mA 0V to VCC −40°C to +85°C Minimum Input Edge Rate (∆V/∆t) AC Devices DC Output Source VIN from 30% to 70% of VCC ±50 mA VCC @ 3.3V, 4.5V, 5.5V DC VCC or Ground Current 125 mV/ns Minimum Input Edge Rate (∆V/∆t) ±50 mA per Output Pin (ICC or IGND) Storage Temperature (TSTG) 0V to VCC Operating Temperature (TA) −0.5V to V CC + 0.5V or Sink Current (IO) 4.5V to 5.5V Output Voltage (VO) −20 mA DC Output Voltage (VO) 2.0V to 6.0V ACT Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V AC ACT Devices −65°C to +150°C VIN from 0.8V to 2.0V Junction Temperature (TJ) VCC @ 4.5V, 5.5V PDIP 140°C 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. DC Electrical Characteristics for AC Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL VOH TA = +25°C VCC (V) Typ 3.0 1.5 TA = −40°C to +85°C Guaranteed Limits 2.1 Units 4.5 2.25 3.15 3.15 5.5 2.75 3.85 3.85 Maximum LOW Level 3.0 1.5 0.9 0.9 Input Voltage 4.5 2.25 1.35 1.35 5.5 2.75 1.65 1.65 Minimum HIGH Level 3.0 2.99 2.9 2.9 Output Voltage 4.5 4.49 4.4 4.4 5.5 5.49 5.4 5.4 3.0 2.56 2.46 4.5 3.86 3.76 5.5 4.86 4.76 Conditions VOUT = 0.1V 2.1 V or VCC − 0.1V VOUT = 0.1V V or VCC − 0.1V V IOUT = −50 µA VIN = VIL or VIH VOL Maximum LOW Level 3.0 0.002 0.1 0.1 Output Voltage 4.5 0.001 0.1 0.1 5.5 0.001 0.1 0.1 3.0 0.36 0.44 4.5 0.36 0.44 5.5 0.36 0.44 IOH = −12 mA V IOH = −24 mA IOH = −24 mA (Note 2) V IOUT = 50 µA VIN = VIL or VIH IOL = 12 mA V IOL = 24 mA IOL = 24 mA (Note 2) VI = VCC IIN Maximum Input (Note 4) Leakage Current ±1.0 µA IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max IOHD Output Current (Note 3) 5.5 −75 mA VOHD = 3.85V Min ICC Maximum Quiescent (Note 4) Supply Current 40.0 µA ±0.1 5.5 5.5 4.0 or GND VIN = VCC or GND Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. 3 www.fairchildsemi.com 74AC174 • 74ACT174 Absolute Maximum Ratings(Note 1) 74AC174 • 74ACT174 DC Electrical Characteristics for ACT Symbol Parameter Minimum HIGH Level VIH VIL VOH TA = +25°C VCC (V) Typ 4.5 1.5 TA = −40°C to +85°C Guaranteed Limits 2.0 2.0 Input Voltage 5.5 1.5 2.0 2.0 Maximum LOW Level 4.5 1.5 0.8 0.8 Units V V Input Voltage 5.5 1.5 0.8 0.8 Minimum HIGH Level 4.5 4.49 4.4 4.4 Output Voltage 5.5 5.49 5.4 5.4 3.86 3.76 Conditions VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V V IOUT = −50 µA V IOH = −24 mA VIN = VIL or VIH 4.5 5.5 VOL IOH = −24 mA (Note 5) 4.86 4.76 Maximum LOW Level 4.5 0.001 0.1 0.1 Output Voltage 5.5 0.001 0.1 0.1 4.5 0.36 0.44 5.5 0.36 0.44 5.5 ±0.1 ±1.0 µA VI = VCC, GND VI = VCC − 2.1V V IOUT = 50 µA V IOL = 24 mA VIN = VIL or VIH IOL = 24 mA (Note 5) IIN Maximum Input ICCT Maximum 1.5 mA IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max IOHD Output Current (Note 6) 5.5 −75 mA VOHD = 3.85V Min ICC Maximum Quiescent 40.0 µA Leakage Current 5.5 ICC/Input Supply Current 0.6 5.5 4.0 VIN = VCC or GND Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time. AC Electrical Characteristics for AC Symbol fMAX tPLH tPHL tPHL Parameter VCC (V) (Note 7) TA = +25°C CL = 50 pF Min Typ TA = −40°C to +85°C CL = 50 pF Max Min Maximum Clock 3.3 90 100 70 Frequency 5.0 100 125 100 Propagation Delay 3.3 2.0 9.0 11.5 1.5 MHz 12.5 CP to Qn 5.0 1.5 6.0 8.5 1.0 9.5 Propagation Delay 3.3 2.0 8.5 11.0 1.5 12.0 CP to Qn 5.0 1.5 6.0 8.0 1.0 9.0 Propagation Delay 3.3 2.5 9.0 11.5 2.0 12.5 MR to Qn 5.0 1.5 7.0 9.0 1.5 10.5 Note 7: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V www.fairchildsemi.com 4 Units Max ns ns ns tS tH tW tREC TA = −40°C to +85°C CL = 50 pF Typ Setup Time, HIGH or LOW 3.3 2.5 6.5 7.0 Dn to CP 5.0 2.0 5.0 5.5 Hold Time, HIGH or LOW 3.3 1.0 3.0 3.0 Dn to CP 5.0 0.5 3.0 3.0 MR Pulse Width, LOW 3.3 1.0 5.5 7.0 5.0 1.0 5.0 5.0 3.3 1.0 5.5 7.0 5.0 1.0 5.0 5.0 Parameter CP Pulse Width tW TA = +25°C CL = 50 pF VCC (V) (Note 8) Symbol Units Guaranteed Minimum Recovery Time 3.3 0 2.5 2.5 MR to CP 5.0 0 2.0 2.0 ns ns ns ns ns Note 8: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V AC Electrical Characteristics for ACT Symbol fMAX Parameter Maximum Clock Frequency tPLH Propagation Delay CP to Qn tPHL Propagation Delay CP to Qn tPHL Propagation Delay MR to Qn TA = +25°C CL = 50 pF TA = −40°C to +85°C CL = 50 pF VCC (V) (Note 9) Min Typ 5.0 165 200 5.0 1.5 7.0 10.5 1.5 11.5 ns 5.0 1.5 7.0 10.5 1.5 11.5 ns 5.0 1.5 6.5 9.5 1.5 11.0 ns Max Min Units Max 140 MHz Note 9: Voltage Range 5.0 is 5.0V ± 0.5V AC Operating Requirements for ACT Symbol tS Parameter Setup Time, HIGH or LOW Dn to CP tH Hold Time, HIGH or LOW Dn to CP TA = +25°C CL = 50 pF TA = −40°C to +85°C CL = 50 pF VCC (V) (Note 10) Typ 5.0 0.5 1.5 1.5 ns 5.0 1.0 2.0 2.0 ns Units Guaranteed Minimum tW MR Pulse Width, LOW 5.0 1.5 3.0 3.5 ns tW CP Pulse Width, HIGH or LOW 5.0 1.5 3.0 3.5 ns trec Recovery Time 5.0 −1.0 0.5 0.5 ns MR to CP Note 10: Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Typ Units CIN Symbol Input Capacitance Parameter 4.5 pF VCC = OPEN CPD Power Dissipation Capacitance 85.0 pF VCC = 5.0V 5 Conditions www.fairchildsemi.com 74AC174 • 74ACT174 AC Operating Requirements for AC 74AC174 • 74ACT174 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body Package Number M16A www.fairchildsemi.com 6 74AC174 • 74ACT174 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D 7 www.fairchildsemi.com 74AC174 • 74ACT174 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 www.fairchildsemi.com 8 74AC174 • 74ACT174 Hex D-Type Flip-Flop with Master Reset Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 9 www.fairchildsemi.com