Rhombus FSIDM-35 Fsidm series fast / ttl buffered 5-tap delay module Datasheet

FSIDM Series FAST / TTL Buffered 5-Tap Delay Modules
8-Pin SIP Package
Electrical Specifications at 25OC
FAST/TTL Logic Buffered
5 Equal Delay Taps
Operating Temperature
Range 0OC to +70OC
8-Pin DIP Versions: see FAMDM Series
14-Pin DIP Versions: see FAIDM Series
Low Voltage CMOS Versions
refer to LVMDM / LVIDM Series
FSIDM 8-Pin SIP Schematic
1
Vcc
2
IN
3
4
5
Tap1 Tap2 Tap3
6
7
8
Tap4 Tap5 GND
Tap Delay Tolerances +/- 5% or 2ns (+/- 1ns <13ns)
FAST 5 Tap
8-Pin SIP P/N
Tap 1
Tap 2
Tap 3
Tap 4
Total - Tap 5
FSIDM-7
FSIDM-9
FSIDM-11
FSIDM-13
FSIDM-15
FSIDM-20
FSIDM-25
FSIDM-30
FSIDM-35
FSIDM-40
FSIDM-50
FSIDM-60
FSIDM-75
FSIDM-100
FSIDM-125
FSIDM-150
FSIDM-200
FSIDM-250
FSIDM-350
FSIDM-500
3.0
3.0
3.0
3.0
3.0
4.0
5.0
6.0
7.0
8.0
10.0
12.0
15.0
20.0
25.0
30.0
40.0
50.0
70.0
100.0
4.0
4.5
5.0
5.5
6.0
8.0
10.0
12.0
14.0
16.0
20.0
24.0
30.0
40.0
50.0
60.0
80.0
100.0
140.0
200.0
5.0
6.0
7.0
8.0
9.0
12.0
15.0
18.0
21.0
24.0
30.0
36.0
45.0
60.0
75.0
90.0
120.0
150.0
210.0
300.0
6.0
7.5
9.0
10.5
12.0
16.0
20.0
24.0
28.0
32.0
40.0
48.0
60.0
80.0
100.0
120.0
160.0
200.0
280.0
400.0
7 ± 1.0
9 ± 1.0
11 ± 1.0
13 ± 1.5
15 ± 1.5
20 ± 2.0
25 ± 2.0
30 ± 2.0
35 ± 2.0
40 ± 2.0
50 ± 2.5
60 ± 3.0
75 ± 3.75
100 ± 5.0
125 ± 6.25
150 ± 7.5
200 ± 10.0
250 ± 12.5
350 ± 17.5
500 ± 25.0
Tap-to-Tap
(ns)
∗∗ 1 ± 0.5
∗∗ 1.5 ± 0.5
∗∗ 2 ± 0.7
∗∗ 2.5 ± 1.0
3 ± 1.0
4 ± 1.5
5 ± 2.0
6 ± 2.0
7 ± 2.0
8 ± 2.0
10 ± 2.0
12 ± 2.0
15 ± 2.5
20 ± 3.0
25 ± 3.0
30 ± 3.0
40 ± 4.0
50 ± 5.0
70 ± 5.0
100 ± 10.0
** These part numbers do not have 5 equal taps. Tap-to-Tap Delays reference Tap 1.
TEST CONDITIONS -- FAST / TTL
OPERATING SPECIFICATIONS
VCC Supply Voltage ................................................ 5.00VDC
Input Pulse Voltage ................................................... 3.20V
Input Pulse Rise Time ....................................... 3.0 ns max.
Input Pulse Width / Period ........................... 1000 / 2000 ns
1. Measurements made at 25OC
2. Delay Times measured at 1.50V level of leading edge.
3. Rise Times measured from 0.75V to 2.40V.
4. 10pf probe and fixture load on output under test.
P/N Description
FSIDM - XXX X
74F Buffered 5 Tap Delay
Molded Package Series:
8-pin SIP: FSIDM
Total Delay in nanoseconds (ns)
Lead Style: Blank = Thru-hole
Examples: FSIDM-25 =
FSIDM-100 =
25ns (5ns per tap)
74F, 8-Pin SIP
100ns (20ns per tap)
74F, 8-Pin SIP
VCC Supply Voltage ................................... 5.00 ± 0.25 VDC
ICC Supply Current .................................... 48 mA Maximum
Logic “1” Input: VIH ........................ 2.00 V min., 5.50 V max.
IIH ............................... 20 µA max. @ 2.70V
Logic “0” Input: VIL .......................................... 0.80 V max.
IIL ............................................ -0.6 mA mA
VOH Logic “1” Voltage Out .................................. 2.40 V min.
VOL Logic “0” Voltage Out ............................... 0.50 V max.
PWI Input Pulse Width ............................. 40% of Delay min.
Operating Temperature Range ............................ 0O to 70OC
Storage Temperature Range ...................... -65O to +150OC
Dimensions in Inches (mm)
.810
(20.57)
MAX.
.180
(4.57)
MAX.
FSIDM Series
Molded 8-Pin SIP Package
.010
(0.25)
TYP.
.155 (3.94)
.145 (3.68)
Specifications subject to change without notice.
Rhombus
Industries Inc.
.120
(3.05)
MIN.
.280
(7.11)
MAX.
.015
(0.38)
TYP.
.020
(0.51)
TYP.
For other values & Custom Designs, contact factory.
.050
(1.27)
TYP.
.100
(2.54)
TYP.
FAMDM 9901
15801 Chemical Lane, Huntington Beach, CA 92649-1595
Phone: (714) 898-0960 • FAX: (714) 896-0971
www.rhombus-ind.com • email: [email protected]
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