TI BQ4011MA-100N 32kx8 nonvolatile sram Datasheet

bq4011/bq4011Y
32Kx8 Nonvolatile SRAM
Features
General Description
➤ Data retention in the absence of
power
The CMOS bq4011 is a nonvolatile
262,144-bit static RAM organized as
32,768 words by 8 bits. The integral
control circuitry and lithium energy
source provide reliable nonvolatility
coupled with the unlimited write
cycles of standard SRAM.
➤ Automatic write-protection
during power-up/power-down
cycles
➤ Industry-standard 28-pin 32K x
8 pinout
➤ Conventional SRAM operation;
unlimited write cycles
➤ 10-year minimum data retention
in absence of power
At this time the integral energy
source is switched on to sustain the
memory until after VCC returns valid.
The bq4011 uses an extremely low
standby current CMOS SRAM,
coupled with a small lithium coin cell
to provide nonvolatility without long
write-cycle times and the write-cycle
limitations associated with EEPROM.
The control circuitry constantly
monitors the single 5V supply for an
out-of-tolerance condition. When
VCC falls out of tolerance, the SRAM
is unconditionally write-protected to
prevent inadvertent write operation.
The bq4011 requires no external circuitry and is socket-compatible with
industry-standard SRAMs and most
EPROMs and EEPROMs.
Pin Names
Block Diagram
➤ Battery internally isolated until
power is applied
Pin Connections
A0 –A14
Address inputs
DQ0–DQ7
Data input/output
CE
Chip enable input
OE
Output enable input
WE
Write enable input
VCC
+5 volt supply input
VSS
Ground
Selection Guide
Part
Number
Maximum
Access
Time (ns)
Negative
Supply
Tolerance
Part
Number
bq4011Y-70
bq4011 -100
100
bq4011 -150
150
bq4011 -200
200
Maximum
Access
Time (ns)
Negative
Supply
Tolerance
70
-10%
-5%
bq4011Y -100
100
-10%
-5%
bq4011Y -150
150
-10%
-5%
bq4011Y -200
200
-10%
Aug. 1993 C
1
bq4011/bq4011Y
As VCC falls past VPFD and approaches 3V, the control
circuitry switches to the internal lithium backup supply,
which provides data retention until valid VCC is applied.
Functional Description
When power is valid, the bq4011 operates as a standard
CMOS SRAM. During power-down and power-up cycles,
the bq4011 acts as a nonvolatile memory, automatically
protecting and preserving the memory contents.
When VCC returns to a level above the internal backup
cell voltage, the supply is switched back to VCC. After
VCC ramps above the VPFD threshold, write-protection
continues for a time tCER (120ms maximum) to allow for
processor stabilization. Normal memory operation may
resume after this time.
Power-down/power-up control circuitry constantly
monitors the VCC supply for a power-fail-detect threshold
VPFD. The bq4011 monitors for VPFD = 4.62V typical for
use in systems with 5% supply tolerance. The bq4011Y
monitors for VPFD = 4.37V typical for use in systems with
10% supply tolerance.
The internal coin cell used by the bq4011 has an
extremely long shelf life and provides data retention for
more than 10 years in the absence of system power.
When VCC falls below the VPFD threshold, the SRAM
automatically write-protects the data. All outputs
become high impedance, and all inputs are treated as
“don’t care.” If a valid access is in process at the time of
power-fail detection, the memory cycle continues to completion. If the memory cycle fails to terminate within
time tWPT, write-protection takes place.
As shipped from Benchmarq, the integral lithium cell is
electrically isolated from the memory. (Self-discharge in
this condition is approximately 0.5% per year.) Following
the first application of VCC, this isolation is broken, and
the lithium backup cell provides data retention on subsequent power-downs.
Truth Table
CE
WE
OE
I/O Operation
Power
Not selected
Mode
H
X
X
High Z
Standby
Output disable
L
H
H
High Z
Active
Read
L
H
L
DOUT
Active
Write
L
L
X
DIN
Active
Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
VCC
DC voltage applied on VCC relative to VSS
-0.3 to 7.0
V
VT
DC voltage applied on any pin excluding VCC
relative to VSS
-0.3 to 7.0
V
TOPR
Operating temperature
TSTG
Storage temperature
TBIAS
Temperature under bias
TSOLDER
Soldering temperature
Note:
Conditions
VT ≤ VCC + 0.3
0 to +70
°C
Commercial
-40 to +85
°C
Industrial “N”
-40 to +70
°C
Commercial
-40 to +85
°C
Industrial “N”
-10 to +70
°C
Commercial
-40 to +85
°C
Industrial “N”
+260
°C
For 10 seconds
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation
should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to
conditions beyond the operational limits for extended periods of time may affect device reliability.
Aug. 1993 C
2
bq4011/bq4011Y
Recommended DC Operating Conditions (TA = TOPR)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
4.5
5.0
5.5
V
bq4011Y/bq4011Y-xxxN
4.75
5.0
5.5
V
bq4011
0
0
0
V
VCC
Supply voltage
VSS
Supply voltage
VIL
Input low voltage
-0.3
-
0.8
V
VIH
Input high voltage
2.2
-
VCC + 0.3
V
Note:
Typical values indicate operation at TA = 25°C.
DC Electrical Characteristics (TA = TOPR, VCCmin
Symbol
Notes
Parameter
≤ VCC ≤ VCCmax)
Minimum
Typical
Maximum
Unit
Conditions/Notes
ILI
Input leakage current
-
-
±1
µA
VIN = VSS to VCC
ILO
Output leakage current
-
-
±1
µA
CE = VIH or OE = VIH or
WE = VIL
VOH
Output high voltage
2.4
-
-
V
IOH = -1.0 mA
VOL
Output low voltage
-
-
0.4
V
IOL = 2.1 mA
ISB1
Standby supply current
-
4
7
mA
CE = VIH
ISB2
Standby supply current
-
2.5
4
mA
CE ≥ VCC - 0.2V,
0V ≤ VIN ≤ 0.2V,
or VIN ≥ VCC - 0.2V
ICC
Operating supply current
-
55
75
mA
Min. cycle, duty = 100%,
CE = VIL, II/O = 0mA
4.55
4.62
4.75
V
bq4011
VPFD
Power-fail-detect voltage
4.30
4.37
4.50
V
bq4011Y
VSO
Supply switch-over voltage
-
3
-
V
Note:
Typical values indicate operation at TA = 25°C, VCC = 5V.
Capacitance (TA = 25°C, F = 1MHz, VCC = 5.0V)
Minimum
Typical
Maximum
Unit
CI/O
Symbol
Input/output capacitance
-
-
10
pF
Output voltage = 0V
CIN
Input capacitance
-
-
10
pF
Input voltage = 0V
Note:
Parameter
These parameters are sampled and not 100% tested.
Aug. 1993 C
3
Conditions
bq4011/bq4011Y
AC Test Conditions
Parameter
Test Conditions
Input pulse levels
0V to 3.0V
Input rise and fall times
5 ns
Input and output timing reference levels
1.5 V (unless otherwise specified)
Output load (including scope and jig)
See Figures 1 and 2
Figure 1. Output Load A
Read Cycle (TA = TOPR, VCCmin
Figure 2. Output Load B
≤ VCC ≤ VCCmax)
-70/-70N
Symbol
Parameter
-100
-150/-150N
Min.
Max.
Min.
Max.
Min.
70
-
100
-
150
-
-200
Max. Min.
Max.
Unit
200
-
ns
Conditions
tRC
Read cycle time
tAA
Address access time
-
70
-
100
-
150
-
200
ns
Output load A
tACE
Chip enable access time
-
70
-
100
-
150
-
200
ns
Output load A
tOE
Output enable to
output valid
-
35
-
50
-
70
-
90
ns
Output load A
tCLZ
Chip enable to output
in low Z
5
-
5
-
10
-
10
-
ns
Output load B
tOLZ
Output enable to
output in low Z
5
-
5
-
5
-
5
-
ns
Output load B
tCHZ
Chip disable to output
in high Z
0
25
0
40
0
60
0
70
ns
Output load B
tOHZ
Output disable to
output in high Z
0
25
0
35
0
50
0
70
ns
Output load B
tOH
Output hold from
address change
10
-
10
-
10
-
10
-
ns
Output load A
Aug. 1993 C
4
bq4011/bq4011Y
Read Cycle No. 1 (Address Access) 1,2
Read Cycle No. 2 (CE Access) 1,3,4
Read Cycle No. 3 (OE Access) 1,5
Notes:
1. WE is held high for a read cycle.
2. Device is continuously selected: CE = OE = VIL.
3. Address is valid prior to or coincident with CE transition low.
4. OE = VIL.
5. Device is continuously selected: CE = VIL.
Aug. 1993 C
5
bq4011/bq4011Y
Write Cycle
(TA = TOPR, VCCmin ≤ VCC ≤ VCCmax)
-70/-70N
Symbol
Parameter
-100
-150/-150N
-200
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Units
Conditions/Notes
tWC
Write cycle time
70
-
100
-
150
-
200
-
ns
tCW
Chip enable to
end of write
55
-
90
-
100
-
150
-
ns
(1)
tAW
Address valid to
end of write
55
-
80
-
90
-
150
-
ns
(1)
tAS
Addr ess
time
0
-
0
-
0
-
0
-
ns
Measured from
address valid to
beginning of write. (2)
tWP
Write pulse
width
55
-
75
-
90
-
130
-
ns
Measured from
beginning of write to
end of write. (1)
tWR1
Write recovery
time (write
cycle 1)
5
-
5
-
5
-
5
-
ns
Measured from WE
going high to end of
write cycle. (3)
tWR2
Write recovery
time (write
cycle 2)
15
-
15
-
15
-
15
-
ns
Measured from CE
going high to end of
write cycle. (3)
tDW
Data valid to end
of write
30
-
40
-
50
-
70
-
ns
Measured from first
low-to-high transition
of either CE or WE.
tDH1
Data hold time
(write cycle 1)
0
-
0
-
0
-
0
-
ns
Measured from WE
going high to end of
write cycle. (4)
tDH2
Data hold time
(write cycle 2)
0
-
0
-
0
-
0
-
ns
Measured from CE
going high to end of
write cycle.(4)
tWZ
Write enabled to
output in high Z
0
25
0
35
0
50
0
70
ns
I/O pins are in output
state. (5)
tOW
Output active
from end of write
5
-
5
-
5
-
5
-
ns
I/O pins are in output
state. (5)
Notes:
setup
1. A write ends at the earlier transition of CE going high and WE going high.
2. A write occurs during the overlap of a low CE and a low WE. A write begins at the later transition
of CE going low and WE going low.
3. Either tWR1 or tWR2 must be met.
4. Either tDH1 or tDH2 must be met.
5. If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in
high-impedance state.
Aug. 1993 C
6
bq4011/bq4011Y
Write Cycle No. 1 (WE-Controlled) 1,2,3
Write Cycle No. 2 (CE-Controlled) 1,2,3,4,5
Notes:
1. CE or WE must be high during address transition.
2. Because I/O may be active (OE low) during this period, data input signals of opposite polarity to the
outputs must not be applied.
3. If OE is high, the I/O pins remain in a state of high impedance.
4. Either tWR1 or tWR2 must be met.
5. Either tDH1 or tDH2 must be met.
Aug. 1993 C
7
bq4011/bq4011Y
Power-Down/Power-Up Cycle (TA = TOPR)
Minimum
Typical
Maximum
Unit
tPF
Symbol
VCC slew, 4.75 to 4.25 V
300
-
-
µs
tFS
VCC slew, 4.25 to VSO
10
-
-
µs
tPU
VCC slew, VSO to VPFD (max.)
0
-
-
µs
tCER
Chip enable recovery time
40
80
120
ms
tDR
Data-retention time in
absence of VCC
10
-
-
years
TA = 25°C. (2)
tDR-N
Data-retention time in
absence of VCC
6
-
-
years
TA = 25°C (2); industrial
temperature range (-N) only.
tWPT
Write-protect time
40
100
150
µs
Delay after VCC slews down
past VPFD before SRAM is
write-protected.
Notes:
Parameter
Conditions
Time during which SRAM is
write-protected after VCC
passes VPFD on power-up.
1. Typical values indicate operation at TA = 25°C, VCC = 5V.
2. Battery is disconnected from circuit until after VCC is applied for the first time. tDR is the
accumulated time in absence of power beginning when power is first applied to the device.
Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode
may affect data integrity.
Power-Down/Power-Up Timing
Aug. 1993 C
8
bq4011/bq4011Y
Data Sheet Revision History
Change No.
Page No.
1
2, 3, 4, 6, 8, 9
2
1, 4, 6, 9
Notes:
Description
Added industrial temperature range for bq4011YMA-150N.
Added 70 ns speed grade for bq4011Y-70 and added industrial
temperature range for bq4011YMA-70N.
Change 1 = Sept 1992 B changes from Sept. 1990 A.
Change 2 = Aug. 1993 C changes from Sept. 1991 B.
28-Pin MA (A-type module)
28-Pin MA (A-Type Module)
Dimension
A
A1
Minimum
0.365
0.015
Maximum
0.375
-
B
C
D
0.017
0.008
1.470
0.023
0.013
1.500
E
e
G
0.710
0.590
0.090
0.740
0.630
0.110
L
0.120
S
0.075
All dimensions are in inches.
Aug. 1993 C
9
0.150
0.110
bq4011/bq4011Y
Ordering Information
bq4011
MA Temperature:
blank = Commercial (0 to +70°C)
N = Industrial (-40 to +85°C)*
Speed Options:
70 = 70 ns
100 = 100 ns
150 = 150 ns
200 = 200 ns
Package Option:
MA = A-type module
Supply Tolerance:
no mark = 5% negative supply tolerance
Y = 10% negative supply tolerance
Device:
bq4011
*Note:
32K x 8 NVSRAM
Only 10% supply (“Y”) version is available in industrial
temperature range; contact factory for speed grade availability.
Aug. 1993 C
10
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
BQ4011MA-100
ACTIVE
DIP MOD
ULE
MA
28
1
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
BQ4011MA-150
ACTIVE
DIP MOD
ULE
MA
28
1
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
BQ4011MA-200
ACTIVE
DIP MOD
ULE
MA
28
1
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
BQ4011YMA-100
ACTIVE
DIP MOD
ULE
MA
28
1
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
BQ4011YMA-150
ACTIVE
DIP MOD
ULE
MA
28
1
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
BQ4011YMA-150N
ACTIVE
DIP MOD
ULE
MA
28
1
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
BQ4011YMA-200
ACTIVE
DIP MOD
ULE
MA
28
1
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
BQ4011YMA-70
ACTIVE
DIP MOD
ULE
MA
28
1
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
BQ4011YMA-70N
ACTIVE
DIP MOD
ULE
MA
28
1
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDI061 – MAY 2001
MA (R-PDIP-T**)
PLASTIC DUAL-IN-LINE
28 PINS SHOWN
Millimeters
Inches
D
Dimension
Min.
Max.
Min.
Max.
A
0.365
0.375
9.27
A1
0.015
–
0.38
9.53
–
B
0.017
0.023
0.43
0.58
C
0.008
0.013
0.20
0.33
D/12 PIN
0.710
0.740
18.03
18.80
D/28 PIN
1.470
1.500
37.34
38.10
D/32 PIN
1.670
1.700
42.42
43.18
D/40 PIN
2.070
2.100
52.58
53.34
E
0.710
0.740
18.03
18.80
e
G
0.590
0.630
14.99
16.00
0.090
0.110
2.29
2.79
L
0.120
0.150
3.05
3.81
S/12 PIN
0.105
0.130
2.67
3.30
S
0.075
0.110
1.91
2.79
E
A
L
A1
C
B
e
S
G
4201975/A 03/01
NOTES: A. All linear dimensions are in inches (mm).
B. This drawing is subject to change without notice.
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
•
1
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Low Power Wireless www.ti.com/lpw
Mailing Address:
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright  2007, Texas Instruments Incorporated
Similar pages