Hynix GMS90L320Q Hynix semiconductor inc. 8-bit single-chip microcontroller Datasheet

HYNIX SEMICONDUCTOR INC.
8-BIT SINGLE-CHIP MICROCONTROLLERS
GMS90C320
User’s Manual (Ver. 1.2)
REVISION HISTORY
VERSION 1.2 (Oct. 2000) This book
Correct the pin number of 44-MQFP package type on page 6.
VERSION 1.1 (Oct. 1999) Before version
Version 1.2
Published by
MCU Application Team
Copy right 2001 Hynix semiconductor, All right reserved.
Additional information of this manual may be served by Hynix semiconductor offices in Korea or Distributors and Representatives listed at address directory.
Hynix semiconductor reserves the right to make changes to any information here in at any time without notice.
The information, diagrams and other data in this manual are correct and reliable; however, Hynix semiconductor is in no
way responsible for any violations of patents or other rights of the third party generated by the use of this manual.
GMS90C320
Device Naming Structure
H(G)MS90X320 XXXX
MCU Series
Hynix semiconductor MCU
Frequency
Blank: 24MHz
40:
40MHz
50:
50MHz
Package Type
Blank: 40PDIP
PL:
44PLCC
Q:
44MQFP
Enhanced ROM-less version
Operating Voltage
C: Normal voltage
L: Low voltage
OCT. 2000 Ver 1.2
GMS90C320
GMS90C320 ordering information
Operating
Voltage (V)
ROM size
(bytes)
RAM size
(bytes)
GMS90C320 40
GMS90C320 PL40
GMS90C320 Q40
ROM-less
256
40
40PDIP
44PLCC
44MQFP
GMS90C320 50
GMS90C320 PL50
GMS90C320 Q50
ROM-less
256
50
40PDIP
44PLCC
44MQFP
GMS90L320
GMS90L320 PL
GMS90L320 Q
ROM-less
256
24
40PDIP
44PLCC
44MQFP
Device Name
Operating max.
Frequency (MHz)
Package Type
4.25~5.5
2.7~5.5
OCT. 2000 Ver 1.2
GMS90C320
GMS90C320/L320
CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
ROM-less Version for 90C52
Operating Voltage (V)
Device Name
ROM
RAM
Operating
Frequency (MHz)
4.25~5.5
GMS90C320
ROM-less
256 × 8bit
40/50
2.7~5.5
GMS90L320
ROM-less
256 × 8bit
24
Features
• Fully compatible to standard MCS-51 microcontroller
• Versions for 40/50 MHz operating frequency
• Low voltage version for 24MHz operating frequency
• 256 bytes of on-chip data RAM
• 64K external program memory space
• 64K external data memory space
• Four 8-bit ports
• Three 16-bit Timers/Counters (Timer 2 with up/down counter feature)
• USART
• Six interrupt sources, two priority levels
• Power saving Idle and power down mode
• 2.7Volt low voltage version available
• P-DIP-40, P-LCC-44, P-MQFP-44 package
RAM
256 x 8
T0
CPU
T2
8-BIT
PORT0
I/O
PORT1
I/O
PORT2
I/O
PORT3
I/O
USART
T1
ROM-less
The GMS90C320 described in this document is compatible with the standard 80C32 can be used for all present standard
80C32 applications.
OCT. 2000 Ver 1.2
1
GMS90C320
44-PLCC Pin Configuration
(top view)
2
P1.4
P1.3
P1.2
P1.1/T2EX
P1.0/T2
N.C.
VCC
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
6
5
4
3
2
1
44
43
42
41
40
(P-LCC-44)
P1.5
7
39
P0.4/AD4
P1.6
8
38
P0.5/AD5
P2.6/A14
T1/P3.5
17
29
P2.5/A13
P2.4/A12
30
28
16
27
P2.7/A15
T0/P3.4
P2.3/A11
31
26
15
P2.2/A10
PSEN
INT1/P3.3
25
32
P2.1/A9
14
24
ALE
INT0/P3.2
P2.0/A8
33
23
13
N.C.
N.C.
TxD/P3.1
22
34
VS S
12
21
EA
N.C.
XTAL1
35
20
11
19
P0.7/AD7
RxD/P3.0
XTAL2
P0.6/AD6
36
RD/P3.7
37
18
9
10
WR/P3.6
P1.7
RESET
OCT. 2000 Ver 1.2
GMS90C320
40-PDIP Pin Configuration
(top view)
(P-DIP-40)
OCT. 2000 Ver 1.2
T2/P1.0
1
40
VCC
T2EX/P1.1
2
39
P0.0/AD0
P1.2
3
38
P0.1/AD1
P1.3
4
37
P0.2/AD2
P1.4
5
36
P0.3/AD3
P1.5
6
35
P0.4/AD4
P1.6
7
34
P0.5/AD5
P1.7
8
33
P0.6/AD6
RESET
9
32
P0.7/AD7
RxD/P3.0
10
31
EA
TxD/P3.1
11
30
ALE
INT0/P3.2
12
29
PSEN
INT1/P3.3
13
28
P2.7/A15
T0/P3.4
14
27
P2.6/A14
T1/P3.5
15
26
P2.5/A13
WR/P3.6
16
25
P2.4/A12
RD/P3.7
17
24
P2.3/A11
XTAL2
18
23
P2.2/A10
XTAL1
19
22
P2.1/A9
VS S
20
21
P2.0/A8
3
GMS90C320
44-PLCC Pin Configuration
(top view)
4
P1.4
P1.3
P1.2
P1.1/T2EX
P1.0/T2
N.C.
VCC
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
44
43
42
41
40
39
38
37
36
35
34
(P-MQFP-44)
P1.5
1
33
P0.4/AD4
P1.6
2
32
P0.5/AD5
P2.6/A14
23
P2.5/A13
P2.4/A12
24
11
22
10
T1/P3.5
21
T0/P3.4
P2.3/A11
P2.7/A15
20
25
P2.2/A10
9
19
INT1/P3.3
P2.1/A9
PSEN
18
INT0/P3.2
26
P2.0/A8
ALE
8
17
TxD/P3.1
27
N.C.
N.C.
7
16
28
VSS
6
15
EA
N.C.
XTAL1
29
14
5
13
P0.7/AD7
RxD/P3.0
XTAL2
P0.6/AD6
30
RD/P3.7
31
4
12
3
WR/P3.6
P1.7
RESET
OCT. 2000 Ver 1.2
GMS90C320
VC C
XTAL1
XTAL2
RESET
VS S
Port 0
8-bit Digital I/O
Port 1
8-bit Digital I/O
Port 2
8-bit Digital I/O
EA
ALE
PSEN
Port 3
8-bit Digital I/O
Logic Symbol
OCT. 2000 Ver 1.2
5
GMS90C320
Pin Definitions and functions
Pin Number
Symbol
Function
P-LCC-44
P-DIP-40
2-9
1-8
40-44,
1-3
2
3
1
2
40
41
11,1319
10-17
5, 713
11
10
5
P3.0/RxD
receiver data input (asynchronous) or data input
output (synchronous) of the serial interface 0
13
11
7
P3.1 / TxD
transmitter data output (asynchronous) or clock
output (synchronous) of the serial interface 0
14
12
8
P3.2 / INT0
interrupt 0 input / timer 0 gate control
15
13
9
P3.3 / INT1
interrupt 1 input / timer 1 gate control
16
14
10
P3.4 / T0
counter 0 input
17
15
11
P3.5 / T1
counter 1 input
18
16
12
P3.6 / WR
the write control signal latches the data byte from
port 0 into the external data memory
19
17
13
P3.7 / RD
the read control signal enables the external data
memory to port 0
XTAL2
20
18
14
O
XTAL2
Output of the inverting oscillator amplifier
XTAL1
21
19
15
I
XTAL1
Input to the inverting oscillator amplifier and input to the internal
clock generator circuits.
To drive the device from an external clock source, XTAL1 should
be driven, while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, since the
input to the internal clocking circuitry is divided down by a divideby-two flip-flop. Minimum and maximum high and low times as
well as rise fall times specified in the AC characteristics must be
observed.
P1.0-P1.7
P3.0-P3.7
6
Input/
Output
P-MQFP44
I/O
Port1
is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins
that have 1s written to them are pulled high by the internal pull-up
resistors and can be used as inputs. As inputs, port 1 pins that are
externally pulled low will source current because of the pulls-ups
(IIL , in the DC characteristics). Pins P1.0 and P1.1 also. Port 1
also receives the low-order address byte during program memory
verification. Port1 also serves alternate functions of Timer 2.
P1.0/T2: Timer/counter 2 external count input
P1.1/T2EX: Timer/counter 2 trigger input
I/O
Port 3
is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins
that have 1s written to them are pulled high by the internal pull-up
resistors, and in that state they can be used as inputs. As inputs,
port 3 pins being externally pulled low will source current (IIL , in
the DC characteristics) because of internal pulls-up resistors. Port
3 also serves the special features of the 80C51 family, as listed
below.
OCT. 2000 Ver 1.2
GMS90C320
Pin Number
Symbol
Input/
Output
Function
P-LCC-44
P-DIP-40
P-MQFP44
P2.0-P2.7
24-31
21-28
18-25
I/O
Port 2
Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2
pins that have 1s written to them are pulled high by the internal
pull-up resistors and can be used as inputs. As inputs, port 2 pins
that are externally pulled low will source current because of the
pulls-ups (IIL , in the DC characteristics). Port 2 emits the highorder address byte during fetches from external program memory
and during accesses to external data memory that use 16-bit
addresses (MOVX @DPTR). In this application it uses strong
internal pull-ups when emitting 1s. During accesses to external
data memory that use 8-bit addresses (MOVX @Ri), port 2 emits
the contents of the P2 special function register.
PSEN
32
29
26
O
The Program Store Enable
The read strobe to external program memory when the device is
executing code from the external program memory. PSEN is activated twice each machine cycle, except that two PSEN activation
are skipped during each access to external data memory. PSEN
is not activated during fetches from internal program memory.
RESET
10
9
4
I
RESET
A high level on this pin for two machine cycles while the oscillator
is running resets the device. An internal diffused resistor to VS S
permits power-on reset using only an external capacitor to VC C .
ALE
33
30
27
O
The Address Latch Enable
Output pulse for latching the low byte of the address during an
access to external memory. In normal operation, ALE is emitted
at a constant rate of 1/6 the oscillator frequency, and can be used
for external timing or clocking. Note that one ALE pulse is skipped
during each access to external data memory.
EA
35
31
29
I
External Access Enable
EA must be external held low to enable the device to fetch code
from external program memory locations 0000H to FFFFH . If EA is
held high, the device executes from internal program memory
unless the program counter contains an address greater than its
internal memory size.
P0.0-P0.7
43-36
39-32
37-30
I/O
Port 0
Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that
have 1s written to them float and can be used as high-impedance
inputs. Port 0 is also the multiplexed low-order address and data
bus during accesses to external program and data memory. In
this application it uses strong internal pull-ups when emitting 1s.
Port 0 also outputs the code bytes during program verification in
the GMS97C5x. External pull-up resistors are required during
program verification.
VS S
22
20
16
-
Circuit ground potential
VC C
44
40
38
-
Supply terminal for all operating modes
N.C.
1,12,
23,34
-
6,17,
28,39
-
No connection
OCT. 2000 Ver 1.2
7
GMS90C320
Function Description
The GMS90 series is fully compatible to the standard 8051 microcontroller family.
It is compatible with the standard 80C32. While maintaining all architectural and operational characteristics of the standard
80C32, the GMS90C320 incorporates some enhancements in the Timer 2 unit.
Figure 1 shows a block diagram of the GMS90C320
XTAL1
XTAL2
OSC & Timing
RESET
CPU
Timer 0
RAM
256 x 8
Port 0
Port 0
8-bit Digital I/O
Port 1
Port 1
8-bit Digital I/O
Port 2
Port 2
8-bit Digital I/O
Port 3
Port 3
8-bit Digital I/O
ALE
PSEN
EA
Timer 1
Timer 2
Interrupt Unit
Serial Channel
Figure 1 Block Diagram of the GMS90C320
8
OCT. 2000 Ver 1.2
GMS90C320
CPU
The GMS90C320 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD
arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. With a 12 MHz crystal, 58% of the instructions are
executed in 1.0µs.
Special Function Register PSW
MSB
LSB
Bit No.
7
6
5
4
3
2
1
0
Addr. D0H
CY
AC
F0
RS1
RS2
OV
F1
P
Bit
Function
CY
Carry Flag
AC
Auxiliary Carry Flag (for BCD operation)
F0
General Purpose Flag
RS1
0
0
1
1
RS0
0
1
0
1
PSW
Register Bank select control bits
Bank 0 selected, data address 00 H -07H
Bank 1 selected, data address 08 H -0FH
Bank 2 selected, data address 10 H -17H
Bank 3 selected, data address 18 H -1FH
OV
Overflow Flag
F1
General Purpose Flag
P
Parity Flag
Set/cleared by hardware each instruction cycle to indicate an odd/
even number of “one” bits in the accumulator, i.e. even parity.
Reset value of PSW is 00H .
OCT. 2000 Ver 1.2
9
GMS90C320
Special Function Registers
All registers, except the program counter and the four general purpose register banks, reside in the special function register
area.
The 27 special function registers (SFR) include pointers and registers that provide an interface between the CPU and the other
on-chip peripherals. There are also 128 directly addressable bits within the SFR area.
All SFRs are listed in Table 1, Table 2, and Table 3.
In Table 1 they are organized in numeric order of their addresses. In Table 2 they are organized in groups which refer to the
functional blocks of the GMS90C320. Table 3 illustrates the contents of the SFRs.
Table 1
Special Function Registers in Numeric Order of their Addresses
Address
Register
Contents after
Reset
Address
Register
Contents after
Reset
80H
81H
82H
83H
84H
85H
86H
87H
P01)
SP
DPL
DPH
reserved
reserved
reserved
PCON
FFH
07H
00H
00H
XXH 2)
XXH 2)
XXH 2)
0XXX0000B 2)
A0H
A1H
A2H
A3H
A4H
A5H
A6H
A7H
P21)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
FFH
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
88H
89H
8AH
8BH
8CH
8DH
8EH
8FH
TCON1)
TMOD
TL0
TL1
TH0
TH1
reserved
reserved
00H
00H
00H
00H
00H
00H
XXH 2)
XXH 2)
A8H
A9H
AAH
ABH
ACH
ADH
AEH
AFH
IE1)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
0X000000B 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
90H
91H
92H
93H
94H
95H
96H
97H
P11)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
FFH
00H
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
B0H
B1H
B2H
B3H
B4H
B5H
B6H
B7H
P31)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
FFH
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
98H
99H
9AH
9BH
9CH
9DH
9EH
9FH
SCON1)
SBUF
reserved
reserved
reserved
reserved
reserved
reserved
00H
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
B8H
B9H
BAH
BBH
BCH
BDH
BEH
BFH
IP1)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
XX000000B 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
1)
: Bit-addressable Special Function Register
2)
: X means that the value is indeterminate and the location is reserved
10
OCT. 2000 Ver 1.2
GMS90C320
Table 1
Special Function Registers in numeric order of their addresses (cont’d)
Address
Register
Contents after
Reset
Address
Register
Contents after
Reset
C0H
C1H
C2H
C3H
C4H
C5H
C6H
C7H
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
E0H
E1H
E2H
E3H
E4H
E5H
E6H
E7H
ACC1)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
00H
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
C8H
C9H
CAH
CBH
CCH
CDH
CEH
CFH
T2CON1)
T2MOD
RC2L
RC2H
TL2
TH2
reserved
reserved
00H
XXXXXXX0B 2)
00H
00H
00H
00H
XXH 2)
XXH 2)
E8H
E9H
EAH
EBH
ECH
EDH
EEH
EFH
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
D0H
D1H
D2H
D3H
D4H
D5H
D6H
D7H
PSW1)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
00H
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
F0H
F1H
F2H
F3H
F4H
F5H
F6H
F7H
B1)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
00H
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
D8H
D9H
DAH
DBH
DCH
DDH
DEH
DFH
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
F8H
F9H
FAH
FBH
FCH
FDH
FEH
FFH
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
1)
: Bit-addressable Special Function Register
2)
: X means that the value is indeterminate and the location is reserved
OCT. 2000 Ver 1.2
11
GMS90C320
Table 2
Special Function Registers - Functional Blocks
Content
after Reset
Block
Symbol
Name
Address
CPU
ACC
B
DPH
DPL
PSW
SP
Accumulator
B-Register
Data Pointer, High Byte
Data Pointer, Low Byte
Program Status Word Register
Stack Pointer
E0H 1)
F0H 1)
83H
82H
D0H 1)
81H
00H
00H
00H
00H
00H
07H
Interrupt System
IE
IP
Interrupt Enable Register
Interrupt Priority Register
A8H 1)
B8H 1)
0X000000B 2)
XX000000B 2)
Ports
P0
P1
P2
P3
Port 0
Port 1
Port 2
Port 3
80H 1)
90H 1)
A0H 1)
B0H 1)
FFH
FFH
FFH
FFH
Serial Channels
PCON
SBUF
SCON
Power Control Register
Serial Channel Buffer Register
Serial Channel 0 Control Register
87H
99H
98H 1)
0XXX0000B 2)
XXH 3)
00H
Timer 0 / Timer 1
TCON
TH0
TH1
TL0
TL1
TMOD
Timer 0/1 Control Register
Timer 0, High Byte
Timer 1, High Byte
Timer 0, Low Byte
Timer 1, Low Byte
Timer Mode Register
88H 1)
8CH
8DH
8AH
8BH
89H
00H
00H
00H
00H
00H
00H
Timer 2
T2CON
T2MOD
RC2H
RC2L
TH2
TL2
Timer 2 Control Register
Timer 2 Mode Register
Timer 2 Reload Capture Register, High Byte
Timer 2 Reload Capture Register, Low Byte
Timer 2, High Byte
Timer 2, Low Byte
C8H 1)
C9H
CBH
CAH
CDH
CCH
00H
XXXXXXX0B 2)
00H
00H
00H
00H
Power Saving
Modes
PCON
Power Control Register
87H
0XXX0000B 2)
1)
Bit-addressable Special Function Registers
2)
This special function register is listed repeatedly since some bits of it also belong to other functional blocks
3)
X means that the value is indeterminate and the location is reserved
12
OCT. 2000 Ver 1.2
GMS90C320
Table 3
Contents of SFRs, SFRs in Numeric Order
Address
Register
80H
P0
81H
SP
82H
DPL
83H
DPH
87H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PCON
SMOD
-
-
-
GF1
GF0
PDE
IDLE
88H
TCON
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
89H
TMOD
GATE
C/T
M1
M0
GATE
C/T
M1
M0
8AH
TL0
8BH
TL1
8CH
TH0
8DH
TH1
90H
P1
98H
SCON
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
99H
SBUF
A0H
P2
A8H
IE
EA
-
ET2
ES
ET1
EX1
ET0
EX0
B0H
P3
B8H
IP
-
-
PT2
PS
PT1
PX1
PT0
PX0
C8H
T2CON
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
C9H
T2MOD
-
-
-
-
-
-
-
DCEN
SFR bit and byte addressable
SFR not bit addressable
-
OCT. 2000 Ver 1.2
This bit location is reserved.
13
GMS90C320
Table 3
Contents of SFRs, SFRs in Numeric Order (cont’d)
Address
Register
CAH
RC2L
CBH
RC2H
CCH
TL2
CDH
TH2
D0H
PSW
E0H
ACC
F0H
B
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CY
AC
F0
RS1
RS0
OV
F1
P
SFR bit and byte addressable
SFR not bit addressable
-
14
This bit location is reserved.
OCT. 2000 Ver 1.2
GMS90C320
Timer / Counter 0 and 1
Timer/Counter 0 and 1 can be used in four operating modes as listed in Table 4:
Table 4
Timer/Counter 0 and 1 Operating Modes
TMOD
Mode
Input Clock
Description
GATE
C/T
M1
M0
Internal
X
X
0
0
OSC
-----------------12 × 32
X
X
0
1
OSC
--------------12
External
(Max.)
ƒ
0
8-bit timer/counter with a
divide-by-32 prescaler
1
16-bit timer/counter
2
8-bit timer/counter with 8-bit
autoreload
X
X
1
0
OSC
--------------12
3
Timer/counter 0 used as one
8-bit timer/counter and one 8bit timer
Timer 1 stops
X
X
1
1
OSC
--------------12
ƒ
OSC
-----------------24 × 32
ƒ
ƒ
OSC
--------------24
ƒ
ƒ
OSC
--------------24
ƒ
ƒ
OSC
--------------24
In the “timer” function (C/T = “0”) the register is incremented every machine cycle. Therefore the count rate is ƒOSC ⁄ 12 .
In the “counter” function the register is incremented in response to a 1-to-0 transition at its corresponding external input pin
(P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a falling edge the max. count rate is ƒOSC ⁄ 24 . External inputs
INT0 and INT1 (P3.2, P3.3) can be programmed to function as a gate to facilitate pulse width measurements.
Figure 2 illustrates the input clock logic.
fO SC
ƒOSC
÷12
⁄ 12
C/T
TMOD
0
Timer 0/1
Input Clock
P3.4/T0
P3.5/T1
max. fO SC /24
1
TR 0/1
Control
TCON
GATE
TMOD
P3.2/INT0
P3.3/INT1
Figure 2 Timer/Counter 0 and 1 Input Clock Logic
OCT. 2000 Ver 1.2
15
GMS90C320
Timer 2
Timer 2 is a 16-bit Timer/Counter with an up/down count feature. It can operate either as timer or as an event counter which
is selected by bit C/T2 (T2CON.1). It has three operating modes as shown in Table 5.
Table 5
Timer/Counter 2 Operating Modes
Input Clock
T2CON
Mode
16-bit Autoreload
16-bit
Capture
Baud Rate
Generator
off
1Note: ↓ =
16
TR2
T2MO
D
DECN
T2CON
EXEN
P1.1
T2EX
Remarks
RxCLK
or
TxCLK
RL2
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
X
X
X
↓
0
1
reload upon overflow
reload trigger (falling edge)
Down counting
Up counting
OSC
--------------12
0
1
1
X
0
X
0
1
1
X
1
↓
16-bit Timer/Counter (only
up-counting)
capture
TH1, TL2 → RC2H, RC2L
OSC
--------------12
1
X
1
X
0
X
1
X
1
X
1
↓
no overflow interrupt request
(TF2)
extra external interrupt
(“Timer 2”)
OSC
--------------12
X
X
0
X
X
X
CP/
Internal
Timer 2 stops
ƒ
ƒ
ƒ
-
External
(P1.0/T2)
ƒ
OSC
max. ---------------
24
ƒ
OSC
max. ---------------
24
ƒ
OSC
max. ---------------
24
-
falling edge
OCT. 2000 Ver 1.2
GMS90C320
Serial Interface (USART)
The serial port is full duplex and can operate in four modes (one synchronous mode, three asynchronous modes) as illustrated
in Table 6. The possible baud rates can be calculated using the formulas given in Table 7.
Table 6
USART Operating Modes
SCON
Mode
Baudrate
SM0
SM1
0
0
0
1
0
1
2
1
0
3
1
1
ƒ
OSC
--------------12
Timer 1/2 overflow rate
ƒ
ƒ
OSC
OSC
--------------- or --------------32
64
Timer 1/2 overflow rate
Description
Serial data enters and exits through RxD.
TxD outputs the shift clock.
8-bit are transmitted/received (LSB first)
8-bit UART
10 bits are transmitted (through TxD) or
received (RxD)
9-bit UART
11 bits are transmitted (through TxD) or
received (RxD)
9-bit UART
Like mode 2 except the variable baud rate
Table 7
Formulas for Calculating Baud rates
Baud Rate
derived from
Oscillator
Timer 1 (16-bit timer)
(8-bit timer with 8-bit autoreload)
Timer 2
OCT. 2000 Ver 1.2
Interface Mode
0
Baud rate
ƒ
OSC
--------------12
2
2 SMOD × ƒOSC
-----------------------------------------64
1, 3
2 SMOD × timer 1 overflow rate -------------------------------------------------------------------------------32
1, 3
2 SMOD × ƒOSC
---------------------------------------------------------32 × 12 × ( 256 – TH1 )
1, 3
ƒ
OSC
-----------------------------------------------------------------------------32 × [ 65536 – ( RC2H,RC2L ) ]
17
GMS90C320
Interrupt System
The GMS90C320 provides 6 interrupt sources with two priority levels. Figure 3 gives a general overview of the interrupt
sources and illustrates the request and control flags.
High Priority
Low Priority
Timer 0 Overflow
Timer 1 Overflow
Timer 2 Overflow
P1.1/
T2EX
TF0
TCON.5
ET1
IE.3
PT1
IP.3
ET2
IE.5
PT2
IP.5
ES
IE.4
PS
IP.4
EX0
IE.0
PX0
IP.0
TF2
T2CON.7
EXEN2
T2CON.3
RI
SCON.0
TI
SCON.1
P3.2/
PT0
IP.1
TF1
TCON.7
EXF2
T2CON.6
USART
ET0
IE.1
IE0
INT0
TCON.1
IT0
TCON.0
P3.3/
IE1
TCON.3
INT1
IT1
TCON.2
EX1
IE.2
EA
IE.7
PX1
IP.2
Figure 3
Interrupt Request Sources
18
OCT. 2000 Ver 1.2
GMS90C320
Table 8
Interrupt Sources and their Corresponding Interrupt Vectors
Source (Request Flags)
Vector
Vector Address
IE0
TF0
IE1
TF1
RI+TI
TF2+EXF2
External interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
Serial port interrupt
Timer 2 interrupt
0003H
000BH
0013H
001BH
0023H
002BH
A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low priority interrupt. A highpriority interrupt cannot be interrupted by any other interrupt source.
If two requests of different priority level are received simultaneously, the request of higher priority is serviced. If requests of
the same priority are received simultaneously, an internal polling sequence determines which request is serviced. Thus within
each priority level there is a second priority structure determined by the polling sequence as shown in Table 9.
Table 9
Interrupt Priority-Within-Level
Interrupt Source
IE0
TF0
IE1
TF1
RI+TI
TF2+EXF2
OCT. 2000 Ver 1.2
External interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
Serial port interrupt
Timer 2 interrupt
Priority
High
↓
Low
19
GMS90C320
Power Saving Modes
Two power down modes are available, the Idle Mode and Power Down Mode.
The bits PDE and IDLE of the register PCON select the Power Down mode or the Idle mode, respectively. If the Power Down
mode and the Idle mode are set at the same time, the Power Down mode takes precedence. Table 10 gives a general overview
of the power saving modes.
Table 10
Power Saving Modes Overview
Mode
Entering Instruction
Example
Leaving by
Remarks
Idle mode
ORL PCON,#01H
- enabled interrupt
- Hardware Reset
CPU is gated off
CPU status registers maintain
their data.
Peripherals are active
Power-Down
Mode
ORL PCON,#02H
Hardware Reset
Oscillator is stopped, contents of
on-chip RAM and SFR’s are maintained (leaving Power Down Mode
means redefinition of SFR contents).
In the Power Down mode of operation, VC C can be reduced to minimize power consumption. It must be ensured, however,
that VC C is not reduced before the Power Down mode is invoked, and that VC C is restored to its normal operating level, before
the Power Down mode is terminated. The reset signal that terminates the Power Down Mode also restarts the oscillator. The
reset should not be activated before VC C is restored to its normal operating level and must be held active long enough to allow
the oscillator to restart and stabilize (similar to power-on reset).
20
OCT. 2000 Ver 1.2
GMS90C320
Absolute Maximum Ratings
Ambient temperature under bias (TA ) .......................................................................................................-40 to + 85°C
Storage temperature (TS T )..........................................................................................................................-65 to + 150°C
Voltage on VC C pins with respect to ground (VS S ).....................................................................................-0.5 V to 6.5 V
Voltage on any pin with respect to ground (VSS ).......................................................................................-0.5 to VC C + 0.5 V
Input current on any pin during overload condition ..................................................................................-10 mA to + 10 mA
Absolute sum of all input currents during overload condition ..................................................................| 100 mA |
Power dissipation.......................................................................................................................................TBD
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of the device. This is
a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for longer periods may
affect device reliability. During overload conditions (VIN > VC C or VIN < VS S ) the Voltage on VC C pins with respect to ground (VS S )
must not exceed the values defined by the absolute maximum ratings.
OCT. 2000 Ver 1.2
21
GMS90C320
DC Characteristics
DC Characteristics for GMS90C320
VC C = 5V + 10%, -15%; VS S =0V; TA = 0°C to 70°C
Parameter
Symbol
Limit Values
Min.
Max.
Unit
Test Conditions
Input low voltage
(except EA, RESET)
VIL
-0.5
0.2VC C - 0.1
V
-
Input low voltage (EA)
VIL1
-0.5
0.2VC C - 0.3
V
-
Input low voltage (RESET)
VIL2
-0.5
0.2VC C + 0.1
V
-
Input high voltage (except
XTAL1, EA, RESET)
VIH
0.2VC C + 0.9
VC C + 0.5
V
-
Input high voltage to XTAL1
VIH 1
0.7VC C
VC C + 0.5
V
-
Input high voltage to EA,
RESET
VIH 2
0.6VC C
VC C + 0.5
V
-
Output low voltage
(ports 1, 2, 3)
VO L
-
0.3
0.45
1.0
V
IO L = 100µA
IO L = 1.6mA1)
IO L = 3.5mA
Output low voltage
(port 0, ALE, PSEN)
VO L1
-
0.3
0.45
1.0
V
IO L = 200µA
IO L = 3.2mA1)
IO L = 7.0mA
Output high voltage
(ports 1, 2, 3)
VO H
2.4
0.9VC C
-
V
IO H = -80µA
IO H = -10µA
Output high voltage
(port 0 in external bus mode,
ALE, PSEN)
VO H 1
2.4
0.9VC C
-
V
IO H = -800µA2)
IO H = -80µA2)
Logic 0 input current
(ports 1, 2, 3)
IIL
-10
-50
µA
VIN = 0.45V
Logical 1-to-0 transition current (ports 1, 2, 3)
IT L
-65
-650
µA
VIN = 2.0V
Input leakage current
(port 0, EA)
ILI
-
±1
µA
0.45 < VIN < VC C
Pin capacitance
CIO
-
10
pF
fC =1MHz, TA = 25°C
IC C
IC C
IC C
IC C
IC C
IC C
IC C
IC C
IP D
-
16
7.5
26
13.5
44
18
55
22.5
50
mA
mA
mA
mA
mA
mA
mA
mA
µA
VC C = 5V4)
VC C = 5V5)
VC C = 5V4)
VC C = 5V5)
VC C = 5V4)
VC C = 5V5)
VC C = 5V4)
VC C = 5V5)
VC C = 5.5V6)
Power supply current:
Active mode, 12MHz3)
Idle mode, 12MHz3)
Active mode, 24 MHz3)
Idle mode, 24MHz3)
Active mode, 40 MHz3)
Idle mode, 40 MHz3)
Active mode, 50 MHz3)
Idle mode, 50 MHz3)
Power Down Mode3)
22
OCT. 2000 Ver 1.2
GMS90C320
1)
Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VO L of ALE and port 3. The
noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions
during bus operation. In the worst case (capacitive loading: > 50pF at 3.3V, > 100pF at 5V), the noise pulse on ALE line may
exceed 0.8V. In such cases it may be desirable to qualify ALE with a schmitt-trigger, or use an address latch with a schmitttrigger strobe input.
2)
Capacitive loading on ports 0 and 2 may cause the VO H on ALE and PSEN to momentarily fall below the 0.9VC C specification
when the address lines are stabilizing.
3)
ICC m ax at other frequencies is given by:
active mode: IC C = 1.0 × ƒO SC + 3.16
idle mode: IC C = 0.37 × ƒO SC + 3.63
where ƒO SC is the oscillator frequency in MHz. ICC values are given in mA and measured at VC C = 5V.
4)
ICC (active mode) is measured with:
XTAL1 driven with tCLC H , tC HCL = 5ns, VIL = VSS + 0.5V, VIH = VCC - 0.5V; XTAL2 = N.C.;
EA = Port 0 = RESET = VCC ; all other pins are disconnected. I C C would be slightly higher if a crystal oscillator is used (appr.
1mA).
5)
ICC (Idle mode) is measured with all output pins disconnected and with all peripherals disabled;
XTAL1 driven with tCLC H , tC HCL = 5ns, VIL = VSS + 0.5V, VIH = VCC - 0.5V; XTAL2 = N.C.;
RESET = EA = VSS ; Port0 = VCC ; all other pins are disconnected;
6)
IPD (Power Down Mode) is measured under following conditions:
EA = Port 0 = VCC ; RESET = VSS ; XTAL2 = N.C.; XTAL1 = VS S ; all other pins are disconnected.
OCT. 2000 Ver 1.2
23
GMS90C320
DC Characteristics for GMS90L320
VC C = 3.3V + 0.3V, -0.6V; VS S =0V; TA = 0°C to 70°C
Limit Values
Parameter
Symbol
Min.
Max.
Unit
Test Conditions
Input low voltage
VIL
-0.5
0.8
V
-
Input high voltage
VIH
2.0
VC C + 0.5
V
-
Output low voltage
(ports 1, 2, 3)
VO L
-
0.45
0.30
V
IO L = 1.6mA1)
IO L = 100µA1)
Output low voltage
(port 0, ALE, PSEN)
VO L1
-
0.45
0.30
V
IO L = 3.2mA1)
IO L = 200µA1)
Output high voltage
(ports 1, 2, 3)
VO H
2.0
0.9VC C
-
V
IO H = -20µA
IO H = -10µA
Output high voltage
(port 0 in external bus mode, ALE,
PSEN)
VO H 1
2.0
0.9VC C
-
V
IO H = -800µA2)
IO H = -80µA2)
Logic 0 input current
(ports 1, 2, 3)
IIL
-1
-50
µA
VIN = 0.45V
Logical 1-to-0 transition current
(ports 1, 2, 3)
IT L
-25
-250
µA
VIN = 2.0V
Input leakage current
(port 0, EA)
ILI
-
±1
µA
0.45 < VIN < VC C
CIO
-
10
pF
fC = 1MHz
TA = 25°C
IC C
IC C
IC C
IC C
IP D
-
10
5.25
16
8.25
10
mA
mA
Pin capacitance
Power supply current:
Active mode, 16 MHz3)
Idle mode, 16MHz3)
Active mode, 24MHz3)
Idle mode, 24MHz3)
Power Down Mode3)
24
µA
VC C = 3.3V4)
VC C = 3.3V5)
VC C = 3.3V4)
VC C = 3.3V5)
VC C = 3.6V6)
OCT. 2000 Ver 1.2
GMS90C320
AC Characteristics
Explanation of the AC Symbols
Each timing symbol has 5 characters. The first character is always a ‘t’ (stand for time). The other characters, depending on
their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters
and what they stand for.
A: Address
C: Clock
D: Input Data
H: Logic level HIGH
I: Instruction (program memory contents)
L: Logic level LOW, or ALE
P: PSEN
Q: Output Data
R: RD signal
OCT. 2000 Ver 1.2
T: Time
V: Valid
W: WR signal
X: No longer a valid logic level
Z: Float
For example,
tA VLL = Time from Address Valid to ALE Low
tLLPL = Time from ALE Low to PSEN Low
25
GMS90C320
AC Characteristics for 12MHz version
VCC = 5V:
VC C = 5V + 10%, −15%; VS S = 0V; TA = 0°C to 70°C
(CL for port 0. ALE and PSEN outputs = 100pF; CL for all other outputs = 80pF)
VCC = 3.3V:
VC C = 3.3V + 0.3V, −0.6V; VS S = 0V; TA = 0°C to 70°C
(CL for port 0. ALE and PSEN outputs = 50pF; CL for all other outputs = 50pF)
Variable clock:
Vcc = 5V: 1/tC LC L = 3.5 MHz to 12 MHz
Vcc = 3.3V: 1/tC LC L = 1 MHz to 12 MHz
External Program Memory Characteristics
12 MHz Oscillator
Parameter
1)
Symbol
Variable Oscillator
1/tCLC L = 3.5 to 12MHz
Min.
Max.
Min.
Max.
Unit
ALE pulse width
tLH LL
127
-
2tC LC L -40
-
ns
Address setup to ALE
tA VLL
43
-
tC LC L -40
-
ns
Address hold after ALE
tLLA X
43
-
tC LC L -40
-
ns
ALE low to valid instruction in
tLLIV
-
233
-
4tC LC L -100
ns
ALE to PSEN
tLLP L
58
-
tC LC L -25
-
ns
PSEN pulse width
tP LP H
215
-
3tC LC L -35
-
ns
PSEN to valid instruction in
tP LIV
-
150
-
3tC LC L -100
ns
Input instruction hold after PSEN
tP XIX
0
-
0
-
ns
Input instruction float after PSEN
tP XIZ 1)
-
63
-
tC LC L -20
ns
Address valid after PSEN
tP XA V 1)
75
-
tC LC L -8
-
ns
Address to valid instruction in
tA VIV
-
302
-
5tC LC L -115
ns
Address float to PSEN
tA ZP L
-10
-
-10
-
ns
Interfacing the GMS90C320 to devices with float times up to 75 ns is permissible. This limited bus contention will not cause any damage
to port 0 Drivers.
26
OCT. 2000 Ver 1.2
GMS90C320
AC Characteristics for 12MHz version
External Data Memory Characteristics
12 MHz Oscillator
Parameter
Symbol
Variable Oscillator
1/tC LCL = 3.5 to 12MHz
Min.
Max.
Min.
Max.
Unit
RD pulse width
tR LR H
400
-
6tC LC L -100
-
ns
WR pulse width
tW LW H
400
-
6tC LC L -100
-
ns
Address hold after ALE
tLLA X 2
127
-
2tC LC L -40
-
ns
RD to valid data in
tR LD V
-
252
-
5tC LC L -165
ns
Data hold after RD
tR H D X
0
-
0
-
ns
Data float after RD
tR H D Z
-
97
-
2tC LC L -70
ns
ALE to valid data in
tLLD V
-
517
-
8tC LC L -150
ns
Address to valid data in
tA VD V
-
585
-
9tC LC L -165
ns
ALE to WR or RD
tLLW L
200
300
3tC LC L -50
3tC LC L +50
ns
Address valid to WR or RD
tA VW L
203
-
4tC LC L -130
-
ns
WR or RD high to ALE high
tW H LH
43
123
tC LC L -40
tC LC L +40
ns
Data valid to WR transition
tQ VW X
33
-
tC LC L -50
-
ns
Data setup before WR
tQ VW H
433
-
7tC LC L -150
-
ns
Data hold after WR
tW H Q X
33
-
tC LC L -50
-
ns
Address float after RD
tR LA Z
-
0
-
0
ns
Advance Information (12MHz)
External Clock Drive
Parameter
Variable Oscillator
(Freq. = 3.5 to 12MHz)
Symbol
Unit
Min.
Max.
Oscillator period (VC C =5V)
Oscillator period (VC C =3.3V)
tC LC L
tC LC L
83.3
83.3
285.7
1
ns
High time
tC H C X
20
tC LC L - tC LC X
ns
Low time
tC LC X
20
tC LC L - tC H C X
ns
Rise time
tC LC H
-
20
ns
Fall time
tC H C L
-
20
ns
OCT. 2000 Ver 1.2
27
GMS90C320
AC Characteristics for 16MHz version
VCC = 5V:
VC C = 5V + 10%, −15%; VS S = 0V; TA = 0°C to 70°C
(CL for port 0. ALE and PSEN outputs = 100pF; CL for all other outputs = 80pF)
VCC = 3.3V:
VC C = 3.3V + 0.3V, −0.6V; VS S = 0V; TA = 0°C to 70°C
(CL for port 0. ALE and PSEN outputs = 50pF; CL for all other outputs = 50pF)
Variable clock:
Vcc = 5V: 1/tC LC L = 3.5 MHz to 16 MHz
Vcc = 3.3V: 1/tC LC L = 1 MHz to 16 MHz
External Program Memory Characteristics
16 MHz Oscillator
Parameter
1)
Symbol
Variable Oscillator
1/tC LCL = 3.5 to 16MHz
Min.
Max.
Min.
Max.
Unit
ALE pulse width
tLH LL
85
-
2tC LC L -40
-
ns
Address setup to ALE
tA VLL
23
-
tC LC L -40
-
ns
Address hold after ALE
tLLA X
43
-
tC LC L -40
-
ns
ALE low to valid instruction in
tLLIV
-
150
-
4tC LC L -100
ns
ALE to PSEN
tLLP L
38
-
tC LC L -25
-
ns
PSEN pulse width
tP LP H
153
-
3tC LC L -35
-
ns
PSEN to valid instruction in
tP LIV
-
88
-
3tC LC L -100
ns
Input instruction hold after PSEN
tP XIX
0
-
0
-
ns
Input instruction float after PSEN
tP XIZ
-
43
-
tC LC L -20
ns
Address valid after PSEN
tP XA V 1)
55
-
tC LC L -8
-
ns
Address to valid instruction in
tA VIV
-
198
-
5tC LC L -115
ns
Address float to PSEN
tA ZP L
-10
-
-10
-
ns
1)
Interfacing the GMS90C320 to devices with float times up to 35 ns is permissible. This limited bus contention will not cause
any damage to port 0 Drivers.
28
OCT. 2000 Ver 1.2
GMS90C320
AC Characteristics for 16MHz
External Data Memory Characteristics
16 MHz Oscillator
Parameter
Symbol
Variable Oscillator
1/tC LCL = 3.5 to 16MHz
Min.
Max.
Min.
Max.
Unit
RD pulse width
tR LR H
275
-
6tC LC L -100
-
ns
WR pulse width
tW LW H
275
-
6tC LC L -100
-
ns
Address hold after ALE
tLLA X 2
127
-
2tC LC L -40
-
ns
RD to valid data in
tR LD V
-
183
-
5tC LC L -130
ns
Data hold after RD
tR H D X
0
-
0
-
ns
Data float after RD
tR H D Z
-
75
-
2tC LC L -50
ns
ALE to valid data in
tLLD V
-
350
-
8tC LC L -150
ns
Address to valid data in
tA VD V
-
398
-
9tC LC L -165
ns
ALE to WR or RD
tLLW L
138
238
3tC LC L −50
3tC LC L +50
ns
Address valid to WR or RD
tA VW L
120
-
4tC LC L -130
-
ns
WR or RD high to ALE high
tW H LH
28
97
tC LC L −35
tC LC L +35
ns
Data valid to WR transition
tQ VW X
13
-
tC LC L −50
-
ns
Data setup before WR
tQ VW H
288
-
7tC LC L -150
-
ns
Data hold after WR
tW H Q X
23
-
tC LC L −40
-
ns
Address float after RD
tR LA Z
-
0
-
0
ns
Advance Information (16MHz)
External Clock Drive
Parameter
Variable Oscillator
(Freq. = 3.5 to 16MHz)
Symbol
Unit
Min.
Max.
Oscillator period
tC LC L
62.5
285.7
ns
High time
tC H C X
17
tC LC L - tC LC X
ns
Low time
tC LC X
17
tC LC L - tC H C X
ns
Rise time
tC LC H
-
17
ns
Fall time
tC H C L
-
17
ns
OCT. 2000 Ver 1.2
29
GMS90C320
AC Characteristics for 24MHz version
VCC = 5V:
VC C = 5V + 10%, −15%; VS S = 0V; TA = 0°C to 70°C
(CL for port 0. ALE and PSEN outputs = 100pF; CL for all other outputs = 80pF)
VCC = 3.3V:
VC C = 3.3V + 0.3V, −0.6V; VS S = 0V; TA = 0°C to 70°C
(CL for port 0. ALE and PSEN outputs = 50pF; CL for all other outputs = 50pF)
Variable clock:
Vcc = 5V: 1/tC LC L = 3.5 MHz to 24 MHz
Vcc = 3.3V: 1/tC LC L = 1 MHz to 24 MHz
External Program Memory Characteristics
24 MHz Oscillator
Parameter
1)
Symbol
Variable Oscillator
1/tC LCL = 3.5 to 24MHz
Min.
Max.
Min.
Max.
Unit
ALE pulse width
tLH LL
43
-
2tC LC L -40
-
ns
Address setup to ALE
tA VLL
17
-
tC LC L -25
-
ns
Address hold after ALE
tLLA X
17
-
tC LC L -25
-
ns
ALE low to valid instruction in
tLLIV
-
80
-
4tC LC L -87
ns
ALE to PSEN
tLLP L
22
-
tC LC L -20
-
ns
PSEN pulse width
tP LP H
95
-
3tC LC L -30
-
ns
PSEN to valid instruction in
tP LIV
-
60
-
3tC LC L -65
ns
Input instruction hold after PSEN
tP XIX
0
-
0
-
ns
Input instruction float after PSEN
tP XIZ
-
32
-
tC LC L -10
ns
Address valid after PSEN
tP XA V 1)
37
-
tC LC L -5
-
ns
Address to valid instruction in
tA VIV
-
148
-
5tC LC L -60
ns
Address float to PSEN
tA ZP L
-10
-
-10
-
ns
1)
Interfacing the GMS90C320 to devices with float times up to 35 ns is permissible. This limited bus contention will not cause
any damage to port 0 Drivers.
30
OCT. 2000 Ver 1.2
GMS90C320
AC Characteristics for 24MHz
External Data Memory Characteristics
24 MHz Oscillator
Parameter
Symbol
Variable Oscillator
1/tC LCL = 3.5 to 24MHz
Min.
Max.
Min.
Max.
Unit
RD pulse width
tR LR H
180
-
6tC LC L -70
-
ns
WR pulse width
tW LW H
180
-
6tC LC L -70
-
ns
Address hold after ALE
tLLA X 2
56
-
2tC LC L -27
-
ns
RD to valid data in
tR LD V
-
118
-
5tC LC L -90
ns
Data hold after RD
tR H D X
0
-
0
-
ns
Data float after RD
tR H D Z
-
63
-
2tC LC L -20
ns
ALE to valid data in
tLLD V
-
200
-
8tC LC L -133
ns
Address to valid data in
tA VD V
-
220
-
9tC LC L -155
ns
ALE to WR or RD
tLLW L
75
175
3tC LC L -50
3tC LC L +50
ns
Address valid to WR or RD
tA VW L
67
-
4tC LC L -97
-
ns
WR or RD high to ALE high
tW H LH
17
67
tC LC L -25
tC LC L +25
ns
Data valid to WR transition
tQ VW X
5
-
tC LC L -37
-
ns
Data setup before WR
tQ VW H
170
-
7tC LC L -122
-
ns
Data hold after WR
tW H Q X
15
-
tC LC L -27
-
ns
Address float after RD
tR LA Z
-
0
-
0
ns
Advance Information (24MHz)
External Clock Drive
Table 11.
Parameter
Variable Oscillator
(Freq. = 3.5 to 24MHz)
Symbol
Unit
Min.
Max.
Oscillator period
tC LC L
41.7
285.7
ns
High time
tC H C X
12
tC LC L - tC LC X
ns
Low time
tC LC X
12
tC LC L - tC H C X
ns
Rise time
tC LC H
-
12
ns
Fall time
tC H C L
-
12
ns
OCT. 2000 Ver 1.2
31
GMS90C320
AC Characteristics for 40MHz version
VC C = 5V + 10%, − 15%; VSS = 0V; TA = 0°C to 70°C
(CL for port 0. ALE and PSEN outputs = 100pF; CL for all other outputs = 80pF)
External Program Memory Characteristics
40 MHz Oscillator
Parameter
1)
Symbol
Variable Oscillator
1/tC LCL = 3.5 to 40MHz
Min.
Max.
Min.
Max.
Unit
ALE pulse width
tLH LL
35
-
2tC LC L −15
-
ns
Address setup to ALE
tA VLL
10
-
tC LC L −15
-
ns
Address hold after ALE
tLLA X
10
-
tC LC L −15
-
ns
ALE low to valid instruction in
tLLIV
-
55
-
4tC LC L −45
ns
ALE to PSEN
tLLP L
10
-
tC LC L −15
-
ns
PSEN pulse width
tP LP H
60
-
3tC LC L −15
-
ns
PSEN to valid instruction in
tP LIV
-
25
-
3tC LC L −50
ns
Input instruction hold after PSEN
tP XIX
0
-
0
-
ns
Input instruction float after PSEN
tP XIZ
-
15
-
tC LC L −10
ns
Address valid after PSEN
tP XA V 1)
20
-
tC LC L −5
-
ns
Address to valid instruction in
tA VIV
-
65
-
5tC LC L −60
ns
Address float to PSEN
tA ZP L
-5
-
-5
-
ns
1)
Interfacing the GMS90C320 to devices with float times up to 20 ns is permissible. This limited bus contention will not cause any damage
to port 0 Drivers.
32
OCT. 2000 Ver 1.2
GMS90C320
AC Characteristics for 40MHz
External Data Memory Characteristics
at 40 MHz Clock
Parameter
Symbol
Variable Clock
1/tC LCL = 3.5 to 40MHz
Min.
Max.
Min.
Max.
Unit
RD pulse width
tR LR H
120
-
6tC LC L -30
-
ns
WR pulse width
tW LW H
120
-
6tC LC L -30
-
ns
Address hold after ALE
tLLA X 2
10
-
tC LC L -15
-
ns
RD to valid data in
tR LD V
-
75
-
5tC LC L -50
ns
Data hold after RD
tR H D X
0
-
0
-
ns
Data float after RD
tR H D Z
-
38
-
2tC LC L -12
ns
ALE to valid data in
tLLD V
-
150
-
8tC LC L -50
ns
Address to valid data in
tA VD V
-
150
-
9tC LC L -75
ns
ALE to WR or RD
tLLW L
60
90
3tC LC L -15
3tC LC L +15
ns
Address valid to WR or RD
tA VW L
70
-
4tC LC L -30
-
ns
WR or RD high to ALE high
tW H LH
10
40
tC LC L -15
tC LC L +15
ns
Data valid to WR transition
tQ VW X
5
-
tC LC L -20
-
ns
Data setup before WR
tQ VW H
125
-
7tC LC L -50
-
ns
Data hold after WR
tW H Q X
5
-
tC LC L -20
-
ns
Address float after RD
tR LA Z
-
0
-
0
ns
Advance Information (40MHz)
External Clock Drive
Parameter
Variable Oscillator
(Freq. = 3.5 to 40MHz)
Symbol
Unit
Min.
Max.
Oscillator period
tC LC L
25
285.7
ns
High time
tC H C X
10
tC LC L - tC LC X
ns
Low time
tC LC X
10
tC LC L - tC H C X
ns
Rise time
tC LC H
-
10
ns
Fall time
tC H C L
-
10
ns
OCT. 2000 Ver 1.2
33
GMS90C320
AC Characteristics for 50MHz version
VC C = 5V + 10%, − 15%; VSS = 0V; TA = 0°C to 70°C
(CL for port 0. ALE and PSEN outputs = 100pF; CL for all other outputs = 80pF)
Variable Clock : VC C = 5V, 1/ tC LC L = 3.5MHz to 50 MHz
External Program Memory Characteristics
50 MHz Oscillator
Parameter
1)
Symbol
Variable Oscillator
1/tC LCL = 3.5 to 50MHz
Min.
Max.
Min.
Max.
Unit
ALE pulse width
tLH LL
25
-
2tC LC L −15
-
ns
Address setup to ALE
tA VLL
5
-
tC LC L −15
-
ns
Address hold after ALE
tLLA X
5
-
tC LC L −15
-
ns
ALE low to valid instruction in
tLLIV
-
40
-
4tC LC L −40
ns
ALE to PSEN
tLLP L
5
-
tC LC L −15
-
ns
PSEN pulse width
tP LP H
45
-
3tC LC L −15
-
ns
PSEN to valid instruction in
tP LIV
-
20
-
3tC LC L −40
ns
Input instruction hold after PSEN
tP XIX
0
-
0
-
ns
Input instruction float after PSEN
tP XIZ 1)
-
10
-
tC LC L −10
ns
Address valid after PSEN
tP XA V 1)
15
-
tC LC L −5
-
ns
Address to valid instruction in
tA VIV
-
45
-
5tC LC L −55
ns
Address float to PSEN
tA ZP L
-5
-
-5
-
ns
Interfacing the GMS90C320 to devices with float times up to 20 ns is permissible. This limited bus contention will not cause any damage
to port 0 Drivers.
34
OCT. 2000 Ver 1.2
GMS90C320
AC Characteristics for 50MHz
External Data Memory Characteristics
at 50 MHz Clock
Parameter
Symbol
Variable Clock
1/tC LCL = 3.5 to 50MHz
Min.
Max.
Min.
Max.
Unit
RD pulse width
tR LR H
90
-
6tC LC L -30
-
ns
WR pulse width
tW LW H
90
-
6tC LC L -30
-
ns
Address hold after ALE
tLLA X 2
25
-
2tC LC L -15
-
ns
RD to valid data in
tR LD V
-
60
-
5tC LC L -40
ns
Data hold after RD
tR H D X
0
-
0
-
ns
Data float after RD
tR H D Z
-
28
-
2tC LC L -12
ns
ALE to valid data in
tLLD V
-
120
-
8tC LC L -40
ns
Address to valid data in
tA VD V
-
125
-
9tC LC L -55
ns
ALE to WR or RD
tLLW L
45
75
3tC LC L -15
3tC LC L +15
ns
Address valid to WR or RD
tA VW L
50
-
4tC LC L -30
-
ns
WR or RD high to ALE high
tW H LH
5
35
tC LC L -15
tC LC L +15
ns
Data valid to WR transition
tQ VW X
5
-
tC LC L -15
-
ns
Data setup before WR
tQ VW H
100
-
7tC LC L -40
-
ns
Data hold after WR
tW H Q X
5
-
tC LC L -15
-
ns
Address float after RD
tR LA Z
-
0
-
0
ns
Advance Information (50MHz)
External Clock Drive
Parameter
Variable Oscillator
(Freq. = 3.5 to 50MHz)
Symbol
Min.
Max.
Unit
Oscillator period
tC LC L
20
285.7
ns
High time
tC H C X
10
tC LC L - tC LC X
ns
Low time
tC LC X
10
tC LC L - tC H C X
ns
Rise time
tC LC H
-
10
ns
Fall time
tC H C L
-
10
ns
OCT. 2000 Ver 1.2
35
GMS90C320
tLHLL
ALE
tLLPL
tAV LL
tPLP H
tLLIV
tPLIV
PSEN
tP X AV
tP X IZ
tPX IX
tAZP L
tLLAX
PORT 0
INSTR.
IN
A0-A7
A0-A7
tAV IV
PORT 2
A8-A15
A8-A15
Figure 4 External Program Memory Read Cycle
36
OCT. 2000 Ver 1.2
GMS90C320
ALE
tLHLL
tW HLH
PSEN
tLLDV
tRLR H
tLLW L
RD
tAV LL
tRHDZ
tRLD V
tLLA X 2
tR HDX
tRLA Z
A0-A7 from
RI or DPL
PORT 0
DATA IN
A0-A7 from PCL
INSTR. IN
tA VW L
tA V DV
PORT 2
P2.0-P2.7 or A8-A15 from DPH
A8-A15 from PCH
Figure 5 External Data Memory Read Cycle
ALE
tLHLL
tW HLH
PSEN
tLLW L
tW LW H
WR
tA VLL
PORT 0
tQ V W X
tLLA X
A0-A7 from
RI or DPL
tW HQ X
tQ V W H
DATA OUT
A0-A7 from PCL
INSTR. IN
tA VW L
PORT 2
P2.0-P2.7 or A8-A15 from DPH
A8-A15 from PCH
Figure 6 External Data Memory Write Cycle
OCT. 2000 Ver 1.2
37
GMS90C320
VC C −0.5V
0.2VCC + 0.9
Test Points
0.2VC C − 0.1
0.45V
AC Inputs during testing are driven at VC C −0.5V for a logic ‘1’ and 0.45V for a logic ‘0’.
Timing measurements are made a VIH m in for a logic ‘1’ and VILm ax for a logic ‘0’.
Figure 7 AC Testing: Input, Output Waveforms
VLO A D + 0.1
VO H − 0.1
Timing Reference Points
VLO A D
VLO A D − 0.1
0.2VCC − 0.1
VO L + 0.1
For timing purposes a port pin is no longer floating when a 100mV change from load voltage
occurs and begins to float when a 100mV change from the loaded V O H / VO L level occurs.
IO L / IO H ≥ 20mA.
Figure 8 Float Waveforms
tCLC L
VCC −0.5V
0.7 VCC
0.2 VCC −0.1
0.45V
tCLC X
tCH CL
tC HCX
tCLCH
Figure 9 External Clock Cycle
38
OCT. 2000 Ver 1.2
GMS90C320
OSCILLATOR CIRCUIT
CRYSTAL OSCILLATOR MODE
C2
DRIVING FROM EXTERNAL SOURCE
N.C.
XTAL2
P-LCC-44/Pin 20
P-DIP-40/Pin 18
M-QFP-44/Pin 14
C1
XTAL1
P-LCC-44/Pin 21
P-DIP-40/Pin 19
M-QFP-44/Pin 15
External Oscillator
Signal
XTAL2
P-LCC-44/Pin 20
P-DIP-40/Pin 18
M-QFP-44/Pin 14
XTAL1
P-LCC-44/Pin 21
P-DIP-40/Pin 19
M-QFP-44/Pin 15
C1, C2 = 30pF ±10pF for Crystals
For Ceramic Resonators, contact resonator manufacturer.
Figure 10 Recommended Oscillator Circuits
Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each crystal and ceramic
resonator have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external
components.
OCT. 2000 Ver 1.2
39
GMS90C320
Plastic Package P-LCC-44
(Plastic Leaded Chip-Carrier)
44PLCC
UNIT: INCH
0.695
0.685
0.012
0.0075
0.021
0.013
0.032
0.026
0.656
0.650
0.695
0.685
0.050 BSC
0.630
0.590
min. 0.020
0.656
0.650
0.120
0.090
0.180
0.165
40
OCT. 2000 Ver 1.2
GMS90C320
Plastic Package P-DIP-40
(Plastic Dual in-Line Package)
40DIP
UNIT: INCH
0.065
0.045
0.100 BSC
0.140
0.120
0.022
0.015
OCT. 2000 Ver 1.2
0.600 BSC
min. 0.015
0.200 max.
2.075
2.045
0.550
0.530
0-15°
0.012
0.008
41
GMS90C320
Plastic Package P-MQFP-44
(Plastic Metric Quad Flat Package)
P-MQFP-44
13.45
12.95
UNIT: MM
0-7°
0.25
0.10
SEE DETAIL “A”
2.35 max.
0.45
0.30
0.80 BSC
0.23
0.13
2.10
1.95
10.10
9.90
13.45
12.95
10.10
9.90
1.03
0.73
1.60
REF
DETAIL “A”
42
OCT. 2000 Ver 1.2
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