SPANSION MBM29PL65LM10TN Flash memory cmos 64 m (4m x 16) bit mirrorflashtm Datasheet

FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20903-1E
FLASH MEMORY
CMOS
64 M (4M × 16) BIT
MirrorFlashTM
MBM29PL65LM-90/10
■ DESCRIPTION
MBM29PL65LM is of 67,108,864 bit capacity +3.0 V -only Flash memory enabling word write, both across- the
chip, comprehensive erase and by-the-unit, individual sector erase.
Its CMOS peripheral circuitry contributes to significant saving in power consumption even at high-speed standby mode operation.
MBM29PL65LM consists of 4M x 16 bit Word mode and erases 128 sectors at ever 32K word. Its package type
is 48-pin TSOP.
Embedded Program AlgorithmTM, when executed with erase or program command sequences, automatically times
the program pulse widths and verifies proper cell margin.
MBM29PL65LM, because of its capability in electrical data erase and program through write command, enables
to rewrite data within the internal system. It is a truly dependable device for vast application possibilities.
■ PRODUCT LINE UP
Part No.
MBM29PL65LM-90
MBM29PL65LM-10
VCC
3.0 V to 3.6 V
3.0 V to 3.6 V
VCCQ
VCC
VCC
Max Address Access Time
90 ns
100 ns
Max CE Access Time
90 ns
100 ns
Max Page Read Access Time
25 ns
30 ns
■ PACKAGE
48-pin plastic TSOP (1)
Marking Side
(FPT-48P-M19)
Notes:
Programming in byte mode ( × 8) is prohibited.
Programming to the address that already contains data is prohibited. (It is mandatory to erase data prior to overprogram on the same
address.
MBM29PL65LM-90/10
■ FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
MirrorFlash MemoryTM*1
0.23 µm Process Technology
4 M × 16 bit configuration
Single 3.0 V read, program and erase
Standard 48-pin TSOP (1) (Package suffix : TN)
Minimum 100,000 program/erase cycles
High performance Page mode (4 words)
Sector erase architecture (Sectors can be grouped in any given combination.)
32K word sectors
Any combination of sectors can be concurrently erased. Also supports full chip erase.
HiddenROM Region
Write Protect by WP pin
Embedded EraseTM*2 Algorithms
Embedded ProgramTM*2 Algorithms
Data Polling and Toggle Bit feature for detection of program or erase cycle completion
Automatic sleep mode
Erase Suspend/Resume
Low VCC write inhibit
Sector Group Protection
Extended Sector Group Protection
Fast Program
Temporary sector group unprotection
In accordance with CFI (Common Flash Memory Interface)
*1 : MirrorFlashTM is a trademark of Fujitsu Limited.
*2 : Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
2
MBM29PL65LM-90/10
■ PIN ASSIGNMENT
TSOP(1)
A15
A14
A13
A12
A11
A10
A9
A8
A21
A20
WE
RESET
ACC
WP
A19
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
(Marking Side)
A16
VCCQ
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
VSS
CE
A0
( FPT-48P-M19 )
■ PIN DESCRIPTIONS
Pin Name
A21 to A0
DQ15 to DQ0
Function
Address Inputs
Data Inputs/Outputs
CE
Chip Enable
OE
Output Enable
WE
Write Enable
WP
Hardware Write Protection
ACC
Hardware Program Acceleration
RESET
Hardware Reset Pin/Temporary Sector Group Unprotection
VCC
Device Power Supply
VCCQ
Output Power Supply
VSS
Device Ground
3
MBM29PL65LM-90/10
■ BLOCK DIAGRAM
DQ15 to DQ0
VCC
VSS
VCCQ
WE
RESET
Input/Output
Buffers
Erase Voltage
Generator
State
Control
WP
ACC
Command
Register
Program Voltage
Generator
Chip Enable
Output Enable
Logic
CE
OE
STB
Timer for
Program/Erase
Address
Latch
Y-Gating
X-Decoder
Cell Matrix
A1, A0
■ LOGIC SYMBOL
22
16
DQ 15 to DQ 0
CE
OE
WE
WP
ACC
RESET
4
Data Latch
Y-Decoder
A21 to A2
A21 to A0
STB
MBM29PL65LM-90/10
■ DEVICE BUS OPERATION
MBM29PL65LM User Bus Operations Table
CE OE WE A0
Operation
Standby
A1
A2
A3
A6
A9 DQ15 to DQ0 RESET WP
H
X
X
X
X
X
X
X
X
Hi-Z
H
X
L
L
H
L
L
L
L
L
VID
Code
H
X
Autoselect Device Code*1
L
L
H
H
L
L
L
L
VID
Code
H
X
Read
L
L
H
A0
A1
A2
A3
A6
A9
DOUT
H
X
Output Disable
L
H
H
X
X
X
X
X
X
Hi-Z
H
X
Write (Program/Erase)
L
H
L
A0
A1
A2
A3
A6
A9
*4
H
*5
Enable Sector Group Protection*2
L
H
L
L
H
L
L
L
X
*4
VID
H
Temporary Sector Group
Unprotection
X
X
X
X
X
X
X
X
X
*4
VID
H
Reset (Hardware)
X
X
X
X
X
X
X
X
X
Hi-Z
L
X
X
X
X
X
X
X
X
X
X
X
H
L
Autoselect Manufacture Code*
Sector Write Protection*
1
3
Legend : L = VIL, H = VIH, X = VIL or VIH. See DC Characteristics for voltage levels.
Hi-Z = High-Z, VID = 11.5 V to 12.5 V
*1 : Manufacturer and device codes may also be accessed via a command register write sequence.
See “MBM29PL65LM Standard Command Definitions”.
*2 : Refer to Sector Group Protection.
*3 : Protects the first 32K words sector (SA0).
*4 : DIN or DOUT as required by command sequence, data pulling, or sector protect algorithm
*5 : If WP/ACC = VIL, the first sector remains protected.
If WP/ACC = VIH, the first sector will be protected or unprotected as determined by the method specified in
“Sector Group Protection” in “■ FUNCTIONAL DESCRIPTION”.
5
MBM29PL65LM-90/10
MBM29PL65LM Standard Command Definitions Table*1
Bus
Write
Cycles
Req'd
Command
Sequence
First Bus Second Bus Third Bus
Write
Write
Write
Cycle
Cycle
Cycle
Fourth Bus
Read/Write
Cycle
Fifth Bus Sixth Bus
Write
Write
Cycle
Cycle
Addr Data Addr
Addr
Data
Addr Data Addr Data
—
—
Data
Addr Data
2
1
2
Reset*
3
555h
AAh 2AAh
55h
555h
F0h
Autoselect
3
555h
AAh 2AAh
55h
555h
Program
4
555h
AAh 2AAh
55h
Chip Erase
6
555h
AAh 2AAh
6
555h
AAh 2AAh
Program/Erase Suspend*
1
XXXh B0h
3
1
XXXh
30h
3
555h
AAh 2AAh
Fast Program*
2
XXXh A0h
Reset from Fast Mode*5
2
XXXh
Write to Buffer
20
555h
Program Buffer to Flash
(Confirm)
1
SA
Write to Buffer Abort Reset*6
3
555h
Extended Sector Group
Protection*7,*8
4
Query*9
Reset*
Sector Erase
XXXh
F0h
—
—
—
—
—
—
—
—
RA*
RD*
13
—
—
—
—
90h
00h*13
04h*13
—
—
—
—
555h
A0h
PA
PD
—
—
—
—
55h
555h
80h
555h
AAh
2AAh 55h 555h 10h
55h
555h
80h
555h
AAh
2AAh 55h
—
—
—
—
—
—
—
—
—
—
—
—
—
55h
555h
20h
—
PD
—
—
90h XXXh 00h*12
—
AAh 2AAh
55h
13
SA
30h
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SA
25h
SA
0Fh
PA
PD
WBL
PD
—
—
—
—
—
—
—
—
—
AAh 2AAh
55h
555h
F0h
—
—
—
—
—
—
XXXh
60h
SGA
60h
SGA
40h
SGA*13
SD*13
—
—
—
—
1
55h
98h
—
—
—
—
—
—
—
—
—
—
3
555h
AAh 2AAh
55h
555h
88h
—
—
—
—
—
—
HiddenROM Program * *
4
555h
AAh 2AAh
55h
555h
A0h
PA
PD
—
—
—
—
HiddenROM Exit*11
4
555h
AAh 2AAh
55h
555h
90h
XXXh
00h
—
—
—
—
3
Program/Erase Resume*
4
Set to Fast Mode*
4
10
HiddenROM Entry*
10, 11
29h
PA
—
= Address of the memory location to be read.
= Address of the memory location to be programmed Addresses are latched on the falling edge of the
write pulse.
SA
= Address of the sector to be erased. The combination of A21, A20, A19, A18, A17, A16 and A15
will uniquely select any sector. See “Sector Address Table”
SGA = Sector Group Address to be protected. See “Sector Group Address Table”. Specify SGA which
constitutes from A21 to A17 and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0).
RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the rising edge of write pulse.
WBL = Write Buffer Location
HRA = Address of the HiddenROM area ; 000000h to 00007Fh
RA
PA
*1 : The command combinations not described in “MBM29PL65LM Standard Command Definitions” are
illegal.
*2 : Both of these reset commands are equivalent except for "Write to Buffer Abort" reset.
*3 : The Erase Suspend and Erase Resume command are valid only during a sector erase operation.
*4 : The Set to Fast Mode command is required prior to the Fast Program command.
*5 : The Reset from Fast Mode command is required to return to the read mode when the device is in fast
mode.
6
MBM29PL65LM-90/10
*6 : Reset to the read mode. The Write to Buffer Abort Reset command is required after the Write to Buffer
operation was aborted.
*7 : This command is valid while RESET = VID.
*8 : Sector Group Address (SGA) with A6 = 0, A3 = 0, A2 = 0, A1 = 1, and A0 = 0
*9 : The valid address are A6 to A0.
*10 : The HiddenROM Entry command is required prior to the HiddenROM programming.
*11 : This command is valid during HiddenROM mode.
*12 : The data “F0h” is also acceptable.
*13 : Indicates read cycle.
Notes : • X = “H” or “L”
• Bus operations are defined in “User Bus Operations Table”.
Autoselect Codes Table
A21 to A17
A6
A3
A2
A1
A0
Code (HEX)
Manufacturer’s Code
X
VIL
VIL
VIL
VIL
VIL
04h
Device Code
X
VIL
VIL
VIL
VIL
VIH
227Eh
X
VIL
VIH
VIH
VIH
VIL
2213h
X
VIL
VIH
VIH
VIH
VIH
2201h
Sector Group Address
VIL
VIL
VIL
VIH
VIL
*2
Type
Extended Device Code*1
Sector Group Protection*3
*1 : At Word mode, a read cycle at address 01h outputs device code. When 227Eh is output, it indicates that reading
two additional codes, called Extended Device Codes, will be required. Therefore the system may continue
reading out these Extended Device Codes at the address of 0Eh, as well as at 0Fh.
*2 : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses.
*3 : Given CE = Fix, wait for one cycle after the rising edge of WE (the last write command), then indicate SGA as
(A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0).
7
MBM29PL65LM-90/10
Sector Address Table
Sector
A21
A20
A19
A18
A17
A16
A15
Sector Size
(Kwords)
Address Range
SA0
0
0
0
0
0
0
0
32
000000h to 007FFFh
SA1
0
0
0
0
0
0
1
32
008000h to 00FFFFh
SA2
0
0
0
0
0
1
0
32
010000h to 017FFFh
SA3
0
0
0
0
0
1
1
32
018000h to 01FFFFh
SA4
0
0
0
0
1
0
0
32
020000h to 027FFFh
SA5
0
0
0
0
1
0
1
32
028000h to 02FFFFh
SA6
0
0
0
0
1
1
0
32
030000h to 037FFFh
SA7
0
0
0
0
1
1
1
32
038000h to 03FFFFh
SA8
0
0
0
1
0
0
0
32
040000h to 047FFFh
SA9
0
0
0
1
0
0
1
32
048000h to 04FFFFh
SA10
0
0
0
1
0
1
0
32
050000h to 057FFFh
SA11
0
0
0
1
0
1
1
32
058000h to 05FFFFh
SA12
0
0
0
1
1
0
0
32
060000h to 067FFFh
SA13
0
0
0
1
1
0
1
32
068000h to 06FFFFh
SA14
0
0
0
1
1
1
0
32
070000h to 077FFFh
SA15
0
0
0
1
1
1
1
32
078000h to 07FFFFh
SA16
0
0
1
0
0
0
0
32
080000h to 087FFFh
SA17
0
0
1
0
0
0
1
32
088000h to 08FFFFh
SA18
0
0
1
0
0
1
0
32
090000h to 097FFFh
SA19
0
0
1
0
0
1
1
32
098000h to 09FFFFh
SA20
0
0
1
0
1
0
0
32
0A0000h to 0A7FFFh
SA21
0
0
1
0
1
0
1
32
0A8000h to 0AFFFFh
SA22
0
0
1
0
1
1
0
32
0B0000h to 0B7FFFh
SA23
0
0
1
0
1
1
1
32
0B8000h to 0BFFFFh
SA24
0
0
1
1
0
0
0
32
0C0000h to 0C7FFFh
SA25
0
0
1
1
0
0
1
32
0C8000h to 0CFFFFh
SA26
0
0
1
1
0
1
0
32
0D0000h to 0D7FFFh
SA27
0
0
1
1
0
1
1
32
0D8000h to 0DFFFFh
SA28
0
0
1
1
1
0
0
32
0E0000h to 0E7FFFh
SA29
0
0
1
1
1
0
1
32
0E8000h to 0EFFFFh
SA30
0
0
1
1
1
1
0
32
0F0000h to 0F7FFFh
(Continued)
8
MBM29PL65LM-90/10
Sector
A21
A20
A19
A18
A17
A16
A15
Sector Size
(Kwords)
Address Range
SA31
0
0
1
1
1
1
1
32
0F8000h to 0FFFFFh
SA32
0
1
0
0
0
0
0
32
100000h to 107FFFh
SA33
0
1
0
0
0
0
1
32
108000h to 10FFFFh
SA34
0
1
0
0
0
1
0
32
110000h to 117FFFh
SA35
0
1
0
0
0
1
1
32
118000h to 11FFFFh
SA36
0
1
0
0
1
0
0
32
120000h to 127FFFh
SA37
0
1
0
0
1
0
1
32
128000h to 12FFFFh
SA38
0
1
0
0
1
1
0
32
130000h to 137FFFh
SA39
0
1
0
0
1
1
1
32
138000h to 13FFFFh
SA40
0
1
0
1
0
0
0
32
140000h to 147FFFh
SA41
0
1
0
1
0
0
1
32
148000h to 14FFFFh
SA42
0
1
0
1
0
1
0
32
150000h to 157FFFh
SA43
0
1
0
1
0
1
1
32
158000h to 15FFFFh
SA44
0
1
0
1
1
0
0
32
160000h to 167FFFh
SA45
0
1
0
1
1
0
1
32
168000h to 16FFFFh
SA46
0
1
0
1
1
1
0
32
170000h to 177FFFh
SA47
0
1
0
1
1
1
1
32
178000h to 17FFFFh
SA48
0
1
1
0
0
0
0
32
180000h to 187FFFh
SA49
0
1
1
0
0
0
1
32
188000h to 18FFFFh
SA50
0
1
1
0
0
1
0
32
190000h to 197FFFh
SA51
0
1
1
0
0
1
1
32
198000h to 19FFFFh
SA52
0
1
1
0
1
0
0
32
1A0000h to 1A7FFFh
SA53
0
1
1
0
1
0
1
32
1A8000h to 1AFFFFh
SA54
0
1
1
0
1
1
0
32
1B0000h to 1B7FFFh
SA55
0
1
1
0
1
1
1
32
1B8000h to 1BFFFFh
SA56
0
1
1
1
0
0
0
32
1C0000h to 1C7FFFh
SA57
0
1
1
1
0
0
1
32
1C8000h to 1CFFFFh
SA58
0
1
1
1
0
1
0
32
1D0000h to 1D7FFFh
SA59
0
1
1
1
0
1
1
32
1D8000h to 1DFFFFh
SA60
0
1
1
1
1
0
0
32
1E0000h to 1E7FFFh
SA61
0
1
1
1
1
0
1
32
1E8000h to 1EFFFFh
SA62
0
1
1
1
1
1
0
32
1F0000h to 1F7FFFh
(Continued)
9
MBM29PL65LM-90/10
Sector
A21
A20
A19
A18
A17
A16
A15
Sector Size
(Kwords)
Address Range
SA63
0
1
1
1
1
1
1
32
1F8000h to 1FFFFFh
SA64
1
0
0
0
0
0
0
32
200000h to 207FFFh
SA65
1
0
0
0
0
0
1
32
208000h to 20FFFFh
SA66
1
0
0
0
0
1
0
32
210000h to 217FFFh
SA67
1
0
0
0
0
1
1
32
218000h to 21FFFFh
SA68
1
0
0
0
1
0
0
32
220000h to 227FFFh
SA69
1
0
0
0
1
0
1
32
228000h to 22FFFFh
SA70
1
0
0
0
1
1
0
32
230000h to 237FFFh
SA71
1
0
0
0
1
1
1
32
238000h to 23FFFFh
SA72
1
0
0
1
0
0
0
32
240000h to 247FFFh
SA73
1
0
0
1
0
0
1
32
248000h to 24FFFFh
SA74
1
0
0
1
0
1
0
32
250000h to 257FFFh
SA75
1
0
0
1
0
1
1
32
258000h to 25FFFFh
SA76
1
0
0
1
1
0
0
32
260000h to 267FFFh
SA77
1
0
0
1
1
0
1
32
268000h to 26FFFFh
SA78
1
0
0
1
1
1
0
32
270000h to 277FFFh
SA79
1
0
0
1
1
1
1
32
278000h to 27FFFFh
SA80
1
0
1
0
0
0
0
32
280000h to 287FFFh
SA81
1
0
1
0
0
0
1
32
288000h to 28FFFFh
SA82
1
0
1
0
0
1
0
32
290000h to 297FFFh
SA83
1
0
1
0
0
1
1
32
298000h to 29FFFFh
SA84
1
0
1
0
1
0
0
32
2A0000h to 2A7FFFh
SA85
1
0
1
0
1
0
1
32
2A8000h to 2AFFFFh
SA86
1
0
1
0
1
1
0
32
2B0000h to 2B7FFFh
SA87
1
0
1
0
1
1
1
32
2B8000h to 2BFFFFh
SA88
1
0
1
1
0
0
0
32
2C0000h to 2C7FFFh
SA89
1
0
1
1
0
0
1
32
2C8000h to 2CFFFFh
SA90
1
0
1
1
0
1
0
32
2D0000h to 2D7FFFh
SA91
1
0
1
1
0
1
1
32
2D8000h to 2DFFFFh
SA92
1
0
1
1
1
0
0
32
2E0000h to 2EE7FFh
SA93
1
0
1
1
1
0
1
32
2E8000h to 2EFFFFh
SA94
1
0
1
1
1
1
0
32
2F0000h to 2F7FFFh
(Continued)
10
MBM29PL65LM-90/10
(Continued)
Sector
A21
A20
A19
A18
A17
A16
A15
Sector Size
(Kwords)
Address Range
SA95
1
0
1
1
1
1
1
32
2F8000h to 2FFFFFh
SA96
1
1
0
0
0
0
0
32
300000h to 307FFFh
SA97
1
1
0
0
0
0
1
32
308000h to 30FFFFh
SA98
1
1
0
0
0
1
0
32
310000h to 317FFFh
SA99
1
1
0
0
0
1
1
32
318000h to 31FFFFh
SA100
1
1
0
0
1
0
0
32
320000h to 327FFFh
SA101
1
1
0
0
1
0
1
32
328000h to 32FFFFh
SA102
1
1
0
0
1
1
0
32
330000h to 337FFFh
SA103
1
1
0
0
1
1
1
32
338000h to 33FFFFh
SA104
1
1
0
1
0
0
0
32
340000h to 347FFFh
SA105
1
1
0
1
0
0
1
32
348000h to 34FFFFh
SA106
1
1
0
1
0
1
0
32
350000h to 357FFFh
SA107
1
1
0
1
0
1
1
32
358000h to 35FFFFh
SA108
1
1
0
1
1
0
0
32
360000h to 367FFFh
SA109
1
1
0
1
1
0
1
32
368000h to 36FFFFh
SA110
1
1
0
1
1
1
0
32
370000h to 377FFFh
SA111
1
1
0
1
1
1
1
32
378000h to 37FFFFh
SA112
1
1
1
0
0
0
0
32
380000h to 387FFFh
SA113
1
1
1
0
0
0
1
32
388000h to 38FFFFh
SA114
1
1
1
0
0
1
0
32
390000h to 397FFFh
SA115
1
1
1
0
0
1
1
32
398000h to 39FFFFh
SA116
1
1
1
0
1
0
0
32
3A0000h to 3A7FFFh
SA117
1
1
1
0
1
0
1
32
3A8000h to 3AFFFFh
SA118
1
1
1
0
1
1
0
32
3B0000h to 3B7FFFh
SA119
1
1
1
0
1
1
1
32
3B8000h to 3BFFFFh
SA120
1
1
1
1
0
0
0
32
3C0000h to 3C7FFFh
SA121
1
1
1
1
0
0
1
32
3C8000h to 3CFFFFh
SA122
1
1
1
1
0
1
0
32
3D0000h to 3D7FFFh
SA123
1
1
1
1
0
1
1
32
3D8000h to 3DFFFFh
SA124
1
1
1
1
1
0
0
32
3E0000h to 3E7FFFh
SA125
1
1
1
1
1
0
1
32
3E8000h to 3EFFFFh
SA126
1
1
1
1
1
1
0
32
3F0000h to 3F7FFFh
SA127
1
1
1
1
1
1
1
32
3F8000h to 3FFFFFh
11
MBM29PL65LM-90/10
Sector Group Address Table
12
Sector Group
Address
A21
A20
A19
A18
A17
Sector Group Size
(Kwords)
Sectors
SGA0
0
0
0
0
0
128
SA0 to SA3
SGA1
0
0
0
0
1
128
SA4 to SA7
SGA2
0
0
0
1
0
128
SA8 to SA11
SGA3
0
0
0
1
1
128
SA12 to SA15
SGA4
0
0
1
0
0
128
SA16 to SA19
SGA5
0
0
1
0
1
128
SA20 to SA23
SGA6
0
0
1
1
0
128
SA24 to SA27
SGA7
0
0
1
1
1
128
SA28 to SA31
SGA8
0
1
0
0
0
128
SA32 to SA35
SGA9
0
1
0
0
1
128
SA36 to SA39
SGA10
0
1
0
1
0
128
SA40 to SA43
SGA11
0
1
0
1
1
128
SA44 to SA47
SGA12
0
1
1
0
0
128
SA48 to SA51
SGA13
0
1
1
0
1
128
SA52 to SA55
SGA14
0
1
1
1
0
128
SA56 to SA59
SGA15
0
1
1
1
1
128
SA60 to SA63
SGA16
1
0
0
0
0
128
SA64 to SA67
SGA17
1
0
0
0
1
128
SA68 to SA71
SGA18
1
0
0
1
0
128
SA72 to SA75
SGA19
1
0
0
1
1
128
SA76 to SA79
SGA20
1
0
1
0
0
128
SA80 to SA83
SGA21
1
0
1
0
1
128
SA84 to SA87
SGA22
1
0
1
1
0
128
SA88 to SA91
SGA23
1
0
1
1
1
128
SA92 to SA95
SGA24
1
1
0
0
0
128
SA96 to SA99
SGA25
1
1
0
0
1
128
SA100 to SA103
SGA26
1
1
0
1
0
128
SA104 to SA107
SGA27
1
1
0
1
1
128
SA108 to SA111
SGA28
1
1
1
0
0
128
SA112 to SA115
SGA29
1
1
1
0
1
128
SA116 to SA119
SGA30
1
1
1
1
0
128
SA120 to SA123
SGA31
1
1
1
1
1
128
SA124 to SA127
MBM29PL65LM-90/10
A6 to A0
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
Common Flash Memory Interface Code Table
DQ15 to DQ0
Description
0051h
0052h
Query-unique ASCII string “QRY”
0059h
0002h
Primary OEM Command Set
0000h
02h : AMD/FJ standard
0040h
Address for Primary Extended Table
0000h
0000h
Alternate OEM Command Set
0000h
(00h = not applicable)
0000h
Address for Alternate OEM Extended Table
0000h
VCC Min (write/erase)
0027h
DQ7 to DQ4: 1V/bit,
DQ3 to DQ0: 100 mV/bit
VCC Max (write/erase)
0036h
DQ7 to DQ4: 1V/bit,
DQ3 to DQ0: 100 mV/bit
0000h
VPP Min voltage (00h = no Vpp pin)
0000h
VPP Max voltage (00h =no Vpp pin)
0007h
Typical timeout per single write 2N µs
0007h
Typical timeout for Min size buffer write 2N µs
000Ah
Typical timeout per individual sector erase 2N ms
0000h
Typical timeout for full chip erase 2N ms
0001h
Max timeout for write 2N times typical
0005h
Max timeout for buffer write 2N times typical
0004h
Max timeout per individual sector erase 2N times typical
0000h
Max timeout for full chip erase 2N times typical
0017h
Device Size = 2N byte
0001h
Flash Device Interface description
0000h
01h : × 16
0005h
Max number of byte in multi-byte write = 2N
0000h
0001h
Number of Erase Block Regions within device (02h = Boot)
007Fh
Erase Block Region 1 Information
0000h
bit 15 to bit 0 : y = number of sectors
0000h
bit 31 to bit 16 : z = size
0001h
(z × 256 Byte)
0000h
Erase Block Region 2 Information
0000h
bit 15 to bit 0 : y = number of sectors
0000h
bit 31 to bit 16 : z = size
0000h
(z × 256 Byte)
(Continued)
13
MBM29PL65LM-90/10
(Continued)
A6 to A0
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
40h
41h
42h
43h
44h
14
DQ15 to DQ0
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0050h
0052h
0049h
0031h
0033h
45h
0008h
46h
0002h
47h
0004h
48h
0001h
49h
0004h
4Ah
0000h
4Bh
0000h
4Ch
0001h
4Dh
00B5h
4Eh
00C5h
4Fh
0004h
50h
01h
Description
Erase Block Region 3 Information
bit 15 to bit 0 : y = number of sectors
bit 31 to bit 16 : z = size
(z × 256 Byte)
Erase Block Region 4 Information
bit 15 to bit 0 : y = number of sectors
bit 31 to bit 16 : z = size
(z × 256 Byte)
Query-unique ASCII string “PRI”
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock
08h : Supported
09h : Not Supported
Erase Suspend
(02h = To Read & Write)
Sector Group Protection
00h : Not Supported
X : Number of sectors in per group
Sector Temporary Unprotection
00h : Not Supported
01h : Supported
Sector Group Protection Algorithm
Dual Operation
(00h = Not Supported)
Burst Mode Type
(00h = Not Supported)
Page Mode Type
(01h = 4-Word Page Supported)
VACC (Acceleration) Supply Minimum
00h = Not Supported
DQ7 to DQ4: 1V/bit,
DQ3 to DQ0: 100mV/bit
VACC (Acceleration) Supply Maximum
00h = Not Supported
DQ7 to DQ4: 1V/bit,
DQ3 to DQ0: 100mV/bit
Write Protect
04h = Uniform Sectors Bottom Write Protect
Program Suspend
00h = Not Supported
01h = Supported
MBM29PL65LM-90/10
■ FUNCTIONAL DESCRIPTION
Standby Mode
There are two ways to implement the standby mode on the device, one using both the CE and RESET pins, and
the other via the RESET pin only.
When using both pins, CMOS standby mode is achieved with CE and RESET input held at VCC ± 0.3 V. Under
this condition the current consumed is less than 5 µA Max. During Embedded Algorithm operation, VCC active
current (ICC2) is required even when CE = “H”. The device can be read with standard access time (tCE) from either
of these standby modes.
When using the RESET pin only, CMOS standby mode is achieved with RESET input held at VSS ± 0.3 V (CE =
“H” or “L”) .
Under this condition the current consumed is less than 5 µA Max. Once the RESET pin is set high, the device
requires tRH as a wake-up time for output to be valid for read access.
During standby mode, the output is in the high impedance state regardless of OE input.
Automatic Sleep Mode
Automatic sleep mode works to resin power consumption during read-out of the device data. This is useful in
the application such as a handy terminal which requires low power consumption.
To activate this mode, the device automatically switches itself to low power mode when address remain stable
during
access time of tACC + 30 ns. It is not necessary to control CE, WE and OE on this mode. The current consumed
is typically 1 µA (CMOS Level) .
During simultaneous operation, VCC active current (ICC2) is required.
Since, the data are latched during this mode, the data are continuously read out. When the addresses are
changed, the mode is automatically canceled and the device reads the data for changed address.
Autoselect
Autoselect mode allows reading out of a binary code and identifies its manufacturer and type. It is intended for
use by programming equipment for the purpose of automatically matching the device to be programmed with
its corresponding programming algorithm. This mode is functional over the entire temperature range of the device.
To activate this mode, the programming equipment must force VID on address pin A9. Three identifier bytes may
then be sequenced from the device outputs by toggling addresses. All addresses are DON’T CARES except A6
to A0.
The manufacturer and device codes may also be read via the command register, for instances when the device
is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is
illustrated in “Common Definitions Table” of “■ DEVICE BUS OPERATIONS”.
A read cycle from address 00h returns the manufacturer’s code (Fujitsu = 04h) . A read cycle from address 01h
outputs device code. At word mode, 227Eh is output, it indicates that two additional codes, called Extended
Device Codes is required. Therefore the system may continue reading out these Extended Device Codes at
addresses of 0Eh and 0Fh. Refer to “Autoselect Codes Table” in “■ DEVICE BUS OPERATIONS”.
Read Mode
The device has two control functions required to obtain data at the outputs. CE is the power control and used
for a device selection. OE is the output control and used to gate data to the output pins if a device is selected.
Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable
access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output
enable access time is the delay from the falling edge of OE to valid data at the output pins. Assuming the
addresses have been stable for at least tACC - tOE time. When reading out a data without changing addresses
after power-up, input hardware reset or to change CE pin from “H” or “L”.
15
MBM29PL65LM-90/10
Page Mode Read
The device is capable of fast Page mode read and are compatible with Page mode Mask ROM read operation.
This mode provides faster read access speed for random locations within a page. Page size is 4 words, within
the appropriate Page being selected by the higher address bits A21 to A2 and the address bits A1 to A0 in Word
mode (A1 to A-1 in Byte mode). The initial page access is equal to the random access (tACC) and subsequent
Page read access (as long as the locations specified by the microprocessor fall within that Page) is equivalent
to the page access time (tPACC).
Output Disable
With the OE input is at logic high level (VIH), output from the device is disabled. This causes the output pins to
be in a high impedance state.
Write
Device erase and programming are accomplished via the command register. The contents of the register serve
as input to the internal state machine. The state machine output dictates the device function.
The command register itself does not occupy any addressable memory location. The register is a latch used to
store the commands, along with the address and data information needed to execute the command. The command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the
falling edge of WE or CE, whichever starts later, while data is latched on the rising edge of WE or CE, whichever
starts first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.
Sector Group Protection
The device features hardware sector group protection. This feature will disable both program and erase operations in any combination of 32 sector groups of memory. See “Sector Group Address Table (MBM29PL65LM)”
in “■ DEVICE BUS OPERATION”. The user’s side can use the sector group protection using programming
equipment. The device is shipped with all sector groups that are unprotected.
To activate it, the programming equipment must force VID on address pin A9 and control pin OE, CE = VIL and
A6 = A3 = A2 = A0 = VIL, A1 = VIH. The sector group addresses (A21, A20, A19, A18, and A17) should be set to the
sector to be protected. “Sector Address Table (MBM29PL65LM)” in “■ DEVICE BUS OPERATION” defines the
sector address for each of the seventy-one (71) individual sectors, and “Sector Group Address Table
(MBM29PL65LM)” in “■ DEVICE BUS OPERATION” defines the sector group address for each of the twentyfour (24) individual group sectors. Programming of the protection circuitry begins on the falling edge of the WE
pulse and is terminated with the rising edge of the same. Sector group addresses must be held constant during
the WE pulse. See “Sector Group Protection Timing Diagram” in “■ TIMING DIAGRAM” and “Sector Group
Protection Algorithm” in “■ FLOW CHART” for sector group protection timing diagram and algorithm.
To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9
with CE and OE at VIL and WE at VIH. Scanning the sector group addresses (A21, A20, A19, A18 and A17) while (A6,
A3, A2, A1, A0) = (0, 0, 0, 1, 0) will produce a logical “1” code at device output DQ0 for a protected sector. Otherwise
the device will produce “0” for unprotected sectors. In this mode, the lower order addresses, except for A0, A1,
A2, A3 and A6 can be either High or Low.
Where the high order addresses (A21, A20, A19, A18 and A17) are the desired sector group address will produce a
logical “1” at DQ0 for a protected sector group. See “Sector Group Protection Verify Autoselect Codes” in
“■ DEVICE BUS OPERATION” for Autoselect codes.
Temporary Sector Group Unprotection
This feature allows temporary unprotection of previously protected sector groups of the devices in order to change
data. The Sector Group Unprotection mode is activated by setting the RESET pin to high voltage (VID). During
this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. Once the VID is taken away from the RESET pin, all the previously protected sector groups will be
16
MBM29PL65LM-90/10
protected again. Refer to “Temporary Sector Group Unprotection Timing Diagram” in ■ SWITCHING WAVEFORMS and “Temporary Sector Group Unprotection Algorithm” in ■ FLOW CHART.
Hardware Reset
The device may be reset by driving the RESET pin to VIL. The RESET pin has a pulse requirement and has to
be kept low (VIL) for at least “tRP” in order to properly reset the internal state machine. Any operation in the process
of being executed is terminated and the internal state machine is reset to the read mode “tREADY” after the RESET
pin is driven low.
Furthermore once the RESET pin goes high the device requires an additional “tRH” before it allows read access.
When the RESET pin is low, the device is in the standby mode for the duration of the pulse and all the data
output pins are tri-stated. If a hardware reset occurs during a program or erase operation, the data at that
particular location are corrupted.
Write Protect (WP)
Aside from Sector Group Protection, MBM29PL65LM provides another function that protects the first sector
(SA0) during programming and erase. When WP = VIL, this first sector (SA0) becomes protected while Sector
Group Protection for all the other sectors are temporarily lifted.
Accelerated Program Operation
The device offers accelerated program operation which enables the programming in high speed. If the system
asserts VACC to the ACC pin, the device automatically enters the acceleration mode and the time required for
program operation will reduce to about 85%. This function is primarily intended to allow high speed program,
so caution is needed as the sector group becomes temporarily unprotected.
The system uses fast program command sequence when programming during acceleration mode. Set command
to fast mode and reset command from fast mode are not necessary. When the device enters the acceleration
mode, the device automatically set to fast mode. Therefore the present sequence is used for programming and
detection of completion during acceleration mode.
Removing VACC from the ACC pin and applying VIL or VIH returns the device to normal operation. Do not remove
VACC from ACC pin while programming. See “Accelerated Program Timing Diagram”.
VCCQ
The output voltage generated on the device is determined based on the VCCQ level. This feature allows the device
to operate in mixed-voltage environments, driving and receiving signals to and from other devices on the same
bus.
17
MBM29PL65LM-90/10
■ COMMAND DEFINITIONS
Device operations are selected by writing specific address and data sequences into the command register.
"MBM29PL65LM Command Definitions Table" in ■ DEVICE BUS OPERATION shows the valid register command sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h) commands are valid only while
the Sector Erase operation is in progress. Also the Program Suspend (B0h) and Program Resume (30h) commands are valid only while the Program operation is in progress. Moreover, Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please note that commands are always written at DQ7
to DQ0 and DQ15 to DQ8 bits are ignored.
Reset Command
In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to Reset mode, verify mode of
secter protect commands, the Read/Reset operation is initiated by writing the Read/Reset command sequence
into the command register. Microprocessor read cycles retrieve array data from the memory. The device remains
enabled for reads until the command register contents are altered.
The device automatically powers-up in the Read/Reset state. In this case, a command sequence is not required
to read data. Standard microprocessor read cycles retrieve array data. This default value ensures that no spurious
alteration of the memory content occurs during the power transition. Refer to the AC Read Characteristics and
Waveforms for specific timing parameters.
Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. Therefore
manufacture and device codes must be accessible while the device resides in the target system. PROM programmers typically access the signature codes by raising A9 to a higher voltage. However multiplexing high
voltage onto the address lines is not generally desired system design practice.
he device contains Autoselect command operation to supplement traditional PROM programming methodology.
The operation is initiated by writing the Autoselect command sequence into the command register.
This is followed by a third write cycle that contains the address and the Autoselect command. Then the manufacture and device codes can be read from the address, and an actual data of memory cell can be read from
the another address.
Following the command write, a read cycle from address 00h returns the manufacturer’s code (Fujitsu=04h).
And, at double word mode, a read cycle at address 01h outputs device code. At word mode, 227Eh is output,
this indicates that two additional codes, called Extended Device Codes will be required. Therefore the system
may continue reading out these Extended Device Codes at the address of 0Eh, as well as at (BA) 0Fh (at word
mode, 1Eh). Refer to "MBM29PL65LX Autoselect Codes Table" in ■ DEVICE BUS OPERATION.
To terminate the operation, it is necessary to write the Reset command sequence into the register. To execute
the Autoselect command during the operation, Reset command sequence must be written before the Autoselect
command.
Program Command
The device is programmed on word-by-word basis (or double word-by-double word). Programming is a four bus
cycle operation. There are two “unlock” write cycles. These are followed by the program set-up command and
data write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later, and the data
is latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever
happens first) starts programming. Upon executing the Embedded Program Algorithm command sequence, the
system is not required to provide further controls or timings. The device automatically provides adequate internally generated program pulses and verify programmed cell margin.
The system can determine the status of the program operation by using DQ7 (Data Polling), DQ6 (Toggle Bit) or
RY/BY. The Data Polling and Toggle Bit are automatically performed at the memory location being programmed.
18
MBM29PL65LM-90/10
The programming operation is completed when the data on DQ7 is equivalent to data written to this bit at which
the devices return to the read mode and plogram addresses are no longer latched. Therefore, the devices require
that a valid address to the devices be supplied by the system at this particular instance. Hence Data Polling
requires the same address which is being programmed.
If hardware reset occurs during the programming operation, the data being written is not guaranteed.
Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success
according to the data polling algorithm but a read from Reset mode will show that the data is still “0”. Only erase
operations can convert from “0”s to “1”s.Refer to "Embedded ProgramTM Algorithm" using typical command
strings and bus operations.
Program Suspend/Resume Command
The Program Suspend command allows the system to interrupt a program operation so that data can be read
from any address. Writing the Program Suspend command (B0h) during the Embedded Program operation
immediately suspends the programming. The bank addresses of sector being programmed should be set when
writing the Program Suspend command.
When the Program Suspend command is written during a programming process, the device halts the program
operation within 1 µs and updates the status bits.
After the program operation has been suspended, the system can read data from any address. The data at
program-suspended address is not valid. Normal read timing and command definitions apply.
After the Program Resume command (30h) is written, the device reverts to programming. The bank addresses
of sectors being suspended should be set when writing the Program Resume command. The system can
determine the program operation status using the DQ7 or DQ6 status bits, just as in the standard program
operation. See “Write Operation Status” for more information. When issuing program suspend command in
4 µs after issuing program command, determine the status of program operation by reading status bit at more
4 µs after issuing program resume command.
The system may also write the Autoselect command sequence in the Program Suspend mode.
The device allows reading Autoselect codes at the addresses within programming sectors, since the codes are
not stored in the memory. When the device exits from the Autoselect mode, the device reverts to the Program
Suspend mode, and is ready for another valid operation. See “Autoselect Command Sequence” for more information.
The system must write the Program Resume command to exit from the Program Suspend mode and continue
programming operation. Further writes of the Resume command are ignored. Another Program Suspend command can be written after the device resumes programming.
Do not read CFI code after HiddenROM Entry and Exit in program suspend mode.
Write Buffer Programming Operations
Write Buffer Programming allows the system write to series of 16 words in one programming operation. This
results in faster effective word programming time than the standard programming algorithms. The Write Buffer
Programming command sequence is initiated by first writing two unlock cycles. This is followed by a third write
cycle selecting the Sector Address in which programming will occur. In forth cycle contains both Sector Address
and unique code for data bus width will be loaded into the page buffer at the Sector Address in which programming
will occur.
The system then writes the starting address/data combination. This “starting address” must be the same Sector
Address used in third and fourth cycles and its lower addresses of A3 to A0 should be 0h. All subsequent address
must be incremented by 1. Addresses are latched on the falling edge of CE or WE, whichever happens later
and the data is latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE
(whichever happens first) starts programming. Upon executing the Write Buffer Programming Operations com-
19
MBM29PL65LM-90/10
mand sequence, the system is not required to provide further controls or timings. The device will automatically
provide adequate internally generated program pulses and verify the programmed cell margin.
DQ7(Data Polling), DQ6(Toggle Bit), DQ5(Exceeded Timing Limits), DQ1(Write-to-Buffer Abort) should be monitored to determine the device status during Write Buffer Programming. In addition to these functions, it is also
possible to indicate to the host system that Write Buffer Programming Operations are either in progress or have
been completed by RY/BY. See “Hardware Sequence Flags”.The Data polling techniques described in “Data
Polling Algorithm” in ■ FLOW CHART should be used while monitoring the last address location loaded into the
write buffer. In addition, it is not neccessary to specify an address in Toggle Bit techniques described in “Toggle
Bit Algorithm” in ■ FLOW CHART. The automatic programing operation is completed when the data on DQ7 is
equivalent to the data written to this bit at which time the device returns to the read mode and addresses are
no longer latched ( See "Hardware Sequence Flags").
The write-buffer programming operation can be suspended using the standard program suspend/resume commands.
Once the write buffer programming is set, the system must then write the “Program Buffer to Flash” command
at the Sector Address. Any other address/data combination will abort the Write Buffer Programming operation
and the device will continue busy state.
The Write Buffer Programming Sequence can be ABORTED by doing the following :
• Different Sector Address is asserted.
• Write data other than the “Program Buffer to Flash" command after the specified number of “data load” cycles.
A “Write-to-Buffer-Abort Reset” command sequence must be written to the device to return to read mode. (See
“MBM29PL65LM Standard Command Definitions” in ■ DEVICE BUS OPERATION for details on this command
sequence.)
Chip Erase Command
Chip erase is a six-bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.
Chip erase does not require the user to program prior to erase. Upon executing the Embedded Erase Algorithm
command sequence the device automatically programs and verifies the entire memory for an all zero data pattern
prior to electrical erase. (Preprogram Function) The system is not required to provide any controls or timings
during these operations.
The system can determine the erase operation status by using DQ7 (Data Polling), or DQ6 (Toggle Bit). The chip
erase begins on the rising edge of the last CE or WE, whichever happens first in the command sequence and
terminates when the data on DQ7 is “1” at which the device returns to read the mode.
Chip Erase Time: Sector Erase Time × All sectors + Chip Program Time (Preprogramming)
Refer to "Embedded EraseTM Algorithm" for typical command strings and bus operations.
Sector Erase Command
Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector
address (any address location within the desired sector) is latched on the falling edge of CE or WE whichever
starts later, while the command (Data = 30h) is latched on the rising edge of CE or WE whichever states first.
After time-out of “tTOW” from the rising edge of the last sector erase command, the sector erase operation will begin.
Multiple sectors are erased concurrently by writing the six bus cycle operations on "MBM29XL12DF Command
Definitions Table" in ■ DEVICE BUS OPERATION. This sequence is followed with writes of the Sector Erase
command to addresses in other sectors desired to be concurrently erased. The time between writes must be
less than “tTOW” otherwise that command is not accepted and erasure does not start. It is recommended that
processor interrupts be disabled during this time to guarantee this condition. The interrupts can be re-enabled
after the last Sector Erase command is written. A time-out of “tTOW” from the rising edge of last CE or WE whichever
starts first initiates the execution of the Sector Erase command(s). If another falling edge of CE or WE, whichever
20
MBM29PL65LM-90/10
starts first occurs within the “tTOW” time-out window the timer is reset. (Monitor DQ3 to determine if the sector
erase timer window is still open, see section DQ3, "Sector Erase Timer".) Any command other than Sector Erase
or Erase Suspend during this time-out period will reset the device to the read mode, ignoring the previous
command string. Resetting the device once execution has begun may corrupt the data in the sector. In that case
restart the erase on those sectors and allow them to complete. Refer to "Write Operation Status" section for
Sector Erase Timer operation. Loading the sector erase buffer may be done in any sequence and with any
number of sectors.
Sector erase does not require the user to program prior to erase. The device automatically programs all memory
locations in the sector(s) to be erased prior to electrical erase (Preprogram function). When erasing a sector or
sectors the remaining unselected sectors are not affected. The system is not required to provide any controls
or timings during these operations.
The system can determine the status of the erase operation by using DQ7 (Data Polling), or DQ6 (Toggle Bit).
The sector erase begins after the “tTOW” time out from the rising edge of CE or WE whichever starts first for the
last sector erase command pulse and terminates when the data on DQ7 is “1” at which time the device returns
to the read mode. See "Write Operation Status" section. Data polling and Toggle Bit must be performed at an
address within any of the sectors being erased.
Multiple Sector Erase Time; [Sector Erase Time + Sector Program Time (Preprogramming)] × Number of Sector
Erase.
Erase Suspend/Resume Command
The Erase Suspend command allows the user to interrupt Sector Erase operation and then perform read to a
sector not being erased. This command is applicable ONLY during the Sector Erase operation within the timeout period for Sectore erase.
Writting the Erase Suspend command (B0h) during the Sector Erase time-out results in immediate termination
of the time-out period and suspension of the erase operation.
Writing the Erase Resume command (30h) resumes the erase operation.
When the “Erase Suspend” command is written during the Sector Erase operation, the device takes a maximum
of “tSPD” to suspend the erase operation. When the devices have entered the erase-suspended mode, the RY/
BY output pin will be at High-Z and the DQ7 bit will be at logic “1” and DQ6 will stop toggling. The user must use
the address of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been suspended. Further writes of the Erase Suspend command are ignored.
When the erase operation is suspended, the device defaults to the erase-suspend-read mode. Reading data in
this mode is the same as reading from the standard read mode except that the data must be read from sectors
that have not been erase-suspended. Successively reading from the erase-suspended sector while the device
is in the erase-suspend-read mode causes DQ2 to toggle. See the section on DQ2.
To resume the operation of Sector Erase, the Resume command (30h) should be written. Any further writes of
the Resume command at this point is ignored. Another Erase Suspend command is written after the chip resumes
erasing.
Do not issuing program command after entering erase-suspend-read mode.
Fast Mode Set/Reset Command
Fast Mode function dispenses with the initial two unlock cycles required in the standard program command
sequence writing Fast Mode command into the command register. In this mode the required bus cycle for
programming is two cycles instead of four bus cycles in standard program command. The read operation is also
executed after exiting this mode. During the Fast mode, do not write any commands other than the Fast program/
Fast mode reset command. To exit this mode, write Fast Mode Reset command into the command register.
Refer to "Embedded Program Algorithm for Fast Mode". The VCC active current is required even CE = VIH during
Fast Mode.
21
MBM29PL65LM-90/10
Fast Programming
During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program
Algorithm is executed by writing program set-up command (A0h) and data write cycles (PA/PD). Refer to "Embedded Program Algorithm for Fast Mode".
Extended Sector Group Protection
In addition to normal sector group protection, the device has Extended Sector Group Protection as extended
function. This function enables protection of the sector group by forcing VID on RESET pin and writes a command
sequence. Unlike conventional procedures, it is not necessary to force VID and control timing for control pins.
The only RESET pin requires VID for sector group protection in this mode. The extended sector group protection
requires VID on RESET pin. With this condition, the operation is initiated by writing the set-up command (60h)
into the command register. Then the sector group addresses pins (A21, A20, A19, A18, and A17) and (A6, A3, A2, A1,
A0) = (0, 0, 0, 1, 0) should be set to the sector group to be protected (set VIL for the other addresses pins is
recommended), and write extended sector group protection command (60h). A sector group is typically protected
in 250 µs.
To verify programming of the protection circuitry, the sector group addresses pins (A20, A19, A18, A17, A16, A15, A14,
A13 and A12) and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) should be set and write a command (40h). Following the
command write, a logical “1” at device output DQ0 will produce for protected sector in the read operation. If the
output data is logical “0”, write the extended sector group protection command (60h) again. To terminate the
operation, set RESET pin to VIH. (Refer to the “Extended Sector Group Protection Timing Diagram” in ■ SWITCHING WAVEFORMS and “Extended Sector Group Protection Algorithm” in ■ FLOW CHART.)
Query Command (CFI : Common Flash Memory Interface)
To verify programming of the protection circuitry, the sector group addresses pins (A20, A19, A18, A17, A16, A15, A14,
A13 and A12) and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) should be set and write a command (40h). Following the
command write, a logical “1” at device output DQ0 will produce for protected sector in the read operation. If the
output data is logical “0”, write the extended sector group protection command (60h) again. To terminate the
operation, set RESET pin to VIH. (Refer to the “Extended Sector Group Protection Timing Diagram” in ■ SWITCHING WAVEFORMS and “Extended Sector Group Protection Algorithm” in ■ FLOW CHART.)
The operation is initiated by writing the query command (98h) into the command register. Following the command
write, a read cycle from specific address retrives device information. Refer to "Common Flash Memory Interface
Code" in ■ DEVICE BUS OPERATION in detail. Please note that output data of upper byte (DQ15 to DQ8) is “0”
in word mode (16 bit) read. To terminate operation, write the Read/Reset command sequence into the register.
HiddenROM Mode
HiddenROM Region
The HiddenROM (HiddenROM) feature provides a Flash memory region that the system may access through
a new command sequence. This is primarily intended for customers who wish to use an Electronic Serial Number
(ESN) in the device with the ESN protected against modification. Once the HiddenROM region is protected, any
further modification of that region is impossible. This ensures the security of the ESN once the product is shipped
to the field. This device occupies the address of the 000000h to 00007Fh.
After the system writes the HiddenROM Entry command sequence, it may read the HiddenROM region by using
device addresses A6 to A0 (A20 to A7 are all “0”). That is, the device sends only program command that would
normally be sent to the address to the HiddenROM region. This mode of operation continues until the system
issues the Exit HiddenROM command sequence, or until power is removed from the device. On power-up, or
following a hardware reset, the device reverts to sending commands to the address.
If you request Fujitsu to program the ESN in the device, please contact a Fujitsu representative for more information.
22
MBM29PL65LM-90/10
HiddenROM Entry Command
The device has a HiddenROM area with One Time Protect function. This area is to enter the security code and
to unable the change of the code once set. Program/erase is possible in this area until it is protected. However
once it is protected, it is impossible to unprotect. Therefore extreme caution is required.
HiddenROM area is 128 words. This area is normally the “outermost” 8K words boot block area. Therefore, write
the HiddenROM entry command sequence to enter the HiddenROM area. It is called HiddenROM mode when
the HiddenROM area appears.
Sectors other than the block area SA0 can be read during HiddenROM mode. Read/program of the HiddenROM
area is possible during HiddenROM mode. Write the HiddenROM reset command sequence to exit the HiddenROM mode. Note that any other commands should not be issued than the HiddenROM program/protection/reset
commands during the HiddenROM mode. When you issue the other commands including the suspend resume
capability, send the HiddenROM reset command first to exit the HiddenROM mode and then issue each command.
HiddenROM Program Command
To program the data to the HiddenROM area, write the HiddenROM program command sequence during HiddenROM mode. This command is the same as the program command in usual except to write the command
during HiddenROM mode. Therefore the detection of completion method is the same as using the DQ7 data
polling, and DQ6 toggle bit. Need to pay attention to the address to be programmed. If the address other than
the HiddenROM area is selected to program, data of the address are changed.During the write into the HiddenROM region, the program suspend command issuance is prohibited.
HiddenROM Protect Command
The method to protect the HiddenROM is to apply high voltage (VID) to A9 and OE, set the sector address in the
HiddenROM area and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) , and apply the write pulse during the HiddenROM
mode. The same command sequence may be used because it is the same as the extension sector group protect
in the past, except that it is in the HiddenROM mode and does not apply high voltage to the RESET pin. Please
refer to above mentioned “Extended Sector Group Protection” for details of sector group protect setting.
The same command sequence may be used because it is the same as the extension sector group protect in
the past, except that it is in the HiddenROM mode and does not apply high voltage to the RESET pin. Please
refer to above mentioned “Extended Sector Group Protection” for details of sector group protect setting.
Other sector will be effected if the address other than those for HiddenROM area is selected for the sector
address, so please be carefull. Once it is protected, protection can not be cancelled, so please pay the closest
attention.
Write Operation Status
Hardware Sequence Flags
Detailed in “Hardware Sequence Flags” are all the status flags which can determine the status of the bank for
the current mode operation. During sector erase, the part provides the status flags automatically to the I/O ports.
The information on DQ2 is address-sensitive. This means that if an address from an erasing sector is consecutively read, the DQ2 bit will toggle. However, DQ2 will not toggle if an address from a non-erasing sector is
consecutively read. This allows users to determine which sectors are in erase and which are not.
23
MBM29PL65LM-90/10
Status
Hardware Sequence Flags Table
DQ6
DQ7
DQ5
DQ3
DQ2
DQ1 *3
DQ7
Toggle
0
0
1
0
0
Toggle
0
1
Toggle *1
N/A
Program-Suspend-Read
(Program Suspend Sector)
Data
Data
Data
Data
Data
Data
Program-Supend -Read
(Non-Program Suspended Sector)
Data
Data
Data
Data
Data
Data
1
1
0
0
Toggle *1
N/A
Erase Suspend Read
(Non-Erase Suspended Sector)
Data
Data
Data
Data
Data
Data
Erase Suspend Program
(Non-Erase Suspended Sector)
DQ7
Toggle
0
0
1 *2
N/A
Embedded Program Algorithm
DQ7
Toggle
1
0
1
N/A
Exceeded Embedded Erase Algorithm
Time
Erase
Erase Suspend Program
Limits
Suspend
(Non-Erase Suspended Sector)
Mode
0
Toggle
1
1
N/A
N/A
DQ7
Toggle
1
0
N/A
N/A
BUSY State
DQ7
Toggle
0
N/A
N/A
0
Exceeded Timing Limits
DQ7
Toggle
1
N/A
N/A
0
ABORT State
N/A
Toggle
0
N/A
N/A
1
Embedded Program Algorithm
Embedded Erase Algorithm
In
Progress
Program
Suspend
Mode
Erase
Suspend
Mode
Write to
Buffer *4
Erase Suspend Read
(Erase Suspended Sector)
*1 : Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle.
*2 : Reading from non-erase suspend sector address will indicate logic “1” at the DQ2 bit.
*3 : DQ1 indicates the Write-to-Buffer ABORT status during Write-Buffer-Programming operations.
*4 : The Data Polling algorithm detailed in “Data Polling Algorithm” in “ ■ FLOW CHART” should be used for WriteBuffer-Programming operations. Note that DQ7 during Write-Buffer-Programming indicates the data-bar for
DQ7 data for the LAST LOADED WRITE-BUFFER ADDRESS location.
DQ7
Data Polling
The device features Data Polling as a method to indicate to the host that the Embedded Algorithms are in
progress or completed. During the Embedded Program Algorithm, an attempt to read the device will produce a
complement of data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to
read the device will produce true data last written to DQ7. During the Embedded Erase Algorithm, an attempt to
read the device will produce a “0” at the DQ7 output. Upon completion of the Embedded Erase Algorithm, an
attempt to read device will produce a “1” on DQ7. The flowchart for Data Polling (DQ7) is shown in “Data Polling
Algorithm”. For programming, the Data Polling is valid after the rising edge of the fourth write pulse in the four
write pulse sequences.
For programming, the Data Polling is valid after the rising edge of the fourth write pulse in the four write pulse
sequences.
For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six
write pulse sequences. Data Polling must be performed at sector addresses of sectors being erased, not protected sectors. Otherwise the status may become invalid.
If a program address falls within a protected sector, Data Polling on DQ7 is active for approximately 1 µs, then
that bank returns to the read mode. After an erase command sequence is written, if all sectors selected for
erasing are protected, Data Polling on DQ7 is active for approximately 400 µs, then the bank returns to read mode.
24
MBM29PL65LM-90/10
Once the Embedded Algorithm operation is close to being completed, the device data pins (DQ7) may change
asynchronously while the output enable (OE) is asserted low. This means that device is driving status information
on DQ7 at one instant, and then that byte’s valid data at the next instant. Depending on when the system samples
the DQ7 output, it may read the status or valid data. Even if device has completed the Embedded Algorithm
operation and DQ7 has a valid data, data outputs on DQ0 to DQ6 may still be invalid. The valid data on DQ0 to
DQ7 will be read on successive read attempts.
The Data Polling feature is active only during the Embedded Programming Algorithm, Embedded Erase Algorithm
or sector erase time-out. See “Toggle Bit Status” and “Data Polling during Embedded Algorithm Operation Timing
Diagram”.
DQ6
Toggle Bit I
The device also features the “Toggle Bit I” as a method to indicate to the host system that the Embedded
Algorithms are in progress or completed.
During Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from the
busy bank will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm
cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During
programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse
sequences. For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse
in the six write pulse sequences. The Toggle Bit I is active during the sector time out.
In programming, if the sector being written is protected, the toggle bit will toggle for about 1 µs and then stop
toggling with data unchanged. In erase, the device will erase all selected sectors except for protected ones. If
all selected sectors are protected, the chip will toggle the toggle bit for about 400 µs and then drop back into
read mode, having data kept remained.
Either CE or OE toggling will cause DQ6 to toggle. In addition, an Erase Suspend/Resume command will cause
DQ6 to toggle.
The system can use DQ6 to determine whether a sector is actively erased or is erase-suspended. When a bank
is actively erased (that is, the Embedded Erase Algorithm is in progress) , DQ6 toggles. When a bank enters the
Erase Suspend mode, DQ6 stops toggling. Successive read cycles during erase-suspend-program cause DQ6
to toggle. See “AC Wavefrom for Toggle Bit I during Embedded Algorithm Operations”.
DQ5
Exceeded Timing Limits
DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count) . Under
these conditions DQ5 will produce “1”. This is a failure condition indicating that the program or erase cycle was
not successfully completed. Data Polling is only operating function of the device under this condition. The CE
circuit will partially power down device under these conditions (to approximately 2 mA) . The OE and WE pins
will control the output disable functions as described in "MBM29PL65LM User Bus Operations Table (DW/W =
VIL)" and "MBM29XL12DF User Bus Operations Table (DW/W = VIH)" in ■ DEVICE BUS OPERATION.
The DQ5 failure condition may also appear if a user tries to program a non-blank location without pre-erase. In
this case the device locks out and never completes the Embedded Algorithm operation. Hence, the system never
reads valid data on DQ7 bit and DQ6 never stop toggling. Once the device has exceeded timing limits, the DQ5
bit will indicate a “1.” Please note that this is not a device failure condition since the device was incorrectly used.
If this occurs, reset device with the command sequence.
DQ3
Sector Erase Timer
After completion of the initial sector erase command sequence, sector erase time-out begins. DQ3 will remain
low until the time-out is completed. Data Polling and Toggle Bit are valid after the initial sector erase command
sequence.
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MBM29PL65LM-90/10
If Data Polling or the Toggle Bit I indicates that a valid erase command has been written, DQ3 may be used to
determine whether the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled erase
cycle has begun. If DQ3 is low (“0”) , the device will accept additional sector erase commands. To insure the
command has been accepted, the system software should check the status of DQ3 prior to and following each
subsequent Sector Erase command. If DQ3 were high on the second status check, the command may not have
been accepted.
See “Hardware Sequence Flags”.
DQ2
Toggle Bit II
This toggle bit II, along with DQ6, can be used to determine whether the device is in the Embedded Erase
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the
device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause
DQ2 to toggle. When the device is in the erase-suspended-program mode, successive reads from the non-erase
suspended sector will indicate a logic “1” at the DQ2 bit.
DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend
Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized
as follows :
For example, DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress.
(DQ2 toggles while DQ6 does not.) See also “Toggle Bit Status” and "DQ2 vs DQ6".
Furthermore DQ2 can also be used to determine which sector is being erased. At the erase mode, DQ2 toggles
if this bit is read from an erasing sector.
Reading Toggle Bits DQ6/DQ2
Whenever the system initially begins reading toggle bit status, it must read DQ7 to DQ0 at least twice in a row
to determine whether a toggle bit is toggling. Typically a system would note and store the value of the toggle bit
after the first read. After the second read, the system would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can
read array data on DQ7 to DQ0 on the following read cycle.
However, if, after the initial two read cycles, the system determines that the toggle bit is still toggling, the system
also should note whether the value of DQ5 is high (see the section on DQ5) . If it is, the system should then
determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5
went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase
operation. If it is still toggling, the device did not complete the operation successfully, and the system must write
the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system
tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the
status of the operation. Refer to “Toggle Bit Algorithm”.
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MBM29PL65LM-90/10
Toggle Bit Status Table
DQ7
DQ6
DQ2
DQ7
Toggle
1
Erase
0
Toggle
Toggle *1
Erase-Suspend-Read
(Erase-Suspended Sector)
1
1
Toggle *1
DQ7
Toggle
1 *2
Mode
Program
Erase-Suspend-Program
*1 : Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle.
*2 : Reading from non-erase suspend sector address will indicate logic “1” at the DQ2 bit.
DQ1
Write-to-Buffer Abort
DQ1 indicates whether a Write-to-Buffer operation was aborted. Under these conditions DQ1 produces a "1".
The system must issue the Write-to-Buffer-Abort-Reset command sequence to return the device to reading array
data. See "Write Buffer Programming Operations" section for more details.
Data Protection
The device is designed to offer protection against accidental erasure or programming caused by spurious system
level signals that may exist during power transitions. During power up device automatically resets internal state
machine to Read mode. Also, with its control register architecture, alteration of memory contents only occurs
after successful completion of specific multi-bus cycle command sequence.
Device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and
power-down transitions or system noise.
Low VCC Write Inhibit
To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less
than VLKO. If VCC < VLKO, the command register is disabled and all internal program/erase circuits are disabled.
Under this condition, the device will reset to the read mode. Subsequent writes will be ignored until the VCC level
is greater than VLKO. It is the user’s responsibility to ensure that the control pins are logically correct to prevent
unintentional writes when VCC is above VLKO.
If Embedded Erase Algorithm is interrupted, the intervened erasing sector(s) is(are) not valid.
Write Pulse “Glitch” Protection
Noise pulses of less than 3 ns (typical) on OE, CE, or WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle, CE and WE
must be a logical zero while OE is a logical one.
Power-up Write Inhibit
Power-up of the device with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to read mode on power-up.
Sector Protection
Device user is able to protect each sector group individually to store and protect data. Protection circuit voids
both write and erase commands that are addressed to protected sectors. Any commands to write or erase
addressed to protected sector are ignored.
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MBM29PL65LM-90/10
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
Min
Max
Tstg
–55
+125
°C
TA
–20
+85
°C
Voltage with Respect to Ground All Pins Except
A9, OE, and RESET *1,*2
VIN, VOUT
–0.5
VCC +0.5
V
Power Supply Voltage *1
VCC,VCCQ
–0.5
+4.0
V
VIN
–0.5
+12.5
V
VACC
–0.5
+12.5
V
Storage Temperature
Ambient Temperature with Power Applied
1, 3
A9, OE, and RESET * *
WP/ACC *1,*3
*1 : Voltage is defined on the basis of VSS = GND = 0 V.
*2 : Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may undershoot
VSS to –0.2 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V.
During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods of up to 20 ns
*3 : Minimum DC input voltage is –0.5V. During voltage transitions, these pins may undershoot VSS to –0.2 V
for periods of up to 20 ns.Voltage difference between input and supply voltage ( VIN–VCC) dose not
exceed to +9.0 V.Maximum DC input voltage is +12.5 V which may overshoot to +14.0 V for periods of
up to 20 ns .
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING RANGES*1
Parameter
Symbol
90
Ambient Temperature
10
VCC Supply Voltage *2, *3
2,
VCCQ Supply Voltage * *
TA
VCC
3
VCCQ
Value
Min
Max
–20
+70
–20
+85
+3.0
+3.6
VCC
Unit
°C
V
V
*1 : Operating ranges define those limits between which the functionality of the device is guaranteed.
*2 : Voltage is defined on the basis of VSS = GND = 0 V.
*3 : VCC and VCCQ supply voltage must be on the same level.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
28
MBM29PL65LM-90/10
■ MAXIMUM OVERSHOOT/MAXIMUM UNDERSHOOT
1. Maximum Undershoot Waveform
+0.6 V
20 ns
20 ns
–0.5 V
–2.0 V
20 ns
2. Maximum Overshoot Waveform 1
20 ns
VCC +2.0 V
VCC +0.5 V
0.7 × VCC
20 ns
20 ns
3. Maximum Overshoot Waveform 2
20 ns
+14.0 V
+12.5 V
VCC +0.5 V
20 ns
20 ns
Note : This waveform is applied for A9, OE and RESET.
29
MBM29PL65LM-90/10
■ ELECTRICAL CHARACTERISTICS
1. DC Characteristics
Parameter
Symbol
Value
Conditions
Typ
Max
WP Pin
–2.0
—
+2.0
Others
–1.0
—
+1.0
–1.0
—
+1.0
µA
Input Leakage Current
ILI
VIN = VSS to VCC,
VCC = VCC Max
Output Leakage Current
ILO
VOUT = VSS to VCC, VCC = VCC Max
A9, OE, RESET Inputs
Leakage Current
ILIT
VCC = VCC Max,
A9, OE, RESET = 12.5 V
—
—
35
µA
VCC Active Current
(Read ) *1,*2
ICC1
CE = VIL, OE = VIH, f = 5 MHz
—
15
25
mA
CE = VIL, OE = VIH, f = 10 MHz
—
35
50
mA
VCC Active Current
(Intra-Page Read ) *2
ICC2
CE = VIL, OE = VIH, tPRC = 25 ns,
4-Word
—
10
20
mA
VCC Active Current
(Program / Erase) *2,*3
ICC3
CE = VIL, OE = VIH
—
50
60
mA
VCC Standby Current *2
ICC4
CE = VCC ± 0.3 V, RESET = VCC ± 0.3
V,
OE = VIH, WP = VCC ± 0.3 V
—
1
5
µA
VCC Reset Current *2
ICC5
RESET = VCC ± 0.3 V,
WP = VCC ± 0.3 V
—
1
5
µA
VCC Automatic Sleep Current
*4
ICC6
CE = VSS ± 0.3 V, RESET = VCC ± 0.3 V,
VIN = VCC ± 0.3 V or Vss ± 0.3 V,
WP = VCC ± 0.3 V
—
1
5
µA
VCC Active Current
(Erase-Suspend-Program) *2
ICC7
CE = VIL, OE = VIH
—
50
60
mA
ACC Accelerated Program
Current
IACC
CE = VIL, OE = VIH,
Vcc = Vcc Max,
ACC =VACC Max
ACC
Pin
—
—
45
Vcc Pin
—
—
60
Input Low Level
VIL
—
–0.5
—
0.6
V
Input High Level
VIH
—
0.7 × VCC
—
VCC + 0.3
V
VACC VCC = 3.0 V to 3.6 V
11.5
12.0
12.5
V
11.5
12.0
12.5
V
—
—
0.45
V
0.85 × VCCQ
—
—
V
2.3
—
2.5
V
Voltage for ACC Sector
Protection/Unprotection and
Program Acceleration
Voltage for Autoselect, and
Temporary Sector Unprotected
VID
VCC = 3.0 V to 3.6 V
Output Low Voltage Level
VOL
IOL = 4.0 mA, VCC = VCC Min,
VCCQ = VCCQ Min
Output High Voltage Level
VOH
IOH = –2.0 mA, VCC = VCC Min,
VCCQ = VCCQ Min
Low VCC Lock-Out Voltage
VLKO
—
*1 : The lCC current listed includes both the DC operating current and the frequency dependent component.
*2 : Maximum ICC values are tested with VCC = VCC Max and VCCQ = VCCQ Max.
*3 : ICC active while Embedded Erase or Embedded Program or Write Buffer Programming is in progress.
*4 : Automatic sleep mode enables the low power mode when address remain stable for tACC + 30 ns.
30
Unit
Min
µA
mA
MBM29PL65LM-90/10
2. AC Characteristics
• Read Only Operations Characteristics
Symbol
MBM29PL65LM-90*
MBM29PL65LM-10*
Min
Typ
Max
Min
Typ
Max
JEDEC
Standard
Condition
Read Cycle Time
tRC
tRC
—
90
—
—
100
—
—
ns
Address to Output Delay
tACC
tACC
CE = VIL,
OE = VIL
—
—
90
—
—
100
ns
Chip Enable to Output Delay
tCE
tCE
OE = VIL
—
—
90
—
—
100
ns
Page Read Cycle Time
tPRC
tPRC
—
25
—
—
30
—
—
ns
Page Address to Output Delay
tPACC
tPACC
CE = VIL,
OE = VIL
—
—
25
—
—
30
ns
Output Enable to Output Delay
tOE
tOE
—
—
—
25
—
—
30
ns
Chip Enable to Output High-Z
tDF
tDF
—
—
—
25
—
—
30
ns
—
0
—
—
0
—
—
ns
—
10
—
—
10
—
—
ns
Parameter
Output Enable
Hold Time
Read
Unit
Toggle and
Data Polling
tOEH
tOEH
Output Enable to Output High-Z
tDF
tDF
—
—
—
25
—
—
30
ns
Output Hold Time From Addresses,
CE or OE, Whichever Occurs First
tOH
tOH
—
0
—
—
0
—
—
ns
tREADY
tREADY
—
—
—
20
—
—
20
µs
RESET Pin Low to Read Mode
* : Test Conditions;
Input pulse levels
: 0.0 V / VCC
Input rise times
: 5 ns
Input fall times
: 5 ns
Timing measurement reference level
Input : 0.5 × VCC
Output : 0.5 × VCC
Output Load
: 1 TTL + 30 pF
•Test Conditions
3.3 V
Diode = 1N3064
or Equivalent
2.7 kΩ
Device
Under
Test
6.2 kΩ
CL
Diode = 1N3064
or Equivalent
31
MBM29PL65LM-90/10
• Write (Erase/Program) Operations
Symbol
MBM29PL65LM-90 MBM29PL65LM-10
Parameter
Unit
JEDEC Standard
Min
Typ
Max
Min
Typ
Max
Write Cycle Time
tWC
tWC
90
—
—
100
—
—
ns
Address Setup Time
tAS
tAS
0
—
—
0
—
—
ns
Address Setup Time to OE Low During
Toggle Bit Polling
tASO
tASO
15
—
—
15
—
—
ns
Address Hold Time
tAH
tAH
45
—
—
45
—
—
ns
Address Hold Time from CE or OE High
During Toggle Bit Polling
tAHT
tAHT
0
—
—
0
—
—
ns
Data Setup Time
tDS
tDS
35
—
—
35
—
—
ns
Data Hold Time
tDH
tDH
0
—
—
0
—
—
ns
Output Enable Setup Time
tOES
tOES
0
—
—
0
—
—
ns
CE High During Toggle Bit Polling
tCEPH
tCEPH
20
—
—
20
—
—
ns
OE High During Toggle Bit Polling
tOEPH
tOEPH
20
—
—
20
—
—
ns
Read Recover Time Before Write
(OE High to WE Low)
tGHWL
tGHWL
0
—
—
0
—
—
ns
Read Recover Time Before Write
(OE High to CE Low)
tGHEL
tGHEL
0
—
—
0
—
—
ns
CE Setup Time
tCS
tCS
0
—
—
0
—
—
ns
WE Setup Time
tWS
tWS
0
—
—
0
—
—
ns
CE Hold Time
tCH
tCH
0
—
—
0
—
—
ns
WE Hold Time
tWH
tWH
0
—
—
0
—
—
ns
CE Pulse Width
tCP
tCP
35
—
—
35
—
—
ns
Write Pulse Width
tWP
tWP
35
—
—
35
—
—
ns
CE Pulse Width High
tCPH
tCPH
25
—
—
25
—
—
ns
Write Pulse Width High
tWPH
tWPH
30
—
—
30
—
—
ns
—
23.5
—
—
23.5
—
µs
—
100
—
—
100
—
µs
Effective Page Programming Time
Per Word
(Write Buffer Programming)
tWHWH1
Programming Time
Sector Erase Operation *1
VCC Setup Time
tWHWH1
Word
tWHWH2
tWHWH2
—
1.0
—
—
1.0
—
s
tVCS
tVCS
50
—
—
50
—
—
µs
(Continued)
32
MBM29PL65LM-90/10
(Continued)
Symbol
Parameter
Rise Time to VID *2
Rise Time to V
ACC 3
*
Voltage Transition Time *
Write Pulse Width *
2
2
MBM29PL65LM-90
MBM29PL65LM-10
Unit
JEDEC
Standard
Min
Typ
Max
Min
Typ
Max
tVIDR
tVIDR
500
—
—
500
—
—
ns
tVACCR
tVACCR
500
—
—
500
—
—
ns
tVLHT
tVLHT
4
—
—
4
—
—
µs
tWPP
tWPP
100
—
—
100
—
—
µs
2
tOESP
tOESP
4
—
—
4
—
—
µs
2
CE Setup Time to WE Active *
tCSP
tCSP
4
—
—
4
—
—
µs
RESET Pulse Width
tRP
tRP
500
—
—
500
—
—
ns
RESET High Time Before Read
tRH
tRH
100
—
—
100
—
—
ns
Delay Time from Embedded Output
Enable
tEOE
tEOE
—
—
90
—
—
100
ns
Erase Time-out Time
tTOW
tTOW
50
—
—
50
—
—
µs
Erase Suspend Transition Time
tSPD
tSPD
—
—
20
—
—
20
µs
OE Setup Time to WE Active *
*1 : This does not include the preprogramming time.
*2 : This timing is for Sector Group Protection operation.
*3 : This timing is for Accelerated Program operation.
■ ERASE AND PROGRAMMING PERFORMANCE
Limits
Parameter
Unit
Remarks
Min
Typ
Max
Sector Erase Time
—
1
15
s
Programming Time
—
100
3000
µs
Effective Page Programming Time
(Write Buffer Programming)
—
23.5
—
µs
Chip Programming Time
—
—
600
s
Absolute Maximum
Programming Time (16 words)
—
—
6
ms
Non programming within the same
page
100,000
—
—
cycle
—
Erase/Program Cycle
Excludes programming time prior
to erasure
Excludes system-level overhead
■ TSOP (1) PIN CAPACITANCE
Parameter
Input Capacitance
Symbol
CIN
Test Setup
Value
Unit
Min
Typ
Max
VIN = 0
—
8
10
pF
Output Capacitance
COUT
VOUT = 0
—
8.5
12
pF
Control Pin Capacitance
CIN2
VIN = 0
—
8
10
pF
RESET pin and ACC Pin
Capacitance
CIN3
VIN = 0
—
20
25
pF
Note : Test conditions TA = +25°C, f = 1.0 MHz
DQ15 pin capacitance is stipulated by output capacitance.
33
MBM29PL65LM-90/10
■ TIMING DIAGRAM
• Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Must Be
Steady
Will Be
Steady
May
Change
from H to L
Will Be
Changing
from H to L
May
Change
from L to H
Will Be
Changing
from L to H
“H” or “L”
Any Change
Permitted
Changing
State
Unknown
Does Not
Apply
Center Line is
HighImpedance
“Off” State
(1) Read Operation Timing Diagram
tRC
Address
Address Stable
tACC
CE
tOE
tDF
OE
tOEH
WE
tCE
Data
34
High-Z
tOH
Output Valid
High-Z
MBM29PL65LM-90/10
(2) Page Read Operation Timing Diagram
A21 to A2
Address Valid
A1, A0
Aa
Ab
tRC
tPRC
Ac
tACC
CE
tCE
OE
tOEH
tOE
tDF
tPACC
WE
tOH
High-Z
Data
Da
tPACC
tOH
Db
tOH
Dc
(3) Hardware Reset Timing Diagram
tRC
Address
Address Stable
tACC
CE
tRH
tRP
tRH
tCE
RESET
tOH
Data
High-Z
Output Valid
35
MBM29PL65LM-90/10
(4) Alternate WE Controlled Program Operation Timing Diagram
3rd Bus Cycle
Data Polling
555h
Address
PA
tWC
tAS
PA
tRC
tAH
CE
tCH
tCS
tCE
OE
tGHWL
tWP
tWPH
tOE
tWHWH1
WE
tDS
A0h
Data
PA
PD
DQ7
DOUT
PD
DQ7
DOUT
: Address of the memory location to be programmed.
: Data to be programmed at word address.
: The output of the complement of the data written to the device.
: The output of the data written to the device
Note : Figure indicates the last two bus cycles out of four bus cycle sequence.
36
tOH
tDF
tDH
DOUT
MBM29PL65LM-90/10
(5) Alternate CE Controlled Program Operation Timing Diagram
3rd Bus Cycle
Address
Data Polling
PA
555h
tWC
tAS
PA
tAH
WE
tWS
tWH
OE
tGHEL
tCP
tCPH
tWHWH1
CE
tDS
tDH
Data
PA
PD
DQ7
DOUT
A0h
PD
DQ 7
D OUT
: Address of the memory location to be programmed.
: Data to be programmed at word address.
: The output of the complement of the data written to the device.
: The output of the data written to the device.
Note : Figure indicates the last two bus cycles out of four bus cycle sequence.
37
MBM29PL65LM-90/10
(6) Chip/Sector Erase Operation Timing Diagram
555h
Address
tWC
2AAh
tAS
555h
555h
2AAh
SA*
SA*
tAH
CE
tCS
tCH
OE
tGHWL
tWP
tWPH
tDS
tDH
tTOW
WE
AAh
Data
10h for Chip Erase
55h
80h
AAh
55h
10h/
30h
30h
tBUSY
RY/BY
tVCS
VCC
* : SA is the sector address for Sector Erase. Address = 555h (Word), AAAh (Byte) for Chip Erase.
38
MBM29PL65LM-90/10
(7) Erase Suspend Operation Timing Diagram
XXXh
Address
tWC
CE
tCS
tCH
tWP
WE
tDS
tSPD
B0h
Data
RY/BY
(8) Data Polling during Embedded Algorithm Operation Timing Diagram
VA
Address
CE
tCH
tDF
tOE
OE
tOEH
WE
4 ms
tCE
*
DQ7
Data
DQ7
DQ7 =
Valid Data
High-Z
tWHWH1 or 2
DQ6 to DQ0
Data
DQ6 to DQ0 =
Output Flag
DQ6 to DQ0
Valid Data
High-Z
tEOE
* : DQ7 = Valid Data (The device has completed the Embedded operation.)
Note : When checking Hardware Sequence Flags during program operations, it should be checked
4 µs after issuing program command.
39
MBM29PL65LM-90/10
(9) Toggle Bit l Timing Diagram during Embedded Algorithm Operations
Address
tAHT tASO
tAHT tAS
CE
tCEPH
WE
tOEPH
4 ms
tOEH
OE
tOE
tDH
DQ 6/DQ2
tCE
Toggle
Data
Data
Toggle
Data
*
Toggle
Data
Stop
Toggling
Output
Valid
* : DQ6 stops toggling (The device has completed the Embedded operation).
Note : When checking Hardware Sequence Flags during program operations, it should be checked
4 µs after issuing program command.
(10) DQ2 vs. DQ6
E nter
E m bedded
E rasing
WE
E rase
S uspend
E rase
E nter E rase
S uspend P rogram
E rase S uspend
R ead
E rase
S uspend
P rogram
DQ6
DQ2*
T oggle
D Q 2 and D Q 6
w ith O E or C E
* : DQ2 is read from the erase-suspended sector.
40
E rase
R esum e
E rase S uspend
R ead
E rase
E rase
C om plete
MBM29PL65LM-90/10
(11) RESET Timing Diagram ( Not during Embedded Algorithms )
CE, OE
tRH
RESET
tRP
tREADY
(12) RESET Timing Diagram ( During Embedded Algorithms )
tREADY
CE, OE
RESET
tRP
41
MBM29PL65LM-90/10
(13) Sector Group Protection Timing Diagram
A21, A20, A19
A18, A17
SGAX
SGAY
A6, A3, A2, A0
A1
VID
VIH
A9
tVLHT
VID
VIH
OE
tVLHT
tVLHT
tVLHT
tWPP
WE
tOESP
tCSP
CE
Data
01h
tVCS
VCC
SGAX : Sector Group Address to be protected
SGAY : Next Sector Group Address to be protected
42
tOE
MBM29PL65LM-90/10
(14) Temporary Sector Group Unprotection Timing Diagram
VCC
tvCS tVIDR
tVLHT
VID
VSS, VIL or VIH
RESET
CE
WE
tVLHT
Program or Erase Command Sequence
tVLHT
Unprotection period
43
MBM29PL65LM-90/10
(15) Extended Sector Group Protection Timing Diagram
V CC
tV C S
RESET
t V LH T
t V ID R
A ddress
SGAX
SGAX
SGAY
A 6, A 3, A 2, A 0
A1
CE
OE
T IM E -O U T
WE
D ata
60h
60h
40h
01h
tO E
SGAX
SGAY
: Sector Group Address to be protected
: Next Sector Group Address to be protected
TIME-OUT : Time-Out window = 250 ms (Min)
44
60h
MBM29PL65LM-90/10
(16) Accelerated Program Timing Diagram
VCC
tVACCR
tVCS
tVLHT
VACC
ACC
CE
WE
tVLHT
Program Command Sequence
tVLHT
Acceleration period
45
MBM29PL65LM-90/10
■ FLOW CHART
(1) Embedded ProgramTM Algorithm
EMBEDDED ALGORITHMS
Start
Write Program
Command Sequence
(See Below)
Data Polling
No
Increment Address
No
Verify Data
?
Yes
Embedded
Program
Algorithm
in progress
Last Address
?
Yes
Programming Completed
Program Command Sequence (Address/Command):
555h/AAh
2AAh/55h
555h/A0h
Program Address/Program Data
46
MBM29PL65LM-90/10
(2) Embedded EraseTM Algorithm
EMBEDDED ALGORITHMS
Start
Write Erase
Command Sequence
(See Below)
Data Polling
No
Data = FFh
?
Yes
Embedded
Erase
Algorithm
in progress
Erasure Completed
Chip Erase Command Sequence
(Address/Command):
Individual Sector/Multiple Sector
Erase Command Sequence
(Address/Command):
555h/AAh
555h/AAh
2AAh/55h
2AAh/55h
555h/80h
555h/80h
555h/AAh
555h/AAh
2AAh/55h
2AAh/55h
555h/10h
Sector Address
/30h
Sector Address
/30h
Sector Address
/30h
Additional sector
erase commands
are optional.
47
MBM29PL65LM-90/10
(3) Data Polling Algorithm
Start
Wait 4 ms after
issuing Program
command
Read Byte
(DQ 7 to DQ 0)
Addr. = VA
DQ 7 = Data?
Yes
No
No
DQ 5 = 1?
Yes
Read Byte
(DQ 7 to DQ 0)
Addr. = VA
DQ 7 = Data?
*
Yes
No
Fail
VA
Pass
= Valid address for programming
= Any of the sector addresses within the sector being erased during sector erase or multiple sector
erases operation
= Any of the sector addresses within the sector not being protected during chip erase operation
(There may not be accurate indications to determine that the data polling has been completed.)
* : DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
48
MBM29PL65LM-90/10
(4) Toggle Bit Algorithm
Start
Wait 4 s after
issuing Program
command
Read DQ7 to DQ0
Addr. = "H" or "L"
*1
Read DQ7 to DQ0
Addr. = "H" or "L"
DQ6
= Toggle?
No
Yes
No
DQ5 = 1?
Yes
*1, *2
Read DQ7 to DQ0
Addr. = "H" or "L"
*1, *2
Read DQ7 to DQ0
Addr. = "H" or "L"
DQ6
= Toggle?
No
Yes
Program/Erase
Operation Not
Complete.Write
Reset Command
Program/Erase
Operation
Complete
*1 : Read Toggle bit twice to determine whether it is toggling.
*2 : Recheck Toggle bit because it may stop toggling as DQ5 changes to “1”.
49
MBM29PL65LM-90/10
(5) Sector Group Protection Algorithm
Start
Setup Sector Group Addr.
(A21, A20, A19, A18, A17)
PLSCNT = 1
OE = VID, A9 = VID
CE = VIL, RESET = VIH
A6 = A3 = A2 = A0 = VIL, A1 = VIH
Activate WE Pulse
Increment PLSCNT
Time out 100 µs
WE = VIH, CE = OE = VIL
(A9 should remain VID)
Read from Sector Group
Addr. = SGA, A1 = VIH
A6 = A3 = A2 = A0 = VIL
(
)
No
PLSCNT = 25?
Yes
Remove VID from A9
Write Reset Command
No
Data = 01h?
Yes
Protect Another Sector
Group?
No
Device Failed
Remove VID from A9
Write Reset Command
Sector Group Protection
Completed
50
Yes
MBM29PL65LM-90/10
(6) Temporary Sector Group Unprotection Algorithm
Start
RESET = VID *1
Perform Erase or
Program Operations
RESET = VIH
Temporary Sector Group
Unprotection Completed
*2
*1 : All protected sector groups are unprotected.
*2 : All previously protected sector groups are protected.
51
MBM29PL65LM-90/10
(7) Extended Sector Group Protection Algorithm
Start
RESET = VID
Wait to 4 µs
Device is Operating in
Temporary Sector Group
Unprotection Mode
No
Extended Sector Group
Protection Entry?
Yes
To Setup Sector Group
Protection Write XXXh/60h
PLSCNT = 1
To Protect Sector Group
Write 60h to Sector Address
(A6 = A3 = A2 = A0 =VIL, A1 = VIH)
Time Out 250 µs
Increment PLSCNT
To Verify Sector Group Protection
Write 40h to Sector Address
(A6 = A3 = A2 = A0 =VIL, A1 = VIH)
Setup Next Sector Group
Address
Read from Sector Group
Address
(A6 = A3 = A2 = A0 =VIL, A1 = VIH)
No
No
PLSCNT = 25?
Yes
Remove VID from RESET
Write Reset Command
Data = 01h?
Yes
Yes
Protection Other Sector
Group ?
No
Device Failed
Remove VID from RESET
Write Reset Command
Sector Group Protection
Completed
52
MBM29PL65LM-90/10
(8) Embedded ProgramTM Algorithm for Fast Mode
FAST MODE ALGORITHM
Start
555h/AAh
Set Fast Mode
2AAh/55h
555h/20h
XXXh/A0h
Program Address/Program Data
Data Polling
Verify Data?
No
In Fast Program
Yes
Increment Address
No
Last Address
?
Yes
Programming Completed
XXXh/90h
Reset Fast Mode
XXXh/F0h
Note : The sequence is applied for Word ( ×16 ) mode.
53
MBM29PL65LM-90/10
■ ORDERING INFORMATION
Part No.
MBM29PL65LM90TN
MBM29PL65LM10TN
MBM29PL65LM
Package
Access Time (ns)
48-pin, plastic TSOP (1)
(FPT-48P-M19)
(Normal Bend)
90 ns
90
Remarks
100 ns
TN
PACKAGE TYPE
TN = 48-Pin Thin Small Outline Package
(TSOP(1)) Standard Pinout
SPEED OPTION
90 = 90 ns access time
10 = 100 ns access time
DEVICE NUMBER/DESCRIPTION
64 Mega-bit (8M × 16)
3.0 V-only Page Mode MirrorFlash
54
MBM29PL65LM-90/10
■ PACKAGE DIMENSION
Note 1) * : Values do not include resin protrusion.
Resin protrusion and gate protrusion are +0.15(.006)Max(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
48-pin plastic TSOP(1)
(FPT-48P-M19)
LEAD No.
1
48
INDEX
Details of "A" part
0.25(.010)
0~8˚
0.60±0.15
(.024±.006)
24
25
* 12.00±0.20
20.00±0.20
(.787±.008)
* 18.40±0.20
(.724±.008)
"A"
0.10(.004)
(.472±.008)
+0.10
1.10 –0.05
+.004
.043 –.002
(Mounting
height)
+0.03
0.17 –0.08
+.001
.007 –.003
C
0.10±0.05
(.004±.002)
(Stand off height)
0.50(.020)
0.22±0.05
(.009±.002)
0.10(.004)
M
2003 FUJITSU LIMITED F48029S-c-6-7
Dimensions in mm (inches)
Note : The values in parentheses are reference values.
55
MBM29PL65LM-90/10
FUJITSU LIMITED
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F0312
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