ON NUP8011MUTAG Transient voltage suppressor Datasheet

NUP8011MU
Transient Voltage Suppressors
ESD Protection Diodes with Low
Clamping Voltage Array
This integrated transient voltage suppressor device (TVS) is
designed for applications requiring transient overvoltage protection. It
is intended for use in sensitive equipment such as computers, printers,
business machines, communication systems, and other applications.
Its integrated design provides very effective and reliable protection for
eight separate lines using only one package. These devices are ideal
for situations where board space is at a premium.
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Features
•
•
•
•
•
•
•
Low Clamping Voltage
UDFN Package, 1.2 x 1.8 mm
Standoff Voltage: 4.3 V
Low Leakage Current
IEC61000−4−2, Level 4 ESD Protection
Moisture Sensitivity Level 1
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Benefits
•
•
•
•
Provides Protection for ESD Industry Standards: IEC 61000, HBM
Protects the Line Against Transient Voltage Conditions
Minimize Power Consumption of the System
Minimize PCB Board Space
(Top View)
Applications
•
•
•
•
•
MARKING
DIAGRAM
8
1
ESD Protection for Data Lines
Wireless Phones
Handheld Products
Notebook Computers
LCD Displays
UDFN8
CASE 517AD
P3
M
G
1
P3 M
G
= Specific Device Code
= Month Code
= Pb−Free Package
MAXIMUM RATINGS (TA = 25°C unless otherwise noted)
Characteristic
Symbol
Value
Unit
Steady State Power − 1 Diode (Note 1)
PD
380
mW
Thermal Resistance,
Junction−to−Ambient
Above 25°C, Derate
RqJA
327
3.05
°C/W
mW/°C
Maximum Junction Temperature
TJmax
150
°C
Operating Temperature Range
TOP
−40 to +85
°C
Storage Temperature Range
Tstg
−55 to +150
°C
Lead Solder Temperature (10 seconds
duration)
TL
260
°C
$8.0
kV
IEC 61000−4−2 (ESD)Contact
Machine Model − Class C
MM
400
V
Human Body Model − Class 3B
HBM
8.0
kV
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Only 1 diode under power. For all 4 diodes under power, PD will be 25%.
Mounted on FR−4 board with min pad.
See Application Note AND8308/D for further description of
survivability specs.
© Semiconductor Components Industries, LLC, 2017
February, 2017 − Rev. 3
1
PIN CONNECTIONS
1
4
8
5
ORDERING INFORMATION
Device
NUP8011MUTAG
Package
UDFN8
(Pb−Free)
Shipping
3000 / Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
NUP8011MU/D
NUP8011MU
ELECTRICAL CHARACTERISTICS
I
(TA = 25°C unless otherwise noted)
IF
Parameter
Symbol
IPP
Maximum Reverse Peak Pulse Current
VC
Clamping Voltage @ IPP
VRWM
IR
IR VF
IT
Maximum Reverse Leakage Current @ VRWM
VBR
V
Breakdown Voltage @ IT
IT
Test Current
IF
Forward Current
VF
Forward Voltage @ IF
Ppk
Peak Power Dissipation
C
VC VBR VRWM
Working Peak Reverse Voltage
IPP
Uni−Directional
Capacitance @ VR = 0 and f = 1.0 MHz
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
ELECTRICAL CHARACTERISTICS (TA = 25°C)
Breakdown Voltage
VBR @ 1 mA (V)
Leakage Current
IRM @ VRM
Typ Capacitance
@ 0 V Bias (pF)
(Note 2)
Typ Capacitance
@ 3 V Bias (pF)
(Note 2)
Device
Device
Marking
Min
Nom
Max
VRWM
IRWM
(mA)
Typ
Max
Typ
Max
NUP8011MUTAG
P3
6.47
6.8
7.14
4.3
1.0
12
14
6.7
9.5
VC
Per IEC61000−4−2
(Note 3)
Figures 1 and 2
(See Below)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Capacitance of one diode at f = 1 MHz, VR = 0 V, TA = 25°C
3. For test procedure see Figures 3 and 4 and Application Note AND8307/D.
Figure 1. ESD Clamping Voltage Screenshot
Positive 8 kV Contact per IEC61000−4−2
Figure 2. ESD Clamping Voltage Screenshot
Negative 8 kV Contact per IEC61000−4−2
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NUP8011MU
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
Ipeak
Level
Test Voltage (kV)
First Peak
Current
(A)
Current at
30 ns (A)
Current at
60 ns (A)
1
2
7.5
4
2
2
4
15
8
4
3
6
22.5
12
6
4
8
30
16
8
100%
90%
I @ 30 ns
I @ 60 ns
10%
tP = 0.7 ns to 1 ns
Figure 3. IEC61000−4−2 Spec
ESD Gun
Oscilloscope
TVS
50 W
Cable
50 W
Figure 4. Diagram of ESD Test Setup
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
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NUP8011MU
TYPICAL ELECTRICAL CHARACTERISTICS
TYPICAL CAPACITANCE (pF)
1 MHz FREQUENCY
14
4.0
3.0
2.0
1.0
0
−100
12
TA = 25°C
10
8
6
4
2
0
−50
0
100
50
150
0
1
2
3
4
T, TEMPERATURE (°C)
BIAS VOLTAGE (V)
Figure 5. Reverse Leakage versus
Temperature
Figure 6. Capacitance
1
IF, FORWARD CURRENT (A)
IR, REVERSE LEAKAGE (nA)
5.0
0.1
0.01
TA = 25°C
0.001
0.6
0.8
1.0
1.2
1.4
VF, FORWARD VOLTAGE (V)
Figure 7. Forward Voltage
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1.6
1.8
5
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NUP8011MU
PACKAGE DIMENSIONS
UDFN8, 1.8x1.2, 0.4P
CASE 517AD
ISSUE D
A
B
D
2X
0.10 C
PIN ONE
REFERENCE
2X
ÉÉÉ
ÉÉÉ
ÇÇ
ÉÉ
MOLD CMPD
EXPOSED Cu
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30 mm FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
A3
A1
E
DETAIL B
ALTERNATE
CONSTRUCTIONS
0.10 C
DIM
A
A1
A3
b
D
E
e
D2
E2
J
K
L
L1
TOP VIEW
0.05 MIN
A
DETAIL B
0.05 C
(A3)
(0.10)
8X
0.05 C
DETAIL A
A1
NOTE 4
C
SIDE VIEW
L
J
DETAIL A
8X
SEATING
PLANE
L1
D2
L
1
E2
SOLDERING FOOTPRINT*
8
K
e
e/2
1.10
DETAIL A
OPTIONAL
CONSTRUCTION
8X
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.13 REF
0.15
0.25
1.80 BSC
1.20 BSC
0.40 BSC
0.90
1.10
0.20
0.30
0.19 REF
0.20 TYP
0.20
0.30
−−−
0.10
7X
8X
0.25
0.45
PACKAGE
OUTLINE
8X b
0.10 C A B
0.05 C
NOTE 3
1.50
BOTTOM VIEW
0.35
1
0.35
0.40 PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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