Revised April 2005 74VHC240 Octal Buffer/Line Driver with 3-STATE Outputs General Description Features The VHC240 is an advanced high speed CMOS octal bus buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The VHC240 is an inverting 3-STATE buffer having two active-LOW output enables. This device is designed to drive buslines or buffer memory address registers. ■ High Speed: tPD An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages. 3.6ns (typ) at TA 25qC ■ Low power dissipation: ICC 4 PA (max) @ TA ■ High noise immunity: VNIH VNIL 25qC 28% VCC (min) ■ Power down protection is provided on all inputs ■ Low noise: VOLP 0.9V (max) ■ Pin and function compatible with 74HC240 Ordering Code: Order Number Package Number 74VHC240M 74VHC240SJ 74VHC240MTC 74VHC240N Package Description M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MTC20 N20A 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Logic Symbol Connection Diagram IEEE/IEC © 2005 Fairchild Semiconductor Corporation DS011506 www.fairchildsemi.com 74VHC240 Octal Buffer/Line Driver with 3-STATE Outputs October 1992 74VHC240 Pin Descriptions Pin Names Description OE1, OE2 3-STATE Output Enable Inputs I0–I7 Inputs O0–O7 Outputs 3-STATE Outputs Truth Tables Inputs Outputs OE1 In (Pins 12, 14, 16, 18) L L H L H L H X Z Inputs Outputs OE1 In (Pins 3, 5, 7, 9) L L H L H L H X Z H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance www.fairchildsemi.com 2 Recommended Operating Conditions (Note 2) 0.5V to 7.0V 0.5V to 7.0V 0.5V to VCC 0.5V 20 mA r20 mA r25 mA r75 mA 65qC to 150qC Supply Voltage (VCC ) DC Input Voltage (VIN) DC Output Voltage (VOUT) Input Diode Current (IIK) Output Diode Current (IOK) DC Output Current (IOUT) DC VCC /GND Current (ICC ) Storage Temperature (TSTG) 2.0V to 5.5V 0V to 5.5V Output Voltage (VOUT) 0V to VCC 40qC to 85qC Operating Temperature (TOPR) Input Rise and Fall Time (tr, tf) Lead Temperature (TL) VCC 3.3V r 0.3V 0 ns/V a 100 ns/V VCC 5.0V r 0.5V 0 ns/V a 20 ns/V Note 1: Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables.Fairchild does not recommend operation outside databook specifications. 260qC (Soldering, 10 seconds) Supply Voltage (VCC) Input Voltage (VIN) Note 2: Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIH VOL IOZ TA Min 25qC Typ 40qC to 85qC TA Max Min 2.0 1.50 1.50 3.0 5.5 0.7 VCC 0.7 VCC LOW Level Input Voltage VOH (V) HIGH Level Input Voltage VIL VCC Parameter Max 2.0 0.50 0.50 0.3 VCC 0.3 VCC 2.0 1.9 2.0 1.9 Output Voltage 3.0 2.9 3.0 2.9 4.5 4.4 4.5 3.0 2.58 2.48 4.5 3.94 3.80 Conditions V 3.0 5.5 HIGH Level Units V V VIN VIH IOH 4.4 0.0 0.1 IOH V LOW Level Output 2.0 Voltage 3.0 0.0 0.1 0.1 4.5 0.0 0.1 0.1 0.1 IOH VIN V VIH IOL or VIL 0.36 0.44 0.36 0.44 5.5 r0.25 r2.5 PA VIN 0 5.5 r0.1 r1.0 PA VIN 5.5V or GND 5.5 4.0 40.0 PA VIN VCC or GND V VOUT ICC Quiescent Supply Current 8 mA 50 PA 3.0 Off-State Current Input Leakage Current 4 mA 4.5 3-STATE Output IIN 50 PA or VIL IOL 4 mA IOL 8 mA VIH or VIL VCC or GND Noise Characteristics Symbol Parameter VCC TA 25qC (V) Typ Limits Units Conditions VOLP (Note 3) Quiet Output Maximum Dynamic VOL 5.0 0.6 0.9 V CL 50 pF VOLV (Note 3) Quiet Output Minimum Dynamic VOL 5.0 0.6 0.9 V CL 50 pF VIHD (Note 3) Minimum HIGH Level Dynamic Input Voltage 5.0 3.5 V CL 50 pF VILD (Note 3) Maximum LOW Level Dynamic Input Voltage 5.0 1.5 V CL 50 pF Note 3: Parameter guaranteed by design. 3 www.fairchildsemi.com 74VHC240 Absolute Maximum Ratings(Note 1) 74VHC240 AC Electrical Characteristics Symbol Parameter tPLH Propagation tPHL Delay Time VCC TA (V) Min 3.3 r 0.3 5.0 r 0.5 tPZL 3-STATE tPZH Output Enable Time 3.3 r 0.3 5.0 r 0.5 25qC TA 40qC to 85qC Typ Max Min Max 5.3 7.5 1.0 9.0 7.8 11.0 1.0 12.5 3.6 5.5 1.0 6.5 5.1 7.5 1.0 8.5 6.6 10.6 1.0 12.5 9.1 14.1 1.0 16.0 4.7 7.3 1.0 8.5 6.2 9.3 1.0 10.5 10.3 14.0 1.0 16.0 9.2 1.0 10.5 tPLZ 3-STATE 3.3 r 0.3 tPHZ Output Disable Time 5.0 r 0.5 tOSLH Output to 3.3 r 0.3 1.5 1.5 tOSHL Output Skew 5.0 r 0.5 1.0 1.0 CIN Input Capacitance 10 10 COUT Output Capacitance CPD Power Dissipation 6.7 Units Conditions ns ns ns RL 1 k: ns ns RL 1 k: ns (Note 4) pF VCC Open 6 pF VCC 5.0V 17 pF (Note 5) 4 CL 15 pF CL 50 pF CL 15 pF CL 50 pF CL 15 pF CL 50 pF CL 15 pF CL 50 pF CL 50 pF CL 50 pF CL 50 pF CL 50 pF Capacitance Note 4: Parameter guaranteed by design. tOSLH |tPLHmax tPLHmin|; tOSHL |tPHLmax tPHLmin| Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr.) C PD * VCC * fIN ICC/8 (per bit). www.fairchildsemi.com 4 74VHC240 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5 www.fairchildsemi.com 74VHC240 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.com 6 74VHC240 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 7 www.fairchildsemi.com 74VHC240 Octal Buffer/Line Driver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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