TOSHIBA TB1308FG

TB1305FG, TB1308FG
TOSHIBA BiCMOS Integrated Circuit Silicon Monolithic
TB1305FG,TB1308FG
Component SW, Sync Separation and H/V Frequency Counter IC for TVs
The TB1305FG and TB1308FG include a component SW block, a
prefilter for AD conversion, sync separation and H/V format
detectors for TV component video signals.
The TB1305FG and TB1308FG contribute to reduction in the
proportion of PCB occupied by LCR filters and to the simplification of
designs on analog interfaces.
2
The TB1305FG and TB1308FG are equipped with an I CBUS
interface through which various functions can be controlled.
P-QFP48-1014-0.80
Weight: 0.83 g (typ.)
Features
COMPONENT BLOCK
・ Component video input: TB1305FG 2 channels, TB1308FG 3 channels; RGB available
・ Component video output
・ Gain switching: 0dB / +6dB
・ Bandwidth filter: prefilter for ADC; 4.2 to 31MHz variable)
SYNC SEPARATION BLOCK
・ Supports 525/60i/60p, 625/50i/50p, 750/50p/60p, 1125/50i/60i/50p/60p, 1250/50i,
VGA @60, SVGA@60, XGA@60, SXGA@60, UXGA@60
・ HD/VD input: 2 channels; positive and negative input acceptable
・ HD/VD output: positive and negative output selectable
・ Masking pseudo-sync for copyguard signal
OTHERS
・ Line detector for D-pin (2 channels)
・ Horizontal and vertical frequency counter
・ Format detection circuit for input signal
・ Automatic sync process switching mode
Lineup
Part No.
Number of component video inputs
TB1305FG
2
TB1308FG
3
1
2007-07-11
TB1305FG, TB1308FG
Block Diagram
IICBUS
LINE1
DET
VD2-IN
BIAS
HD2-IN
BIAS
ADDRESS
LINE2
DET
LINE3
DET
IICBUS
VD-OUT
POL
HD-OUT
POL
H-C/D
V-C/D
FREQ COUNT
DUMMY SYNC
H Vcc
+6dB AMP
MUTE
SYNC TIP
/BIAS
Y1/G1-IN
LINE2-1
BAND
WIDTH
BIAS
YCbCr SW
NC
(SYNC3-IN)
LINE1-1
YCbCr SW
+6dB AMP
MUTE
SYNC1-IN
NC
BAND
WIDTH
Vf0ADJ
Cr-OUT
SYNC TIP
CLAMP
YCbCr SW
+6dB AMP
MUTE
Cr2/R2-IN
SW LINE2
BAND
WIDTH
H GND
Cb2/B2-IN
LINE3-2
SYNC SW
H/V
SEP
SYNC SW
Cb-OUT
BIAS
BIAS
V SEP
Y2/G2-IN
LINE2-2
SW
DET
SYNC-OUT
Y-OUT
SYNC TIP
/BIAS
Cb1/B1-IN
LINE3-1
SYNC TIP
CLAMP
BIAS
Cr1/R1-IN
NOTE: Pins 38, 39, 41 and 43 are available for the TB1308FG only. The pins are NC for the TB1305FG.
The TB1305FG and TB1308FG do not support weak signals, ghost signals or other non-standard signals.
Some functional blocks, circuits or constants may be omitted or simplified in the block diagram for explanatory purposes.
2
2007-07-11
TB1305FG, TB1308FG
Pin Functions
The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes.
Pin
No.
Pin Name
Function
Interface Circuit
Input Signal/Output Signal
31
3.3V
VCC pin for the logical circuits.
50Ω
DIG VCC
Supply power through a resistor from pin 31
like the Application Circuit. This pin voltage
is clipped to 3.3 V (typ.) by the internal
regulator.
50Ω
22
500Ω
22
3.3 V (typ.)
33
20
DIG GND
31
H VCC
33
H GND
46
C VCC
44
C GND
GND pin for the logical circuits.
VCC pin for the sync circuits.
Connect 5.0 V (typ.)
GND pin for the sync circuits.
VCC pin for the video circuits.
Connect 5.0 V (typ.)
GND pin for the video circuits.
⎯
⎯
⎯
5.0 V (typ.)
⎯
⎯
⎯
5.0 V (typ.)
⎯
⎯
Y or G input pin.
39
Y3/G3-IN
The clamp system is selectable by CLAMP
register.
5
14
(39)
47
NOTE: Pin 39 is not available for the
TB1305FG. It is an NC pin.
Y or CVBS input pin.
47
Y-IN
Input the Y or CVBS signal in NTSC, PAL or
SECAM from an AV-SW via a clamp
capacitor.
200Ω
100kΩ
Sync tip level: 2.1 V (typ.)
The clamp system is selectable by CLAMP
register.
Cb/Cr, Pb/Pr or B/R input pin.
10
Cr2/R2-IN
Input the signal via a capacitor.
12
Cb2/B2-IN
43
Cr3/R3-IN
NOTE: Pins 41 and 43 are not available for
the TB1305FG. They are NC pins.
41
Cb3/B3-IN
Y/CVBS signal’s amplitude:
1.0 Vp-p (with sync)
2.7 V bias (typ.)
100kΩ
RGB/YCbCr/YPbPr signal
amplitude:
0.7 Vp-p (without sync)
44
1.7 V bias (typ.)
5V
Chroma signal input pin.
C
45
3.6V
200Ω
1.7V (typ)
1.5V
When this pin’s voltage is High, TEST mode
for shipping is active. The pin voltage must
be less than 3.6 V during operating.
Prohibited
30.2kΩ
Input C signal from AV-SW via a capacitor.
C-IN
Bias level: 2.7 V (typ.)
200Ω
46
45
44
46
1
3
10
12
(43)
(41)
12kΩ
Cb1/B1-IN
2.8V
Cr1/R1-IN
3
200Ω
1
Bias level: 2.7 V (typ.)
RGB/YCbCr/YPbPr signal
amplitude:
0.7 Vp-p (without sync)
12kΩ
Y2/G2-IN
2.8V
14
Sync tip level: 2.1 V (typ.)
46
200Ω
Input the signal via a clamp capacitor.
200Ω
Y1/G1-IN
2.9V/1.5V
5
TEST
44
0V
Sync tip level: 1.75 V (typ.)
8
SYNC1-IN
16
SYNC2-IN
38
SYNC3-IN
10kΩ
31
Composite SYNC input pin to separate into
H- and V-SYNC.
Input the signal via a resister and a clamp
capacitor.
1Vp-p
or
8
16
(38)
NOTE: Pin 38 is not available for the
TB1305FG. It is an NC pin.
33
3
1Vp-p
2007-07-11
TB1305FG, TB1308FG
Pin
No.
Pin Name
Function
Interface Circuit
Input Signal/Output Signal
HD input pin.
HD2-IN
The polarity of the input signal is detected
and its leading edge becomes a timing
trigger.
23
24
25
26
VD input pin.
VD1-IN
25
VD2-IN
6
LINE1-1
LINE1 (number of lines) detection pin.
15
LINE1-2
Connect LINE1 of D-pin.
11
LINE3-2
Connect LINE3 of D-pin.
4
LINE2-1
LINE2 (i/p) detection pin.
20kΩ
150kΩ
2
6
11
15
200Ω
SW LINE1
SW LINE detection pin.
9
SW LINE2
Connect SW LINE of D-pin.
32
Y-OUT
Y, G or CVBS signal output pin.
34
Cb-OUT
Cb, Pb, B or C signal output pin.
36
Cr-OUT
Cr, Pr or R signal output pin.
28
SYNC-OUT
Separated composite sync output pin.
1kΩ
Th1
Th2
DC
44
46
4
9
13
48
Connect LINE2 of D-pin.
48
DC
200Ω
DC
1kΩ
10kΩ
LINE3 (aspect ratio) detection pin.
46
150kΩ
LINE3-1
LINE2-2
or
20
The polarity of the input signal is detected
and its leading edge becomes a timing
trigger.
2
13
200Ω
Input a separated vertical sync signal (1.0 to
2.0 Vp-p) via a resister and a coupling
capacitor.
23
1.45 V bias (typ.)
22
20kΩ
26
Input a separated horizontal sync signal
(1.0 to 2.0 Vp-p) via a resister and a
coupling capacitor.
10kΩ
HD1-IN
40kΩ
24
44
DC
46
32
34
36
100Ω
AC: 0 dB or +6 dB (typ.)
44
3.4V(typ.)
250Ω
31
VD-OUT
30
HD-OUT
28
29
30
The polarity of the output is selectable by
HV-POL register.
3.4V(typ.)
0.1V(typ.)
100Ω
3.3kΩ
HD or VD output pin.
29
The tailing edge of the VD-OUT has a jitter.
Use the leading edge only.
0.1V(typ.)
or
33
3.4V(typ.)
0.1V(typ.)
31
17
42
DAC1
DAC2
17
42
1-bit DAC output pin.
Open-collector pin.
100Ω
100Ω
TEST
DC
DAC
33
4
2007-07-11
TB1305FG, TB1308FG
Pin
No.
Pin Name
Function
Interface Circuit
Input Signal/Output Signal
31
500Ω
Crystal connection pin.
21
XTAL
2.5kΩ
21
Connect a 3.579545 MHz crystal for NTSC
demodulation to generate internal clocks.
⎯
33
46
35
Vf0ADJ
35
A filter pin to adjust bandwidth filter
characteristics.
200Ω
⎯
200Ω
44
1kΩ
46
40
BIAS FIL
A filter pin for internal bias circuits.
40
⎯
1kΩ
800Ω
44
31
22
18
SDA
Th: 2.25V(typ.)
Th: 1.50V(typ.)
SDA
SDA pin for I2CBUS.
5kΩ
18
H to L: 1.50 V (typ.)
L to H: 2.25 V (typ.)
50Ω
ACK
20
31
22
19
SCL
Th: 2.25V(typ.)
Th: 1.50V(typ.)
SCL pin for I2CBUS.
19
5kΩ
H to L: 1.50 V (typ.)
L to H: 2.25 V (typ.)
20
Connect to 5 V Vcc or GND. Or leave this
pin open.
27
1kΩ
40Ω
ADDRESS
Th1
Th2
10kΩ
Slave address switching pin.
27
20kΩ
60kΩ
20kΩ
46
5 V Vcc:
DCH/DDH
Open:
DAH/DBH
GND:
D8H/D9H
44
These pins are not used.
7
37
NC
Connect to GND.
⎯
NOTE: Pins 38, 39, 41 and 43 of the
TB1305FG are not used . Connect them to
GND.
5
⎯
2007-07-11
TB1305FG, TB1308FG
BUS Control Map
Write Mode
Slave address: D8H
/ DAH / DCH
SA
D7
D6
D5
D4
D3
00
MUTE
FILPASS
HD WIDTH
DAC2
DAC1
01
f0 SW
02
fc HALF
03
HV-SEP
D2
D1
YCbCr SW
D0
PRESET
GAIN
00000000
BANDWIDTH
00000000
SYNC SW
VGA-SEP
1(PS MASK)
HV FREQ
A SYNC
S MODE
CLAMP
00000000
HV-POL
VD PHS
00000000
NOTE: Set PS MASK = 1 (ON) for except “Sync on G” input.
Remark: SA = Sub-Address.
Read Mode
Slave address: D9H
D7
0
D6
LINE1
D4
LINE2
1
HD-POL
VD-POL
2
H FM2
V FM2
3
∗
4
D5
/ DBH / DDH
D3
LINE3
D2
D1
D0
SW LINE1
SW LINE2
∗
H FORMAT
H IN
V IN
V-SYNC-W
V FORMAT
∗
VERSION
V FREQ DET
H FREQ DET
∗: Undefined
6
2007-07-11
TB1305FG, TB1308FG
Bus Control Functions
Write Mode
Register Name
MUTE
FILPASS
Function
Swtches mute mode.
Preset Value
NORMAL
0: NORMAL
1: Video mute
Switches the bandwidth limit filter.
(0)
ON
0: ON (by-pass)
1: OFF
(0)
Switches the width of HD-OUT.
HD WIDTH
0: WIDE
1: NARROW
Remark: HD WIDTH = 1 (NARROW) is recommended for the 1125/50p/60p format
owing to crosstalk from HD-OUT to video signals so that spike noises on video
signals will occur.
WIDE
(0)
1-bit DAC switching
DAC1,2
Output voltages of DAC1 (pin 17) and DAC2 (pin 42) are controlled. DAC1/2 are
open-collector pins.
0: LOW (ON)
LOW
(0)
1: HIGH (OPEN)
Switches the component video input and line input
00: Y1 / Cb1 / Cr1 / LINE1, 2, 3-1 (pins 1, 2, 3, 4, 5, 6)
YCbCr SW
01: Y2 / Cb2 / Cr2 / LINE1, 2, 3-2 (pins 10, 11, 12, 13, 14, 15)
10: Y / C (pins 45, 47. Cr-out is muted.)
Y1 / Cb1 / Cr1
(00)
11: Y3 / Cb3 / Cr3 (pins 39, 41, 43)
NOTE: The data (11) is not available for the TB1305FG.
Switches the output gain.
Gain of YCbCr output (pins 32, 34, 36) is controlled.
GAIN
0: 0 dB
1: +6 dB
0 dB
(0)
Remark: GAIN = 0 (0 dB) is recommended for the 1125/50p/60p format since this
offers superior frequency characteristics to those of +6 dB mode.
f0 SW
Switches the f0 of bandwidth limit filter
0: HIGH
HIGH
1: LOW
Switches the f0 of bandwidth limit filter
BANDWIDTH
MIN
0000000: MIN (low)
(0000000)
1111111: MAX (high)
Switches the frequency of bandwidth limit filters for Cb/Cr
fc HALF
The cutoff frequency of bandwidth limit filters for Cb/Cr is 1/2 to Y.
0: OFF (same for 3 outputs)
(0)
1: ON (1/2 fc for Cb/Cr)
7
OFF
(0)
2007-07-11
TB1305FG, TB1308FG
Register Name
Function
Preset Value
Switches sync input.
Sync input to HD/VD-OUT and to SYNC-OUT is selected.
HD OUT (pin 30)
VD OUT (pin 29)
000
SYNC SW
SYNC OUT (pin 28)
SYNC1 (pin 8)
001
SYNC2 (pin 16)
010
SYNC3 (pin 38: TB1308FG only)
011
Not available
SYNC1
100
HD1 (pin 24)
VD1 (pin 23)
SYNC1 (pin 8)
101
HD2 (pin 26)
VD2 (pin 25)
SYNC2 (pin 16)
110
HD1 (pin 24)
VD1 (pin 23)
SYNC3
(pin 38 : TB1308FG only)
111
HD2 (pin 26)
VD2 (pin 25)
SYNC3
(pin 38: TB1308FG only)
(000)
NOTE: SYNC3 of the data 010, 110, 111 is not available for the TB1305FG.
Input format setting
Set the horizontal and vertical mode according to the format that is input.
0000: 15.625 kHz, 50 Hz (625i)
0001: 15.75 kHz, 60 Hz (525i)
0010: 31.25 kHz, 50 Hz (625p)
0011: 31.5 kHz, 60 Hz (525p, VGA@60Hz)
0100: 28.125 kHz, 50 Hz (1125/50i) 0101: 33.75 kHz, 60 Hz (1125/60i)
HV FREQ
0111: 45 kHz, 60 Hz (750/60p, XGA@60Hz) 15.625 kHz, 50 Hz
0110: 37.5 kHz, 50 Hz (750/50p)
(0000)
1000: 31.25 kHz, 50 Hz (1250i)
1001: 37.9 kHz, 60 Hz (SVGA@60Hz)
1010: 64 kHz, 60 Hz (1125/60p, SXGA@60Hz)
1011: 75 kHz, 60 Hz (UXGA@60Hz)
1100: 56.25 kHz, 50 Hz (1125/50p)
1101 ~ 1111: Not available
Switches the separation level.
The H/V sync separation level to SYNC-IN (pins 8, 16, 38) is switched.
HV-SEP
0: LOW
1: HIGH
LOW
(0)
Remark: The separation level is changed according to the ratio of negative sync
width per H period and the connected resistance.
Switches the separation level.
VGA-SEP
The H/V sync separation level to SYNC-IN (pins 8, 16, 38) is switched for PC
signals.
0: Normal (component video)
1: VGA
Normal
(0)
Remark: The separation level is changed according to the ratio of negative sync
width per H period and the connected resistance.
Switches the mask mode for pseudo-sync.
PS MASK
Pseudo-syncs in lines are removed.
0: OFF (V-BLK period only)
OFF
1: ON (all lines)
(0)
NOTE: Set PS MASK = 1 (ON) for except “Sync on G”.
8
2007-07-11
TB1305FG, TB1308FG
Register Name
Function
Preset Value
Automatic sync processing mode.
A-SYNC
Sync processing mode is changed in accordance with the results obtained by the
internal format detection circuits. Format detection is performed for a SYNC or
HD/VD signal selected by SYNC SW. The result of detection is returned to H, V
FORMAT and H, V FM2.
The HV FREQ setting is invalid when this mode is active.
OFF
(0)
0: OFF (manual switching mode by HV FREQ setting)
1: ON
Switches sync output mode.
S MODE
This function sets the dummy HD/VD output mode when there is no input. The
frequency of the dummy HD/VD output depends on the HV FREQ setting (when
A-SYNC = OFF) or H, V FORMAT (when A-SYNC = ON).
H, V IN shows whether there is no input or not.
0: OFF (No HD and free-run VD output (approx. 44 Hz), when there is no input.
However, in 1250i mode, no HD and no VD output, when there is no input.)
OFF
(00)
1: ON (Dummy HD/VD output when there is no input)
Switches Y clamping mode.
CLAMP
This function sets the clamping mode for pins 5, 14, 39.
0: SYNC TIP CLAMP
1: BIAS
Switches the polarity of the HD/VD output.
HV-POL
This function sets the polarity of HD/VD OUT (pins 29, 30).
0: Positive
1: Negative
SYNC TIP
(0)
Positive
(0)
Switches the phase of dummy VD output.
VD PHS
VD PHS compensates for delay time so that the dummy VD-OUT phase is the
same as that form the separated V-sync.
No-delay
(0)
0: No delay
1: 0.2 H delay (0.15 H delay for 1125/50p)
Read Mode
Register Name
Function
LINE1 detection for D-pin (for the number of lines)
LINE1
00: 525 (480)
01: 750 (720)
10: ----
11: 1125 (1080)
Detects the voltage of LINE1 selected by YCbCr SW. 11 is returned when the pin is not connected.
LINE2 detection for D-pin (for i/p)
LINE2
0: Interlace
1: Progressive
Detects the voltage of LINE2 selected by YCbCr SW. 1 is returned when the pin is not connected.
LINE3 detection for D-pin (for aspect ratio)
LINE3
00: 4:3
01: 4:3 letter box
10: ----
11: 16:9
Detects the voltage of LINE3 selected by YCbCr SW. 11 is returned when the pin is not connected.
SW LINE1
SW LINE2
SW LINE1 (pin 48) detection for D-pin
0: Connected
1: Not connected
SW LINE1 (pin 9) detection for D-pin
0: Connected
1: Not connected
Polarity detection to HD-IN
HD-POL
0: Positive
1: Negative
Detects the width from the HD-IN pin to determine whether it is negative or not. When the High level of
the input HD-IN is wider than approx 14 µs, HD-POL shows 1.
9
2007-07-11
TB1305FG, TB1308FG
Register Name
Function
Polarity detection to VD-IN
VD-POL
0: Positive
1: Negative
Detects the width from the VD-IN pin to determine whether it is negative or not. When the High level of
the input VD-IN is wider than approx 4.5 ms, VD-POL shows 1.
Horizontal format detection
H FORMAT
0000: 15.625/15.75kHz 0001: 28.125kHz
0010: 31.25/31.5kHz
0011: 33.75kHz
0100: 37.5/37.9kHz
0101: 45/48kHz
0110: 64kHz/67.5kHz
0111: 75kHz
1000 56.25kHz
1001 ~ 1111: Undefined
Detects a horizontal format (horizontal frequency).
NOTE1: Format detection errors such as the following can occur when suppressed syncs are input. See
NOTE3 in the function description on Automatic sync processing mode, too.
525i input → 525p detected, 625i input → 625p detected, 1125i input → 1125p detected
525p/625p input → No V-sync detected
NOTE2: When 525i, 625i, 1125/50i or 1125/60i signal is input, H FORMAT data can be incorrect caused
by the pseudo-syncs for copy guard or the equalizing pulses.
Vertical format detection
V FORMAT
00: 50 Hz
01: 60 Hz
10 ~ 11: Undefined
Detects a vertical format (horizontal frequency) according to V FREQ DET data.
Horizontal format detection 2
H FM2
0: Known
1: Unknown
Detects whether an input is in one of the defined formats or not. This is based on H FORMAT data.
NOTE: H FM2 may indicate Unknown, when 525p input with pseudo sync signal for copy guard is input.
Vertical format detection 2
V FM2
0: Known
1: Unknown
Detects whether an input is in one of the defined formats or not. This is based on V FORMAT data.
H IN
V IN
Input detection to horizontal syncs
0: No signal
1: Signal
Input detection to vertical syncs
0: No signal
1: Signal
V-SYNC width detection
0: Wide
V-SYNC-W
VERSION
1: Narrow
Detects V-SYNC width for detecting 1250i format.
Under A-SYNC = 1 (ON), V-SYNC-W shows 1, when the VD width from the VD-IN pin is narrower than
approx 69 µs, or when the V-SYNC width from the SYNC-IN pin is narrower than approx 27 µs.
IC version identification
00: TB1305FG
01: TB1308FG
10: ----
11: ----
Counts the vertical frequency of an input selected by SYNC SW.
0000000: Over 3.5kHz
1001111: 44Hz or less
1010000～1111111: No signal
V FREQ DET
How to calculate a vertical frequency (Y):
Convert data read from V FREQ DET into decimal value and call it X.
Vertical frequency (Y) = 1 ÷ (X × 2.8607 × 10-4)
[Hz]
The error range of X is −1 to +1.
Counts the horizontal frequency of an input selected by SYNC SW.
00000000: No signal
H FREQ DET
11111111: Over 85kHz
How to calculate a horizontal frequency (Y):
Convert data read from H FREQ DET into decimal value and call it X.
Horizontal frequency (Y) = 1 ÷ (0.003 ÷ X)
[Hz]
The error range of X is −1 to +1.
10
2007-07-11
TB1305FG, TB1308FG
Note 1: In determining the decision algorithms (detection range, detection times and so on) for H/V frequency detection,
it is necessary to take into account both previously mentioned cautions and other factors such as signal
conditions and I2CBUS data transmission in the course of prototype TV set evaluation.
Note 2: The READ BUS flags indicate that a certain signal is detected at a given moment. However, the detection result
will not be very reliable if only one flag is checked. To obtain accuracy, it is recommended that a judgment will be
made on the basis of confirming several times and verifying agreement among the majority of flags read in a
sequence and/or at the same time.
11
2007-07-11
TB1305FG, TB1308FG
Function Descriptions
Vertical sync separation for 1250i/50
When HV FREQ = 1000, the vertical sync separation for 1250i/50 is accomplished through the use of a special circuit.
The phase of the VD-out (pin 29) depends on the H-SYNC timing shown in the figure below. There is no VD-out when
there is no H-SYNC input.
In the manual sync processing mode (A-SYNC = OFF), use READ BUS functions, V-SYNC-W and H, V FORMAT (or H,
V FREQ DET) to detect 1250i/50.
NOTE: The VD-OUT’s tailing edge has a jitter. Use the leading edge only.
HD width
HD-OUT width is selectable by HD WIDTH, as below. HD WIDTH = 1 (NARROW) is recommended for the
1125/50p/60p format owing to crosstalk from HD-OUT to video signals so that spike noises on video signals will occur.
1125/60p signal
SYNC-IN
(Y-IN)
HD-OUT
(HD WIDTH=1)
0.65us (typ)
HD-OUT
(HD WIDTH=0)
1.65us (typ)
12
2007-07-11
TB1305FG, TB1308FG
Automatic sync processing mode (A-SYNC)
Counted horizontal and vertical frequency data to input signal are returned to READ BUS functions, H, V FREQ DET.
Also, the detected format is returned to H, V FORMAT and H, FM2 when the H/V frequencies are in internal defined
ranges. Input detection results, which indicate whether there is an input or not, for H, V-SYNC or HD, VD are returned to
H, V IN. In automatic sync processing mode (when A-SYNC = ON), the TB1305FG and TB1308FG operate as indicated
in the following table according to these READ data.
INPUT
CONDITION
Standard format
H, V FORMAT status
The format as input
H, V FM2 status
H, V IN status
HD, VD outputs
Known
Signal
The separated sync as
input
The status indicates not
The separated sync as
the current condition
Unknown
Signal
input
but the last detected
format.
Dummy HD and VD, of
Known:
The status indicates not
which the frequency
the current condition The status indicates not
No signal
No input
depends on the H, V
but the last detected the current condition but
FORMAT status
the last detected format.
format.
NOTE 3: The following format detection errors can occur when suppressed syncs are input.
525i input → 525p detected, 625i input→ 625p detected, 1125i input→ 1125p detected
525p/625p inputs → In case of the 525p/625p sync amplitude become bigger from zero to its standard
gradually, V-sync of the input is not detected even though the sync amplitude is got back to its standard
amplitude.
The V-sync separation performance to the suppressed sync input may be improved when VGA-SEP is set to
1 (VGA), though the H and V separation level are also changed.
NOTE 4: We recommend recognizing a format by H/V FREQ DET rather than one by H/V FORMAT because H
FORMAT and H FM2 can indicate an incorrect data for 525i, 625i, 525p, 1125/50i and 1125/60i caused by the
pseudo-syncs for copy guard or the equalizing pulses.
NOTE 5: Dummy HD and VD may become unstable while the mode is changing from one format to another.
Non-standard
format
By the way, in A-SYNC = OFF and S-MODE = ON mode, dummy HD and VD are output according to HV FREQ setting
when there is no input.
Manual sync processing mode (A-SYNC = OFF *NOTE6)
HV FREQ = 625p is required to separate H-SYNC and V-SYNC properly. Set HV FREQ = 625p to count H/V-SYNC for
Manual sync processing mode.
The following is an example of how to detect H/V frequency when A-SYNC=OFF.
1. Set HV FREQ = 625p(0010) and read data such as H, V FREQ DET.
2. Detect the H/V frequencies by microprocessor or similar means, depending on the data obtained.
3. Set HV FREQ and so on to the detected mode.
4. Continue to monitor the obtained data such as H, V FREQ DET. When any alteration is recognized, set HV FREQ
= 625p(0010) and detect again.
Decision algorithms (for detection range, detection times and so on) for H/V frequency detection should be determined
taking into account the above-mentioned errors in measuring H/V frequencies and the other factors such as signal
conditions and I2CBUS data transmission in the course of prototype TV set evaluation.
NOTE 6: We recommend recognizing formats for 525i and 625i signals by another device such as a color-decoder, not
by this product, because 525i and 625i signals include non-standard signals.
However, if you use this product to recognize formats including the standard 525i and 625i, set “A-SYNC =
ON”. Otherwise, H/V FREQ DET and H/V FORMAT may indicate incorrect value and VD-OUT may lock
irregularly for 525i and 625i signals. Refer to the “Application circuit 3 (system configuration)”, too.
13
2007-07-11
TB1305FG, TB1308FG
Sync separation level
The sync separation level is changed according to the ratio of H-sync width to one line and the connected resistance.
Typical sync separation levels for each format are as follows. Then, VGA-SEP=1 for VGA to UXGA.
Format
625/50i
525/60i
625/50p
525/60p
1125/50i
1125/60i
750/50p
750/60p
1250/50i
1125/50p
1125/60p
VGA/60
SVGA/60
XGA/60
SXGA/60
HV-SEP = 0 (LOW)
R = 1.2 kΩ
R = 1.5 kΩ
R = 1.8 kΩ
22
22
22
21
31
26
29
24
25
36
31
15
15
17
27
28
28
28
27
39
33
37
31
32
45
39
19
18
22
33
33
34
34
32
45
39
43
37
37
51
45
23
22
26
39
HV-SEP = 1 (HIGH)
R = 1.2 kΩ
R = 1.5 kΩ
R = 1.8 kΩ
24
24
25
24
40
34
37
32
32
45
39
16
16
19
30
32
31
31
30
49
43
46
40
41
54
49
21
20
24
37
37
37
38
36
54
50
52
47
47
58
55
25
24
28
43
Unit [%] ; where 286 mVp-p sync for 525/60i and 300 mVp-p sync for others
For “Sync on G” signal, HD-OUT is not output during V-sync period because there is no H-sync during V-sync period.
Furthermore, for Sync on G of XGA input, HD-OUT disappears during active video period caused by unexpected lock of
the internal V-BLK.
The format detection and sync separation performances are changed due to the separation level set by HV-SEP,
VGA-SEP setting and/or the connected resistance with SYNC-IN pin. The careful evaluations are required to set the
separation level under consideration of expected input conditions such as a suppressed sync input, an input with V-sag
and APL (Average Picture Level) fluctuations.
Note on Sync input pin
If the AC-coupling circuit is put before the SYNC-IN pin, the picture on the screen may be not stable. This is because
the sync separation circuit is unable to follow the DC level fluctuation caused by APL (Average Picture Level) change in
the input signal, and the HD and/or VD output is unable to synchronize the input.
It is recommended to input signals via the DC-coupling buffer if necessary.
For the DC level fluctuation caused by APL change, the sync separation ability may be improved to change the
setting of HV-SEP, VGA-SEP and/or changing the resister R. Furthermore, adding a high-resistance around several
MΩ between SYNC-IN pin and GND (or Vcc) may improve the sync separation ability.
Adding DC restoration circuit such as a clamp circuit can be also effective for the improvement of DC level fluctuation.
Also, refer to Sync separation level descriptions.
14
2007-07-11
TB1305FG, TB1308FG
Prefilter for AD converter
The filter of the TB1305FG and TB1308FG can be used as a prefilter for AD converter. The cutoff frequency is
controllable by I2CBUS functions, FILPASS, f0-SW, BANDWIDTH and fc HALF.
The characteristics for cutoff frequency and delay time are as below.
10
0
Gain [dB]
-10
-20
-30
f0
f0
f0
f0
-40
SW
SW
SW
SW
-50
1.E+04
10k
= Low, BANDWIDTH = min, fc HALF = ON
= Low, BANDWIDTH = min
= High, BANDWIDTH = min
= High, BANDWIDTH = max
1.E+05
100k
1.E+06
1M
Frequency [Hz]
1.E+07
10M
1.E+08
100M
Figure. Typical prefilter frequency characteristics
Cutoff frequency (-3 dB point) [MHz]
35
f0
f0
f0
f0
30
25
SW
SW
SW
SW
=
=
=
=
Low, fc HALF = ON
High, fc HALF = ON
Low
High
20
15
10
5
0
0
20
40
60
80
100
120
BANDWIDTH data [Dec]
Figure. Typical cutoff frequency (-3 dB point) characteristics of prefilter due to
BANDWIDTH data.
15
2007-07-11
TB1305FG, TB1308FG
200
180
f0 SW = Low, fc HALF = ON
f0 SW = High, fc HALF = ON
160
f0 SW = Low
f0 SW = High
Delay time [ns]
140
120
100
80
60
40
20
0
0
20
40
60
80
100
120
BANDWIDTH data [Dec]
Figure. Typical delay-time (group delay @ 1MHz) characteristics of prefilter due to
BANDWIDTH data.
Note on 1125/50p/60p input
When 1125/50p and/or 60p signal are input, GAIN = 0(0dB) and FILPASS = 0(ON) are recommended due to the
performance of the slew rate and cutoff frequency of the TB1305FG and TB1308FG circuits. A gain amplifier and/or a
prefilter for 1125/50p/60p should be added as external circuits, if necessary.
Note on video output pins
To conduct the video signal from the TB1305FG or TB1308FG to the following circuits, a buffer such as the one in
the application circuits is required due to the drive capability of the TB1305FG and TB1308FG being insufficient,
especially for high-frequency components.
The DC levels of the video output vary according to I2CBUS functions, the APL of the input and temperature
drift.Therefore, the DC levels should be re-clamped in connected circuits such as AD converters.
Recommended crystal oscillator
When a connected crystal oscillator is used for the XO, the following oscillation specifications are required.
Oscillation frequency (fundamental): 3.579545 MHz (for NTSC decoding)
Frequency tolerance: +/- 50 ppm
External CW input into crystal oscillator pin
Instead of connecting a crystal oscillator, it is possible to input an external CW (Continual Wave) into pin 21 through a
capacitor as below.
The specifications required for CW input are as follows.
Input frequency (fundamental): 3.579545 MHz +/- 50 ppm
Input amplitude: 1.0 Vp-p +/- 0.5 Vp-p
16
2007-07-11
TB1305FG, TB1308FG
How to deal with unused pins
Unused pins should be dealt with as below. Pins not mentioned below should be connected properly.
Pin No.
Pin Name
Procedure
Pin No.
Pin Name
Procedure
1
Cr1/R1-IN
Procedure 1
25
VD2-IN
Procedure 4
2
LINE3-1
Procedure 2
26
HD2-IN
Procedure 4
3
Cb1/B1-IN
Procedure 1
27
ADDRESS
Procedure 3
4
LINE2-1
Procedure 2
28
SYNC-OUT
Procedure 3
5
Y1/G1-IN
Procedure 1
29
VD-OUT
Procedure 3
6
LINE1-1
Procedure 2
30
HD-OUT
Procedure 3
7
NC
Procedure 2
32
Y-OUT
Procedure 3
8
SYNC1-IN
Procedure 3
34
Cb-OUT
Procedure 3
9
SW LINE2
Procedure 2
36
Cr-OUT
Procedure 3
10
Cr2/R2-IN
Procedure 1
37
NC
Procedure 2
11
LINE3-2
Procedure 2
38
SYNC3-IN
Procedure 3
12
Cb2/B2-IN
Procedure 1
39
Y3/G3-IN
Procedure 1
13
LINE2-2
Procedure 2
41
Cb3/B3-IN
Procedure 1
14
Y2/G2-IN
Procedure 1
42
DAC2
Procedure 3
15
LINE1-2
Procedure 2
43
Cr3/R3-IN
Procedure 1
16
SYNC2-IN
Procedure 3
45
C-IN
Procedure 1
17
DAC1
Procedure 3
47
Y-IN
Procedure 1
23
VD1-IN
Procedure 4
48
SW LINE1
Procedure 2
24
HD1-IN
Procedure 4
－
－
－
Procedure 1: Connect a 1 µF capacitor between this pin and GND.
Procedure 2: Connect to GND.
Procedure 3: Leave open.
Procedure 4: Connect a 10 kΩ resister between this pin and GND.
NOTE: Pins 38, 39, 41 and 43 are NC pins for the TB1305FG. Of these, any unused pins should be dealt with
as in “Procedure 2”.
17
2007-07-11
TB1305FG, TB1308FG
2
How to Start the I CBUS
How to send bus data after power on is described below. Use software to handle the procedure.
1. Turn power on.
2. Transmit all write data.
2
How to Transmit/Receive via the I CBUS
Slave Address: Can Be Changed Using Pin 27.
Pin 27-GND: D8H/D9H
Pin 27-OPEN: DAH/DBH
A6
A5
A4
A3
A2
A1
A0
W/R
A6
A5
A4
A3
A2
A1
A0
W/R
1
1
0
1
1
0
0
0/1
1
1
0
1
1
0
1
0/1
Pin 27-Vcc: DCH/DDH
A6
A5
A4
A3
A2
A1
A0
W/R
1
1
0
1
1
1
0
0/1
Start and Stop Conditions
SDA
SCL
S
P
Start condition
Stop condition
Bit Transmission
SDA
SCL
SDA must not be changed
SDA may be changed
Acknowledgement
SDA from
transmitter
High impedance at bit 9
SDA from receiver
Low impedance at bit
9 only
SCL from master
1
8
9
S
Clock pulse for acknowledgement
18
2007-07-11
TB1305FG, TB1308FG
Data Transmit Format 1
S
Slave address
7-bit
0 A
MSB
S: Start condition
Sub address
8-bit
A
Transmit data
8-bit
A P
MSB
MSB
A: Acknowledgement
P: End condition
Data Transmit Format 2
S
Slave address
0 A
Sub address
A
Transmit data 1
Sub address
･･････
A
A
･･････
Transmit data n
A P
Data Receive Format
S
Slave address
7-bit
1 A
Receive data 1
8-bit
A P
MSB
MSB
MSB
Receive data n
･････････
To receive data, the master transmitter changes to a receiver immediately after the first
acknowledgement. The slave receiver changes to a transmitter.
The end condition is always created by the master.
Optional Data Transmit Format (Automatic Increment Mode)
S
Slave address
7-bit
0 A 1
MSB
Sub address
7-bit
MSB
A
Transmit data 1
8-bit
MSB
････
Transmit data n
8-bit
A P
MSB
In this way, sub-addresses are automatically incremented from the specified sub-address and data are
set.
I2CBUS Conditions
Parameter
Symbol
Min.
Typ.
Max.
Unit
Low level input voltage
VIL
0
−
1.1
V
High level input voltage
VIH
2.8
−
H-Vcc
V
Hysteresis of Schmitt trigger inputs
Vhys
−
0.7
−
V
Low level output voltage at 3 mA sink current
VOL1
0
−
0.6
V
Ii
-10
−
10
µA
Input current each I/O pin with an input voltage
between 0.1 VDD and 0.9 VDD
Ci
−
−
10
pF
fSCL
0
−
400
kHz
tHD;STA
0.6
−
−
µs
tLOW
1.3
−
−
µs
Capacitance for each I/O pin
SCL clock frequency
Hold time START condition
Low period of SCL clock
tHIGH
0.6
−
−
µs
Set-up time for a repeated START condition
tSU;STA
0.6
−
−
µs
Data hold time
tHD;DAT
50
−
−
ns
Data set-up time
tSU;DAT
100
−
−
ns
Set-up time for STOP condition
tSU;STO
0.6
−
−
µs
tBUF
1.3
−
−
µs
High period of SCL clock
Bus free time between a STOP and START condition
NOTE: This parameter is not tested during production and is provided only as information to assist the design of applications.
19
2007-07-11
TB1305FG, TB1308FG
Absolute Maximum Ratings (Ta = 25°C)
Characteristic
Symbol
Rating
Unit
VCCmax
6.0
V
Input pin voltage
Vin
GND − 0.3 ~ Vcc + 0.3
V
Y or Sync input amplitude (pins 5, 8, 14, 16, 38, 39, 47)
(Pins 38, 39 are for the TB1308FG only.)
Yin
2.0
Vp-p
PD(Note 5)
1136
mW
Power dissipation reduction rate
1/θja
9.1
mW/°C
Operating temperature
Topr
−20 ~ 75
°C
Storage temperature
Tstg
−55 ~ 150
°C
Supply voltage
Power dissipation
Note 5: Refer to the figure below.
Power consumption reduction ratio
PD (mW)
1136
682
0
0
25
75
Ambient temperature
150
Ta
(°C)
Figure. PD - Ta Curve
Note 6: Handle pins 7 and 37 of the TB1305FG and TB1308FG with special care. These ICs are sensitive to
electrostatic discharge and surge impulse.
Install the product correctly. Otherwise, it may result in break down, damage and/or degradation to the product
or equipment.
The absolute maximum ratings of a semiconductor device are a set of specified parameter values that must not
be exceeded during operation, even for an instant.
If any of these ratings are exceeded during operation, the electrical characteristics of the device may be
irreparably altered, in which case the reliability and lifetime of the device can no longer be guaranteed.
Moreover, operations with exceeded ratings may cause breakdown, damage and/or degradation in other
equipment. Applications using the device should be designed so that no maximum rating will ever be exceeded
under any operating conditions.
Before using, creating and/or producing designs, refer to and comply with the precautions and conditions set
forth in these documents.
20
2007-07-11
TB1305FG, TB1308FG
Operating conditions
Characteristic
Description
Min.
Pins 31, 46
4.7
5.0
5.3
Pin 22; supply power from H Vcc (pin 31) via a resistor.
3.1
3.3
3.5
Y signal input amplitude
Pins 5, 8, 14, 16, 38, 39, 47; with sync
⎯
1.0
⎯
Vp-p
G signal input amplitude
Pins 8, 16, 38; with sync
⎯
1.0
⎯
Vp-p
Pins 5, 14, 39
0
⎯
60
Pin 47
0
⎯
8
Chroma signal input amplitude
Pin 45
⎯
0.3
2
Vp-p
DC voltage of chroma input pin
Pin 45
⎯
⎯
3.6
V
Cb, Cr, Pb, Pr signal input amplitude
Pins 1, 3, 10, 12, 41, 43; 100% color bar signal
⎯
0.7
⎯
Vp-p
Cb, Cr, Pb, Pr signal input frequency
Pins 1, 3, 10, 12, 41, 43
0
⎯
60
MHz
R, G, B signal input amplitude
Pins 1, 3, 5, 10, 12, 14, 39, 41, 43; 100% white signal
without sync
⎯
0.7
⎯
Vp-p
R, G, B signal input frequency
Pins 1, 3, 5, 10, 12, 14, 39, 41, 43, 39, 41, 43
0
⎯
60
MHz
HD, VD signal input amplitude
Pins 23, 24, 25, 26
1.0
⎯
2.0
Vp-p
HD input frequency
Pins 24, 26 for freq counter
0
⎯
85
kHz
VD input frequency
Pins 23, 25 for freq counter
Hz
Supply voltage (VCC)
Y signal input frequency
LINE1,3
LINE detection input
voltage
Pins 2, 6, 11, 15
LINE2
Pins 4, 13
SW LINE
Pins 9, 48
ADDRESS switching voltage
Pin 27
SDA input current
Pin 18
Typ.
Max.
44
⎯
3500
H
3.5
5.0
C-Vcc
M
1.4
2.2
2.4
L
⎯
GND
0.6
H
1.4
2.2
C-Vcc
L
⎯
GND
0.6
H
1.4
5.0
C-Vcc
L
⎯
GND
0.6
88/89H
⎯
GND
0.6
DA/DBH
DC/DDH
Unit
V
MHz
V
V
V
V
Pin open
3.5
C-Vcc
C-Vcc
⎯
⎯
3
mA
Remark: Supply power to all Vcc pins (pins 22, 31 and 46).
NOTE: Pins 38, 39, 41 and 43, as Y/Cb/Cr/SYNC3-IN, are available for the TB1308FG only. Pins 38, 39, 41 and 43 of
the TB1305FG are NC pins.
21
2007-07-11
TB1305FG, TB1308FG
Electrical Characteristics
(Unless otherwise specified, C and H VCC = 5 V, D VCC = 3.3 V, Ta = 25°C, I2CBUS data: preset values)
Current Consumption
Pin Name
Symbol
Test Conditions
Min
Typ.
Max
C VCC (pin 46)
ICCC
⎯
30.0
38.0
46.0
H VCC (pin 31)
ICCH
⎯
4.5
6.0
7.5
D VCC (pin 22)
ICCD
Resistance to 5 V; R = 150 Ω
8.5
10.5
12.5
Unit
mA
Pin Voltage (test condition: no signal input)
Pin No.
Pin Name
Symbol
Test Conditions
Min
Typ.
Max
1
Cr1/R1-IN
V1
⎯
2.6
2.7
2.8
2
LINE3-1
V2
⎯
4.8
⎯
⎯
3
Cb1/B1-IN
V3
⎯
2.6
2.7
2.8
4
LINE2-1
V4
⎯
4.8
⎯
⎯
5
Y1/G1-IN
V5
⎯
1.95
2.1
2.25
6
LINE1-1
V6
⎯
4.8
⎯
⎯
8
SYNC1-IN
V8
⎯
1.4
1.75
2.1
9
SW LINE2
V9
⎯
4.8
⎯
⎯
10
Cr2/R2-IN
V10
⎯
2.6
2.7
2.8
11
LINE3-2
V11
⎯
4.8
⎯
⎯
12
Cb2/B2-IN
V12
⎯
2.6
2.7
2.8
13
LINE2-2
V13
⎯
4.8
⎯
⎯
14
Y2/G2-IN
V14
⎯
1.95
2.1
2.25
15
LINE1-2
V15
⎯
4.8
⎯
⎯
16
SYNC2-IN
V16
⎯
1.4
1.75
2.1
21
XTAL
V21
⎯
3.7
3.85
4.0
Resistance to 5 V; R = 150 Ω
22
DIG Vcc
V22
3.2
3.35
3.5
23
VD1-IN
V23
⎯
1.2
1.45
1.7
24
HD1-IN
V24
⎯
1.2
1.45
1.7
25
VD2-IN
V25
⎯
1.2
1.45
1.7
26
HD2-IN
V26
⎯
1.2
1.45
1.7
27
ADDRESS
V27
1.8
2.0
2.2
32
Y-OUT
V32
⎯
0.3
1.0
1.7
34
Cb-OUT
V34
⎯
1.5
1.95
2.4
35
Vf0ADJ
V35
⎯
2.2
2.5
2.8
36
Cr-OUT
V36
⎯
1.5
1.95
2.4
38
SYNC3-IN
V38
For the TB1308FG only
1.4
1.75
2.1
39
Y3/G3-IN
V39
For the TB1308FG only
1.95
2.1
2.25
40
BIAS FIL
V40
1.6
1.8
2.0
41
Cb3/B3-IN
V41
For the TB1308FG only
2.6
2.7
2.8
43
Cr3/R3-IN
V43
For the TB1308FG only
2.6
2.7
2.8
45
C-IN
V45
⎯
1.6
1.7
1.8
47
Y-IN
V47
⎯
1.95
2.1
2.25
48
SW LINE1
V48
⎯
4.8
⎯
⎯
Pin open
⎯
22
Unit
V
2007-07-11
TB1305FG, TB1308FG
Video Block
Characteristic
Input dynamic
range
Symbol
Sync-tip clamp mode
Vdsync
Bias mode
Vdbias
Chroma input
I/O gain
I/O frequency
characteristic 1
Gfoffg0
GAIN = 1
Gfoffg6
GAIN = 0
Gfong0
GAIN = 1
Gfong6
GAIN = 0
fg0
GAIN = 1
fg6
BANDWIDTH = max
I/O frequency
characteristic 2
I/O frequency
characteristic 3
I/O frequency
characteristic 4
I/O frequency
characteristic 5
Differential 1 of
frequency
characteristic
among 3 outputs
Differential 2 of
frequency
characteristic
among 3 outputs
Differential 3 of
frequency
characteristic
among 3 outputs
I/O delay time 1
BANDWIDTH = cnt
fLcnt
fLmin
BANDWIDTH = max
fHmax
BANDWIDTH = cnt
fHcnt
BANDWIDTH = min
fHmin
BANDWIDTH = max
fhfLmax
BANDWIDTH = cnt
I/O delay time 3
FILPASS = 1, BANDWIDTH = max
Pin 45
FILPASS = 0, input = 0.2Vp-p 10 kHz
FILPASS = 1, f0 SW = 0,
BANDWIDTH = min,
input = 0.2 Vp-p 10 kHz
FILPASS = 0, -3 dB point, NOTE 7
fLmax
BANDWIDTH = min
fhfLcnt
FILPASS = 1, GAIN = 0, f0 SW = 1,
-3 dB point, NOTE 7
FILPASS = 1, GAIN = 0, f0 SW = 0,
-3 dB point, NOTE 7
FILPASS = 1, GAIN = 0, f0 SW = 1,
fc HALF = 1, -3 dB point, NOTE 7
Typ.
Max
1.40
1.65
⎯
1.40
1.65
⎯
1.40
1.65
⎯
-1.0
-0.5
0
5.0
5.5
6.0
-0.5
0
0.5
5.5
6.0
6.5
70
90
110
60
80
100
18.4
20.5
22.6
11.4
12.7
14.0
3.7
4.2
4.7
27.9
31.0
34.1
21.6
24.0
26.4
14.6
16.3
18.0
9.2
10.3
11.4
5.7
6.4
7.1
fhfLmin
1.85
2.1
2.35
BANDWIDTH = max
fhfHmax
13.9
15.5
17.1
BANDWIDTH = cnt
fhfHcnt
10.8
12
13.2
BANDWIDTH = min
fhfHmin
7.3
8.2
9.1
-10
0
10
-10
0
10
GAIN = 0
FILPASS = 1, GAIN = 0, f0 SW = 0,
fc HALF = 1, -3 dB point, NOTE 7
fdg0
FILPASS = 0, -3 dB point, NOTE 7
GAIN = 1
fdg6
BANDWIDTH = max
fdHmax
BANDWIDTH = cnt
fdHcnt
BANDWIDTH = min
fdHmin
BANDWIDTH = max
fdHmax
BANDWIDTH = cnt
fdHcnt
BANDWIDTH = min
fdHmin
GAIN = 0
Tdg0
GAIN = 1
Tdg6
BANDWIDTH = cnt
FILPASS = 1, f0 SW = 1, -3 dB point,
NOTE 7
FILPASS = 1, f0 SW = 0, -3 dB point,
NOTE 7
FILPASS = 0, 1 MHz, NOTE 7
TdLmax
TdLcnt
FILPASS = 1, GAIN = 0, f0 SW = 1,
1 MHz, NOTE 7
-0.90
0
0.90
-0.54
0
0.54
-0.18
0
0.18
-1.30
0
1.30
-1.05
0
1.05
-0.70
0
0.70
⎯
5
10
⎯
5
10
18
23
28
29
34
39
TdLmin
85
95
105
BANDWIDTH = max
TdHmax
10
15
20
15
20
25
BANDWIDTH = cnt
TdHcnt
BANDWIDTH = min
TdHmin
FILPASS = 1, GAIN = 0, f0 SW = 0,
1 MHz, NOTE 7
BANDWIDTH = cnt
TdhfLcnt
BANDWIDTH = min
TdhfLmin
FILPASS = 1, GAIN = 0, f0 SW = 1,
fc HALF = 1, 1 MHz, NOTE 7
23
Unit
Vp-p
dB
MHz
MHz
MHz
MHz
MHz
MHz
BANDWIDTH = min
BANDWIDTH = max TdhfLmax
I/O delay time 4
Min
BANDWIDTH = min
BANDWIDTH = max
I/O delay time 2
Vdchrm
GAIN = 0
Test Conditions
22
27
32
35
40
45
58
65
72
170
190
210
MHz
MHz
ns
ns
ns
ns
2007-07-11
TB1305FG, TB1308FG
Characteristic
Symbol
Test Conditions
BANDWIDTH = max TdhfHmax
I/O delay time 5
Differential 1 of
delay time among
3 outputs
Differential 2 of
delay time among
3 outputs
Differential 3 of
delay time
between Y and
Cb/Cr outputs
Differential 4 of
delay time
between Cb and
Cr outputs
BANDWIDTH = cnt
TdhfHcnt
BANDWIDTH = min
TdhfHmin
GAIN = 0
Tddg0
GAIN = 1
Tddg6
BANDWIDTH = max
TddHmax
BANDWIDTH = cnt
TddHcnt
BANDWIDTH = min
TddHmin
BANDWIDTH = max
TddHmax
BANDWIDTH = cnt
TddHcnt
BANDWIDTH = min
TddHmin
BANDWIDTH = max
TddHmax
BANDWIDTH = cnt
TddHcnt
BANDWIDTH = min
TddHmin
FILPASS = 1, GAIN = 0, f0 SW = 0,
fc HALF = 1, 1 MHz, NOTE 7
FILPASS = 0, 1 MHz, NOTE 7
FILPASS = 1, f0 SW = 1, 1 MHz,
NOTE 7
FILPASS = 1, f0 SW = 0,
fc HALF = 1, 1 MHz, NOTE 7
FILPASS = 1, f0 SW = 0,
fc HALF = 1, 1 MHz, NOTE 7
Min
Typ.
Max
22
27
32
29
34
39
45
50
55
-10
0
10
-10
0
10
-10
0
10
-10
0
10
-10
0
10
0
10
20
10
20
30
35
45
55
-10
0
10
-10
0
10
-10
0
10
Unit
ns
ns
ns
ns
ns
Mute mode attenuation
Gmute
30 MHz sin wave input, NOTE 7
⎯
⎯
-50
dB
Crosstalk among inputs
Gcrs
30 MHz sin wave input, NOTE 7
⎯
⎯
-50
dB
NOTE 7: This parameter is not tested during production and is provided only as information to assist the design of applications.
Synchronization Block (Test condition: A-SYNC = 1 (ON))
Characteristic
Symbol
1125/60i
Min
Typ
Max
28
32
VsepL1
HV-SEP = 0, 286 mVp-p sync,
NOTE 7
24
VsepH1
HV-SEP = 1, 286 mVp-p sync,
NOTE 7
27
31
35
VsepL2
HV-SEP = 0, 0.3 Vp-p sync, NOTE 7
30
34
38
VsepH2
HV-SEP = 1, 0.3 Vp-p sync, NOTE 7
40
44
48
VsepL3
HV-SEP = 0, VGA-SEP = 1, 0.3 Vp-p
sync, NOTE 7
14
18
22
VsepH3
HV-SEP = 1, VGA-SEP = 1, 0.3 Vp-p
sync, NOTE 7
16
20
24
525/60i
H/V-sync separation level
Test Conditions
SVGA/60
Unit
%
%
%
Threshold amplitude for HD input
VthHD
SYNC SW = 100
0.8
⎯
⎯
Vp-p
Threshold amplitude for VD input
VthVDn
SYNC SW = 100
0.9
⎯
⎯
Vp-p
VhdH
High level
3.2
3.4
3.5
VhdL
Low level
⎯
0.1
0.4
HD-OUT voltage
Thdw0
HD WIDTH = 0
1.55
1.65
1.75
Thdw1
HD WIDTH = 1
0.55
0.65
0.75
H sync-in to HD-out
Thdp1
SYNC-SW = 000, 1125/60p input
130
150
170
ns
HD-in to HD-out
Thdp2
SYNC-SW = 100, NOTE 7
23
28
32
ns
HD-OUT width
HD-OUT phase
V
24
us
2007-07-11
TB1305FG, TB1308FG
Characteristic
Symbol
VD-OUT voltage
Sync sep
VD-OUT width
3.4
3.5
VvdL
Low level
⎯
0.1
0.4
Separated VD-OUT
⎯
290
⎯
⎯
285
⎯
⎯
270
⎯
Tvdws
Tvdweven
VD-OUT phase
Max
3.2
1250i EVEN
V sync-in to VD-out
Typ.
High level
Tvdwodd
Free-run 2
Min
VvdH
1250i ODD
Free-run 1
Test Conditions
When 1250i input
Tvdwfi
Free-run VD-OUT in interlace mode
⎯
4
⎯
Tvdwfp
Free-run VD-OUT in progressive
mode
⎯
8
⎯
Tvdp1
625/50i input
0.15
0.20
0.26
Tvdp2
525/60i input
0.15
0.20
0.26
Tvdp3
625/50p input
0.15
0.20
0.26
Tvdp4
525/60p input
0.15
0.20
0.26
Tvdp5
1125/50i input
0.15
0.20
0.26
Tvdp6
1125/60i input
0.15
0.20
0.26
Tvdp7
750/50p input
0.15
0.20
0.26
Tvdp8
750/60p input
0.15
0.20
0.26
Unit
V
us
us
H
H
Tvdp9
1125/50p input
0.10
0.15
0.20
Tvdp10
1125/60p input
0.15
0.20
0.26
Tvdp11
VGA/60 input
0.15
0.20
0.26
Tvdp12
SVGA/60 input
0.15
0.20
0.26
Tvdp13
XGA input
0.15
0.20
0.26
Tvdp14
SXGA input
0.15
0.20
0.26
Tvdp15
UXGA input
0.15
0.20
0.26
H sync-in to VD-out
Tvdp16
1250/50i input, H sync-in to VD-out
330
340
350
ns
VD-in to VD-out
Tvdp17
SYNC-SW=100, NOTE 7
23
28
32
ns
⎯
⎯
52
⎯
⎯
48
Minimum amplitude for
suppressed V-sync to
separate
SYNC－OUT voltage
HV-SEP = 0
VsupvL
HV-SEP = 1
VsupvH
Suppressed H/V-sync input, without
picture, NOTE 7
VsoH
High level
3.2
3.4
3.5
VsoL
Low level
⎯
0.1
0.4
25
%
V
2007-07-11
TB1305FG, TB1308FG
Characteristic
Symbol
Dummy HD-OUT frequency
Dummy VD-OUT frequency
VD PHS delay phase
LINE1 detection threshold
LINE2 detection threshold
LINE3 detection threshold
SW LINE detection threshold
DAC1,2 output voltage
Test mode threshold voltage
Min
Typ.
Max
fh156
HV FREQ = 0000, S MODE = 1
⎯
15.564
⎯
fh157
HV FREQ = 0001, S MODE = 1
⎯
15.701
⎯
fh312
HV FREQ = 0010, S MODE = 1
⎯
31.401
⎯
fh315
HV FREQ = 0011, S MODE = 1
⎯
31.401
⎯
fh281
HV FREQ = 0100, S MODE = 1
⎯
27.966
⎯
fh337
HV FREQ = 0101, S MODE = 1
⎯
33.771
⎯
fh375
HV FREQ = 0110, S MODE = 1
⎯
37.288
⎯
fh450
HV FREQ = 0111, S MODE = 1
⎯
44.746
⎯
fh1250
HV FREQ = 1000, S MODE = 1
⎯
31.401
⎯
fh379
HV FREQ = 1001, S MODE = 1
⎯
37.288
⎯
fh640
HV FREQ = 1010, S MODE = 1
⎯
63.923
⎯
fh750
HV FREQ = 1011, S MODE = 1
⎯
74.577
⎯
fh562
HV FREQ = 1100, S MODE = 1
⎯
55.932
⎯
fv625i
HV FREQ = 0000, S MODE = 1
⎯
312.5
⎯
fv525i
HV FREQ = 0001, S MODE = 1
⎯
262.5
⎯
fv625p
HV FREQ = 0010, S MODE = 1
⎯
625
⎯
fv525p
HV FREQ = 0011, S MODE = 1
⎯
525
⎯
fv1125i5
HV FREQ = 0100, S MODE = 1
⎯
562.5
⎯
fv1125i6
HV FREQ = 0101, S MODE = 1
⎯
562.5
⎯
fv750p5
HV FREQ = 0110, S MODE = 1
⎯
750
⎯
fv750p6
HV FREQ = 0111, S MODE = 1
⎯
750
⎯
fv1250iO
HV FREQ = 1000, S MODE = 1,
ODD
⎯
624.5
⎯
fv1250iE
HV FREQ = 1000, S MODE = 1,
EVEN
⎯
625.5
⎯
fvsvga
HV FREQ = 1001, S MODE = 1
⎯
628
⎯
fvsxga
HV FREQ = 1010, S MODE = 1
⎯
1066
⎯
fvuxga
HV FREQ = 1011, S MODE = 1
⎯
1250
⎯
fv1125p5
HV FREQ = 1100, S MODE = 1
⎯
1125
⎯
0.15
0.2
0.26
0.1
0.15
0.2
0.8
1.0
1.2
2.8
3.0
3.2
0.8
1.0
1.2
0.8
1.0
1.2
2.8
3.0
3.2
Pin 9, 48
0.8
1.0
1.2
others
Tvdphs1
1125/50p
Tvdphs2
L⇔M
Vln1LM
M⇔H
Vln1MH
L⇔H
Vln2LH
L⇔M
Vln3LM
M⇔H
Vln3MH
L⇔H
VlnsLH
Input impedance of LINE input pin
Test Conditions
No input, S MODE = 1, VD PHS = 1
Pin 6, 15
Pin 4, 13
Pin 2, 11
Pin 2,4,6,9,11,13,15,48, NOTE 7
120
150
⎯
VdacH
High level
4.8
5.0
⎯
VdacL
Low level
⎯
0.2
0.4
Vontest
Pin 45, turned-on voltage for test
mode
3.6
⎯
⎯
Zline
26
Unit
kHz
H
H
V
kΩ
V
V
2007-07-11
27
Y-IN
C-IN
Cr3-IN
Cb3-IN
Y3-IN
75Ω
R47
75Ω
R45
75Ω
L46
+
0.1μF
C48
1μF C47
0.01μF
C46
B
SW1
A
1μF
C43
10kΩ
R42
1μF
CE46 47μF
100pF
C45
C41
75Ω
DAC2-OUT
1μF
R41
R43
CE40
75Ω
+
1μF
R39
C39
Y-IN
SW LINE1
48
C Vcc
C-IN
47
46
45
C GND
Cr3/R3-IN
43
44
DAC2
Cb3/B3-IN
BIAS FIL
Y3/G3-IN
42
41
40
39
Q32,Q34,Q36=2SA562TM
L3
1
38
2
37
3
36
4
35
33
32
31
30
29
5
6
7
8
9
10
TB1305FG/TB1308FG
34
11
28
12
27
13
26
14
25
LINE1-2
SYNC2-IN
DAC1
SDA
SCL
DIG GND
XTAL
DIG Vcc
VD1-IN
HD1-IN
15
16
17
18
19
20
21
22
23
24
100Ω
47μF
X21 CE22 C21
R19A
R16
0.1μF
C15
0.1μF 1.5kΩ
C16
10kΩ
R17
470Ω
R18A
R22
R23B
75Ω
VD1-IN
HD1-IN
DAC1-OUT
SDA
SCL
1/2W 150Ω
3.579545MHz 10pF
470Ω
75Ω
R24B
0.01μF C22
4.7μF 100Ω
CE23 R23A
1μF
CE24 R24A
+
Vcc 5V
TB1305FG, TB1308FG
Test circuit
Components in the test circuits are only used to obtain and confirm the device characteristics. These components and
circuits do not warrant to prevent the application equipment from malfunction or failure.
2007-07-11
TB1305FG, TB1308FG
Application circuit 1 (TB1305FG: typical values)
Input video signals, which are driven with low impedance.
The application circuits shown in this document are examples provided for reference purposes only. Thorough evaluation
is required in the mass production design phase.
By furnishing these examples of application circuits, Toshiba does not grant the use of any industrial property rights.
28
2007-07-11
29
Y-IN
C-IN
Cr3-IN
Cb3-IN
Y3-IN
DAC2-OUT
+
0.1μF
1μF
0.01μF
47μF
100pF
1μF
10kΩ
1μF
1μF
+
1μF
26
25
Y-IN
SW LINE1
47
48
C Vcc
C-IN
45
46
C GND
Cr3/R3-IN
43
44
DAC2
42
1
3
4
INPUT1 (D-pin 1)
2
5
6
7
8
9
TB1308FG
10
12
13
INPUT2 (D-pin 2)
11
14
16
15
LINE1-2
17
SYNC2-IN
DAC1
18
SDA
DIG GND
19
20
XTAL
SCL
21
22
27
DIG Vcc
28
Cb3/B3-IN
29
41
30
23
31
VD1-IN
32
BIAS FIL
33
40
34
24
35
HD1-IN
36
Y3/G3-IN
37
39
38
0.1μF
0.1μF 1.5kΩ
10kΩ
470Ω
470Ω
10pF
3.579545MHz
47μF
VD1-IN
HD1-IN
DAC1-OUT
SDA
SCL
1/2W 150Ω
100Ω
100Ω
0.01μF
4.7μF
1μF
+
Vcc 5V
TB1305FG, TB1308FG
Application circuit 2 (TB1308FG: typical values)
Input video signals, which are driven with low impedance.
The application circuits shown in this document are examples provided for reference purposes only. Thorough evaluation
is required in the mass production design phase.
By furnishing these examples of application circuits, Toshiba does not grant the use of any industrial property rights.
2007-07-11
TB1305FG, TB1308FG
Application circuit 3 (system configuration)
(1) For non-standard signals such as CVBS, YC (S-video), 525i, 625i or so.
TB1305/08
The TB1305FG and TB1308FG cannot be used for non-standard signals such as weak strength signals, ghost signals
and so on. Therefore, these signals should be dealt with through the use of another device such as a color-decoder
which is capable of handling these signals. In such cases, the signal switcher and the video circuits of the TB1305FG
and TB1308FG can be used.
The TB1305FG and TB1308FG cannot distinguish between component and RGB video. The different kinds of input
signal should be separated through the use of different signal-specific input pins; for example, specific-purpose pins for
RGB video input only or component video input only.
(2) For standard component video (SMPTE STANDARD) and standard RGB video (VESA STANDARD)
TB1305/08
The TB1305FG and TB1308FG can detect a format type for standard signal inputs.
The application circuits shown in this document are examples provided for reference purposes only. Thorough evaluation
is required in the mass production design phase.
By furnishing these examples of application circuits, Toshiba does not grant the use of any industrial property rights.
30
2007-07-11
TB1305FG, TB1308FG
Package dimensions
P-QFP48-1014-0.80
Unit: mm
Weight: 0.83 g (typ.)
31
2007-07-11
TB1305FG, TB1308FG
Appendix: Comparison Table of the Family
1) Pin functions
Pin No.
TB1305FG
TB1308FG
Pin 38
Pin 39
Pin 41
Pin 43
NC
NC
NC
NC
SYNC3-IN
Y3/G3-IN
Cb3/B3-IN
Cr3/R3-IN
2) Write BUS functions
Name
Data
TB1305FG
TB1308FG
YCbCr SW
11
010
110
111
Not available
Not available
HD1/VD1/Not available
HD2/VD2/Not available
Y3/Cb3/Cr3
SYNC3
HD1/VD1/SYNC3
HD2/VD2/SYNC3
Name
TB1305FG
TB1308FG
VERSION
00: TB1305FG
01: TB1308FG
SYNC SW
3) Read BUS functions
32
2007-07-11
TB1305FG, TB1308FG
About solderability, following conditions were confirmed
• Solderability
(1) Use of Sn-37Pb solder Bath
· solder bath temperature = 230°C
· dipping time = 5 seconds
· the number of times = once
· use of R-type flux
(2) Use of Sn-3.0Ag-0.5Cu solder Bath
· solder bath temperature = 245°C
· dipping time = 5 seconds
· the number of times = once
· use of R-type flux
RESTRICTIONS ON PRODUCT USE
• The information contained herein is subject to change without notice. 021023_D
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc. 021023_A
• The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer’s own risk. 021023_B
• The products described in this document shall not be used or embedded to any downstream products of which
manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q
•
The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which
may result from its use. No license is granted by implication or otherwise under any patents or other rights of
TOSHIBA or the third parties.
•
Please use this product in compliance with all applicable laws and regulations that regulate the inclusion or use
of controlled substances. Toshiba assumes no liability for damage or losses occurring as a result of
noncompliance with applicable laws and regulations.
• The products described in this document are subject to the foreign exchange and foreign trade control laws.
33
2007-07-11