TC55V400AFT-55,-70 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 262,144-WORD BY 16-BIT FULL CMOS STATIC RAM DESCRIPTION The TC55V400AFT is a 4,194,304-bit static random access memory (SRAM) organized as 262,144 words by 16 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 2.3 to 3.6 V power supply. Advanced circuit technology provides both high speed and low power at an operating current of 3 mA/MHz and a minimum cycle time of 55 ns. It is automatically placed in low-power mode at 0.5 mA standby current (at VDD = 3 V, Ta = 25°C, maximum) when chip enable ( CE1 ) is asserted high or (CE2) is asserted low. There are three control inputs. CE1 and CE2 are used to select the device and for data retention control, and output enable ( OE ) provides fast memory access. Data byte control pin ( LB , UB ) provides lower and upper byte access. This device is well suited to various microprocessor system applications where high speed, low power and battery backup are required. And, with a guaranteed operating extreme temperature range of -40° to 85°C, the TC55V400AFT can be used in environments exhibiting extreme temperature conditions. The TC55V400AFT is available in normal and reverse pinout plastic 48-pin thin-small-outline package (TSOP). FEATURES · · · · · · · · Low-power dissipation Operating: 10.8 mW/MHz (typical) Single power supply voltage of 2.3 to 3.6 V Power down features using CE1 and CE2 Data retention supply voltage of 1.5 to 3.6 V Direct TTL compatibility for all inputs and outputs Wide operating temperature range of -40° to 85°C Standby Current (maximum): 3.6 V 7 mA 3.0 V 5 mA Access Times (maximum): TC55V400AFT · PIN ASSIGNMENT (TOP VIEW) -55 -70 Access Time 55 ns 70 ns CE1 Access Time 55 ns 70 ns CE2 Access Time 55 ns 70 ns OE Access Time 30 ns 35 ns Package: TSOPⅠ48-P-1214-0.50 (AFT) (Weight: 0.38 g typ) PIN NAMES 48 PIN TSOP A0~A17 1 48 CE1 , CE2 Read/Write Control OE Output Enable I/O1~I/O16 25 (Normal) Chip Enable R/W LB , UB 24 Address Inputs Data Byte Control Data Inputs/Outputs VDD Power GND Ground NC No Connection Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name A15 A14 A13 A12 A11 A10 A9 A8 NC NC R/W CE2 NC UB LB NC Pin No. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Name A17 A7 A6 A5 A4 A3 A2 A1 A0 CE1 GND OE I/O1 I/O9 I/O2 I/O10 39 40 41 42 43 44 45 46 Pin No. 33 34 35 36 37 38 Pin Name I/O3 I/O11 I/O4 I/O12 VDD I/O5 I/O13 I/O6 I/O14 I/O7 I/O15 I/O8 I/O16 GND 47 48 NC A16 2001-09-04 1/11 TC55V400AFT-55,-70 BLOCK DIAGRAM DATA INPUT BUFFER I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 ROW ADDRESS DECODER ROW ADDRESS REGISTER VDD GND MEMORY CELL ARRAY 2,048 ´ 128 ´ 16 (4,194,304) DATA OUTPUT BUFFER I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 DATA INPUT BUFFER ROW ADDRESS BUFFER CE A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A17 DATA OUTPUT BUFFER SENSE AMP COLUMN ADDRESS DECODER COLUMN ADDERSS REGISTER COLUMN ADDRESS BUFFER CLOCK GENERATOR CE A0 A1 A2 A3 A14 A15 A16 R/W OE UB LB CE1 CE CE2 OPERATING MODE MODE Read Write Output Deselect Standby CE1 L L CE2 H H OE L * R/W H L LB UB L L I/O1~I/O8 Output I/O9~I/O16 POWER Output IDDO H L High-Z Output IDDO L H Output High-Z IDDO IDDO L L Input Input H L High-Z Input IDDO L H Input High-Z IDDO High-Z High-Z IDDO High-Z High-Z IDDS L H H H * * L H * * H H H * * * * * * L * * * * * = don't care H = logic high L = logic low 2001-09-04 2/11 TC55V400AFT-55,-70 MAXIMUM RATINGS SYMBOL RATING VALUE UNIT -0.3~4.6 V -0.3*~4.6 V VDD Power Supply Voltage VIN Input Voltage VI/O Input/Output Voltage PD Power Dissipation Tsolder Soldering Temperature (10s) 260 °C Tstg Storage Temperature -55~150 °C Topr Operating Temperature -40~85 °C -0.5~VDD + 0.5 V 0.6 W *: -3.0 V when measured at a pulse width of 50ns DC RECOMMENDED OPERATING CONDITIONS (Ta = -40° to 85°C) SYMBOL 2.3 V~3.6 V PARAMETER MIN TYP UNIT MAX VDD Power Supply Voltage 2.3 3.0 3.6 VIH Input High Voltage 2.2 ¾ VDD + 0.3 V VIL Input Low Voltage -0.3* ¾ VDD ´ 0.22 V 1.5 ¾ 3.6 V VDH Data Retention Supply Voltage V -3.0 V when measured at a pulse width of 50 ns *: DC CHARACTERISTICS (Ta = -40° to 85°C, VDD = 2.3 to 3.6 V) SYMBOL PARAMETER TEST CONDITION MIN TYP MAX UNIT ¾ ¾ ±1.0 mA Input Leakage Current VIN = 0 V~VDD IOH Output High Current VOH = VDD - 0.5 V -0.5 ¾ ¾ mA IOL Output Low Current VOL = 0.4 V 2.1 ¾ ¾ mA ILO Output Leakage Current CE1 = VIH or CE2 = VIL or R/W = VIL or OE = VIH, VOUT = 0 V~VDD ¾ ¾ ±1.0 mA 55 ns ¾ ¾ 70 70 ns ¾ ¾ 60 1 ms ¾ ¾ 10 55 ns ¾ ¾ 65 70 ns ¾ ¾ 55 1 ms ¾ ¾ 5 ¾ ¾ 2 IIL CE1 = VIL and CE2 = VIH and R/W = VIH and IOUT = 0 mA, Other Input = VIH/VIL lDDO1 VDD = t 3 V ± 10% cycle Operating Current CE1 = 0.2 V and VDD = CE2 = VDD - 0.2 V and t R/W = VDD - 0.2 V, IOUT = 0 mA, 3 V ± 10% cycle Other Input = VDD - 0.2 V/0.2 V lDDO2 CE = VIH or CE2 = VIL IDDS1 CE1 = VDD - 0.2 V or CE2 = 0.2 V VDD = 1.5 V~3.6 V Standby Current IDDS2 (Note) mA mA VDD = 3 V ± 10% Ta = 25°C ¾ ¾ 0.6 Ta = -40~85°C ¾ ¾ 6 VDD = 3.3 V ± 0.3 V Ta = 25°C ¾ ¾ 0.7 Ta = -40~85°C ¾ ¾ 7 Ta = 25°C ¾ 0.05 0.5 Ta = -40~40°C ¾ ¾ 1 Ta = -40~85°C ¾ ¾ 5 VDD = 3.0 V Note: mA mA In standby mode with CE1 ³ VDD - 0.2 V, these limits are assured for the condition CE2 ³ VDD - 0.2 V or CE2 £ 0.2 V. CAPACITANCE (Ta = 25°C, f = 1 MHz) SYMBOL PARAMETER TEST CONDITION MAX UNIT CIN Input Capacitance VIN = GND 10 pF COUT Output Capacitance VOUT = GND 10 pF Note: This parameter is periodically sampled and is not 100% tested. 2001-09-04 3/11 TC55V400AFT-55,-70 AC CHARACTERISTICS AND OPERATING CONDITIONS (Ta = -40° to 85°C, VDD = 2.7 to 3.6 V) READ CYCLE TC55V400AFT SYMBOL PARAMETER -55 UNIT -70 MIN MAX MIN MAX tRC Read Cycle Time 55 ¾ 70 ¾ tACC Address Access Time ¾ 55 ¾ 70 tCO1 Chip Enable( CE1 ) Access Time ¾ 55 ¾ 70 tCO2 Chip Enable(CE2) Access Time ¾ 55 ¾ 70 tOE Output Enable Access Time ¾ 30 ¾ 35 tBA Data Byte Control Access Time ¾ 30 ¾ 35 tCOE Chip Enable Low to Output Active 5 ¾ 5 ¾ tOEE Output Enable Low to Output Active 0 ¾ 0 ¾ tBE Data Byte Control Low to Output Active 0 ¾ 0 ¾ tOD Chip Enable High to Output High-Z ¾ 25 ¾ 30 tODO Output Enable High to Output High-Z ¾ 25 ¾ 30 tBD Data Byte Control High to Output High-Z ¾ 25 ¾ 30 tOH Output Data Hold Time 10 ¾ 10 ¾ ns WRITE CYCLE TC55V400AFT SYMBOL PARAMETER -55 UNIT -70 MIN MAX MIN MAX tWC Write Cycle Time 55 ¾ 70 ¾ tWP Write Pulse Width 45 ¾ 50 ¾ tCW Chip Enable to End of Write 50 ¾ 60 ¾ tBW Data Byte Control to End of Write 45 ¾ 50 ¾ tAS Address Setup Time 0 ¾ 0 ¾ tWR Write Recovery Time 0 ¾ 0 ¾ tODW R/W Low to Output High-Z ¾ 25 ¾ 30 tOEW R/W High to Output Active 0 ¾ 0 ¾ tDS Data Setup Time 25 ¾ 30 ¾ tDH Data Hold Time 0 ¾ 0 ¾ ns AC TEST CONDITIONS PARAMETER Output load Input pulse level TEST CONDITION 30 pF + 1 TTL Gate 0.4 V, 2.4 V Timing measurements VDD ´ 0.5 Reference level VDD ´ 0.5 t R, t F 5 ns 2001-09-04 4/11 TC55V400AFT-55,-70 AC CHARACTERISTICS AND OPERATING CONDITIONS (Ta = -40° to 85°C, VDD = 2.3 to 3.6 V) READ CYCLE TC55V400AFT SYMBOL PARAMETER -55 UNIT -70 MIN MAX MIN MAX tRC Read Cycle Time 70 ¾ 85 ¾ tACC Address Access Time ¾ 70 ¾ 85 tCO1 Chip Enable( CE1 ) Access Time ¾ 70 ¾ 85 tCO2 Chip Enable(CE2) Access Time ¾ 70 ¾ 85 tOE Output Enable Access Time ¾ 35 ¾ 45 tBA Data Byte Control Access Time ¾ 35 ¾ 45 tCOE Chip Enable Low to Output Active 5 ¾ 5 ¾ tOEE Output Enable Low to Output Active 0 ¾ 0 ¾ tBE Data Byte Control Low to Output Active 0 ¾ 0 ¾ tOD Chip Enable High to Output High-Z ¾ 30 ¾ 35 tODO Output Enable High to Output High-Z ¾ 30 ¾ 35 tBD Data Byte Control High to Output High-Z ¾ 30 ¾ 35 tOH Output Data Hold Time 10 ¾ 10 ¾ ns WRITE CYCLE TC55V400AFT SYMBOL PARAMETER -55 UNIT -70 MIN MAX MIN MAX tWC Write Cycle Time 70 ¾ 85 ¾ tWP Write Pulse Width 50 ¾ 55 ¾ tCW Chip Enable to End of Write 60 ¾ 70 ¾ tBW Data Byte Control to End of Write 50 ¾ 55 ¾ tAS Address Setup Time 0 ¾ 0 ¾ tWR Write Recovery Time 0 ¾ 0 ¾ tODW R/W Low to Output High-Z ¾ 30 ¾ 35 tOEW R/W High to Output Active 0 ¾ 0 ¾ tDS Data Setup Time 30 ¾ 35 ¾ tDH Data Hold Time 0 ¾ 0 ¾ ns AC TEST CONDITIONS PARAMETER TEST CONDITION Output load 30 pF + 1 TTL Gate Input pulse level VDD - 0.2 V, 0.2 V Timing measurements VDD ´ 0.5 Reference level VDD ´ 0.5 t R, t F 5 ns 2001-09-04 5/11 TC55V400AFT-55,-70 TIMING DIAGRAMS READ CYCLE (See Note 1) tRC Address tACC tCO1 tOH CE1 tCO2 CE2 tOE tOD OE tBA tODO UB , LB tBE tOEE DOUT tBD VALID DATA OUT Hi-Z Hi-Z tCOE INDETERMINATE WRITE CYCLE 1 (R/W CONTROLLED) (See Note 4) tWC Address tAS tWP tWR R/W tCW CE1 tCW CE2 tBW UB , LB tODW DOUT (See Note 2) tOEW Hi-Z tDS DIN (See Note 5) (See Note 3) tDH VALID DATA IN (See Note 5) 2001-09-04 6/11 TC55V400AFT-55,-70 WRITE CYCLE 2 ( CE1 CONTROLLED) (See Note 4) tWC Address tAS tWP tWR R/W tCW CE1 tCW CE2 tBW UB , LB tBE DOUT Hi-Z tODW Hi-Z tCOE tDS DIN VALID DATA IN (See Note 5) WRITE CYCLE 3 (CE2 CONTROLLED) tDH (See Note 4) tWC Address tAS tWP tWR R/W tCW CE1 tCW CE2 tBW UB , LB tBE DOUT Hi-Z tODW Hi-Z tCOE tDS DIN (See Note 5) tDH VALID DATA IN 2001-09-04 7/11 TC55V400AFT-55,-70 WRITE CYCLE 4 ( UB, LB CONTROLLED) (See Note 4) tWC Address tAS tWP tWR R/W tCW CE1 tCW CE2 tBW UB , LB tBE DOUT Hi-Z tODW Hi-Z tCOE tDS DIN Note: (1) (See Note 5) tDH VALID DATA IN R/W remains HIGH for the read cycle. (2) If CE1 goes LOW(or CE2 goes HIGH) coincident with or after R/W goes LOW, the outputs will remain at high impedance. (3) If CE1 goes HIGH(or CE2 goes LOW) coincident with or before R/W goes HIGH, the outputs will remain at high impedance. (4) If OE is HIGH during the write cycle, the outputs will remain at high impedance. (5) Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied. 2001-09-04 8/11 TC55V400AFT-55,-70 DATA RETENTION CHARACTERISTICS (Ta = -40° to 85°C) SYMBOL PARAMETER VDH MIN TYP MAX UNIT 1.5 ¾ 3.6 V Ta = -40~40°C ¾ ¾ 1 Ta = -40~85°C ¾ ¾ 5 VDH = 3.6 V Ta = -40~85°C ¾ ¾ 7 0 ¾ ¾ ns ¾ ¾ ns Data Retention Supply Voltage VDH = 3.0 V IDDS2 Standby Current tCDR Chip Deselect to Data Retention Mode Time tR Note: Recovery Time tRC (See Note) mA Read cycle time CE1 CONTROLLED DATA RETENTION MODE VDD VDD (See Note 1) DATA RETENTION MODE 2.7 V (See Note 2) (See Note 2) VIH tCDR CE1 VDD - 0.2 V tR GND CE2 CONTROLLED DATA RETENTION MODE VDD VDD (See Note 3) DATA RETENTION MODE 2.7 V CE2 VIH VIL tCDR tR 0.2 V GND Note: (1) In CE1 controlled data retention mode, minimum standby current mode is entered when CE2 £ 0.2 V or CE2 ³ VDD - 0.2 V. (2) When CE1 is operating at the VIH level, the operating current is given by IDDS1 during the transition of VDD from 2.7 to 2.3V. (3) In CE2 controlled data retention mode, minimum standby current mode is entered when CE2 £ 0.2 V. 2001-09-04 9/11 TC55V400AFT-55,-70 PACKAGE DIMENSIONS Weight: 0.38 g (typ) 2001-09-04 10/11 TC55V400AFT-55,-70 RESTRICTIONS ON PRODUCT USE 000707EBA · TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. · The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. · The products described in this document are subject to the foreign exchange and foreign trade laws. · The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. · The information contained herein is subject to change without notice. 2001-09-04 11/11