HP HFBR-5803T Fddi 100 mb/s atm and fast ethernet transceivers in low cost 1 x 9 package style Datasheet

HFBR-5803/5803T/5803A/5803AT
FDDI, 100 Mb/s ATM, and Fast Ethernet
Transceivers in Low Cost 1 x 9 Package
Style
Data Sheet
Description
The HFBR-5800 family of transceivers from Agilent provide the
system designer with products
to implement a range of Fast
Ethernet, FDDI and ATM
(Asynchronous Transfer Mode)
designs at the 100 Mb/s-125
MBd rate.
The transceivers are all supplied
in the industry standard 1 x 9
SIP package style with either a
duplex SC or a duplex ST*
connector interface.
FDDI PMD, ATM and Fast Ethernet
2 km Backbone Links
The HFBR-5803/5803T are
1300 nm products with optical
performance compliant with the
FDDI PMD standard. The FDDI
PMD standard is ISO/IEC
9314-3:
1990 and ANSI X3.166 - 1990.
These transceivers for 2 km
multimode fiber backbones are
supplied in the small 1 x 9
duplex SC or ST package style.
The HFBR-5803/-5803T is useful
for both ATM 100 Mb/s
interfaces and Fast Ethernet 100
Base-FX interfaces. The ATM
Forum User-Network Interface
(UNI) Standard, Version 3.0,
defines the Physical Layer for
100 Mb/s Multimode Fiber
Interface for ATM in Section 2.3
to be the FDDI PMD Standard.
Likewise, the Fast Ethernet
Alliance defines the Physical
Layer for 100 Base-FX for Fast
Ethernet to be the FDDI PMD
Standard.
ATM applications for physical
layers other than 100 Mb/s
Multimode Fiber Interface are
supported by Agilent. Products
are available for both the single
mode and the multimode fiber
SONET OC-3c (STS-3c) ATM
interfaces and the 155 Mb/s-194
MBd multimode fiber ATM
interface as specified in the ATM
Forum UNI.
Contact your Agilent sales
representative for information
on these alternative Fast
Ethernet, FDDI and ATM
products.
Ordering Information
The HFBR-5803/5803T/5803A/
5803AT 1300 nm products are
available for production orders
through the Agilent Component
Field Sales Offices and
Authorized Distributors world
wide.
0 °C to +70 °C
HFBR-5803/5803T
-10 °C TO +85 °C
HFBR-5803A/5803AT
Features
• Full compliance with the optical
performance requirements of the
FDDI PMD standard
• Full compliance with the FDDI
LCF-PMD standard
• Full compliance with the optical
performance requirements of the
ATM 100 Mb/s physical layer
• Full compliance with the optical
performance requirements of
100 Base-FX version of IEEE 802.3u
• Multisourced 1 x 9 package style
with choice of duplex SC or
duplex ST* receptacle
• Wave solder and aqueous wash
process compatible
• Manufactured in an ISO 9002
certified facility
• Single +3.3 V or +5 V power
supply
Applications
• Multimode fiber backbone links
• Multimode fiber wiring closet to
desktop links
• Very low cost multimode fiber
links from wiring closet to
desktop
• Multimode fiber media converters
*ST is a registered trademark of AT&T
Lightguide Cable Connectors.
Note: The “T” in the product numbers
indicates a transceiver with a duplex ST
connector receptacle.
Product numbers without a “T” indicate
transceivers with a duplex SC connector
receptacle.
Transmitter Sections
The transmitter section of the
HFBR-5803 and HFBR-5805
series utilize 1300 nm Surface
Emitting InGaAsP LEDs. These
LEDs are packaged in the optical
subassembly portion of the
transmitter section. They are
driven by a custom silicon IC
which converts differential
PECL logic signals, ECL
referenced (shifted) to a +3.3 V
or +5 V supply, into an analog
LED drive current.
Receiver Sections
The receiver sections of the
HFBR-5803 and HFBR-5805
series utilize InGaAs PIN photodiodes coupled to a custom
silicon transimpedance
preamplifier IC. These are
packaged in the optical subassembly portion of the receiver.
These PIN/preamplifier combinations are coupled to a custom
quantizer IC which provides the
final pulse shaping for the logic
output and the Signal Detect
function. The data output is differential. The signal detect
output is single-ended. Both
data and signal detect outputs
are PECL compatible, ECL
referenced (shifted) to a +3.3 V
or +5 V power supply.
Package
The overall package concept for
the Agilent transceivers consists
of the following basic elements;
two optical subassemblies, an
electrical subassembly and the
housing as illustrated in Figure 1
and Figure 1a.
The package outline drawings
and pin out are shown in
Figures 2, 2a and 3. The details
of this package outline and pin
out are compliant with the
multisource definition of the 1 x
9 SIP. The low profile of the
Agilent transceiver design
complies with the maximum
height allowed for the duplex SC
connector over the entire length
of the package.
The optical subassemblies utilize
a high volume assembly process
together with low cost lens
elements which result in a cost
effective building block.
The electrical subassembly consists of a high volume multilayer
printed circuit board on which
the IC chips and various surfacemounted passive circuit
elements are attached.
The outer housing including the
duplex SC connector receptacle
or the duplex ST ports is molded
of filled nonconductive plastic to
provide mechanical strength and
electrical isolation. The solder
posts of the Agilent design are
isolated from the circuit design
of the transceiver and do not
require connection to a ground
plane on the circuit board.
The transceiver is attached to a
printed circuit board with the
nine signal pins and the two
solder posts which exit the
bottom of the housing. The two
solder posts provide the primary
mechanical strength to
withstand the loads imposed on
the transceiver by mating with
duplex or simplex SC or ST
connectored fiber cables.
The package includes internal
shields for the electrical and
optical subassemblies to ensure
low EMI emissions and high
immunity to external EMI fields.
ELECTRICAL SUBASSEMBLY
DUPLEX SC
RECEPTACLE
DIFFERENTIAL
DATA OUT
PIN PHOTODIODE
SINGLE-ENDED
SIGNAL
DETECT OUT
QUANTIZER IC
PREAMP IC
OPTICAL
SUBASSEMBLIES
DIFFERENTIAL
LED
DATA IN
DRIVER IC
TOP VIEW
Figure 1. SC Connector Block Diagram.
2
ELECTRICAL SUBASSEMBLY
DUPLEX ST
RECEPTACLE
DIFFERENTIAL
DATA OUT
PIN PHOTODIODE
SINGLE-ENDED
SIGNAL
DETECT OUT
QUANTIZER IC
PREAMP IC
OPTICAL
SUBASSEMBLIES
DIFFERENTIAL
LED
DATA IN
DRIVER IC
TOP VIEW
Figure 1a. ST Connector Block Diagram.
Case Temperature
Measurement Point
39.12
MAX.
(1.540)
12.70
(0.500)
AREA
RESERVED
FOR
PROCESS
PLUG
25.40
MAX.
(1.000)
AGILENT
6.35
(0.250)
HFBR-5803
DATE CODE (YYWW)
SINGAPORE
12.70
(0.500)
5.93 ± 0.1
(0.233 ± 0.004)
+ 0.08
– 0.05
+ 0.003 )
(0.030
– 0.002
0.75
3.30 ± 0.38
(0.130 ± 0.015)
10.35 MAX.
(0.407)
2.92
(0.115)
Ø
23.55
(0.927)
18.52
(0.729)
0.46
(9x)
(0.018)
NOTE 1
20.32 [8x(2.54/.100)]
(0.800)
4.14
(0.163
17.32 20.32
23.32
(0.682 (0.800) (0.918)
16.70
(0.657)
0.87
(0.034)
1.27 + 0.25
– 0.05
(0.050 + 0.010 )
– 0.002
NOTE 1
23.24
(0.915)
15.88
(0.625)
NOTE 1: THE SOLDER POSTS AND ELECTRICAL PINS ARE PHOSPHOR BRONZE WITH TIN LEAD OVER NICKEL PLATING.
DIMENSIONS ARE IN MILLIMETERS (INCHES).
Figure 2. SC Connector Package Outline Drawing with standard height.
3
42 MAX.
(1.654)
5.99
(0.236)
24.8
(0.976)
12.7
(0.500)
25.4
MAX.
(1.000)
Case Temperature
Measurement Point
12.0
MAX.
(0.471)
3.2
(0.126)
20.32
Ø 0.46
(0.018)
NOTE 1
20.32
[(8x (2.54/0.100)]
(0.800)
22.86
(0.900)
21.4
(0.843)
3.6
(0.142)
+ 0.08
0.5
- 0.05
(0.020) + 0.003
( - 0.002
(
HFBR-5803T
DATE CODE (YYWW)
SINGAPORE
3.3 ± 0.38
(0.130 ± 0.015)
± 0.38
(± 0.015)
Ø 2.6
(0.102)
+ 0.25
- 0.05
(0.050) + 0.010
( - 0.002 )
1.27
17.4
(0.685)
20.32
(0.800)
1.3
(0.051)
23.38
(0.921)
18.62
(0.733)
NOTE 1: PHOSPHOR BRONZE IS THE BASE MATERIAL FOR THE POSTS & PINS WITH TIN LEAD OVER NICKEL PLATING.
DIMENSIONS IN MILLIMETERS (INCHES).
Figure 2a. ST Connector Package Outline Drawing with standard height.
1 = VEE
N/C
2 = RD
Rx
3 = RD
4 = SD
5 = VCC
6 = VCC
7 = TD
Tx
8 = TD
N/C
9 = VEE
TOP VIEW
Figure 3. Pin Out Diagram.
4
Transceiver Optical Power Budget
versus Link Length
Optical Power Budget (OPB) is
the available optical power for a
fiber optic link to accommodate
fiber cable losses plus losses due
to in-line connectors, splices,
optical switches, and to provide
margin for link aging and
unplanned losses due to cable
plant reconfiguration or repair.
Figure 4 illustrates the predicted
OPB associated with the
transceiver series specified in
this data sheet at the Beginning
of Life (BOL). These curves
represent the attenuation and
chromatic plus modal dispersion
losses associated with the 62.5/
125 µm and 50/125 µm fiber
cables only. The area under the
curves represents the remaining
OPB at any link length, which is
available for overcoming nonfiber cable related losses.
Agilent LED technology has
produced 1300 nm LED devices
with lower aging characteristics
than normally associated with
these technologies in the
industry. The industry convention is 1.5 dB aging for 1300 nm
LEDs. The Agilent 1300 nm
LEDs will experience less than
1 dB of aging over normal commercial equipment mission life
periods. Contact your Agilent
sales representative for
additional details.
5
12
When used in Fast Ethernet,
FDDI and ATM 100 Mb/s
applications the performance of
the 1300 nm transceivers is
guaranteed over the signaling
rate of 10 MBd to
125 MBd to the full conditions
listed in individual product
specification tables.
2.5
TRANSCEIVER RELATIVE OPTICAL POWER BUDGET
AT CONSTANT BER (dB)
The following information is
provided to answer some of the
most common questions about
the use of these parts.
Figure 4 was generated with a
Agilent fiber optic link model
containing the current industry
conventions for fiber cable
specifications and the FDDI
PMD and LCF-PMD optical
parameters. These parameters
are reflected in the guaranteed
performance of the transceiver
specifications in this data sheet.
This same model has been used
extensively in the ANSI and
IEEE committees, including the
ANSI X3T9.5 committee, to
establish the optical performance
requirements for various fiber
optic interface standards. The
cable parameters used come
from the ISO/IEC JTC1/SC 25/
WG3 Generic Cabling for
Customer Premises per
DIS 11801 document and the
EIA/TIA-568-A Commercial
Building Telecommunications
Cabling Standard per SP-2840.
2.0
1.5
1.0
0.5
0
0.5
0
25
50
75
100
125
150
175 200
SIGNAL RATE (MBd)
CONDITIONS:
1. PRBS 27-1
2. DATA SAMPLED AT CENTER OF DATA SYMBOL.
3. BER = 10-6
4. TA = +25° C
5. VCC = 3.3 V to 5 V dc
6. INPUT OPTICAL RISE/FALL TIMES = 1.0/2.1 ns.
HFBR-5803, 62.5/125 µm
Figure 5. Transceiver Relative Optical Power
Budget at Constant BER vs. Signaling Rate.
10
OPTICAL POWER BUDGET (dB)
Application Information
The Applications Engineering
group in the Agilent Fiber Optics
Communication Division is
available to assist you with the
technical understanding and
design trade-offs associated with
these transceivers. You can
contact them through your
Agilent sales representative.
8
HFBR-5803
50/125 µm
6
4
2
0
0.3 0.5
1.0
1.5
2.0
2.5
FIBER OPTIC CABLE LENGTH (km)
Figure 4. Optical Power Budget at BOL versus
Fiber Optic Cable Length.
Transceiver Signaling Operating
Rate Range and BER Performance
For purposes of definition, the
symbol (Baud) rate, also called
signaling rate, is the reciprocal
of the shortest symbol time. Data
rate (bits/sec) is the symbol rate
divided by the encoding factor
used to encode the data
(symbols/bit).
The transceivers may be used
for other applications at signaling rates outside of the 10 MBd
to 125 MBd range with some
penalty in the link optical power
budget primarily caused by a
reduction of receiver sensitivity.
Figure 5 gives an indication of
the typical performance of these
1300 nm products at different
rates.
These transceivers can also be
used for applications which
require different Bit Error Rate
(BER) performance. Figure 6
illustrates the typical trade-off
between link BER and the
receivers input optical power
level.
1 x 10-2
BIT ERROR RATE
1 x 10-3
1 x 10-4
HFBR-5803 SERIES
violating the Annex E allocation
example. In practice the typical
contribution of the Agilent transceivers is well below these
maximum allowed amounts.
damage which may be induced
by electrostatic discharge (ESD).
The HFBR-5800 series of
transceivers meet MIL-STD-883C
Method 3015.4 Class 2 products.
Recommended Handling Precautions
Agilent recommends that normal
static precautions be taken in
the handling and assembly of
these transceivers to prevent
Care should be used to avoid
shorting the receiver data or
signal detect outputs directly to
ground without proper current
limiting impedance.
1 x 10-5
1 x 10-6
CENTER OF SYMBOL
1 x 10-7
1 x 10-8
1 x 10-9
1 x 10-10
1 x 10-11
1 x 10-12
-6
-4
-2
0
2
4
RELATIVE INPUT OPTICAL POWER - dB
CONDITIONS:
1. 155 MBd
2. PRBS 27-1
3. CENTER OF SYMBOL SAMPLING
4. TA = +25°C
5. VCC = 3.3 V to 5 V dc
6. INPUT OPTICAL RISE/FALL TIMES = 1.0/2.1 ns.
Figure 6. Bit Error Rate vs. Relative Receiver
Input Optical Power.
Rx
Tx
000
000
000
000
000
000
000
000
NO INTERNAL CONNECTION
Transceiver Jitter Performance
The Agilent 1300 nm
transceivers are designed to
operate per the system jitter
allocations stated in Tables E1 of
Annexes E of the FDDI PMD and
LCF-PMD standards.
The Agilent 1300 nm
transmitters will tolerate the
worst case input electrical jitter
allowed in these tables without
violating the worst case output
jitter requirements of Sections
8.1 Active Output Interface of
the FDDI PMD and LCF-PMD
standards.
The Agilent 1300 nm receivers
will tolerate the worst case input
optical jitter allowed in Sections
8.2 Active Input Interface of the
FDDI PMD and LCF-PMD
standards without violating the
worst case output electrical
jitter allowed in the Tables E1 of
the Annexes E.
The jitter specifications stated in
the following 1300 nm
transceiver specification tables
are derived from the values in
Tables E1 of Annexes E. They
represent the worst case jitter
contribution that the transceivers are allowed to make to
the overall system jitter without
6
NO INTERNAL CONNECTION
HFBR-5803
TOP VIEW
Rx
VEE
1
000
000
000
000
RD
2
RD
3
0000
0000
0000
0000
0000
0000
0000
0000
SD
4
0000
0000
0000
0000
Rx
VCC
5
Tx
VCC
6
0000
0000
0000
0000
TD
7
0000
0000
0000
0000
C1
0000
0000
0000
0000
Tx
VEE
9
TD
8
0000
0000
0000
0000
000
000
000
000
C2
VCC
L1
TERMINATION
AT PHY
DEVICE
INPUTS
VCC
R5
R8
0000
0000
0000
0000
0000
0000
RD
RD
SD
0000
0000
0000
VCC
R4
C5
TERMINATION
AT TRANSCEIVER
INPUTS
R10
0000
0000
0000
R3
R1
C3
C4
VCC FILTER
AT VCC PINS
TRANSCEIVER
R9
R7
C6
R6
R2
L2
0000
0000
0000
0000
0000
0000
TD
TD
NOTES:
THE SPLIT-LOAD TERMINATIONS FOR ECL SIGNALS NEED TO BE LOCATED AT THE INPUT
OF DEVICES RECEIVING THOSE ECL SIGNALS. RECOMMEND 4-LAYER PRINTED CIRCUIT
BOARD WITH 50 OHM MICROSTRIP SIGNAL PATHS BE USED.
R1 = R4 = R6 = R8 = R10 = 130 OHMS FOR +5.0 V OPERATION, 82 OHMS FOR +3.3 V OPERATION.
R2 = R3 = R5 = R7 = R9 = 82 OHMS FOR +5.0 V OPERATION, 130 OHMS FOR +3.3 V OPERATION.
C1 = C2 = C3 = C5 = C6 = 0.1 µF.
C4 = 10 µF.
L1 = L2 = 1 µH COIL OR FERRITE INDUCTOR.
Figure 7. Recommended Decoupling and Termination Circuits
Solder and Wash Process
Compatibility
The transceivers are delivered
with protective process plugs
inserted into the duplex SC or
duplex ST connector receptacle.
This process plug protects the
optical subassemblies during
wave solder and aqueous wash
processing and acts as a dust
cover during shipping.
These transceivers are compatible with either industry
standard wave or hand solder
processes.
Shipping Container
The transceiver is packaged in a
shipping container designed to
protect it from mechanical and
ESD damage during shipment or
storage.
Board Layout - Decoupling Circuit
and Ground Planes
It is important to take care in
the layout of your circuit board
to achieve optimum
performance from these
transceivers. Figure 7 provides a
good example of a schematic for
a power supply decoupling
circuit that works well with
these parts. It is further
recommended that a contiguous
ground plane be provided in the
circuit board directly under the
transceiver to provide a low
inductance ground for signal
return current. This recommendation is in keeping with good
high frequency board layout
practices.
Board Layout - Hole Pattern
The Agilent transceiver complies
with the circuit board “Common
Transceiver Footprint” hole
pattern defined in the original
multisource announcement
which defined the 1 x 9 package
style. This drawing is reproduced in Figure 8 with the
addition of ANSI Y14.5M
compliant dimensioning to be
used as a guide in the mechanical layout of your circuit board.
2 x Ø 1.9 ± 0.1
(0.075 ± 0.004)
20.32
(0.800)
9 x Ø 0.8 ± 0.1
(0.032 ± 0.004)
20.32
(0.800)
2.54
(0.100)
TOP VIEW
DIMENSIONS ARE IN MILLIMETERS (INCHES)
Figure 8. Recommended Board Layout Hole Pattern
7
Board Layout - Art Work
The Applications Engineering
group has developed Gerber file
artwork for a multilayer printed
circuit board layout incorporating the recommendations above.
Contact your local Agilent sales
representative for details.
Board Layout - Mechanical
For applications providing a
choice of either a duplex SC or a
duplex ST connector interface,
while utilizing the same pinout
on the printed circuit board, the
ST port needs to protrude from
the chassis panel a minimum of
9.53 mm for sufficient clearance
to install the ST connector.
Please refer to Figure 8a for a
mechanical layout detailing the
recommended location of the
duplex SC and duplex ST transceiver packages in relation to
the chassis panel.
42.0
12.0
0.51
0000
0000
0000
0000
0000
0000
9.53
0000
(NOTE 1) 0000
0000
0000
0000
0000
0000
0000
0000
24.8
12.09
0000
0000
0000
0000
0000
11.1
6.79
0.75
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
25.4
39.12
25.4
NOTE 1: MINIMUM DISTANCE FROM FRONT
OF CONNECTOR TO THE PANEL FACE.
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
Figure 8a. Recommended Common Mechanical Layout for SC and ST 1 x 9 Connectored Transceivers.
Regulatory Compliance
These transceiver products are
intended to enable commercial
system designers to develop
equipment that complies with
the various international
regulations governing certification of Information Technology
Equipment. See the Regulatory
Compliance Table for details.
Additional information is
available from your Agilent sales
representative.
8
Electrostatic Discharge (ESD)
There are two design cases in
which immunity to ESD damage
is important.
The first case is during handling
of the transceiver prior to
mounting it on the circuit board.
It is important to use normal
ESD handling precautions for
ESD sensitive devices. These
precautions include using
grounded wrist straps, work
benches, and floor mats in ESD
controlled areas.
The second case to consider is
static discharges to the exterior
of the equipment chassis containing the transceiver parts. To
the extent that the duplex SC
connector is exposed to the
outside of the equipment chassis
it may be subject to whatever
ESD system level test criteria
that the equipment is intended
to meet.
Regulatory Compliance Table
Feature
Test Method
Performance
Electrostatic Discharge (ESD) to MIL-STD-883C
Meets Class 1 (<1999 Volts)
the Electrical Pins
Withstand up to 1500 V applied between electrical pins.
Method 3015.4
Electrostatic Discharge (ESD) to Variation of
Typically withstand at least 25 kV without damage when the Duplex SC
the Duplex SC Receptacle
IEC 801-2
Connector Receptacle is contacted by a Human Body Model probe.
Electromagnetic Interference
FCC Class B
Typically provide a 13 dB margin (with duplex SC package) or a 9 dB margin
(EMI)
CENELEC CEN55022
(with duplex ST package) to the noted standard limits when tested at a certified
Class B (CISPR 22B)
VCCI Class 2
Immunity
test range with the transceiver mounted to a circuit card without a chassis
enclosure.
Variation of
Typically show no measurable effect from a 10 V/m field swept from 10 to 450
IEC 801-3
MHz applied to the transceiver when mounted to a circuit card without a
chassis enclosure.
Electromagnetic Interference (EMI)
Most equipment designs utilizing
these high speed transceivers
from Agilent will be required to
meet the requirements of FCC in
the United States, CENELEC
EN55022 (CISPR 22) in Europe
and VCCI in Japan.
Dl - TRANSMITTER OUTPUT OPTICAL
SPECTRAL WIDTH (FWHM) - nm
200
180
160
3.0
Immunity
Equipment utilizing these
transceivers will be subject to
radio-frequency electromagnetic
fields in some environments.
These transceivers have a high
immunity to such fields.
1.5
3.5
2.0
140 2.5
120
3.0
tr/f - TRANSMITTER
OUTPUT OPTICAL
RISE/FALL TIMES - ns
3.5
100
1200
1300
1320
1340
1360
1380
l C - TRANSMITTER OUTPUT OPTICAL
CENTER WAVELENGTH - nm
HFBR-5803 FDDI TRANSMITTER TEST RESULTS
OF l C, Dl AND tr/f ARE CORRELATED AND
COMPLY WITH THE ALLOWED SPECTRAL WIDTH
AS A FUNCTION OF CENTER WAVELENGTH FOR
VARIOUS RISE AND FALL TIMES.
Figure 9. Transmitter Output Optical Spectral
Width (FWHM) vs. Transmitter Output Optical
Center Wavelength and Rise/Fall Times.
9
In all well-designed chassis, two
0.5" holes for ST connectors to
protrude through will provide
4.6 dB more shielding than one
1.2" duplex SC rectangular
cutout. Thus, in a well-designed
chassis, the duplex ST 1 x 9
transceiver emissions will be
identical to the duplex SC 1 x 9
transceiver emissions.
For additional information
regarding EMI, susceptibility,
ESD and conducted noise testing
procedures and results on the
1 x 9 Transceiver family, please
refer to Applications Note 1075,
Testing and Measuring Electromagnetic Compatibility
Performance of the HFBR-510X/
520X Fiber Optic Transceivers.
Transceiver Reliability and
Performance Qualification Data
The 1 x 9 transceivers have
passed Agilent reliability and
performance qualification
testing and are undergoing
ongoing quality monitoring.
Details are available from your
Agilent sales representative.
These transceivers are manufactured at the Agilent Singapore
location which is an ISO 9002
certified facility.
Accessory Duplex SC Connectored
Cable Assemblies
Agilent recommends for optimal
coupling the use of flexible-body
duplex SC connectored cable.
Accessory Duplex ST Connectored
Cable Assemblies
Agilent recommends the use of
Duplex Push-Pull connectored
cable for the most repeatable
optical power coupling
performance.
4.40
1.975
1.25
4.850
10.0
1.025
1.00
0.975
0.90
5.6
0.075
RELATIVE AMPLITUDE
100% TIME
INTERVAL
40 ± 0.7
± 0.725
0.50
± 0.725
0% TIME
INTERVAL
0.10
0.025
0.0
-0.025
-0.05
0.075
1.525
0.525
5.6
10.0
1.975
4.40
4.850
80 ± 500 ppm
TIME - ns
THE HFBR-5803 OUTPUT OPTICAL PULSE SHAPE SHALL FIT WITHIN THE BOUNDARIES OF THE
PULSE ENVELOPE FOR RISE AND FALL TIME MEASUREMENTS.
Figure 10. Output Optical Pulse Envelope.
RELATIVE INPUT OPTICAL POWER (dB)
5
4
3
2.5 x 10-10 BER
2
1.0 x 10-12 BER
1
0
-4
-3
-2
-1
0
1
2
3
4
EYE SAMPLING TIME POSITION (ns)
CONDITIONS:
1.TA = +25°C
2. VCC = 3.3 V to 5 V dc
3. INPUT OPTICAL RISE/FALL TIMES = 1.0/2.1 ns.
4. INPUT OPTICAL POWER IS NORMALIZED TO
CENTER OF DATA SYMBOL.
5. NOTE 19 AND 20 APPLY.
Figure 11. Relative Input Optical Power vs.
Eye Sampling Time Position.
10
1.525
0.525
-31.0 dBm
MIN (PO + 4.0 dB OR -31.0 dBm)
PA(PO + 1.5 dB < PA < -31.0 dBm)
OPTICAL POWER
PO = MAX (PS OR -45.0 dBm)
(PS = INPUT POWER FOR BER < 102)
INPUT OPTICAL POWER
(> 1.5 dB STEP INCREASE)
INPUT OPTICAL POWER
(> 4.0 dB STEP DECREASE)
-45.0 dBm
ANS _ MAX
SIGNAL
DETECT
OUTPUT
AS _ MAX
SIGNAL _ DETECT (ON)
SIGNAL _ DETECT (OFF)
TIME
AS _ MAX - MAXIMUM ACQUISITION TIME (SIGNAL).
AS _ MAX IS THE MAXIMUM SIGNAL _ DETECT ASSERTION TIME FOR THE STATION.
AS _ MAX SHALL NOT EXCEED 100.0 µs. THE DEFAULT VALUE OF AS _ MAX IS 100.0 µs.
ANS _ MAX - MAXIMUM ACQUISITION TIME (NO SIGNAL).
ANS _ MAX IS THE MAXIMUM SIGNAL _ DETECT DEASSERTION TIME FOR THE STATION.
ANS _ MAX SHALL NOT EXCEED 350 µs. THE DEFAULT VALUE OF AS _ MAX IS 350 µs.
Figure 12. Signal Detect Thresholds and Timing.
11
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause catastrophic damage to the device. Limits apply to each parameter in
isolation, all other parameters having values within the recommended operating conditions. It should not be assumed that limiting values
of more than one parameter can be applied to the product at the same time. Exposure to the absolute maximum ratings for extended
periods can adversely affect device reliability.
Parameter
Symbol
Min.
Storage Temperature
TS
-40
Typ.
Max.
Unit
+100
°C
Reference
Lead Soldering Temperature
TSOLD
+260
°C
Lead Soldering Time
tSOLD
10
sec.
Supply Voltage
VCC
-0.5
7.0
V
Data Input Voltage
VI
-0.5
VCC
V
Differential Input Voltage
VD
1.4
V
Output Current
IO
50
mA
Max.
Unit
Reference
Note 1
Recommended Operating Conditions
Parameter
Symbol
Min.
Ambient Operating Temperature
HFBR-5803/5803T
Typ.
TA
0
+70
°C
Note A
HFBR-5803A/5803AT
Supply Voltage
TA
VCC
-10
3.135
+85
3.5
°C
V
Note B
VCC
4.75
5.25
V
Data Input Voltage - Low
VIL - VCC
-1.810
-1.475
V
Data Input Voltage - High
VIH - VCC
-1.165
-0.880
Data and Signal Detect Output Load
50
RL
V
W
Note 2
Notes:
A. Ambient Operating Temperature corresponds to transceiver case temperature of 0°C mininum to +85 °C maximum with necessary airflow applied.
Recommended case temperature measurement point can be found in Figure 2.
B. Ambient Operating Temperature corresponds to transceiver case temperature of -10 °C mininum to +100 °C maximum with necessary airflow applied.
Recommended case temperature measurement point can be found in Figure 2.
Transmitter Electrical Characteristics
(HFBR-5803/5803T: TA = 0°C to +70°C, VCC = 3.135 V to 3.5 V or 4.75 V to 5.25 V)
(HFBR-5803A/HFBR-5803AT: TA = -10°C to +85°C, VCC = 3.135 V to 3.5 V or 4.75 V to 5.25 V)
Parameter
Symbol
Typ.
Max.
Unit
Reference
Supply Current
ICC
133
175
mA
Note 3
at VCC = 3.3 V
PDISS
0.45
0.6
W
at VCC = 5.0 V
PDISS
0.76
0.97
W
Power Dissipation
Data Input Current - Low
IIL
Data Input Current - High
IIH
12
Min.
-350
-2
18
µA
350
µA
Receiver Electrical Characteristics
(HFBR-5803/5803T: TA = 0°C to +70°C, VCC = 3.135 V to 3.5 V or 4.75 V to 5.25 V)
(HFBR-5803A/HFBR-5803AT: TA = -10°C to +85°C, VCC = 3.135 V to 3.5 V or 4.75 V to 5.25 V)
Parameter
Symbol
Typ.
Max.
Unit
Reference
Supply Current
ICC
87
120
mA
Note 4
at VCC = 3.3 V
PDISS
0.15
0.25
W
Note 5
at VCC = 5.0 V
PDISS
0.3
0.5
W
Note 5
Power Dissipation
Min.
Data Output Voltage - Low
VOL - VCC
-1.840
-1.620
V
Note 6
Data Output Voltage - High
VOH - VCC
-1.045
-0.880
V
Note 6
Data Output Rise Time
tr
0.35
2.2
ns
Note 7
Data Output Fall Time
tf
0.35
2.2
ns
Note 7
Signal Detect Output Voltage - Low
VOL - VCC
-1.840
-1.620
V
Note 6
Signal Detect Output Voltage - High
VOH - VCC
-1.045
-0.880
V
Note 6
Signal Detect Output Rise Time
tr
0.35
2.2
ns
Note 7
Signal Detect Output Fall Time
tf
0.35
2.2
ns
Note 7
Transmitter Optical Characteristics
(HFBR-5803/5803T: TA = 0°C to +70°C, VCC = 3.135 V to 3.5 V or 4.75 V to 5.25 V)
(HFBR-5803A/HFBR-5803AT: TA = -10°C to +85°C, VCC = 3.135 V to 3.5 V or 4.75 V to 5.25 V)
Parameter
Output Optical Power
BOL
62.5/125 µm, NA = 0.275 Fiber
EOL
Output Optical Power
BOL
50/125 µm, NA = 0.20 Fiber
EOL
Symbol
Min.
PO
-19
Max.
Unit
Reference
-14
dBm avg.
Note 11
-14
dBm avg.
Note 11
-20
PO
-22.5
-23.5
Optical Extinction Ratio
Output Optical Power at Logic “0” State
Typ.
0.05
PO (“0”)
0.2
%
Note 12
-45
dBm avg.
Note 13
1380
nm
Note 14
nm
Note 14
Center Wavelength
lC
Spectral Width - FWHM
Dl
147
Spectral Width - nm RMS
Optical Rise Time
tr
0.6
63
1.9
3.0
ns
Figure 9
Note 14, 15
Optical Fall Time
tf
0.6
1.6
3.0
ns
Note 14, 15
1270
1308
Figure 9, 10
Figure 9, 10
Duty Cycle Distortion Contributed by the Transmitter
DCD
0.6
ns p-p
Note 16
Data Dependent Jitter Contributed by the Transmitter
DDJ
0.6
ns p-p
Note 17
Random Jitter Contributed by the Transmitter
RJ
0.69
ns p-p
Note 18
13
Receiver Optical and Electrical Characteristics
(HFBR-5803/5803T: TA = 0°C to +70°C, VCC = 3.135 V to 3.5 V or 4.75 V to 5.25 V)
(HFBR-5803A/HFBR-5803AT: TA = -10°C to +85°C, VCC = 3.135 V to 3.5 V or 4.75 V to 5.25 V)
Parameter
Symbol
Input Optical Power Minimum at Window Edge
PIN Min. (W)
Min.
Typ.
Max.
Unit
-33.9
-31
dBm avg.
Reference
Note 19
Figure 11
Input Optical Power Minimum at Eye Center
PIN Min. (C)
-35.2
-31.8
dBm avg.
Note 20
Figure 11
Input Optical Power Maximum
PIN Max.
-14
1270
dBm avg.
Note 19
Operating Wavelength
l
1380
nm
Duty Cycle Distortion Contributed by the Receiver
DCD
0.4
ns p-p
Data Dependent Jitter Contributed by the Receiver
DDJ
1.0
ns p-p
Note 9
Random Jitter Contributed by the Receiver
RJ
2.14
ns p-p
Note 10
Signal Detect - Asserted
PA
PD + 1.5 dB
-33
dBm avg.
Note 21, 22
Signal Detect - Deasserted
PD
-45
Note 8
Figure 12
dBm avg.
Note 23, 24
Figure 12
Signal Detect - Hysteresis
PA - PD
1.5
Signal Detect Assert Time (off to on)
AS_Max
0
2
100
dB
Figure 12
µs
Note 21, 22
Figure 12
Signal Detect Deassert Time (on to off)
ANS_Max
0
8
350
µs
Note 23, 24
Figure 12
Notes:
1. This is the maximum voltage that can be
applied across the Differential Transmitter
Data Inputs to prevent damage to the input
ESD protection circuit.
2. The outputs are terminated with 50 W
connected to VCC -2 V.
3. The power supply current needed to operate
the transmitter is provided to differential
ECL circuitry. This circuitry maintains a
nearly constant current flow from the power
supply. Constant current operation helps to
prevent unwanted electrical noise from
being generated and conducted or emitted
to neighboring circuitry.
4. This value is measured with the outputs
terminated into 50 W connected to V CC - 2 V
and an Input Optical Power level of
-14 dBm average.
5. The power dissipation value is the power
dissipated in the receiver itself. Power
dissipation is calculated as the sum of the
products of supply voltage and currents,
minus the sum of the products of the output
voltages and currents.
6. This value is measured with respect to VCC
with the output terminated into 50 W
connected to VCC - 2 V.
7. The output rise and fall times are measured
between 20% and 80% levels with the
output connected to VCC -2 V through 50 W.
8. Duty Cycle Distortion contributed by the
receiver is measured at the 50% threshold
14
using an IDLE Line State, 125 MBd
(62.5 MHz square-wave), input signal. The
input optical power level is -20 dBm
average. See Application Information Transceiver Jitter Section for further
information.
9. Data Dependent Jitter contributed by
the receiver is specified with the FDDI DDJ
test pattern described in the FDDI PMD
Annex A.5. The input optical power level is 20 dBm average. See Application Information - Transceiver Jitter Section for further
information.
10. Random Jitter contributed by the receiver is
specified with an IDLE Line State,
125 MBd (62.5 MHz square-wave), input
signal. The input optical power level is at
maximum “PIN Min. (W)”. See Application
Information - Transceiver Jitter Section for
further information.
11. These optical power values are measured
with the following conditions:
• The Beginning of Life (BOL) to the End of
Life (EOL) optical power degradation is
typically 1.5 dB per the industry
convention for long wavelength LEDs.
The actual degradation observed in
Agilent’s 1300 nm LED products is
< 1 dB, as specified in this data sheet.
• Over the specified operating voltage and
temperature ranges.
•
With HALT Line State, (12.5 MHz squarewave), input signal.
• At the end of one meter of noted optical
fiber with cladding modes removed.
The average power value can be converted
to a peak power value by adding 3 dB.
Higher output optical power transmitters
are available on special request.
12. The Extinction Ratio is a measure of the
modulation depth of the optical signal. The
data “0” output optical power is compared
to the data “1” peak output optical power
and expressed as a percentage. With the
transmitter driven by a HALT Line State
(12.5 MHz square-wave) signal, the average
optical power is measured. The data “1”
peak power is then calculated by adding 3
dB to the measured average optical power.
The data “0” output optical power is found
by measuring the optical power when the
transmitter is driven by a logic “0” input.
The extinction ratio is the ratio of the
optical power at the “0” level compared to
the optical power at the “1” level expressed
as a percentage or in decibels.
13. The transmitter provides compliance with
the need for Transmit_Disable commands
from the FDDI SMT layer by providing an
Output Optical Power level of < -45 dBm
average in response to a logic “0” input.
This specification applies to either 62.5/125
µm or 50/125 µm fiber cables.
14. This parameter complies with the FDDI PMD
requirements for the trade-offs between
center wavelength, spectral width, and rise/
fall times shown in Figure 9.
15. This parameter complies with the optical
pulse envelope from the FDDI PMD shown
in Figure 10. The optical rise and fall times
are measured from 10% to 90% when the
transmitter is driven by the FDDI HALT Line
State (12.5 MHz square-wave) input signal.
16. Duty Cycle Distortion contributed by the
transmitter is measured at a 50% threshold
using an IDLE Line State, 125 MBd
(62.5 MHz square-wave), input signal. See
Application Information - Transceiver Jitter
Performance Section of this data sheet for
further details.
17. Data Dependent Jitter contributed by the
transmitter is specified with the FDDI test
pattern described in FDDI PMD Annex A.5.
See Application Information - Transceiver
Jitter Performance Section of this data
sheet for further details.
18. Random Jitter contributed by the
transmitter is specified with an IDLE Line
State, 125 MBd (62.5 MHz square-wave),
input signal. See Application Information Transceiver Jitter Performance Section of
this data sheet for further details.
19. This specification is intended to indicate the
performance of the receiver section of the
transceiver when Input Optical Power signal
characteristics are present per the following
definitions. The Input Optical Power
dynamic range from the minimum level (with
a window time-width) to the maximum level
is the range over which the receiver is
guaranteed to provide output data with a Bit
Error Ratio (BER) better than or equal to 2.5
x 10 -10.
• At the Beginning of Life (BOL)
• Over the specified operating temperature
and voltage ranges
• Input symbol pattern is the FDDI test
pattern defined in FDDI PMD Annex A.5
with 4B/5B NRZI encoded data that
contains a duty cycle base-line wander
effect of 50 kHz. This sequence causes a
near worst case condition for intersymbol interference.
• Receiver data window time-width is
2.13 ns or greater and centered at
mid-symbol. This worst case window
time-width is the minimum allowed
eye-opening presented to the FDDI PHY
PM._Data indication input (PHY input)
per the example in FDDI PMD Annex E.
This minimum window time-width of 2.13
ns is based upon the worst case FDDI
PMD Active Input Interface optical
conditions for peak-to-peak DCD (1.0 ns),
DDJ (1.2 ns) and RJ (0.76 ns) presented
to the receiver.
To test a receiver with the worst case FDDI
PMD Active Input jitter condition requires
exacting control over DCD, DDJ and RJ jitter
components that is difficult to implement
15
20.
21.
22.
23.
24.
with production test equipment. The
receiver can be equivalently tested to the
worst case FDDI PMD input jitter conditions
and meet the minimum output data window
time-width of 2.13 ns. This is accomplished
by using a nearly ideal input optical signal
(no DCD, insignificant DDJ and RJ) and
measuring for a wider window time-width of
4.6 ns. This is possible due to the cumulative
effect of jitter components through their
superposition (DCD and DDJ are directly
additive and RJ components are rms
additive). Specifically, when a nearly ideal
input optical test signal is used and the
maximum receiver peak-to-peak jitter
contributions of DCD (0.4 ns), DDJ (1.0 ns),
and RJ (2.14 ns) exist, the minimum window
time-width becomes 8.0 ns -0.4 ns - 1.0 ns 2.14 ns = 4.46 ns, or conservatively 4.6 ns.
This wider window time-width of 4.6 ns
guarantees the FDDI PMD Annex E
minimum window time-width of 2.13 ns
under worst case input jitter conditions to
the Agilent receiver.
• Transmitter operating with an IDLE Line
State pattern, 125 MBd (62.5 MHz
square-wave), input signal to simulate
any cross-talk present between the
transmitter and receiver sections of the
transceiver.
All conditions of Note 19 apply except that
the measurement is made at the center of
the symbol with no window time-width.
This value is measured during the transition
from low to high levels of input optical
power.
The Signal Detect output shall be asserted
within 100 µs after a step increase of the
Input Optical Power. The step will be from a
low Input Optical Power, - -45 dBm, into the
range between greater than PA, and
-14 dBm. The BER of the receiver output will
be 10-2 or better during the time, LS_Max
(15 µs) after Signal Detect has been
asserted. See Figure 12 for more
information.
This value is measured during the transition
from high to low levels of input optical
power. The maximum value will occur when
the input optical power is either -45 dBm
average or when the input optical power
yields a BER of 10-2 or larger, whichever
power is higher.
Signal detect output shall be de-asserted
within 350 µs after a step decrease in the
Input Optical Power from a level which is
the lower of; -31 dBm or P D + 4 dB (PD is the
power level at which signal detect was deasserted), to a power level of -45 dBm or
less. This step decrease will have occurred
in less than 8 ns. The receiver output will
have a BER of 10 -2 or better for a period of
12 µs or until signal detect is de-asserted.
The input data stream is the Quiet Line
State. Also, signal detect will be deasserted within a maximum of 350 µs after
the BER of the receiver output degrades
above 10-2 for an input optical data stream
that decays with a negative ramp function
instead of a step function. See Figure 12 for
more information.
www.agilent.com/
semiconductors
For product information and a complete list of
distributors, please go to our web site.
For technical assistance call:
Americas/Canada: +1 (800) 235-0312 or
(408) 654-8675
Europe: +49 (0) 6441 92460
China: 10800 650 0017
Hong Kong: (+65) 6756 2394
India, Australia, New Zealand: (+65) 6755 1939
Japan: (+81 3) 3335-8152(Domestic/International), or
0120-61-1280(Domestic Only)
Korea: (+65) 6755 1989
Singapore, Malaysia, Vietnam, Thailand, Philippines,
Indonesia: (+65) 6755 2044
Taiwan: (+65) 6755 1843
Data subject to change.
Copyright © 2003 Agilent Technologies, Inc.
Obsoletes: 5988-9313EN
March 1, 2005
5989-2604EN
Similar pages