Preliminary Revised May 2000 74LVTH16835 Low Voltage 18-Bit Universal Bus Driver with 3-STATE Outputs (Preliminary) General Description Features The LVTH16835 consists of 18-bit universal bus drivers which combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, or clocked modes. Data flow from A to Y is controlled by the output-enable (OE) input. This device operates in the transparent mode when the latch-enable (LE) input is HIGH. The A data is latched if the clock (CLK) input is held at a HIGH or LOW logic level. If LE is LOW, the A-bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of the CLK. When OE is HIGH, the outputs are in the high-impedance state. ■ Input and output interface capability to systems at 5V VCC ■ Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs ■ Live insertion/extraction permitted ■ Power Up/Down high impedance provides glitch-free bus loading ■ Outputs source/sink −32 mA/+64 mA ■ Latch-up performance exceeds 500 mA The LVTH16835 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. The bus driver is designed for low voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVTH16835 is fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation. Ordering Code: Order Number Package Number 74LVTH16835MEA MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Package Description 74LVTH16835MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2000 Fairchild Semiconductor Corporation DS500102 www.fairchildsemi.com 74LVTH16835 Low Voltage 18-Bit Universal Bus Driver May 2000 74LVTH16835 Preliminary Connection Diagram Pin Descriptions Pin Names Description A1–A18 Data Register Inputs Y1–Y18 3-STATE Outputs CLK Clock Pulse Input OE Output Enable Input LE Latch Enable Input Truth Table Inputs OE LE CLK A Output Y Z H X X X L H X L L L H X H H L L ↑ L L L L ↑ H H L L H X Y0 (Note 1) L L L X Y0 (Note 2) H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance ↑ = HIGH-to-LOW Clock Transition Note 1: Output level before the indicated steady-state input conditions were established, provided that CLK was HIGH before LE went LOW. Note 2: Output level before the indicated steady-state input conditions were established. Logic Diagram www.fairchildsemi.com 2 Preliminary Symbol Parameter Value Conditions Units VCC Supply Voltage −0.5 to +4.6 VI DC Input Voltage −0.5 to +7.0 VO DC Output Voltage −0.5 to +7.0 Output in 3-STATE V −0.5 to +7.0 Output in HIGH or LOW State (Note 4) V V V IIK DC Input Diode Current −50 VI < GND mA IOK DC Output Diode Current −50 VO < GND mA IO DC Output Current 64 VO > VCC Output at HIGH State 128 VO > VCC Output at LOW State mA ICC DC Supply Current per Supply Pin ±64 mA IGND DC Ground Current per Ground Pin ±128 mA TSTG Storage Temperature −65 to +150 °C Recommended Operating Conditions Symbol Parameter VCC Supply Voltage VI Input Voltage IOH HIGH-Level Output Current IOL LOW-Level Output Current TA Free-Air Operating Temperature ∆t/∆V Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V Min Max Units 2.7 3.6 V 0 5.5 V −32 mA 64 mA −40 85 °C 0 10 ns/V Note 3: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 4: IO Absolute Maximum Rating must be observed. 3 www.fairchildsemi.com 74LVTH16835 Absolute Maximum Ratings(Note 3) 74LVTH16835 Preliminary DC Electrical Characteristics Symbol VIK Input Clamp Diode Voltage T A = −40°C to +85°C VCC Parameter (V) Min Max Units −1.2 2.7 V VO ≤ 0.1V or VIH Input HIGH Voltage 2.7–3.6 VIL Input LOW Voltage 2.7–3.6 VOH Output HIGH Voltage 2.7–3.6 VCC − 0.2 V IOH = −100 µA 2.7 2.4 V IOH = −8 mA 3.0 2.0 V IOH = −32 mA VOL II(HOLD) II(OD) II Output LOW Voltage Bushold Input Minimum Drive 2.0 Conditions II = −18 mA V 0.8 VO ≥ VCC − 0.1V 2.7 0.2 V IOL = 100 µA 2.7 0.5 V IOL = 24 mA 3.0 0.4 V IOL = 16 mA 3.0 0.5 V IOL = 32 mA 3.0 0.55 V IOL = 64 mA 75 µA VI = 0.8V −75 µA VI = 2.0V 500 µA (Note 5) −500 µA (Note 6) 3.0 Bushold Input Over-Drive Current to Change State 3.0 Input Current 3.6 10 µA VI = 5.5V Control Pins 3.6 ±1 µA VI = 0V or VCC Data Pins 3.6 −5 µA VI = 0V 1 µA VI = VCC ±100 µA IOFF Power Off Leakage Current IPU/PD Power up/down 3-STATE 0 0V ≤ VI or VO ≤ 5.5V VO = 0.5V to 3.0V 0–1.5V ±100 µA IOZL 3-STATE Output Leakage Current 3.6 −5 µA VO = 0.5V IOZH 3-STATE Output Leakage Current 3.6 5 µA VO = 3.0V IOZH+ 3-STATE Output Leakage Current 3.6 10 µA VCC < VO ≤ 5.5V ICCH Power Supply Current 3.6 0.19 mA Outputs HIGH ICCL Power Supply Current 3.6 5 mA Outputs LOW ICCZ Power Supply Current 3.6 0.19 mA Outputs Disabled ICCZ+ Power Supply Current 3.6 0.19 mA VCC ≤ VO ≤ 5.5V, ∆ICC Increase in Power Supply Current 3.6 0.2 mA One Input at VCC − 0.6V Output Current VI = GND or VCC Outputs Disabled (Note 7) Other Inputs at VCC or GND Note 5: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 6: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 7: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND. Dynamic Switching Characteristics Symbol Parameter (Note 8) TA = 25°C VCC (V) Min Typ Conditions Max Units CL = 50 pF, RL = 500Ω VOLP Quiet Output Maximum Dynamic VOL 3.3 0.8 V (Note 9) VOLV Quiet Output Minimum Dynamic VOL 3.3 −0.8 V (Note 9) Note 8: Characterized in SSOP package. Guaranteed parameter, but not tested. Note 9: Max number of outputs defined as (n). n−1 data inputs are driven 0V to 3V. Output under test held LOW. www.fairchildsemi.com 4 Preliminary TA = −40°C to +85°C, CL = 50 pF, RL = 500 Ω Symbol VCC = 3.3 ± 0.3V Parameter Min fMAX Max 150 VCC = 2.7V Min 150 MHz tPLH Propagation Delay 1.3 3.7 1.3 4.0 tPHL A to Y 1.3 3.7 1.3 4.0 tPLH Propagation Delay 1.5 5.1 1.5 5.7 tPHL LE to Y 1.5 5.1 1.5 5.7 tPLH Propagation Delay 1.5 5.1 1.5 5.7 tPHL CLK to Y 1.5 5.1 1.5 5.7 tPZH Output Enable Time 1.3 4.6 1.3 5.5 1.3 4.6 1.3 5.5 1.7 5.8 1.7 6.3 1.7 5.8 1.7 6.3 tPZL tPHZ Output Disable Time tPLZ tS tH tW Setup Time A before CLK 2.1 A before LE, CLK HIGH 2.3 1.5 A before LE, CLK LOW 1.5 0.5 Hold Time ns ns ns ns ns 2.4 A after CLK 1.0 0.0 A after LE 0.8 0.8 LE HIGH 3.3 3.3 CLK HIGH or LOW 3.3 3.3 Pulse Duration Units Max ns ns ns tOSLH Output to Output Skew 1.0 1.0 tOSHL (Note 10) 1.0 1.0 ns Note 10: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Capacitance (Note 11) Typical Units CIN Symbol Input Capacitance Parameter VCC = 0V, VI = 0V or VCC Conditions 4 pF COUT Output Capacitance VCC = 3.0V, VO = 0V or VCC 8 pF Note 11: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012. 5 www.fairchildsemi.com 74LVTH16835 AC Electrical Characteristics 74LVTH16835 Preliminary Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Package Number MS56A www.fairchildsemi.com 6 Preliminary 74LVTH16835 Low Voltage 18-Bit Universal Bus Driver Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 7 www.fairchildsemi.com