Sony CXD2073Q Digital comb filter (ntsc) Datasheet

CXD2073Q
Digital Comb Filter (NTSC)
For the availability of this product, please contact the sales office.
Description
The CXD2073Q is an adaptive comb filter compatible
with NTSC system, and provide high-precision Y/C
separation with a single chip.
Features
• Y/C separation by adaptive processing
• Horizontal aperture compensation circuit
• 8-bit A/D converter (1 channel)
• 8-bit D/A converter (2 channels)
• One 1H delay line
• 4 PLL
• Clamp circuit
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings (Ta = 25°C, VSS = 0V)
• Supply voltage
DVDD VSS – 0.5 to +7.0 V
DAVD VSS – 0.5 to +7.0 V
ADVD VSS – 0.5 to +7.0 V
PLVD VSS – 0.5 to +7.0 V
• Input voltage
VI
VSS – 0.5 to VDD +0.5 V
• Output voltage
VO
VSS – 0.5 to VDD +0.5 V
• Operating temperature
Topr
–20 to +75
°C
• Storage temperature
Tstg
–55 to +150
°C
Recommended Operating Conditions
• Supply voltage
DVDD
5.0 ± 0.25
DAVD
5.0 ± 0.25
ADVD
5.0 ± 0.25
PLVD
5.0 ± 0.25
• Operating temperature
Topr
–20 to +75
32 pin QFP (Plastic)
Applications
Y/C separation for color TVs and VCRs
V
V
V
V
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E97411B86-PS
CXD2073Q
TST1
TST2
DVSS
DVDD
NC
DVDD
DVSS
TST3
Pin Configuration (Top View)
24
23
22
21
20
19 18
17
FIN 25
16 APCN
CKSL 26
15 MOD1
CPO 27
14 MOD2
VCV 28
13 INIT
PLVD 29
12 IRF
PLVS 30
11 VB
3
4
5
6
7
8
DAVS
2
AYO
1
DAVD
VRF
NC
9
ACO
CLPO 32
ADVD
VG
ADVS
10
ADIN
CLPEN 31
Block Diagram
DL
ADIN 1
CLPO 32
A/D
1H
Clamp
Chroma
Output
Block
Logic Operation
Block
1/4
VCO
FIN 25
28
VCV
26
CKSL
27
CPO
SEL
–2–
Internal clock
D/A
7
AYO
D/A
4
ACO
CXD2073Q
Pin Description
Symbol
I/O
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
ADIN
ADVS
ADVD
ACO
NC
DAVD
AYO
DAVS
VRF
VG
VB
IRF
INIT
I
—
—
O
—
—
O
—
I
O
O
O
I
14
MOD2
I
15
MOD1
I
16
APCN
I
17
18
19
20
21
22
23
24
TST3
DVSS
DVDD
NC
DVDD
DVSS
TST2
TST1
O
—
—
—
—
—
O
I
25
FIN
I
26
CKSL
I
27
CPO
O
28
VCV
I
29
30
PLVD
PLVS
—
—
31
CLPEN
I
32
CLPO
O
Comb filter analog input (A/D converter input)
Analog ground for A/D converter
Analog power supply for A/D converter (+5V)
Analog chroma signal output
Leave this pin open.
Analog power supply for D/A converter (+5V)
Analog luminance signal output
Analog ground for D/A converter
D/A converter reference voltage setting. Sets the full-scale value for D/A converter.
Connect to DAVD via a capacitor of approximately 0.1µF.
Connect to DAVS via a capacitor of approximately 0.1µF.
Connect a resistor of 16 times (16R) that of the output resistor "R" of AYO pin.
Test. Normally, fix to Low.
Y/C separation status setting pins
MOD2 MOD1
L
L
Adaptive processing mode
L
H
BPF separation fixed mode
H
L
Y through mode
H
H
Simple comb mode
Aperture compensation switching
L: Aperture compensation OFF
H: Aperture compensation ON
Test. Normally, leave this pin open.
Digital ground
Digital power supply (+5V)
Leave this pin open.
Digital power supply (+5V)
Digital ground
Test. Normally, leave this pin open.
Test. Normally, fix to Low.
Clock input. Input burst-locked clock. Input fsc when the PLL is used. Input 4fsc
when the PLL is not used.
PLL control.
L: When the PLL is not used. The 4fsc clock input to FIN is supplied internally.
H: When the PLL is used. The 4fsc clock from VCO oscillation output is
supplied internally.
Phase comparison output for the internal PLL. Leave open when the PLL is not
used.
VCO oscillation control voltage input for the internal PLL. Connect to PLVS when
the PLL is not used.
PLL analog power supply (+5V)
PLL analog ground
Clamp enable
L: Clamp function is enabled. Set to L when the internal clamp is used.
H: Clamp function is disabled. Set to H when the internal clamp is not used.
Connect to ADIN when clamp circuit is used.
Leave this pin open when clamp circuit is not used.
Pin No.
–3–
CXD2073Q
Electrical Characteristics
Item
(VDD = 5 ± 0.25V, VSS = 0V, Ta = –20 to +75°C)
Symbol
Conditions
Min.
Typ.
Max.
Unit
—
4.75
5.0
5.25
V
—
–20
—
+75
°C
—
55
80
mA
VDD × 0.7
—
VDD
V
VSS
—
VDD × 0.3
V
DVDD
Supply voltage
ADVD
DAVD
PLVD
Operating temperature
Topr
Supply current
IDD
Clock 14MHz
High level input voltage
VIH
Low level input voltage
VIL
CMOS level
(Pin 13 to 16, 24, 26, 31)
High level output voltage
VOH
IOH = –2mA (Pin 17 and 23) VDD – 0.8
—
VDD
V
Low level output voltage
VOL
IOL = 4mA (Pin 17 and 23)
VSS
—
0.4
V
Logical Vth
LVth
—
VDD/2
—
V
Input voltage
VIN
0.5
—
VDD
Vp-p
Feedback resistor
RFB
250k
1M
2.5M
Ω
FIN (Pin 27)
A/D Converter Characteristics
(VDD = 5V, Ta = 25°C, f = 10MHz)
Symbol
Min.
Typ.
Max.
Unit
—
8
—
bit
14.3
—
—
MSPS
—
18
—
MHz
BOTTOM
0.48
0.52
0.56
V
TOP – BOTTOM
1.96
2.08
2.22
V
Differential linearity error
ED
–1.0
—
+1.0
LSB
Integral linearity error
EL
–3.0
—
+3.0
LSB
Item
Resolution
n
Max. conversion speed
fmax
Analog input band width
BW
Input bias
–3dB
D/A Converter Characteristics
(VDD = 5V, VRF = 2V, IRF = 3.3kΩ, R = 200Ω, Ta = 25°C, f = 10MHz)
Symbol
Item
Conditions
Conditions
Min.
Typ.
Max.
Unit
—
8
—
bit
Resolution
n
Max. conversion speed
fmax
—
14.3
—
—
MSPS
Differential linearity error
ED
—
–0.8
—
+0.8
LSB
Integral linearity error
EL
—
–2.0
—
+2.0
LSB
Output full-scale voltage
VFS
—
1.805
1.90
1.995
V
Output full-scale current
IFS
—
—
9.5
15
mA
Output offset voltage
VOS
—
—
—
1.0
mV
Precision guaranteed
output voltage range
VOC
—
1.8
—
2.1
V
–4–
CXD2073Q
Clamp
(VDD = 5V, Ta = 25°C, f = 10MHz)
Item
Symbol
Clamp level∗1
Conditions
CLV
Min.
Typ.
Max.
Unit
—
0.67
—
V
∗1 Sync tip clamp
Description of Functions
• Horizontal aperture compensation
Compensates aperture degradation accompanied by D/A conversion.
This compensation is effective for the following modes; adaptive processing, Y through, and simple comb
modes.
• Switching of Y/C separation modes
The following four modes can be set; however, the adaptive processing mode or Y through mode is normally
used.
(1) Adaptive processing mode
This mode detects interline correlation, switches between comb filter processing and BPF processing,
and operates Y/C separation.
(2) Y through mode
The composite video signal input from ADIN (Pin 1) is A/D converted. It is also D/A converted, and then
output from AYO (Pin 7).
At this time, the output of ACO (Pin 4) is the same output as that of adaptive processing mode.
(3) BPF mode
C signal is generated by passing composite video signal through BPF.
Y output is a signal in which the C signal generated is subtracted from input composite video signal.
(4) Simple comb mode
Y/C separation is operated by the comb filter processing forcibly.
Modes
MOD1 (Pin 15)
MOD2 (Pin 14)
Adaptive processing mode
L
L
Y through mode
L
H
BPF mode
H
L
Simple comb mode
H
H
• Selection Pin Setting Table
Pin No.
Symbol
H
L
14
15
MOD2
MOD1
See the table above.
16
APCN
Horizontal aperture compensation ON
Horizontal aperture compensation OFF
26
CKSL
Internal 4-multiple PLL used
Internal 4-multiple PLL not used
31
CLPEN
Internal clamp not used
Internal clamp used
–5–
CXD2073Q
Application Circuit for D/A Converter
6
10µ
DAVD
AYO
Y OUT
7
200
(R)
0.1µ
3k
8
DAVS
VRF
9
2k
0.1µ
3.3k
IRF 12
(R')
ACO
C OUT
4
200
(R)
0.1µ
VG 10
0.1µ
VB 11
: analog power supply 5V
: analog ground
• Method of selecting output resistance
The CXD2073Q has a built-in current output-type D/A converter. To obtain the output voltages, connect
resistors to AYO and ACO pins.
VFS = IFS × R
Here, VFS is output full-scale voltage, IFS is output full-scale current, and R is the output resistance
connected to each IO.
In addition, connect a resistance of 16 times the output resistor to the reference current pin IRF. In the case
where the value comes to be impractical, use a value of resistance as close to the value calculated as
possible. At that time,
VFS = VRF × 16 × R/R'.
R is the output resistance connected to each IO, R' is the resistance connected to IRF, and VRF is the VRF
pin voltage. Power consumption can be reduced by using higher resistance values, but then glitch energy
and data settling time increase contrastingly. Select optimum resistance values according to the system
applications.
In case of the circuit above, VFS = 2 [V] × 16 × 0.2k/3.3k ≈ 1.93 [V], IFS = 1.93/0.2k ≈ 9.65 [mA].
–6–
CXD2073Q
Notes on Operation
• Power supply, ground
Separate the analog and digital systems around the device to reduce noise effect. Both analog and digital
VDD are respectively bypassed to VSS as close to these VDD and VSS pins as possible through ceramic
capacitors of approximately 0.1µF.
Also, layout the power supply and ground pattern of the board substrate as wide as possible to lower
impedance.
• Clock
Use the burst-locked clock. Separate the clock line on the board substrate as far as possible from analogrelated pins, analog power supply, and analog ground.
• ADIN (analog input signal)
(1) Low impedance drive
The input signal to ADIN (Pin 1) should be driven at the low impedance and its wiring should be as short
as possible.
(2) Input level
Set the input signal peak-to-peak value VPP to 1.75V or less. Additionally, VPP is recommended to be
1.3V or more since the A/D converter input dynamic range should be made as large as possible.
C
2.60V (Reference top voltage typical value for internal A/D converter)
B
VPP
0.67V (Sync tip clamp level)
A
0.52V (Reference bottom voltage typical value for internal A/D converter)
The DC level at the ADIN pin is as shown in the diagram above when the internal sync tip clamp is used.
Labeling the internal D/A converter AYO output full-scale voltage as VFS, the correspondence between
the ADIN pin voltage and AYO output pin voltage (DC level) is as follows;
DC voltage at point A → 0 [V]
DC voltage at point B → AYO maximum output voltage [V]
DC voltage at point C → VFS [V]
The VFS is the AYO output voltage generated when the voltage equivalent to the point C is input.
• Internal delay
The delay from the internal A/D converter to the D/A converter output is 21.5 clocks + αns (α: D/A converter
analog output delay = approximately 20ns).
The 21.5 clocks are the sum of the clocks shown below;
A/D converter : 3.5 clocks (“0.5” is for fetching the data at the fall of the clock.)
Internal logic : 17 clocks
D/A converter : 1 clock
–7–
CXD2073Q
Application Circuit
(1) In case that fsc is used as clock
D5V
X'tal
3.58MHz
H
L
21
20
19
18
17
NC
DVDD
DVSS
TST3
H
L
H
L
H
L
26 CKSL
16
APCN
MOD1 15
27 CPO
MOD2 14
28 VCV
INIT 13
29 PLVD
IRF 12
30 PLVS
VB 11
31 CLPEN
VG 10
25 FIN
560
22
DVDD
0.001µ
23
DVSS
Clock
Generator
24
TST2
Burst-locked
Clock
0.1µ
TST1
0.1µ
56k
0.022µ
A5V
3.3k
0.1µ
0.1µ
ADVD
ACO
NC
DAVD
AYO
DAVS
32
CLPO
ADVS
L
0.1µ
ADIN
H
1
2
3
4
5
6
7
8
0.1µ
A5V
VRF 9
5k
10µ
0.1µ
200
A5V
200
A5V
LPF
Composite
video input
10µ
LPF
Y output
LPF
C output
analog power supply (5V)
analog ground
digital power supply (5V)
digital ground
H: CMOS High level
L: CMOS Low level
Recommended LPF: TH327LSJS-2513LCAS (TOKO)
(–3dB at 8MHz)
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
–8–
CXD2073Q
(2) In case that 4fsc is used as clock
D5V
0.1µ
L
21
20
19
18
17
NC
DVDD
DVSS
TST3
26 CKSL
16
APCN
MOD1 15
27 CPO
MOD2 14
28 VCV
INIT 13
29 PLVD
IRF 12
30 PLVS
VB 11
31 CLPEN
VG 10
25 FIN
H
22
DVDD
0.001µ
23
DVSS
Clock
Generator
24
TST2
Burst-locked
Clock
0.1µ
TST1
X'tal
14.3MHz
H
L
H
L
H
L
3.3k
A5V
0.1µ
0.1µ
ACO
NC
DAVD
AYO
DAVS
CLPO
ADVD
32
ADVS
L
0.1µ
ADIN
H
1
2
3
4
5
6
7
8
0.1µ
A5V
VRF 9
5k
10µ
0.1µ
200
A5V
200
A5V
LPF
Composite
video input
10µ
LPF
Y output
LPF
C output
analog power supply (5V)
analog ground
digital power supply (5V)
digital ground
H: CMOS High level
L: CMOS Low level
Recommended LPF: TH327LSJS-2513LCAS (TOKO)
(–3dB at 8MHz)
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
–9–
CXD2073Q
Example of Representative Characteristics
Analog I/O amplitude ratio vs. VRF pin voltage
Analog I/O amplitude ratio
Input signal peak-to-peak voltage ≤ 1.75V
1.5
Output amplitude
Input amplitude
1.0
Input
ADIN AYO
VRF
0.5
CXD2073Q
D/A output amplitude
A/D input amplitude
2
1
VRF [V]
VFS – Output full-scale voltage [V]
Output full-scale voltage vs. Ambient temperature
1.95
1.90
VDD = 5V
VRF = 2V
IRF = 3.3kΩ
R = 200Ω
0
25
–25
0
50
75
Ta – Ambient temperature [°C]
AYO (Y output) frequency response
Gain ratio [dB]
0
Input
–1
Gain for f = f [MHz]
Gain for f = 0.5 [MHz]
–2
0.5
1
2
Frequency [MHz]
5
– 10 –
ADIN AYO
CXD2073Q
R
200Ω
R
200Ω
CXD2073Q
Package Outline
Unit: mm
32PIN QFP (PLASTIC)
9.0 ± 0.2
24
0.1
+ 0.35
1.5 – 0.15
+ 0.3
7.0 – 0.1
17
16
32
9
(8.0)
25
1
+ 0.2
0.1 – 0.1
0.8
0.24
M
+ 0.1
0.127 – 0.05
0° to 10°
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
QFP-32P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
QFP032-P-0707
LEAD MATERIAL
42 ALLOY
PACKAGE MASS
0.2g
JEDEC CODE
– 11 –
0.50
8
+ 0.15
0.3 – 0.1
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