Hitachi HM628128ALR-7SL 131,072-word x 8-bit high speed cmos static ram Datasheet

ADE-XXX-XXX
HM628128A Series
131,072-word × 8-bit High Speed CMOS Static RAM
Rev. X
January 1995
The Hitachi HM628128A is a CMOS static RAM
organized 128 kword × 8 bit. It realizes higher
density, higher performance and low power
consumption by employing 0.8 µm Hi-CMOS
process technology.
It offers low power standby power dissipation;
therefore, it is suitable for battery back-up systems.
The device, packaged in a 525-mil SOP (460-mil
body SOP) or a 600-mil plastic DIP, or a 8 × 20
mm TSOP with thickness of 1.2 mm, is available
for high density mounting. TSOP package is
suitable for cards, and reverse type TSOP is also
provided.
Features
• High speed
— Fast access time: 55/70/85/100 ns (max)
• Low power
— Active: 75 mW (typ)
— Standby: 10 µW (typ)
• Single 5 V supply
• Completely static memory
No clock or timing strobe required
• Equal access and cycle times
• Common data input and output
Three state output
• Directly TTL compatible
All inputs and outputs
• Capability of battery back up operation
2 chip selection for battery back up
HM628128A Series
Ordering Information
Package
Type No.
Access
time
Package
600-mil 32-pin
plastic DIP
(DP-32)
HM628128ALT–5
HM628128ALT–7
HM628128ALT–8
HM628128ALT–10
55 ns
70 ns
85 ns
100 ns
8 mm × 20 mm
32-pin TSOP
(normal type)
(TFP-32D)
55 ns
70 ns
85 ns
100 ns
HM628128ALT–5L
HM628128ALT–7L
HM628128ALT–8L
HM628128ALT–10L
55 ns
70 ns
85 ns
100 ns
HM628128ALP–5SL
HM628128ALP–7SL
HM628128ALP–8SL
HM628128ALP–10SL
55 ns
70 ns
85 ns
100 ns
HM628128ALT-5SL
HM628128ALT-7SL
HM628128ALT-8SL
HM628128ALT-10SL
55 ns
70 ns
85 ns
100 ns
HM628128ALFP–5
HM628128ALFP–7
HM628128ALFP–8
HM628128ALFP–10
55 ns
70 ns
85 ns
100 ns
HM628128ALR–5
HM628128ALR–7
HM628128ALR–8
HM628128ALR–10
55 ns
70 ns
85 ns
100 ns
HM628128ALFP–5L
HM628128ALFP–7L
HM628128ALFP–8L
HM628128ALFP–10L
55 ns
70 ns
85 ns
100 ns
HM628128ALR–5L
HM628128ALR–7L
HM628128ALR–8L
HM628128ALR–10L
55 ns
70 ns
85 ns
100 ns
HM628128ALR-5SL
HM628128ALR-7SL
HM628128ALR-8SL
HM628128ALR-10SL
55 ns
70 ns
85 ns
100 ns
Type No.
Access
time
HM628128ALP–5
HM628128ALP–7
HM628128ALP–8
HM628128ALP–10
55 ns
70 ns
85 ns
100 ns
HM628128ALP–5L
HM628128ALP–7L
HM628128ALP–8L
HM628128ALP–10L
HM628128ALFP–5SL 55 ns
HM628128ALFP–7SL 70 ns
HM628128ALFP–8SL 85 ns
HM628128ALFP–10SL 100 ns
2
525-mil 32-pin
plastic SOP
(FP-32D)
8 mm × 20 mm
32-pin TSOP
(reverse type)
(TFP-32DR)
HM628128A Series
Pin Arrangement
HM628128ALP/ALFP Series
HM628128ALT Series
NC
1
32
VCC
A16
2
31
A15
A14
3
30
CS2
A12
4
29
WE
A7
5
28
A13
A6
6
27
A8
A5
7
26
A9
A4
8
25
A11
A3
9
24
OE
A2
10
23
A10
A1
11
22
CS1
A0
12
21
I/O7
I/O0
13
20
I/O6
I/O1
14
19
I/O5
I/O2
15
18
I/O4
VSS
16
17
I/O3
(Top View)
A4
A5
A6
A7
A12
A14
A16
NC
VCC
A15
CS2
WE
A13
A8
A9
A11
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
I/O3
I/O4
I/O5
I/O6
I/O7
CS1
A10
OE
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
VSS
I/O2
I/O1
I/O0
A0
A1
A2
A3
(Top View)
HM628128ALR Series
A11
A9
A8
A13
WE
CS2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
(Top View)
Pin Description
Pin name
Function
Pin name
Function
A0 – A16
Address
OE
Output enable
I/O0 – I/O7
Input/output
NC
No connection
CS1
Chip select 1
VCC
Power supply
CS2
Chip select 2
VSS
Ground
WE
Write enable
3
HM628128A Series
Block Diagram
(MSB)
A13
V CC
A15
V SS
A6
A7
A12
Row
Decoder
A14
•
•
•
•
•
Memory Matrix
512 x 2,048
A16
A5
A4
(LSB)
I/O0
•
•
Column I/O
•
•
Input
Data
Control
Column Decoder
I/O7
(LSB)
A8 A9 A11 A10 A0 A1 A2 A3
(MSB)
•
•
CS2
CS1
Timing Pulse Generator
Read/Write Control
WE
OE
Function Table
CS1
CS2
OE
WE
Mode
VCC current
I/O pin
Ref. cycle
H
X
X
X
Standby
ISB, ISB1
High-Z
—
X
L
X
X
Standby
ISB, ISB1
High-Z
—
L
H
H
H
Output disable
ICC
High-Z
—
L
H
L
H
Read
ICC
Dout
Read cycle
L
H
H
L
Write
ICC
Din
Write cycle (1)
L
H
L
L
Write
ICC
Din
Write cycle (2)
Note:
4
X: H or L
HM628128A Series
Absolute Maximum Ratings
Parameter
Supply voltage relative to VSS
Voltage on any pin relative to VSS
*1
Symbol
Value
VCC
–0.5 to +7.0
*2
Unit
VT
–0.5
Power dissipation
PT
1.0
W
Operating temperature
Topr
0 to +70
°C
Storage temperature
Tstg
–55 to +125
°C
Storage temperature under bias
Tbias
–10 to +85
°C
Note:
to VCC +
V
0.3*3
V
1. With respect to VSS
2. –3.0 V for pulse half-width ≤ 30 ns
3. Maximum voltage is 7.0V.
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
VCC
4.5
5.0
5.5
V
VSS
0
0
0
V
Input voltage
VIH
2.2
—
VCC + 0.3
V
(HM628128A-7/8/10)
VIL
–0.3 *1
—
0.8
V
Input voltage
VIH
2.4
—
VCC + 0.3
V
(HM628128A-5)
VIL
–0.3 *1
—
0.8
V
Note:
1. –3.0 V for pulse half-width ≤ 30 ns
5
HM628128A Series
DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V)
Parameter
Symbol
Min
Typ*1
Max
Unit
Test conditions
Input leakage current
|ILI|
—
—
1.0
µA
Vin = VSS to VCC
Output leakage current
|ILO|
—
—
1.0
µA
CS1 = VIH or CS2 = VIL or
OE = VIH or WE = VIL,
VI/O = VSS to VCC
Operating power supply
current: DC
ICC
—
15
30
mA
CS1 = VIL, CS2 = VIH,
Others = VIH/VIL
II/O = 0 mA
Operating power supply
current
—
ICC1
(HM628128
A-7/8/10)
45
70
mA
ICC1
—
(HM628128
A-5)
50
80
mA
Min cycle, duty = 100%,
CS1 = VIL, CS2 = VIH,
Others = VIH/VIL
II/O = 0 mA
ICC2
—
15
25
mA
Cycle time = 1 µs, duty = 100%,
II/O = 0 mA, CS1 ≤ 0.2 V,
CS2 ≥ VCC – 0.2 V
VIH ≥ VCC – 0.2 V, VIL ≤ 0.2 V
Standby power supply
current: DC
ISB
—
1
2
mA
(1) CS1 = VIH, CS2 = VIH or
(2) CS2 = VIL
Standby power supply
current (1): DC
ISB1
—
(L version)
2
100
µA
ISB1
(L-L/L-SL
version)
—
2
50
µA
0 V ≤ Vin ≤ VCC ,
(1) CS1 ≥ VCC – 0.2 V,
CS2 ≥ VCC – 0.2 V or
(2) 0 V ≤ CS2 ≤ 0.2 V
VOL
—
—
0.4
V
IOL = 2.1 mA
VOH
2.4
—
—
V
IOH = –1.0 mA
Output voltage
Note:
1. Typical values are at VCC = 5.0 V, Ta = +25°C and specified loading.
Capacitance (Ta = 25°C, f = 1.0 MHz)*1
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Input capacitance
Cin
—
—
8
pF
Vin = 0 V
Input/output capacitance
CI/O
—
—
10
pF
VI/O = 0 V
Note:
6
1. This parameter is sampled and not 100% tested.
HM628128A Series
AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, unless otherwise noted.)
Test Conditions
• Input pulse levels: 0.8 V to 2.4 V (HM628128A-7/8/10)
0 V to 3 V (HM628128A-5)
• Input rise and fall times: 5 ns
• Input and output timing reference levels: 1.5 V
• Output load: 1 TTL Gate and CL (100 pF) (HM628128A-7/8/10)
1 TTL Gate and CL (30 pF) (HM628128A-5) (Including scope & jig)
Read Cycle
HM628128A
-5
-7
-8
-10
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Notes
Read cycle time
tRC
55
—
70
—
85
—
100
—
ns
Address access time
tAA
—
55
—
70
—
85
—
100
ns
Chip selection to
tCO1
—
55
—
70
—
85
—
100
ns
output valid
tCO2
—
55
—
70
—
85
—
100
ns
Output enable to
output valid
tOE
—
30
—
35
—
45
—
50
ns
Chip selection to
tLZ1
5
—
10
—
10
—
10
—
ns
2, 3
output in low-Z
tLZ2
5
—
10
—
10
—
10
—
ns
2, 3
Output enable to
output in low-Z
tOLZ
5
—
5
—
5
—
5
—
ns
2, 3
Chip deselection to
tHZ1
0
20
0
25
0
30
0
35
ns
1, 2, 3
output in high-Z
tHZ2
0
20
0
25
0
30
0
35
ns
1, 2, 3
Output disable to
output in high-Z
tOHZ
0
20
0
25
0
30
0
35
ns
1, 2, 3
Output hold from
address change
tOH
5
—
10
—
10
—
10
—
ns
7
HM628128A Series
Read Timing Waveform *4
t RC
Address
Address Valid
t AA
CS1
t CO1
t LZ1
t HZ1
t CO2
t LZ2
t HZ2
t OE
t OHZ
CS2
OE
t OLZ
Dout
High Impedance
t OH
Data Valid
Notes: 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and
are not referred to output voltage levels.
2. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given
device and from device to device.
3. This parameter is sampled and not 100% tested.
4. WE is high for read cycle.
8
HM628128A Series
Write Cycle
HM628128A
-5
-7
-8
-10
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Write cycle time
tWC
55
—
70
—
85
—
100
—
ns
Chip selection to
end of write
tCW
50
—
60
—
75
—
80
—
ns
Address setup time
tAS
0
—
0
—
0
—
0
—
ns
Address valid to
end of write
tAW
50
—
60
—
75
—
80
—
ns
Write pulse width
tWP
40
—
50
—
55
—
60
—
ns
Write recovery time
tWR
0
—
0
—
0
—
0
—
ns
Write to output in
high-Z
tWHZ
0
20
0
25
0
30
0
35
ns
Data to write time
overlap
tDW
25
—
30
—
35
—
40
—
ns
Data hold from
write time
tDH
0
—
0
—
0
—
0
—
ns
Output active from
end of write
tOW
5
—
5
—
5
—
5
—
ns
Notes
10
10
9
HM628128A Series
Write Timing Waveform (1) (OE Clock)
t WC
Address Valid
Address
t AW
OE
t CW *2
CS1
t WR*4
*6
CS2
t WP *1
t AS *3
WE
t OHZ *5
High Impedance
Dout
t DW
Din
10
t DH
Data Valid
HM628128A Series
Write Timing Waveform (2) (OE low Fixed)
t WC
Address
Address Valid
t CW
t WR*4
*2
CS1
*6
CS2
t AW
t WP *1
WE
*11
t OH
t AS *3
t OW
t WHZ *5
*7
Dout
*8
High Impedance
t DW
t DH
*9
Din
Data Valid
Notes: 1. A write occurs during the overlap of a low CS1, a high CS2, and a low WE. A write begins at the
latest transition among CS1 going low, CS2 going high, and WE going low. A write ends at the
earliest transition among CS1 going high, CS2 going low, and WE going high. tWP is measured
from the beginning of write to the end of write.
2. tCW is measured from the later of CS1 going low or CS2 going high to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the earliest of CS1 or WE going high or CS2 going low to the end of write
cycle.
5. During this period, I/O pins are in the output state; therefore, the input signals of the opposite
phase to the outputs must not be applied.
6. If the CS1 goes low simultaneously with WE going low or after the WE going low, the outputs
remain in a high impedance state.
7. Dout is the same phase of the latest written data in this write cycle.
8. Dout is the read data of next address.
9. If CS1 is low and CS2 high during this period, I/O pins are in the output state. Therefore, the
input signals of opposite phase to the outputs must not be applied to them.
10. This parameter is sampled and not 100% tested.
11. In the write cycle with OE low fixed, tWP must satisfy the following equation to avoid a problem of
11
HM628128A Series
data bus contention.
tWP ≥ tDW min + tWHZ max
Low VCC Data Retention Characteristics (Ta = 0 to +70°C)
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions*4
VCC for data retention
VDR
2.0
—
—
V
CS1 ≥ VCC – 0.2 V,
CS2 ≥ VCC – 0.2 V or
0 V ≤ CS2 ≤ 0.2 V
Vin>0 V
Data retention current
—
ICCDR
(L version)
1
50*1
µA
—
ICCDR
(L-L version)
1
30*2
µA
VCC = 3.0 V, Vin ≥ 0 V
CS1 ≥ VCC – 0.2V
CS2 ≥ VCC – 0.2 V or
0 V ≤ CS2 ≤ 0.2 V
ICCDR
(L-SL
version)
—
1
15*3
µA
Chip deselect to
data retention time
tCDR
0
—
—
ns
Operation recovery time
tR
5
—
—
ms
See retention waveform
Low VCC Data Retention Timing Waveform (1) (CS1 Controlled)
t CDR
Data retention mode
tR
V CC
4.5 V
2.2 V
V DR1
CS1 > VCC – 0.2 V
CS1
0V
Low VCC Data Retention Timing Waveform (2) (CS2 Controlled)
t CDR
Data retention mode
V CC
4.5 V
CS2
V DR2
0.4 V
0V
12
0 V < CS2 < 0.2 V
tR
HM628128A Series
Notes: 1.
2.
3.
4.
20 µA max at Ta = 0 to 40˚C (L-version).
6 µA max at Ta = 0 to 40˚C (L-L-version).
3 µA max at Ta = 0 to 40˚C (L-SL-version).
CS2 controls address buffer, WE buffer, CS1 buffer, OE buffer, and Din buffer. If CS2 controls
data retention mode, Vin levels (address, WE, OE, CS1, I/O) can be in the high impedance state.
If CS1 controls data retention mode, CS2 must be CS2 ≥ VCC – 0.2 V or 0 V ≤ CS2 ≤ 0.2 V. The
other input levels (address, WE, OE, I/O) can be in the high impedance state.
13
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