Sharp LH5P8128 Cmos 1m (128k x 8) pseudo-static ram Datasheet

LH5P8128
FEATURES
• 131,072 × 8 bit organization
• Access times (MAX.): 60/80/100 ns
CMOS 1M (128K × 8) Pseudo-Static RAM
PIN CONNECTIONS
32-PIN DIP
32-PIN SOP
• Cycle times (MIN.): 100/130/160 ns
TOP VIEW
RFSH
1
32
• Single +5 V power supply
A16
2
31
A15
A14
3
30
CE2
• Power consumption:
Operating: 572/385/275 mW (MAX.)
Standby (CMOS level): 1.1 mW (MAX.)
A12
4
29
R/W
• TTL compatible I/O
• Available for auto-refresh and self-refresh
modes
• 512 refresh cycles/8 ms
• Compatible with standard 1M
SRAM pinout
• Packages:
32-pin, 600-mil DIP
32-pin, 525-mil SOP
32-pin, 8 × 20 mm2 TSOP (Type I)
VCC
A7
5
28
A13
A6
6
27
A8
A5
7
26
A9
A4
8
25
A11
A3
9
24
OE
A2
10
23
A10
A1
11
22
CE1
A0
12
21
I/O7
I/O0
13
20
I/O6
I/O1
14
19
I/O5
I/O2
15
18
I/O4
GND
16
17
I/O3
5P8128-1
Figure 1. Pin Connections for DIP and
SOP Packages
32-PIN TSOP (Type I)
DESCRIPTION
The LH5P8128 is a 1M bit Pseudo-Static RAM
organized as 131,072 × 8 bits. It is fabricated using
silicon-gate CMOS process technology.
A PSRAM uses on-chip refresh circuitry with a DRAM
memory cell for pseudo static operation which eliminates external clock inputs, while having the same
pinout as industry standard SRAMs. Moreover, due to
the functional similarities between PSRAMs and
SRAMs, existing 128K × 8 SRAM sockets can be filled
with the LH5P8128 with little or no changes. The
advantage is the cost savings realized with the lower
cost PSRAM.
The LH5P8128 PSRAM has the ability to fill the gap
between DRAM and SRAM by offering low cost, low
power standby and a simple interface.
A11
1
32
OE
A9
2
31
A10
A8
3
30
CE1
A13
4
29
I/O7
R/W
5
28
I/O6
CE2
6
27
I/O5
A15
7
26
I/O4
VCC
8
25
I/O3
RFSH
9
24
GND
A16
10
23
I/O2
A14
11
22
I/O1
A12
12
21
I/O0
A7
13
20
A0
A6
14
19
A1
A5
15
18
A2
A4
16
17
A3
NOTE: Reverse bend available on request.
5P8128-1A
Figure 2. Pin Connections for TSOP Package
1
CMOS 1M (128K × 8) Pseudo-Static RAM
LH5P8128
16 GND
32 VCC
A0 12
A1 11
A2 10
A3 9
A4 8
A5 7
A6
A7
A8
A9
VBB GENERATOR
COLUMN
ADDRESS
BUFFER
COLUMN
DECODER
6
5
27
26
A10 23
A11 25
A12 4
A13 28
A14 3
A15 31
SENSE
AMPS
ROW
ADDRESS
BUFFER
REFRESH
ADDRESS
COUNTER
EXT/INT
ADDRESS
MUX
ROW
DECODER
I/O
SELECTOR
CE2 30
13 I/O0
14 I/O1
15 I/O2
17 I/O3
18 I/O4
19 I/O5
20 I/O6
MEMORY
ARRAY
DATA
OUT
BUFFER
A16 2
CE1 22
DATA
IN
BUFFER
21 I/O7
CLOCK
GENERATOR
REFRESH
CONTROLLER
REFRESH
TIMER
RFSH 1
OE 24
R/W 29
NOTE: Pin numbers apply to the 32-pin DIP or SOP.
5P8128-2
Figure 3. LH5P8128 Block Diagram
PIN DESCRIPTION
SIGNAL
A0 - A16
R/W
OE
2
PIN NAME
Address input
Read/Write input
Output Enable Input
SIGNAL
CE1, CE2
RFSH
I/O0 - I/O7
PIN NAME
Chip Enable input
Refresh input
Data input/output
CMOS 1M (128K × 8) Pseudo-Static RAM
LH5P8128
ABSOLUTE MAXIMUM RATINGS
SYMBOL
RATING
UNIT
NOTE
Applied voltage on any pins
Output short circuit current
Power dissipation
Operating temperature
PARAMETER
VT
IO
PD
Topr
-1.0 to +7.0
50
600
0 to +70
V
mA
mW
1
Storage temperature
Tstg
-55 to +150
°C
°C
NOTE:
1. The maximum applicable voltage on any pin with respect to GND.
RECOMMENDED OPERATING CONDITIONS (TA = 0 to +70°C)
PARAMETER
Supply voltage
Input voltage
SYMBOL
MIN.
TYP.
MAX.
UNIT
VCC
4.5
5.0
5.5
V
GND
0
0
0
V
VIH
2.4
VCC + 0.3
V
VIL
-1.0
0.8
V
CAPACITANCE (TA = 0 to +70°C, f = 1MHz, VCC = 5.0 V ±10%)
PARAMETER
Input capacitance
Input/output capacitance
CONDITIONS
SYMBOL
A0 - A16
MIN.
MAX.
UNIT
CIN1
8
pF
R/W, OE
CIN2
5
pF
CE1, CE2
CIN3
5
pF
RFSH
CIN4
5
pF
I/O0 - I/O7
COUT1
10
pF
DC CHARACTERISTICS (TA = 0 to +70°C, VCC = 5.0 V ±10%)
PARAMETER
SYMBOL
CONDITIONS
ICC1
tRC = tRC (MIN)
MIN.
LH5P8128-60
Operating current
LH5P8128-80
Standby current
Self-refresh average
current
CMOS Input
TTL Input
CMOS Input
UNIT
NOTE
mA
1, 2
104
70
LH5P8128-10
TTL Input
MAX.
50
1
ICC2
0.2
1
ICC3
0.2
mA
mA
Input leakage current
ILI
0 V ≤ VIN ≤ 6.5 V
0 V except on test pins
-10
10
µA
I/O leakage current
ILO
0 V ≤ VOUT ≤ VCC + 0.3 V
Output in highimpedance state
-10
10
µA
Output HIGH voltage
VOH
IOUT = -1 mA
2.4
Output LOW voltage
VOL
IOUT = 4 mA
1, 3
1, 4
1, 5
1, 6
V
0.4
V
NOTES:
1. Specified values are with outputs open.
2. Depends on the cycle time.
3. CE1 = VIH, RFSH = VIH
4. CE1 = VCC - 0.2 V, RFSH = VCC - 0.2 V
5. CE1 = VIH, RFSH = VIL
6. CE1 = VCC - 0.2 V, RFSH = 0.2 V
3
CMOS 1M (128K × 8) Pseudo-Static RAM
LH5P8128
AC ELECTRICAL CHARACTERISTICS
(TA = 0 to +70°C, VCC = 5.0 V ±10%)
1,2,3
LH5P8128-60
LH5P8128-10
SYMBOL
Random read, write cycle time
Read modify write cycle time
CE pulse width
CE precharge time
Address setup time
Address hold time
Read command setup time
Read command hold time
CE access time
OE access time
CE to output in Low-Z
OE to output in Low-Z
Output enable from end of write
Chip disable to output in High-Z
Output disable to output in High-Z
Write enable to output in High-Z
OE setup time
OE hold time
Write command pulse width
Write command setup time
Write command hold time
Data setup time from write
Data setup time from CE
Data hold time from write
Data hold time from CE
Transition time (rise and fall)
Refresh time interval
Refresh command hold time
Auto refresh cycle time
Refresh delay time from CE
Refresh pulse width
(Auto refresh)
Refresh precharge time
(Auto refresh)
Refresh pulse width (Self refresh)
CE delay time from refresh
precharge (Self refresh)
tRC
tRMW
tCE
tP
tAS
tAH
tRCS
tRCH
tCEA
tOEA
tCLZ
tOLZ
tWLZ
tCHZ
tOHZ
tWHZ
tOES
tOEH
tWP
tWCS
tWCH
tDSW
tDSC
tDHW
tDHC
tT
tREF
tRHC
tFC
tRFD
100
165
60
40
0
15
0
0
tFAP
30
tFP
30
30
30
ns
tFAS
8,000
8,000
8,000
ns
tFRS
140
160
190
ns
MIN.
MAX.
10,000
MIN.
130
195
80
40
0
20
0
0
60
25
20
0
0
0
10
30
30
40
25
25
0
0
3
MAX.
10,000
20
0
0
35
8
15
100
30
160
235
100
50
0
25
0
0
30
INPUT
OUTPUT
10,000
100
35
25
25
25
0
10
30
30
50
30
30
0
0
3
MAX.
20
0
0
35
8
15
130
40
8,000
MIN.
80
30
20
20
20
NOTES:
1. In order to initialize the circuit, CE1 should be kept at VIH or CE2
should be kept at VIL for 100 µs after power-up, followed by at
least 8 dummy cycles.
2. AC characteristics are measured at t T = 5 ns.
3. AC characteristics are measured at the following condition (see
figure at right).
4. Address is latched at the negative edge of CE1 or at the positive
edge of CE2.
5. Measured with a load equivalent to 2TTL + 100 pF.
6. Data is latched at the positive edge of W/R or at the positive
edge of CE1 or at the negative edge of CE2.
4
LH5P8128-80
PARAMETER
30
30
30
0
10
30
30
60
35
35
0
0
3
35
8
15
160
50
8,000
30
8,000
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
NOTE
4
4
5
5
6
6
6
6
ns
2.6 V
2.4 V
0.8 V
0.6 V
2.2 V
0.8 V
5P8128-3
Figure 4. AC Characteristics
CMOS 1M (128K × 8) Pseudo-Static RAM
LH5P8128
tRC
tP
CE1
VIH
VIL
CE2
VIH
VIL
tCE
tAS
A0 - A16
VIH
VIL
OE
VIH
VIL
tAH
ADDRESS
INPUT
tRCS
R/W
tRCH
VIH
VIL
tOEA
tCEA
tOHZ
tOLZ
tCLZ
I/O0 - I/O7
VOH
VOL
tCHZ
VALID-DATA OUTPUT
tFP
tFRS
RFSH
tRHC
tRFD
VIH
VIL
NOTE: Operation possible using only CE2 (CE1) by fixing CE1 to LOW (CE2 to HIGH).
5P8128-4
Figure 5. Read Cycle
5
CMOS 1M (128K × 8) Pseudo-Static RAM
LH5P8128
tRC
tCE
tP
CE1
VIH
VIL
CE2
VIH
VIL
tAS
A0 - A16
VIH
VIL
tAH
ADDRESS
INPUT
tOES
OE
tOEH
VIH
VIL
tWCS
tWCH
tWP
R/W
VIH
VIL
tDSW
tDHW
tDSC
V
I/O0 - I/O7 VOH
OL
tDHC
DATA INPUT
tFP
tFRS
RFSH
tRHC
VIH
VIL
NOTE: Operation possible using only CE2 (CE1) by fixing CE1 to LOW (CE2 to HIGH).
Figure 6. Write Cycle 1 (OE = HIGH)
6
tRFD
5P8128-5
CMOS 1M (128K × 8) Pseudo-Static RAM
LH5P8128
tRC
tCE
tP
CE1
VIH
VIL
CE2
VIH
VIL
tAS
A0 - A16
VIH
VIL
OE
VIH
VIL
tAH
ADDRESS
INPUT
tWCS
tWCH
tWP
R/W
VIH
VIL
tDSW
tDHW
tDSC
DIN
VIH
VIL
tDHC
VALID DATA INPUT
tWHZ
I/O0 - I/O7
tCLZ
tOHZ
tOLZ
tWLZ
tCHZ
V
DOUT VOH
OL
tFP
tFRS
RFSH
tRHC
tRFD
VIH
VIL
NOTE: Operation possible using only CE2 (CE1) by fixing CE1 to LOW (CE2 to HIGH).
5P8128-6
Figure 7. Write Cycle 2 (OE Clock)
7
CMOS 1M (128K × 8) Pseudo-Static RAM
LH5P8128
tRC
tCE
tP
CE1
VIH
VIL
CE2
VIH
VIL
tAS
A0 - A16
VIH
VIL
OE
VIH
VIL
tAH
ADDRESS
INPUT
tWCS
tWCH
tWP
R/W
VIH
VIL
tDSW
tDHW
tDSC
DIN
VIH
VIL
VALID DATA INPUT
tWHZ
I/O0 - I/O7
tCLZ
DOUT
tDHC
tCHZ
tWLZ
VOH
VOL
tFP
tFRS
RFSH
tRHC
VIH
VIL
NOTE: Operation possible using only CE2 (CE1) by fixing CE1 to LOW (CE2 to HIGH).
Figure 8. Write Cycle 3 (OE = LOW)
8
tRFD
5P8128-7
CMOS 1M (128K × 8) Pseudo-Static RAM
LH5P8128
tRMW
tP
CE1
VIH
VIL
CE2
VIH
VIL
tAS
A0 - A16
VIH
VIL
OE
VIH
VIL
tAH
ADDRESS
INPUT
tRCS
tWCS
tWP
R/W
VIH
VIL
tOEA
tDSW
tDSC
tCEA
DIN
VIH
VIL
tDHC
DATA INPUT
tOLZ
I/O0 - I/O7
tWHZ
tCLZ
DOUT
tDHW
VOH
VOL
tOHZ
tCHZ
tWLZ
DATA OUTPUT
tFP
tFRS
RFSH
tRHC
tRFD
VIH
VIL
NOTE: Operation possible using only CE2 (CE1) by fixing CE1 to LOW (CE2 to HIGH).
5P8128-8
Figure 9. Read-Modify-Write Cycle
9
CMOS 1M (128K × 8) Pseudo-Static RAM
LH5P8128
tRC
tCE
tP
CE1
VIH
VIL
CE2
VIH
VIL
tAS
A0 - A8
VIH
VIL
tAH
ADDRESS
INPUT
tOEH
OE
VIH
VIL
tOES
tRCS
R/W
VIH
VIL
I/O0 - I/O7
VOH
VOL
tRCH
HIGH-Z
tFP
tFRS
RFSH
tRFD
tRHC
VIH
VIL
NOTE: A9 - A16 = Don't Care.
5P8128-9
Figure 10. CE Only Refresh
CE1
VIH
VIL
CE2
VIH
VIL
OR
CE1
VIH
VIL
CE2
VIH
VIL
tRFD
tFP
RFSH
VIH
VIL
I/O0 - I/O7
VOH
VOL
tRHC
tFAS
HIGH-Z
NOTE: OE, R/W, A0 - A16 = Don't Care.
5P8128-10
Figure 11. Self Refresh Cycle
10
tFRS
CMOS 1M (128K × 8) Pseudo-Static RAM
CE1
VIH
VIL
CE2
VIH
VIL
LH5P8128
OR
CE1
VIH
VIL
tFC
CE2
tFC
VIH
VIL
tRFD
tFP
tRHC
tFAP
tFP
tFAP
tFP
V
RFSH VOH
OL
I/O0 - I/O7
VOH
VOL
HIGH-Z
NOTE: OE, R/W, A0 - A16 = Don't Care.
5P8128-11
Figure 12. Auto Refresh Cycle
11
CMOS 1M (128K × 8) Pseudo-Static RAM
LH5P8128
PACKAGE DIAGRAMS
32DIP (DIP032-P-0600)
32
17
DETAIL
13.45 [0.530]
12.95 [0.510]
1
0° TO 15°
16
0.30 [0.012]
0.20 [0.008]
41.30 [1.626]
40.70 [1.602]
15.24 [0.600]
TYP.
4.50 [0.177]
4.00 [0.157]
5.20 [0.205]
5.00 [0.197]
3.50 [0.138]
3.00 [0.118]
0.51 [0.020] MIN.
2.54 [0.100]
TYP.
0.60 [0.024]
0.40 [0.016]
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
32DIP
32-pin, 600-mil DIP
32SOP (SOP032-P-0525)
1.27 [0.050]
TYP.
0.50 [0.020]
0.30 [0.012]
1.40 [0.055]
32
17
11.50 [0.453]
11.10 [0.437]
1
14.50 [0.571]
13.70 [0.539]
12.50 [0.492]
16
1.40 [0.055]
0.20 [0.008]
0.10 [0.004]
20.80 [0.819]
20.40 [0.803]
0.15 [0.006]
1.275 [0.050]
2.90 [0.114]
2.50 [0.098]
0.20 [0.008]
0.00 [0.000]
1.275 [0.050]
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
32SOP
32-pin, 525-mil SOP
12
CMOS 1M (128K × 8) Pseudo-Static RAM
LH5P8128
32TSOP (Type I) (TSOP032-P-0820)
0.30 [0.012]
0.10 [0.004]
0.50 [0.020]
TYP.
32
17
18.60 [0.732]
18.20 [0.717]
1
20.30 [0.799]
19.70 [0.776]
19.00 [0.748]
16
8.20 [0.323]
7.80 [0.307]
0.20 [0.008]
0.10 [0.004]
0.15 [0.006]
1.10 [0.043]
0.90 [0.035]
1.20 [0.047] MAX.
0.425 [0.017] 0.20 [0.008]
0.00 [0.000]
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT
MINIMUM LIMIT
32TSOP
32-pin, 8 × 20 mm2 TSOP (Type I)
ORDERING INFORMATION
LH5P8128
Device Type
X
Package
- ##
Speed
60 60
80 80
10 100
Access Time (ns)
Blank 32-pin, 600-mil DIP (DIP032-P-0600)
N 32-pin, 525-mil SOP (SOP032-P-0525)
T 32-pin, 8 x 20 mm2 TSOP (Type I) (TSOP032-P-0820)
TR 32-pin, 8 x 20 mm2 TSOP (Type I) Reverse bend (TSOP032-P-0820)
CMOS 1M (128K x 8) Pseudo-Static RAM
Example: LH5P8128N-60 (CMOS 1M (128K x 8) Pseudo-Static RAM, 60 ns, 32-pin, 525-mil SOP)
5P8128-12
13
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