FAIRCHILD 74LCXZ245

Revised March 2005
74LCXZ245
Low Voltage Bidirectional Transceiver
with 5V Tolerant Inputs and Outputs
General Description
Features
The 74LCXZ245 contains eight non-inverting bidirectional
buffers with 3-STATE outputs and is intended for bus oriented applications. The device is designed for low voltage
(2.5V and 3.3V) VCC applications with capability of interfacing to a 5V signal environment. The T/R input determines
the direction of data flow through the device. The OE input
disables both the A and B ports by placing them in a high
impedance state.
■ 5V tolerant inputs and outputs
The 74LCXZ245 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintaining CMOS low power dissipation. When VCC is between 0V
and 1.5V, the 74LCXZ245 is on the high impedance state
during power up or power down. This places the outputs in
the high impedance (Z) state preventing intermittent low
impedance loading or glitching in bus oriented applications.
■ 2.3V–3.6V VCC specifications provided
■ 7.0 ns tPD max (VCC
3.3V), 10 PA ICC max
■ Power down high impedance inputs and outputs
■ Supports live insertion/withdrawal (Note 1)
■ r24 mA output drive (VCC
3.0V)
■ Implements patented noise/EMI reduction circuitry
■ Latch-up performance exceeds 500 mA
■ ESD performance:
Human body model ! 2000V
Machine model ! 200V
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to VCC through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number
Package Number
74LCXZ245WM
Package Description
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74LCXZ245SJ
M20D
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LCXZ245MSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
74LCXZ245MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
Description
OE
Output Enable Input
T/R
Transmit/Receive Input
A0–A7
Side A Inputs or 3-STATE Outputs
B0–B7
Side B Inputs or 3-STATE Outputs
© 2005 Fairchild Semiconductor Corporation
DS500362
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74LCXZ245 Low Voltage Bidirectional Transceiver with 5V Tolerant Inputs and Outputs
October 2000
74LCXZ245
Truth Table
Inputs
Outputs
OE
T/R
L
L
Bus B0 – B7 Data to Bus A0 – A7
L
H
Bus A0 – A7 Data to Bus B0 – B7
H
X
HIGH Z State on A0 – A7, B0 – B7 (Note 2)
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
Z High Impedance
Note 2: Unused bus terminals during HIGH Z State must be held HIGH or LOW.
Logic Diagram
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Symbol
Parameter
VCC
Supply Voltage
VI
DC Input Voltage
VO
DC Output Voltage
IIK
DC Input Diode Current
IOK
DC Output Diode Current
Value
IO
DC Output Source/Sink Current
ICC
DC Supply Current per Supply Pin
IGND
DC Ground Current per Ground Pin
TSTG
Storage Temperature
Conditions
0.5 to 7.0
0.5 to 7.0
0.5 to 7.0
0.5 to VCC 0.5
50
50
50
r50
r100
r100
65 to 150
Units
V
V
Output in 3-STATE
Output in HIGH or LOW State (Note 4)
VI GND
V
mA
VO GND
mA
VO ! VCC
mA
mA
mA
qC
Recommended Operating Conditions (Note 5)
Symbol
Parameter
VCC
Supply Voltage
VI
Input Voltage
VO
Output Voltage
IOH/IOL
Min
Max
2.7
3.6
V
0
5.5
V
HIGH or LOW State
0
VCC
3-STATE
0
5.5
Operating
Output Current
TA
Free-Air Operating Temperature
't/'V
Input Edge Rate, VIN
0.8V 2.0V, VCC
VCC
3.0V 3.6V
VCC
2.7V - 3.0V
VCC
2.3V - 2.7V
r24
r12
r8
Units
V
mA
40
85
qC
0
10
ns/V
3.0V
Note 3: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.
Note 4: IO Absolute Maximum Rating must be observed.
Note 5: Unused inputs or I/O pins must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
VIH
Parameter
Conditions
HIGH Level Input Voltage
VIL
LOW Level Input Voltage
VOH
HIGH Level Output Voltage
VCC
TA
40qC to 85qC
(V)
Min
2.3 2.7
1.7
2.7 3.6
2.0
2.3 2.7
VOL
LOW Level Output Voltage
100 PA
IOH
IOH
IOH
0.8
2.3 - 3.6
VCC 0.2
8 mA
2.3
1.8
12 mA
2.7
2.2
18 mA
3.0
2.4
2.2
24 mA
3.0
IOL
100 PA
2.3 3.6
0.2
IOL
8mA
2.3
0.6
IOL
12 mA
2.7
0.4
IOL
16 mA
3.0
0.4
IOL
24 mA
Input Leakage Current
0 d VI d 5.5V
IOZ
3-STATE I/O Leakage
0 d VO d 5.5V
VI
V IH or VIL
IOFF
Power-Off Leakage Current
VI or VO
IPU/PD
Power Up/ Power Down
VO
3-STATE Output Current
VI
5.5V
to VCC
V CC or GND
3
V
V
IOH
II
Units
V
0.7
2.7 - 3.6
IOH
Max
V
3.0
0.55
2.3 3.6
r5.0
PA
2.3 3.6
r5.0
PA
0
10
PA
0 1.5
r5.0
PA
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74LCXZ245
Absolute Maximum Ratings(Note 3)
74LCXZ245
DC Electrical Characteristics
Symbol
(Continued)
Parameter
VCC
Conditions
(V)
ICC
Quiescent Supply Current
VI
VCC or GND
3.6V d VI, VO d 5.5V (Note 6)
'ICC
Increase in ICC per Input
VIH
VCC 0.6V
TA
40qC to 85qC
Min
Units
Max
2.3 3.6
225
2.3 3.6
r225
2.3 3.6
500
PA
PA
Note 6: Outputs disabled or 3-STATE only.
AC Electrical Characteristics
40qC to 85qC, RL
TA
Symbol
VCC
Parameter
500:
3.3V r 0.3V
VCC
50 pF
CL
CL
2.7V
Units
50 pF
Min
Max
Min
Max
tPHL
Propagation Delay
1.5
7.0
1.5
8.0
tPLH
An to Bn or Bn to An
1.5
7.0
1.5
8.0
tPZL
Output Enable Time
1.5
8.5
1.5
9.5
1.5
8.5
1.5
9.5
1.5
7.5
1.5
8.5
1.5
7.5
1.5
8.5
tPZH
tPLZ
Output Disable Time
tPHZ
tOSHL
Output to Output Skew
1.0
tOSLH
(Note 7)
1.0
ns
ns
ns
ns
Note 7: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Dynamic Switching Characteristics
Symbol
VOLP
VOLV
Parameter
Quiet Output Dynamic Peak VOL
Quiet Output Dynamic Valley VOL
VCC
(V)
Conditions
25qC
TA
Typical
CL
50 pF, VIH
3.3V, VIL
0V
3.3
0.8
CL
30 pF, VIH
2.5V, VIL
0V
2.5
0.6
CL
50 pF, VIH
3.3V, V IL
0V
3.3
0.8
CL
30 pF, VIH
2.5V, VIL
0V
2.5
0.6
Units
V
V
Capacitance
Symbol
Parameter
Conditions
CIN
Input Capacitance
VCC
Open, VI
CI/O
Input/Output Capacitance
VCC
3.3V, VI
0V or VCC
CPD
Power Dissipation Capacitance
VCC
3.3V, VI
0V or VCC, f
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0V or VCC
10 MHz
Typical
Units
7
pF
8
pF
25
pF
74LCXZ245
AC LOADING and WAVEFORMS Generic for LCX Family
FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance)
Test
Switch
tPLH, tPHL
Open
tPZL, tPLZ
6V at VCC 3.3 r 0.3V
VCC x 2 at VCC 2.5 r 0.2V
tPZH,tPHZ
GND
Waveform for Inverting and Non-Inverting Functions
3-STATE Output High Enable and
Disable Times for Logic
Propagation Delay. Pulse Width and trec Waveforms
Setup Time, Hold Time and Recovery Time for Logic
trise and tfall
3-STATE Output Low Enable and
Disable Times for Logic
FIGURE 2. Waveforms
(Input Characteristics; f =1MHz, tR = tF = 3ns)
Symbol
VCC
3.3V r 0.3V
2.7V
2.5V r 0.2V
Vmi
1.5V
1.5V
VCC/2
Vmo
1.5V
1.5V
VCC/2
Vx
VOL 0.3V
VOL 0.3V
VOL 0.15V
Vy
VOH 0.3V
VOH 0.3V
VOH 0.15V
5
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74LCXZ245
Schematic Diagram Generic for LCX Family
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74LCXZ245
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
7
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74LCXZ245
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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74LCXZ245
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
Package Number MSA20
9
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74LCXZ245 Low Voltage Bidirectional Transceiver with 5V Tolerant Inputs and Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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