IXYS IXDD509 9 ampere low-side ultrafast mosfet drivers with enable for fast, controlled shutdown Datasheet

IXDD509 / IXDE509
9 Ampere Low-Side Ultrafast MOSFET Drivers
with Enable for fast, controlled shutdown
Features
General Description
• Built using the advantages and compatibility
of CMOS and IXYS HDMOSTM processes
• Latch-Up Protected up to 9 Amps
• High 9A peak output current
• Wide operating range: 4.5V to 30V
• -55°C to +125°C Extended operating
temperature
• Ability to disable output under faults
• High capacitive load drive capability:
1800pF in <15ns
• Matched rise and fall times
• Low propagation delay time
• Low output impedance
• Low supply current
The IXDD509 and IXDE509 are high speed high current gate
drivers specifically designed to drive the largest IXYS
MOSFETs & IGBTs to their minimum switching time and
maximum parctical frequency limits. The IXDD509 and
IXDE509 can source and sink 9 Amps of Peak Current
while producing voltage rise and fall times of less than
30ns. The inputs of the Drivers are compatible with TTL or
CMOS and are virtually immune to latch up over the entire
operating range. Patented* design innovations eliminate
cross conduction and current "shoot-through". Improved
speed and drive capabilities are further enhanced by
matched rise and fall times.
Applications
•
•
•
•
•
•
•
•
•
•
•
Driving MOSFETs and IGBTs
Limiting di/dt under short circuit
Motor controls
Line drivers
Pulse generators
Local power ON/OFF switch
Switch mode power supplies (SMPS)
DC to DC converters
Pulse transformer driver
Class D switching amplifiers
Power charge pumps
The IXDD509 and IXDE509 incorporate a unique ability to
disable the output under fault conditions. When a logical
low is forced into the Enable input, both final output stage
MOSFETs, (NMOS and PMOS) are turned off. As a result,
the output of the IXDD509 or IXDE509 enters a tristate high
impedance mode and with additional circuitry, achieves a
Soft Turn-Off of the MOSFET/IGBT when a short circuit is
detected. This helps prevent damage that could occur to
the MOSFET/IGBT if it were to be switched off abruptly due
to a dv/dt over-voltage transient.
The IXDD509 and IXDE509 are available in the 8-Pin P-DIP
(PI) package, the 8-Pin SOIC (SIA) package, and the 6Lead DFN (D1) package, (which occupies less than 65% of
the board area of the 8-Pin SOIC).
*United States Patent 6,917,227
Ordering Information
Part Number
IXDD509PI
IXDD509SIA
IXDD509SIAT/R
IXDD509D1
IXDD509D1T/R
IXDE509PI
IXDE509SIA
IXDE509SIAT/R
IXDE509D1
IXDE509D1T/R
Description
9A Low Side Gate Driver I.C.
9A Low Side Gate Driver I.C.
9A Low Side Gate Driver I.C.
9A Low Side Gate Driver I.C.
9A Low Side Gate Driver I.C.
9A Low Side Gate Driver I.C.
9A Low Side Gate Driver I.C.
9A Low Side Gate Driver I.C.
9A Low Side Gate Driver I.C.
9A Low Side Gate Driver I.C.
Package
Type
8-Pin PDIP
8-Pin SOIC
8-Pin SOIC
6-Lead DFN
6-Lead DFN
8-Pin PDIP
8-Pin SOIC
8-Pin SOIC
6-Lead DFN
6-Lead DFN
Packing Style
Tube
Tube
13” Tape and Reel
2” x 2” Waffle Pack
13” Tape and Reel
Tube
Tube
13” Tape and Reel
2” x 2” Waffle Pack
13” Tape and Reel
Pack
Qty
50
94
2500
56
2500
50
94
2500
56
2500
Configuration
Non-Inverting
with Enable
Inverting
with Enable
NOTE: All parts are lead-free and RoHS Compliant
Copyright © 2007 IXYS CORPORATION All rights reserved
DS99679A(10/07)
First Release
IXDD509 / IXDE509
Figure 1 - IXDD509 9A Non-Inverting Gate Driver Functional Block Diagram
Vcc
Vcc
200 K
P
ANTI-CROSS
CONDUCTION
CIRCUIT *
*
IN
EN
OUT
N
GND
GND
Figure 2 - IXDE509 Inverting 9A Gate Driver Functional Block Diagram
Vcc
Vcc
200 K
P
ANTI-CROSS
CONDUCTION
CIRCUIT *
IN
EN
United States Patent 6,917,227
Copyright © 2007 IXYS CORPORATION All rights reserved
N
GND
GND
*
OUT
2
IXDD509 / IXDE509
Absolute Maximum Ratings (1)
Operating Ratings (2)
Parameter
Supply Voltage
All Other Pins (unless specified
otherwise)
Junction Temperature
Storage Temperature
Lead Temperature (10 Sec)
Parameter
Value
Operating Supply Voltage
4.5V to 30V
Operating Temperature Range
-55 °C to 125 °C
Package Thermal Resistance *
θJ-A (typ) 125 °C/W
8-PinPDIP
(PI)
8-Pin SOIC
(SIA)
θJ-A(typ) 200 °C/W
6-Lead DFN
(D1)
θJ-A(typ) 125-200 °C/W
θJ-C(max) 2.0 °C/W
6-Lead DFN
(D1)
6-Lead DFN
(D1)
θJ-S(typ) 6.3 °C/W
Value
35 V
-0.3 V to VCC + 0.3V
150 °C
-65 °C to 150 °C
300 °C
Electrical Characteristics @ TA = 25o C (3)
Unless otherwise noted, 4.5V ≤ VCC ≤ 30V .
All voltage measurements with respect to GND. IXD_509 configured as described in Test Conditions. (4)
Symbol
Parameter
Test Conditions
Min
VIH, VENH
High input & EN voltage
4.5V ≤ VCC ≤ 18V
2.4
VIL, VENL
Low input & EN voltage
4.5V ≤ VCC ≤ 18V
VIN
Input voltage range
VEN
Enable voltage range
IIN
Input current
VOH
High output voltage
VOL
Low output voltage
ROH
IPEAK
High state output
resistance
Low state output
resistance
Peak output current
IDC
Continuous output current
tR
ROL
0V ≤ VIN ≤ VCC
V
0.8
V
-5
VCC + 0.3
V
-.3
VCC + 0.3
V
-10
10
µA
V
0.025
V
0.6
1
Ω
VCC = 18V
0.4
0.8
Ω
VCC = 15V
9
tF
Fall time
tONDLY
VCC
On-time propagation
delay
Off-time propagation
delay
Enable to output high
delay time
Disable to output high
impedance delay time
Power supply voltage
ICC
Power supply current
tDOLD
Units
VCC = 18V
Rise time
tENOH
Max
VCC - 0.025
Limited by package power
dissipation
CLOAD =10,000pF VCC =18V
tOFFDLY
Typ
A
2
A
25
45
ns
CLOAD =10,000pF VCC =18V
23
40
ns
CLOAD =10,000pF VCC =18V
18
35
ns
CLOAD =10,000pF VCC =18V
19
30
ns
VCC =18V
25
50
ns
VCC =18V
60
80
ns
18
30
V
1
75
3
75
µA
mA
mA
4.5
VCC = 18V, VIN = 0V
VIN = 3.5V
VIN = VCC
IXYS reserves the right to change limits, test conditions, and dimensions.
3
IXDD509 / IXDE509
Electrical Characteristics @ temperatures over -55 oC to 125 oC (3)
Unless otherwise noted, 4.5V ≤ VCC ≤ 30V , Tj < 150oC
All voltage measurements with respect to GND. IXD_502 configured as described in Test Conditions. All specifications are for one channel. (4)
Symbol
Parameter
Test Conditions
Min
High input voltage
4.5V ≤ VCC ≤ 18V
2.4
VIL
Low input voltage
4.5V ≤ VCC ≤ 18V
VIN
Input voltage range
IIN
Input current
VIH
VOH
High output voltage
VOL
Low output voltage
High state output
resistance
Low state output
resistance
Continuous output
current
Rise time
ROH
ROL
IDC
tR
tF
tONDLY
tOFFDLY
tENOH
tDOLD
VCC
ICC
Fall time
On-time propagation
delay
Off-time propagation
delay
Enable to output high
delay time
Disable to output high
impedance delay time
Power supply voltage
Power supply current
0V ≤ VIN ≤ VCC
Typ
Max
Units
0.8
V
V
-5
VCC + 0.3
V
-10
10
µA
VCC - 0.025
V
0.025
V
VCC = 18V
2
Ω
VCC = 18V
1.5
Ω
1
A
CLOAD =10,000pF VCC =18V
60
ns
CLOAD =10,000pF VCC =18V
60
ns
CLOAD =10,000pF VCC =18V
55
CLOAD =10,000pF VCC =18V
40
VCC = 18V
VCC = 18V
4.5
VCC = 18V, VIN = 0V
VIN = 3.5V
VIN = VCC
18
ns
ns
60
ns
100
ns
30
V
0.13
3
0.13
µA
mA
mA
Notes:
1. Operating the device beyond the parameters listed as “Absolute Maximum Ratings” may cause permanent
damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
2. The device is not intended to be operated outside of the Operating Ratings.
3. Electrical Characteristics provided are associated with the stated Test Conditions.
4. Typical values are presented in order to communicate how the device is expected to perform, but not necessarily
to highlight any specific performance limits within which the device is guaranteed to function.
*
The following notes are meant to define the conditions for the θJ-A, θJ-C and θJ-S values:
1) The θJ-A (typ) is defined as junction to ambient. The θJ-A of the standard single die 8-Lead PDIP and 8-Lead SOIC are dominated by the
resistance of the package, and the IXD_5XX are typical. The values for these packages are natural convection values with vertical boards
and the values would be lower with forced convection. For the 6-Lead DFN package, the θJ-A value supposes the DFN package is
soldered on a PCB. The θJ-A (typ) is 200 °C/W with no special provisions on the PCB, but because the center pad provides a low
thermal resistance to the die, it is easy to reduce the θJ-A by adding connected copper pads or traces on the PCB. These can reduce
the θJ-A (typ) to 125 °C/W easily, and potentially even lower. The θJ-A for DFN on PCB without heatsink or thermal management will
vary significantly with size, construction, layout, materials, etc. This typical range tells the user what he is likely to get if he does no
thermal management.
2) θJ-C (max) is defined as juction to case, where case is the large pad on the back of the DFN package. The θJ-C values are generally not
published for the PDIP and SOIC packages. The θJ-C for the DFN packages are important to show the low thermal resistance from junction to
the die attach pad on the back of the DFN, -- and a guardband has been added to be safe.
3) The θJ-S (typ) is defined as junction to heatsink, where the DFN package is soldered to a thermal substrate that is mounted on a heatsink.
The value must be typical because there are a variety of thermal substrates. This value was calculated based on easily available IMS in the
U.S. or Europe, and not a premium Japanese IMS. A 4 mil dialectric with a thermal conductivity of 2.2W/mC was assumed. The result was
given as typical, and indicates what a user would expect on a typical IMS substrate, and shows the potential low thermal resistance for the
DFN package.
Copyright © 2007 IXYS CORPORATION All rights reserved
4
IXDD509 / IXDE509
Pin Description
PIN
SYMBOL
FUNCTION
1,8
VCC
Supply Voltage
2
IN
Input
3
EN
Enable
6,7
OUT
Output
4,8
GND
Ground
DESCRIPTION
Power supply input voltage. These pins provide power to
the entire device. The range for this voltage is from 4.5V to
30V.
Input signal-TTL or CMOS compatible.
The device ENABLE pin. This pin, when driven low,
disables the chip, forcing a high impedance state at the
output. EN can be pulled high by a resistor.
Driver Output. For application purposes, these pins are
connected, through a resistor, to Gate of a MOSFET/IGBT.
The device ground pins. Internally connected to all circuitry,
these pins provide ground reference for the entire chip and
should be connected to a low noise analog ground plane for
optimum performance.
CAUTION: Follow proper ESD procedures when handling and assembling this component.
PIN CONFIGURATIONS
8 PIN DIP (PI)
8 PIN SOIC (SIA)
VCC
1
IN
2
EN
3
GND
4
8 PIN DIP (PI)
8 PIN SOIC (SIA)
I
X
D
E
5
0
9
8
VCC
VCC
1
7
OUT
IN
2
6
OUT
EN
3
5
GND
GND
4
I
X
D
D
5
0
9
6 LEAD DFN (D1)
(Bottom View)
VCC
6
OUT
5
GND
4
I
X
D
E
5
0
9
8
VCC
7
OUT
6
OUT
5
GND
6 LEAD DFN (D1)
(Bottom View)
1 IN
VCC
6
2 EN
OUT
5
3 GND
GND
4
I
X
D
D
5
0
9
1 IN
2 EN
3 GND
NOTE: Solder tabs on bottoms of DFN packages are grounded
Figure 3 - Characteristics Test Diagram
VOUT
Vcc
VIN
5V
0V
Vcc
10uf
0.01uf
VIN
1
8
Vcc
2
7
IXDE
3
IXDD / IXDE
0V
5
4
IXYS reserves the right to change limits, test conditions, and dimensions.
6
5
Agilent 1147A
Current Probe
CLOAD
IXDD
0V
IXDD509 / IXDE509
Figure 4 - Timing Diagrams
Non-Inverting (IXDD509) Timing Diagram
5V
90%
INPUT 2.5V
10%
0V
PWMIN
tONDLY
tOFFDLY
tR
tF
Vcc
90%
OUTPUT
10%
0V
Inverting (IXDE509) Timing Diagram
5V
90%
INPUT 2.5V
10%
0V
PWMIN
tONDLY
tOFFDLY
tF
VCC
90%
OUTPUT
10%
0V
Copyright © 2007 IXYS CORPORATION All rights reserved
6
tR
IXDD509 / IXDE509
Typical Performance Characteristics
Fig. 5
Fig. 6
Rise Time vs. Supply Voltage
Fall Time vs. Supply Voltage
35
35
30
25
Fall Time (ns)
Rise Time (ns)
30
10000pF
20
15
5400pF
10
25
10000
20
15
5400p
10
1000pF
5
1000
5
100
100pF
0
0
0
5
10
15
20
25
30
0
35
5
Rise / Fall Time (ns)
Rise / Fall Time vs. Temperature
VSUPPLY = 15V CLOAD = 1000pF
20
25
30
35
Fig. 8
Rise Time vs. Capacitive Load
8
35
7
30
Rise Time (ns)
6
5
4
3
2
5V
25
15V
30V
20
15
10
5
1
0
-50
0
50
100
0
100
150
1000
Fig. 9
Fig. 10
Fall Time vs. Capacitive Load
Input Threshold Levels vs. Supply Voltage
2.5
35
30
Threshold Level (V)
5
25
15V
30
20
15
10
5
0
100
10000
Load Capacitance (pF)
Temperature (C)
Fall Time (ns)
15
Supply Voltage (V)
Supply Voltage (V)
Fig. 7
10
1000
2
Positive going input
1.5
Negative going input
1
0.5
0
10000
0
Load Capacitance (pF)
IXYS reserves the right to change limits, test conditions, and dimensions.
5
10
15
20
25
Supply Voltage (V)
7
30
35
IXDD509 / IXDE509
Fig. 12
Fig. 11
Propagation Delay vs. Supply Voltage
Rising Input, CLOAD = 1000pF
Input Threshold Levels vs. Temperature
VSUPPLY = 15V
40
Propagation Delay Time (ns)
Input Threshold Level (V)
3
2.5
2
Positive going input
1.5
Negative going input
1
0.5
35
30
25
20
15
10
5
0
0
-50
0
50
100
0
150
5
10
Temperature (C)
Fig. 13
20
25
30
35
Supply Voltage (V)
Fig. 14
Propagation Delay vs. Supply Voltage
Falling Input, CLOAD = 1000pF
50
Propagation Delay vs. Temperature
VSUPPLY = 15V CLOAD = 1000pF
35
45
Propagation Delay Time (ns)
Propagation Delay Time (ns)
15
40
35
30
25
20
15
10
5
30
25
Negative going input
20
Positve going input
15
10
5
0
0
5
10
15
20
25
30
0
35
-50
Supply Voltage (V)
50
100
150
Temeprature (C)
Fig. 16
Fig. 15
Quiescent Current vs. Temperature
Quiescent Current vs. Supply Voltage
VSUPPLY = 15V
10000
1000
Quiescent Current (uA)
Quiesent Current (uA)
0
1000
Inverting / Non-Inverting
Input = "1"
100
Inverting
Input = "0"
10
1
Non-inverting
Input = "0"
0.1
Inverting / Non-inverting, Input= "1"
100
10
Inverting, Input= "0"
1
Non-inverting, Input= "0"
0.1
0.01
0.01
0
5
10
15
20
25
30
-50
35
50
Temperature (C)
Supply Voltage (V)
Copyright © 2007 IXYS CORPORATION All rights reserved
0
8
100
150
IXDD509 / IXDE509
Fig. 17
Fig. 18
Supply Current vs. Capacitive Load
VSUPPLY = 5V
Supply Current (mA)
Supply Current (mA)
100
2MHz
1MHz
100
10
100kH
1
10kHz
0.1
0.01
100
1000
Supply Current vs. Frequency
VSUPPLY = 5V
10000pF
5400pF
1000pF
10
100pF
1
0.1
0.01
10000
10
100
Load Capacitance (pF)
Fig. 19
10000
Frequency (kHz)
Fig. 20
Supply Current vs. Capacitive Load
VSUPPLY = 15V
Supply Current vs. Frequency
VSUPPLY = 15V
1000
1000
1M Hz
100
100kHz
10
10kHz
1
10000pF
Supply Current (mA)
2M Hz
Supply Current (mA)
1000
5400pF
100
1000pF
100pF
10
1
0.1
100
1000
10000
0.1
10
Load Capacitance (pF)
1000
1000
Fig. 22
Supply Current vs. Frequency
VSUPPLY = 30V
1000
2MHz
10000pF
5400pF
100
100kHz
10
10kHz
1
Supply Current (mA)
Supply Current (mA)
1MHz
0.1
100
10000
Frequency (kHz)
Supply Current vs. Capacitive Load
VSUPPLY = 30V
Fig. 21
100
1000pF
100
100pF
10
1
0.1
1000
10
10000
1000
Frequency (kHz)
Load Capacitance (pF)
IXYS reserves the right to change limits, test conditions, and dimensions.
100
9
10000
IXDD509 / IXDE509
Fig. 24
Output Sink Current vs. Supply Voltage
Output Source Current vs. Supply Voltage
25
0
20
-5
Sink Current (A)
Source Current (A)
Fig. 23
15
10
-10
-15
-20
5
-25
0
0
5
10
15
20
25
30
0
35
5
10
Output Source Current vs. Temperature
VSUPPLY = 15V
30
35
0
Output Sink Current (A)
Output Source Current (A)
25
Output Sink Current vs. Temperature
VSUPPLY = 15V
Fig. 26
12
10
8
6
4
2
0
-2
-4
-6
-8
-10
-12
-14
-50
0
50
100
150
-50
0
50
Temperature (C)
100
150
Temperature (C)
Fig. 28
Fig. 27
Low State Output Resistance vs. Supply Voltage
High State Output Resistance vs. Supply Voltage
1.2
Output Resistance (ohms)
1.4
Output Rsistance (ohms)
20
Supply Voltage (V)
Supply Voltage (V)
Fig. 25
15
1.2
1
0.8
0.6
0.4
0.2
1
0.8
0.6
0.4
0.2
0
0
0
5
10
15
20
25
30
0
35
10
15
20
Supply Voltage (V)
Supply Voltage (V)
Copyright © 2007 IXYS CORPORATION All rights reserved
5
10
25
30
35
IXDD509 / IXDE509
Fig. 29
ENABLE Threshold vs. Temperature
VSUPPLY = 15V
Fig. 30
ENABLE Threshold vs. Supply Voltage
2.5
2
2
Enable Threshold (V)
Positive Going Level (V)
1.8
1.5
1
0.5
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0
0
5
10
15
20
25
30
35
-50
0
Supply Voltage (V)
50
100
150
Temperature (C)
Fig. 31
Fig. 32
ENABLE Propagation vs. Temperature
VSUPPLY = 15V
ENABLE Propagation Time vs. Supply Voltage
100
160
ENABLE Delay Time (ns)
ENABLE Delay Time (ns)
90
140
120
100
Negative going ENABLE to high impedance state
80
60
40
Positve going ENABLE to output ON
20
80
70
60
Negative going ENABLE to high impedance state
50
40
30
Positive going ENABLE to output ON
20
10
0
0
0
5
10
15
20
25
30
35
-50
Supply Voltage (V)
50
Temperature (C)
Figure 33 - Typical Application Short Circuit di/dt Limit
IXYS reserves the right to change limits, test conditions, and dimensions.
0
11
100
150
IXDD509 / IXDE509
APPLICATIONS INFORMATION
Short Circuit di/dt Limit
by the inductance of the wire connecting the source resistor to
ground. (Those glitches might cause false triggering of the
comparator).
A short circuit in a high-power MOSFET module such as the
VM0580-02F, (580A, 200V), as shown in Figure 27, can cause
the current through the module to flow in excess of 1500A for
10µs or more prior to self-destruction due to thermal runaway.
For this reason, some protection circuitry is needed to turn off
the MOSFET module. However, if the module is switched off
too fast, there is a danger of voltage transients occuring on the
drain due to Ldi/dt, (where L represents total inductance in
series with drain). If these voltage transients exceed the
MOSFET's voltage rating, this can cause an avalanche breakdown.
The comparator's output should be connected to a SRFF(Set
Reset Flip Flop). The flip-flop controls both the Enable signal,
and the low power MOSFET gate. Please note that CMOS 4000series devices operate with a VCC range from 3 to 15 VDC, (with
18 VDC being the maximum allowable limit).
A low power MOSFET, such as the 2N7000, in series with a
resistor, will enable the VMO580-02F gate voltage to drop
gradually. The resistor should be chosen so that the RC time
constant will be 100us, where "C" is the Miller capacitance of
the VMO580-02F.
The IXDD509 and IXDE509 have the unique capability to softly
switch off the high-power MOSFET module, significantly
reducing these Ldi/dt transients.
For resuming normal operation, a Reset signal is needed at
the SRFF's input to enable the IXDD509/IXDE509 again. This
Reset can be generated by connecting a One Shot circuit
between the IXDD509/IXDE509 Input signal and the SRFF
restart input. The One Shot will create a pulse on the rise of the
IXDD509/IXDE509 input, and this pulse will reset the SRFF
outputs to normal operation.
Thus, the IXDD509/IXDE509 help to prevent device destruction
from both dangers; over-current, and avalanche breakdown
due to di/dt induced over-voltage transients.
The IXDD509/IXDE509 are designed to not only provide ±9A
under normal conditions, but also to allow their outputs to go
into a high impedance state. This permits the IXDD509/IXDE509
output to control a separate weak pull-down circuit during
detected overcurrent shutdown conditions to limit and separately control dVGS/dt gate turnoff. This circuit is shown in Figure
34.
When a short circuit occurs, the voltage drop across the lowvalue, current-sensing resistor, (Rs=0.005 Ohm), connected
between the MOSFET Source and ground, increases. This
triggers the comparator at a preset level. The SRFF drives a low
input into the Enable pin disabling the IXDD509/IXDE509
output. The SRFF also turns on the low power MOSFET,
(2N7000).
Referring to Figure 34, the protection circuitry should include
a comparator, whose positive input is connected to the source
of the VM0580-02. A low pass filter should be added to the input
of the comparator to eliminate any glitches in voltage caused
In this way, the high-power MOSFET module is softly turned off
by the IXDD509/IXDE509, preventing its destruction.
Figure 34 - Application Test Diagram
+
Ld
10uH
IXDD509/IXDE509
Rd
IXDD409
0.1ohm
VCC
VCCA
Rg
OUT
IN
EN
+
-
VCC
+
-
VIN
-
High_Power
VMO580-02F
1ohm
Rsh
1600ohm
GND
GND
Rs
Low_Power
2N7002/PLP
Ls
R+
10kohm
20nH
One Shot Circuit
Rcomp
5kohm
NAND
CD4011A
NOT1
CD4049A
NOT2
CD4049A
Ccomp
1pF
Ros
0
Comp
LM339
+
V+
V-
C+
100pF
+
R
1Mohm
REF
Cos
1pF
Q
NOT3
CD4049A
NOR1
CD4001A
EN
NOR2
CD4001A
SR Flip-Flop
Copyright © 2007 IXYS CORPORATION All rights reserved
12
S
-
VB
IXDD509 / IXDE509
Supply Bypassing and Grounding Practices, Output Lead inductance
OUTPUT LEAD INDUCTANCE
Of equal importance to Supply Bypassing and Grounding
are issues related to the Output Lead Inductance. Every
effort should be made to keep the leads between the
driver and it’s load as short and wide as possible. If the
driver must be placed farther than 0.2” from the load, then
the output leads should be treated as transmission
lines. In this case, a twisted-pair should be considered,
and the return line of each twisted pair should be placed
as close as possible to the ground pin of the driver, and
connect directly to the ground terminal of the load.
When designing a circuit to drive a high speed MOSFET
utilizing the IXDD509/IXDE509, it is very important to keep
certain design criteria in mind, in order to optimize
performance of the driver. Particular attention needs to be
paid to Supply Bypassing, Grounding, and minimizing the
Output Lead Inductance.
Say, for example, we are using the IXDD509 to charge a
5000pF capacitive load from 0 to 25 volts in 25ns…
Using the formula: I= C(∆V / ∆t), where ∆V=25V C=5000pF
& ∆t=25ns we can determine that to charge 5000pF to 25
volts in 25ns will take a constant current of 5A. (In reality,
the charging current won’t be constant, and will peak
somewhere around 9A).
SUPPLY BYPASSING
In order for our design to turn the load on properly, the
IXDD509 must be able to draw this 5A of current from the
power supply in the 25ns. This means that there must be
very low impedance between the driver and the power
supply. The most common method of achieving this low
impedance is to bypass the power supply at the driver with
a capacitance value that is a magnitude larger than the
load capacitance. Usually, this would be achieved by
placing two different types of bypassing capacitors, with
complementary impedance curves, very close to the driver
itself. (These capacitors should be carefully selected, low
inductance, low resistance, high-pulse current-service
capacitors). Lead lengths may radiate at high frequency
due to inductance, so care should be taken to keep the
lengths of the leads between these bypass capacitors and
the IXDD509 to an absolute minimum.
GROUNDING
In order for the design to turn the load off properly, the
IXDD509 must be able to drain this 5A of current into an
adequate grounding system. There are three paths for
returning current that need to be considered: Path #1 is
between the IXDD509 and it’s load. Path #2 is between the
IXDD509 and it’s power supply. Path #3 is between the
IXDD509 and whatever logic is driving it. All three of these
paths should be as low in resistance and inductance as
possible, and thus as short as practical. In addition, every
effort should be made to keep these three ground paths
distinctly separate. Otherwise, for instance, the returning
ground current from the load may develop a voltage that
would have a detrimental effect on the logic line driving the
IXDD509.
IXYS reserves the right to change limits, test conditions, and dimensions.
13
IXDD509 / IXDE509
A2
b
b2
b3
c
D
D1
E
E1
e
eA
eB
L
E
H
B
C
D
E
e
H
h
L
M
N
D
A
A1
e
B
h X 45
N
L
C
]
0.018 [0.47]
0.137 [3.48]
IXYS Corporation
3540 Bassett St; Santa Clara, CA 95054
Tel: 408-982-0700; Fax: 408-496-0670
e-mail: [email protected]
www.ixys.com
0.120 [3.05]
0.020 [0.51]
[
S0.002^0.000; o S0.05^0.00;o
0.039 [1.00]
0.035 [0.90]
0.157±0.005 [3.99±0.13]
0.197±0.005 [5.00±0.13]
0.019 [0.49]
M
0.100 [2.54]
IXYS Semiconductor GmbH
Edisonstrasse15 ; D-68623; Lampertheim
Tel: +49-6206-503-0; Fax: +49-6206-503627
e-mail: [email protected]
Copyright © 2007 IXYS CORPORATION All rights reserved
14