Mitsubishi M5M5Y5672TG-22 18874368-bit(262144-word by 72-bit) network sram Datasheet

MITSUBISHI LSIs
2001.May Rev.0.1
M5M5Y5672TG – 25,22,20
Advanced Information
Notice: This is not final specification.
Some parametric limits are subject to change.
18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
DESCRIPTION
The M5M5Y5672TG is a family of 18M bit synchronous SRAMs
organized as 262144-words by 72-bit. It is designed to eliminate
dead bus cycles when turning the bus around between reads
and writes, or writes and reads. Mitsubishi's SRAMs are
fabricated with high performance, low power CMOS technology,
providing greater reliability. M5M5Y5672TG operates on a single
1.8V power supply and are 1.8V CMOS compatible.
FEATURES
• Fully registered inputs and outputs for pipelined operation
• Fast clock speed: 250, 225, and 200 MHz
• Fast access time: 2.6, 2.8, 3.2 ns
• Single 1.8V +150/-100mV power supply VDD
• Separate VDDQ for 1.8V I/O
• Individual byte write (BWa# - BWh#) controls may be tied
LOW
• Single Read/Write control pin (W#)
• Echo Clock outputs track data output drivers
• ZQ mode pin for user-selectable output drive strength
• 2 User programmable chip enable inputs for easy depth
expansion
• Linear or Interleaved Burst Modes
• JTAG boundary scan support
APPLICATION
Synchronous circuitry allows for precise cycle control triggered
by a positive edge clock transition.
Synchronous signals include : all Addresses, all Data Inputs,
all Chip Enables (E1#, E2, E3), Address Advance/Load (ADV),
Byte Write Enables (BWa#, BWb#, BWc#, BWd#, BWe#, BWf#,
BWg#, BWh#), Echo Clock outputs (CQ1, CQ1#, CQ2, CQ2#)
and Read/Write (W#). Write operations are controlled by the
eight Byte Write Enables (BWa# - BWh#) and Read/Write(W#)
inputs. All writes are conducted with on-chip synchronous
self-timed write circuitry.
The Echo Clocks are delayed copies of the RAM clock, CLK.
Echo Clocks are designed to track changes in output driver
delays due to variance in die temperature and supply voltage.
The ZQ pin supplied with selectable impedance drivers, allows
selection between nominal drive strength (ZQ LOW) for
multi-drop bus application and low drive strength (ZQ floating or
HIGH) point-to-point applications.
The sense of two User-Programmable Chip Enable inputs (E2,
E3), whether they function as active LOW or active HIGH inputs,
is determined by the state of the programming inputs, EP2 and
EP3.
The Linear Burst order (LBO#) is DC operated pin. LBO# pin
will allow the choice of either an interleaved burst, or a linear
burst.
All read, write and deselect cycles are initiated by the ADV
Low input. Subsequent burst address can be internally
generated as controlled by the ADV HIGH input.
High-end networking products that require high bandwidth, such
as switches and routers.
FUNCTION
PACKAGE
M5M5Y5672TG
Bump
Body Size
Bump Pitch
209(11X19) bump BGA
14mm X 22mm
1mm
PART NAME TABLE
Part Name
Frequency
Access
Cycle
Active Current
(max.)
Standby Current
(max.)
M5M5Y5672TG -25
250MHz
2.6ns
4.0ns
550mA
20mA
M5M5Y5672TG -22
225MHz
2.8ns
4.4ns
500mA
20mA
M5M5Y5672TG -20
200MHz
3.2ns
5.0ns
450mA
20mA
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18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
BUMP LAYOUT(TOP VIEW)
209 bump BGA
1
2
3
4
5
6
7
8
9
10
11
A
DQg
DQg
A6
E2
A7
ADV
A8
E3
A9
DQb
DQb
B
DQg
DQg
BWc#
BWg#
NC
W#
A17
BWb#
BWf#
DQb
DQb
C
DQg
DQg
BWh#
BWd#
NC
E1#
NC
BWe#
BWa#
DQb
DQb
D
DQg
DQg
VSS
NC
NC
MCL
NC
NC
VSS
DQb
DQb
E
DQPg
DQPc
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
DQPf
DQPb
F
DQc
DQc
VSS
VSS
VSS
ZQ
VSS
VSS
VSS
DQf
DQf
G
DQc
DQc
VDDQ
VDDQ
VDD
EP2
VDD
VDDQ
VDDQ
DQf
DQf
H
DQc
DQc
VSS
VSS
VSS
EP3
VSS
VSS
VSS
DQf
DQf
J
DQc
DQc
VDDQ
VDDQ
VDD
MCH
VDD
VDDQ
VDDQ
DQf
DQf
K
CQ2
CQ2#
CLK
NC
VSS
MCL
VSS
NC
NC
CQ1#
CQ1
L
DQh
DQh
VDDQ
VDDQ
VDD
MCH
VDD
VDDQ
VDDQ
DQa
DQa
M
DQh
DQh
VSS
VSS
VSS
MCL
VSS
VSS
VSS
DQa
DQa
N
DQh
DQh
VDDQ
VDDQ
VDD
MCH
VDD
VDDQ
VDDQ
DQa
DQa
P
DQh
DQh
VSS
VSS
VSS
MCL
VSS
VSS
VSS
DQa
DQa
R
DQPd
DQPh
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
DQPa
DQPe
T
DQd
DQd
VSS
NC
NC
LBO#
NC
NC
VSS
DQe
DQe
U
DQd
DQd
NC
A3
NC
A15
NC
A11
NC
DQe
DQe
V
DQd
DQd
A5
A4
A16
A1
A13
A12
A10
DQe
DQe
W
DQd
DQd
TMS
TDI
A2
A0
A14
TDO
TCK
DQe
DQe
Note1. MCH means “Must Connect High”. MCH should be connected to HIGH.
Note2. MCL means “Must Connect Low”. MCL should be connected to LOW.
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18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
BLOCK DIAGRAM
VDD
A0
A1
A2~17
VDDQ
18
18
16
ADDRESS
REGISTER
A1
A1'
D1
LINEAR/
Q1
D0
INTERLEAVED
BURST
COUNTER
Q0
A0
LBO#
A0'
18
CLK
WRITE ADDRESS
REGISTER1
WRITE ADDRESS
REGISTER2
18
WRITE
DRIVERS
72
E1#
E2
E3
INPUT
REGISTER1
INPUT
REGISTER0
ECHO CLOCK
OUTPUT REGISTERS
W#
MEMORY
ARRAY
READ
LOGIC
CHIP ENABLE
CONTROL
LOGIC
EP2
EP3
OUTPUT BUFFERS
BYTE a
|
BYTE h
ECHO CLOCK
OUTPUT BUFFERS
128Kx72
WRITE REGISTRY
AND
DATA COHERENCY
CONTROL LOGIC
OUTPUT SELECT
BWa#
BWb#
BWc#
BWd#
BWe#
BWf#
BWg#
BWh#
OUTPUT REGISTERS
ADV
DQa
DQPa
DQb
DQPb
DQc
DQPc
DQd
DQPd
DQe
DQPe
DQf
DQPf
DQg
DQPg
DQh
DQPh
CQ1
CQ1#
CQ2
CQ2#
ZQ
VSS
Note3. The BLOCK DIAGRAM does not include the Boundary Scan logic. See Boundary Scan chapter.
Note4. The BLOCK DIAGRAM illustrates simplified device operation. See TRUTH TABLE, PIN FUNCTION
and timing diagrams for detailed information.
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18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
PIN FUNCTION
Pin
Name
A0~A17
Synchronous
Address
Inputs
BWa#, BWb#,
BWc#, BWd#,
Bwe#, BWf#,
BWg#, BWh#
Synchronous
Byte Write
Enables
CLK
Clock Input
E1#
Synchronous
Chip Enable
E2, E3
Synchronous
Chip Enable
EP2, EP3
Chip Enable
Program Pin
Synchronous
Address
Advance/Load
ADV
Function
These inputs are registered and must meet the setup and hold times around the rising edge of
CLK. A0 and A1 are the two least significant bits (LSB) of the address field and set the internal
burst counter if burst is desired.
These active LOW inputs allow individual bytes to be written when a WRITE cycle is active and
must meet the setup and hold times around the rising edge of CLK. BYTE WRITEs need to be
asserted on the same cycle as the address. BWs are associated with addresses and apply to
subsequent data. BWa# controls DQa, DQPa pins; BWb# controls DQb, DQPb pins; BWc#
controls DQc, DQPc pins; BWd# controls DQd, DQPd pins; BWe# controls DQe, DQPe pins;
BWf# controls DQf, DQPf pins; BWg# controls DQg, DQPg pins; BWh# controls DQh, DQPh pins.
This signal registers the address, data, chip enables, byte write enables and burst control inputs
on its rising edge.
All synchronous inputs must meet setup and hold times around the clock's rising edge.
This active LOW input is used to enable the device and is sampled only when a new external
address is loaded (ADV is LOW).
These pins are user-programmable chip enable inputs. The sense of the inputs, whether they
function as active LOW or HIGH inputs, is determined by the state of the programming inputs,
EP2 and EP3.
These pins determine the sense of the user-programmable chip enable inputs, whether they
function as active LOW or active HIGH inputs.
When HIGH, this input is used to advance the internal burst counter, controlling burst access after
the external address is loaded. When HIGH, W# is ignored. A LOW on this pin permits a new
address to be loaded at CLK rising edge.
CQ1, CQ1#,
CQ2, CQ2#
Echo Clock
Outputs
The Echo Clocks are delayed copies of the main RAM clock, CLK.
ZQ
Output
Impedance
Control
This pin allows selection between RAM nominal drive strength (ZQ low) for multi-drop bus
applications and low drive strength (ZQ floating or high) point-to-point application.
W#
Synchronous
Read/Write
This active input determines the cycle type when ADV is LOW. This is the only means for
determining READs and WRITEs. READ cycles may not be converted into W RITEs (and vice
versa) other than by loading a new address. A LOW on the pin permits BYTE WRITE operations
and must meet the setup and hold times around the rising edge of CLK. Full bus width WRITEs
occur if all byte write enables are LOW.
DQa,DQPa,DQb,DQPb,
DQc,DQPc,DQd,DQPd,
DQe,DQPe,DQf,DQPf,
DQg,DQPg,DQh,DQPh
Synchronous
Data I/O
Byte “a” is DQa , DQPa pins; Byte “b” is DQb, DQPb pins; Byte “c” is DQc, DQPc pins; Byte “d” is
DQd,DQPd pins; Byte “e” is DQe, DQPe pins; Byte “f” is DQf, DQPf pins; Byte “g” is DQg, DQPg
pins; Byte “h” is DQh, DQPh pins. Input data must meet setup and hold times around CLK rising
edge.
Burst Mode
Control
This DC operated pin allows the choice of either an interleaved burst or a linear burst. If this pin is
HIGH or NC, an interleaved burst occurs. When this pin is LOW, a linear burst occurs, and input
leak current to this pin.
VDD
VDD
Core Power Supply
VSS
VSS
Ground
VDDQ
I/O buffer Power supply
LBO#
VDDQ
TDI
Test Data Input
TDO
Test Data Output
TCK
Test Clock
TMS
Test Mode Select
MCH
Must Connect High
These pins should be connected to HIGH
MCL
Must Connect Low
These pins should be connected to LOW
No Connect
These pins are not internally connected and may be connected to ground.
NC
These pins are used for Boundary Scan Test.
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18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
Read Operation
Pipelined Read
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1#, E2 and
E3) are active, the write enable input signal (W#) is deasserted high, and ADV is asserted low. The address presented to the address
inputs is latched into the address register and presented to the memory core and control logic. The control logic determines that a read
access is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge of clock the
read data is allowed to propagate through the output register and onto the output pins.
CLK
E1#
ADV
W#
BWx#
ADD
A
B
C
Q(A)
DQ
D
Q(B)
E
Q(C)
CQ
Read A
Deselect
Read B
Read C
Read D
Read E
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18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
Write Operation
Double Late Write
Write operation occurs when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1#, E2 and E3)
are active and the write enable input signal (W#) is asserted low.
Double Late Write means that Data In is required on the third rising edge of clock. It is designed to eliminate dead bus cycles when
turning the bus around between reads and writes, or writes and reads.
CLK
E1#
ADV
W#
BWx#
ADD
A
B
C
D
Q(A)
DQ
D(B)
E
Q(C)
F
D(D)
CQ
Read A
Write B
Read C
Write D
Read E
Read F
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18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
Special Function
Burst Cycles
The SRAM provides an on-chip burst address generator that can be utilized, if desired, to further simplify burst read or write
implementations. The ADV control pin, when driven high, commands the SRAM to advance the internal address counter and use the
counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the
SRAM by driving the ADV pin low, into Load mode.
Burst Read
CLK
E1#
ADV
W#
BWx#
ADD
A
B
Q(A)
DQ
Q(A+1)
Q(A+2)
Q(A+3)
CQ
Read A
Burst Read
A+1
Burst Read
A+2
Burst Read
A+3
Read B
Burst Read
B+1
Burst Write
CLK
E1#
ADV
W#
BWx#
ADD
A
B
DQ
D(A)
D(A+1)
D(A+2)
Burst Write
A+2
Burst Write
A+3
Burst Write
A
D(A+3)
CQ
Write A
Burst Write
A+1
Write B
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18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
DC OPERATED TRUTH TABLE
Name
LBO#
Input Status
HIGH or NC
Operation
Interleaved Burst Sequence
LOW
Linear Burst Sequence
Note5. LBO# is DC operated pin.
Note6. NC means No Connection.
Note7. See BURST SEQUENCE TABLE about interleaved and Linear Burst Sequence.
BURST SEQUENCE TABLE
(1) Interleaved Burst Sequence (when LBO# = HIGH or NC)
Operation
A17~A2
A1,A0
First access, latch external address
A17~A2
0,0
0,1
1,0
1,1
Second access(first burst address)
latched A17~A2
0,1
0,0
1,1
1,0
0,0
0,1
0,1
0,0
Third access(second burst address)
latched A17~A2
1,0
1,1
Fourth access(third burst address)
latched A17~A2
1,1
1,0
1,0
1,1
(2) Linear Burst Sequence (when LBO# = LOW)
Operation
A17~A2
A1,A0
First access, latch external address
A17~A2
0,0
0,1
Second access(first burst address)
latched A17~A2
0,1
1,0
1,1
0,0
Third access(second burst address)
latched A17~A2
1,0
1,1
0,0
0,1
1,1
0,0
0,1
1,0
Fourth access(third burst address)
latched A17~A2
Note8. The burst sequence wraps around to its initial state upon completion.
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18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
Echo Clock
The SRAM features Echo Clocks, CQ1,CQ2, CQ1#, and CQ2# that track the performance of the output drivers. The Echo Clocks are
delayed copies of the main RAM clock, CLK. Echo Clocks are designed to track changes in output driver delays due to variance in
die temperature and supply voltage. The Echo Clocks are designed to fire with the rest of the data output drivers. The SRAM
provide both in-phase, or true, Echo Clock outputs (CQ1 and CQ2) and inverted Echo Clock outputs (CQ1# and CQ2#).
It should be noted that deselection of the SRAM via E2 and E3 also deselects the Echo Clock output drivers. The deselection of
Echo Clock drivers is always pipelined to the same degree as output data. Deselection of the SRAM via E1# does not deactivate the
Echo Clocks.
Programmable Enable
The SRAM features two user programmable chip enable inputs, E2 and E3. The sense of the inputs, whether they function as active
low or active high inputs, is determined by the state of the programming inputs, EP2 and EP3. For example, if EP2 is held at HIGH, E2
functions as an active high enable. If EP2 is held to LOW, E2 functions as an active low chip enable input.
Programmability of E2 and E3 allows for banks of depth expansion to be accomplished with no additional logic. By programming the
enable inputs of four SRAMs in binary sequence (00,01,10,11) and driving the enable inputs with two address inputs, four SRAMs can
be made to look like one larger SRAM to the system.
Example Four Bank Depth Schematic
A0~A19
7 E1#
CK
W#
DQa~DQh
A0~A17
A18
A19
Bank0
A
E3#
E2#
E1#
CK
W#
DQ
CQ
Bank1
A0~A17
A18
A19
A
E3
E2#
E1#
CK
W#
DQ
CQ
Bank2
A0~A17
A18
A19
A
E3#
E2
E1#
CK
W#
DQ
CQ
Bank3
A0~A17
A18
A19
A
E3
E2
E1#
CK
W#
DQ
CQ
CQ
Bank Enable Truth Table
EP2
EP3
E2
E3
Bank0
LOW
LOW
Active Low
Active Low
Bank1
LOW
HIGH
Active Low
Active High
Bank2
HIGH
LOW
Active High
Active Low
Bank3
HIGH
HIGH
Active High
Active High
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Echo Clock Control in Two Banks
CLK
ADD
A
B
C
D
E
F
E1#
E2# Bank1
E2 Bank2
DQ
Bank1
Q(A)
Q(C)
CQ
Bank1
CQ Bank1
+ CQ Bank2
CQ
Bank2
DQ
Bank2
Q(B)
Q(D)
Note9. E1# does not deselect the Echo Clock Outputs. Echo Clock outputs are synchronously
deselected by E2 or E3 being sampled false.
It should be noted that deselection of the SRAM via E2 and E3 also deselects the Echo Clock output drivers. The deselection of
Echo Clock drivers is always pipelined to the same degree as output data. Deselection of the SRAM via E1# does not deactivate the
Echo Clocks.
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Pipelined Read Bank Switch with E1# Deselect
CLK
ADD
A
B
C
D
E
E1#
E2# Bank1
E2 Bank2
DQ
Bank1
Q(A)
CQ
Bank1
CQ Bank1
+ CQ Bank2
CQ
Bank2
DQ
Bank2
Q(B)
Q(C)
Note10. E1# does not deselect the Echo Clock Outputs. Echo Clock outputs are synchronously
deselected by E2 or E3 being sampled false.
In some applications it may be appropriate to pause between banks; to deselect both SRAMs with E1# before resuming read
operations. An E1# deselect at a bank switch will allow at least one clock to be issued from the new bank before the first read cycle
in the bank. Although the following drawing illustrates a E1# read pause upon switching from Bank 1 to Bank 2, a write to Bank 2
would have the same effect, causing the SRAM in Bank 2 to issue at least one clock before it is needed.
Output Driver Impedance Control
The ZQ pin of SRAMs supplied with selectable impedance drivers, allows selection between SRAM nominal drive strength
(ZQ low) for multi-drop bus applications and low drive strength (ZQ floating or high) point-to-point applications.
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TRUTH TABLE
CLK
E1#
(tn)
E
(tn)
ADV
(tn)
W#
(tn)
BW#
(tn)
Previous
Operation
Current
Operation
DQ/CQ
(tn)
DQ/CQ
(tn+1)
DQ/CQ
(tn+2)
L->H
X
F
L
X
X
X
Bank Deselect
***
High-Z
---
L->H
X
X
H
X
X
Bank Deselect
Bank Deselect (Continue)
High-Z
High-Z
---
L->H
H
T
L
X
X
X
Deselect
***
High-Z / CQ
---
L->H
X
X
H
X
X
Deselect
Deselect (Continue)
High-Z / CQ
High-Z / CQ
---
L->H
L
T
L
L
T
X
***
***
Dn / CQ
(tn)
L->H
L
T
L
L
F
X
***
***
High-Z / CQ
L->H
X
X
H
X
T
Write
***
Dn-1 / CQ
(tn-1)
Dn / CQ
(tn)
L->H
X
X
H
X
F
Write
***
Dn-1 / CQ
(tn-1)
High-Z / CQ
L->H
L
T
L
H
X
X
L->H
X
X
H
X
X
Write
Loads new address
Stores DQx if BWx#=LOW
Write (Abort)
Loads new address
No data stored
Write Continue
Increments address by 1
Stores DQx if BWx#=LOW
Write Continue (Abort)
Increments address by 1
No data stored
Read
Loads new address
Read Continue
Increments address by 1
Read
***
Qn-1 / CQ
(tn-1)
Qn / CQ
(tn)
Qn / CQ
(tn)
-----
Note11. If E2=EP2 and E3=EP3 then E=”T” else E=”F”.
Note12. If one or more BWx#=LOW then BW#=”T” else BW#=”F”.
Note13. “H” = input “HIGH”; “L” = input “LOW”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
Note14. “ *** “ = indicates that the DQ input requirement / output state and CQ output state are determined by the previous operation.
Note15. “ --- “ = indicates that the DQ input requirement / output state and CQ output state are determined by the next operation.
Note16. DQs are tri-stated in response to Bank Deselect, Deselect and Write commands, one full cycle after the command is sampled.
Note17. CQs are tri-stated in response to Bank Deselect commands only, one full cycle after the command is sampled.
Note18. Up to three (3) Continue operations may be initiated after a Read or Write operation is initiated to burst transfer up to four (4)
distinct pieces of data per single external address input. If a fourth (4) Continue operation is initiated, the internal address
wraps back to the initial external (base) address.
WRITE TRUTH TABLE
BWb#
BWc#
BWd#
BWe#
BWf#
BWg#
Function
W#
BWa#
BWh#
H
X
X
X
X
X
X
X
X
Read
L
L
H
H
H
H
H
H
H
Write Byte “a”
L
H
L
H
H
H
H
H
H
Write Byte “b”
L
H
H
L
H
H
H
H
H
Write Byte “c”
L
H
H
H
L
H
H
H
H
Write Byte “d”
L
H
H
H
H
L
H
H
H
Write Byte “e”
L
H
H
H
H
H
L
H
H
Write Byte “f”
L
H
H
H
H
H
H
L
H
Write Byte “g”
L
H
H
H
H
H
H
H
L
Write Byte “h”
L
L
L
L
L
L
L
L
L
Write All Bytes
L
H
H
H
H
H
H
H
H
Write Abort / NOP
Note19. X means "don't care". H means logic HIGH. L means logic LOW.
Note20. All inputs must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
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STATE DIAGRAM
X, F, L, X or X, X, H, X
L, T, L, H
Bank
Deselect
L, T, L, L
H, T, L, X
X, F, L, X
Deselect
L, T, L, H
L, T, L, L
H, T, L, X or X, X, H, X
H, T, L, X
H, T, L, X
L, T, L, L
Read
Write
X, F, L, X
L, T, L, H
L, T, L, H
X, F, L, X
X, X, H, X
X, X, H, X
L, T, L, H
H, T, L, X
Write
Continue
X, F, L, X
L, T, L, L
L, T, L, L
L, T, L, L
L, T, L, H
H, T, L, X
Write
Continue
X, X, H, X
X, F, L, X
X, X, H, X
Key
n
Input Command Code
n+1
n+2
n+3
Clock
f
Transition
f
Command
Current State (n)
Next State (n+1)
Current State
f
f
f
Next State
Current State & Next State Definition for Read/Write Control State Diagram
Note21. The notation “X, X, X, X” controlling the state transitions above indicate the states of inputs E1#, E, ADV, and W# respectively.
Note22. If (E2=EP2 and E3=EP3) then E=”T” else E=”F”.
Note23. “H” = input “HIGH”; “L” = input “LOW”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
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ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Conditions
Ratings
Unit
VDD
Power Supply Voltage
-0.5*~2.5
V
VDDQ
I/O Buffer Power Supply Voltage
-0.5*~2.5
V
VI
Input Voltage
-0.5~VDDQ+0.5(≤2.5V max.) **
V
VO
Output Voltage
PD
Maximum Power Dissipation (VDD)
TOPR
Operating Temperature
TSTG(bias)
Storage Temperature(bias)
With respect to VSS
-0.5~VDDQ+0.5(≤2.5V max.) **
V
1072.5
mW
0~70
°C
-10~85
°C
TSTG
Storage Temperature
-65~150
Note24. * This is -1.0V~3.6V when pulse width≤2ns, and -0.5V~2.5V in case of DC.
** This is -1.0V~VDDQ+1.0V(≤3.6V max.) when pulse width≤2ns, and –0.5V~VDDQ+0.5V in case of DC.
°C
DC ELECTRICAL CHARACTERISTICS
(1) Power Supplies
Symbol
Parameter
Condition
Limits
Min
Max
Unit
VDD
Power Supply Voltage
1.70
1.95
V
VDDQ
I/O Buffer Power Supply Voltage
1.70
1.95
V
(2) CMOS I/O DC Input Characteristics
Symbol
VIH
Parameter
Condition
High-level Input Voltage
Limits
Min
Max
0.65*VDDQ
VIL
Low-level Input Voltage
-0.3*
Note25. *VIL min is –1.0V and VIH max is VDDQ+1.0V(max. 3.6V) in case of AC (Pulse width ≤ 2ns).
Unit
VDDQ+0.3
V
0.35*VDDQ
V
(3) Input and Output Leakage Characteristics
Symbol
Parameter
Input Leakage Current
IIL
IOL
Condition
Limits
Min
Max
Unit
VI = 0V~VDDQ
10
µA
Input Leakage Current of
EP2, EP3, LBO#, ZQ, MCH, MCL pins
VI = 0V~VDDQ
10
µA
Output Leakage Current
VI/O = 0V~VDDQ
10
µA
(except EP2, EP3, LBO#, ZQ, MCH, MCL pins)
(4) Selectable Impedance Output Driver DC Electrical Characteristics
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Symbol
Parameter
Limits
Condition
VOHL
Low Drive Output High Voltage
IOHL = -4mA
VOLL
Low Drive Output Low Voltage
IOLL = 4mA
VOHH
High Drive Output High Voltage
IOHH = -8mA
Min
Max
Unit
VDDQ-0.4V
V
0.4
V
VDDQ-0.4V
V
VOLH
High Drive Output Low Voltage
IOLH = 8mA
Note26. ZQ=H; High Impedance output driver setting
Note27. ZQ=L; Low Impedance output driver setting
0.4
V
(5) Operating Currents
Symbol
ICC1
ICC2
ICC3
Parameter
Limits
Condition
Min
Max
Device selected;
Output open
All other inputs
VI≤VIL or VI≥VIH
4.0ns cycle (250MHz)
550
Power Supply Current
: Operating
4.4ns cycle (225MHz)
500
5.0ns cycle (200MHz)
450
Power Supply Current
:Chip Disable
and Bank Deselect
E1#≥VIH or (E2 or E3 False)
Output open
All other inputs
VI≤VIL or VI≥VIH
4.0ns cycle (250MHz)
140
CMOS Standby Current
(CLK stopped standby mode)
4.4ns cycle (225MHz)
110
5.0ns cycle (200MHz)
100
Device deselected; Output open CLK frequency=0Hz
All inputs V I≤VSS+0.1V or VI≥VDDQ-0.1V
20
Unit
mA
mA
mA
CAPACITANCE
Symbol
CI
Parameter
Input Capacitance
CO
Input / Output (DQ) Capacitance
Note28. This parameter is sampled.
Condition
Limits
Min
Typ
Max
Unit
VI=GND, V I=25mVrms, f=1MHz
6
pF
VO=GND, VO=25mVrms, f=1MHz
8
pF
THERMAL RESISTANCE
Symbol
Parameter
Condition
Limits
Min
Typ
Max
Unit
θJA
Thermal resistance Junction Ambient
TBD
TBD
pF
θJC
Thermal resistance Junction to Case
TBD
TBD
pF
AC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, VDD=1.70~1.95V, unless otherwise noted)
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(1) MEASUREMENT CONDITION
Input pulse levels · ······································· VIH=VDDQ, VIL=0V
Input rise and fall times · ······························ faster than or equal to 1V/ns
Input timing reference levels · ······················ VIH=VIL=VDDQ / 2
Output reference levels · ······························ VIH=VIL=VDDQ / 2
Output load · ················································· Fig.1
30pF
(Including wiring and JIG)
Q
ZO=50Ω
50Ω
VT =VDDQ / 2
Fig.1 Output load
Input
Waveform
VDDQ / 2
toff
tplh
Output
Waveform
Input
Waveform
VDDQ / 2
VDDQ / 2
tphl
Vh
Output
Waveform
(toff)
Vl
ton
Vh-(0.2(Vh-Vz)) Vz+(0.2(Vh-Vz))
Vz
0.2(Vz-Vl)
Vz-(0.2(Vz-Vl))
(ton)
Fig.3 Tri-State measurement
Fig.2 Tdly measurement
Note29.Valid Delay Measurement is made from the VDDQ/2 on the input waveform to the VDDQ/2 on the output waveform.
Input waveform should have a slew rate of faster than or equal to 1V/ns.
Note30.Tri-state toff measurement is made from the VDDQ/2 on the input waveform to the output waveform moving 20%
from its initial to final Value VDDQ/2.
Note:the initial value is not VOL or VOH as specified in DC ELECTRICAL CHARACTERISTICS table.
Note31. Tri-state ton measurement is made from the VDDQ/2 on the input waveform to the output waveform moving 20%
from its initial Value VDDQ/2 to its final Value.
Note:the final value is not VOL or VOH as specified in DC ELECTRICAL CHARACTERISTICS table.
Note32.Clocks,Data,Address and control signals will be tested with a minimum input slew rate of faster than or equal to 1V/ns.
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(2)TIMING CHARACTERISTICS
Symbol
Parameter
Clock
tKHKH
Clock Cycle Time
tKHKL
Clock HIGH Time
tKLKH
Clock LOW Time
Output times
tKHQV
Clock HIGH to Output Valid
tKHQX
Clock HIGH to Output Invalid
tKHQX1 Clock HIGH to Output in Low-Z
tKHQZ
Clock HIGH to Output in High-Z
tCHCL
Echo Clock HIGH Time
tCLCH
Echo Clock LOW Time
tKHCH
Clock HIGH to Echo Clock HIGH
tKLCL
Clock LOW to Echo Clock LOW
tKHCX1 Clock HIGH to Echo Clock Low-Z
tKHCZ
Clock HIGH to Echo Clock High-Z
tCHQV
Echo Clock HIGH to Output Valid
tCHQX
Output Invalid to Echo Clock HIGH
Setup Times
tAVKH
Address Valid to Clock HIGH
tadvVKH ADV Valid to Clock HIGH
tWVKH
Write Valid to Clock HIGH
tBxVKH Byte Write Valid to Clock HIGH (BWa#~BWh#)
tEVKH
Enable Valid to Clock HIGH (E1#,E2,E3)
tDVKH
Data In Valid Clock HIGH
Hold Times
tKHAX
Clock HIGH to Address don’t care
tKHadvX Clock HIGH to ADV don’t care
tKHWX Clock HIGH to Write don’t care
tKHBxX Clock HIGH to Byte Write don’t care (BWa#~BWh#)
tKHEX
Clock HIGH to Enable don’t care (E1#,E2,E3)
tKHDX
Clock HIGH to Data In don’t care
250MHz
-25
Min
Max
Limits
225MHz
-22
Min
Max
200MHz
-20
Min
Max
4.0
1.5
1.5
4.4
1.6
1.6
5.0
1.8
1.8
2.6
0.5
0.5
0.5
1.25
1.25
0.5
0.5
0.5
0.5
2.6
2.5
2.5
2.5
0.5
-0.5
0.8
0.8
0.8
0.8
0.8
0.8
2.8
0.6
0.6
0.6
1.35
1.35
0.5
0.5
0.5
0.5
2.8
2.7
2.7
2.7
0.5
-0.5
1.0
1.0
1.0
1.0
1.0
1.0
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
Note33. Test conditions is specified with the output loading shown in Fig.1 unless otherwise noted.
Note34. tKHQX1, tKHQZ, tKHCX1, tKHCZ are sampled.
Note35. LBO#, EP2, EP3, ZQ is static and must not change during normal operation.
ns
ns
ns
3.2
0.7
0.7
0.7
1.55
1.55
0.5
0.5
0.5
0.5
Unit
3.2
3.1
3.1
3.1
0.5
-0.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.2
1.2
1.2
1.2
1.2
1.2
ns
ns
ns
ns
ns
ns
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
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Timing Parameter Key
tKHKH
CLK
tKHAX
tKHKL
tKLKH
tAVKH
ADD
C
D
E
tKHQV
tKHQZ
tKHQX1
tKHQX
DQ
QB
tCHQV
tKHCH
tCHQX
tKLCL
tKHCZ
CQ
tKHCX1
tCLCH
tCHCL
=CQ High-Z
tKHKH
CLK
tKHAX
tKHKL
tKLKH
tAVKH
ADD
A
B
C
tnVKH
tKHnX
E1#, E2, E3
W#, BWx#,
ADV
tDVKH
tKHDX
DQ
QA
Note36. tnVKH=tEVKH, tWVKH, tBxVKH, tadvVKH, etc. and tKHnX=tKHEX, tKHWX, tKHBxX, tKHadvX, etc.
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JTAG PORT OPERATION
Overview
The JTAG Port on this SRAM operates in a manner consistent with IEEE Standard 1149.1-1990, a serial boundary scan interface
standard (commonly referred to as JTAG), but dose not implement all of the function required for 1149.1 compliance. Unlike JTAG
implementations that have been common among SRAM vendors for the last several years, this implementation dose offer a form of
EXTEST, known as Clock Assisted EXTEST, reducing or eliminating the "hand coding" that has been required to overcome the test
program compiler errors caused by previous non-compliant implementation. The JTAG Port interfaces with conventional CMOS logic
level signaling.
Disabling the JTAG port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. To
assure normal operation of the SRAM with the JTAG Port unused, the TCK, TDI and TMS pins may be left floating or tied to High. The
TDO pin should be left unconnected.
JTAG Pin Description
Test Clock (TCK)
The TCK input is clock for all TAP events. All inputs are captured on the rising edge of TCK and the Test Data Out (TDO) propagates
from the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP Controller state machine. An undriven
TMS input will produce the same result as a logic one input level.
Test Data In (TDI)
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between the TDI and TDO pins.
the register placed between the TDI and TDO pins is determined by the state of the TAP Controller state machine and the instruction
that is currently loaded in the TAP Instruction Resister (refer to the TAP Controller State Diagram). An undriven TDI Input will produce
the same result as a logic one input level.
Test Data Out (TDO)
The TDO output is active depending on the state of the TAP Controller state machine. Output changes in response to the falling edge
of TCK. This is the output side of the serial registers placed between the TDI and TDO pins.
Note:
This device dose not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS
is held high for five rising edges of TCK. The TAP Controller is also reset automatically at power-up.
JTAG Port Registers
Overview
The various JTAG registers, referred to as Test Access Port or TAP Registers, are selected (one at a time) via the sequence of 1s and
0s applied to TMS as TCK is strobed. Each of TAP Registers are serial shift registers that capture serial input data on the rising edge of
TCK and push serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP Controller when it is moved into the Run-Test/Idle, or the
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various data register states. Instructions are 3 bits long. The Instruction Resister can be loaded when it is placed between the TDI and
TDO pins. The Instruction Resister is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is
placed in the Test-Logic-Reset state.
Bypass Register
The Bypass resister is a single-bit register that can be placed between the TDI and TDO pins. It allows serial test data to be passed
through the SRAM's JTAG Port to another device in the scan chain with as little delay as possible.
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the SRAM's input or I/O pins. The
flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port's TDO pins. The Boundary
Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and
the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control
of the TAP Controller, is loaded with the contents of the SRAM's I/O ring when the controller is in the Capture-RD state and then is
placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and
EXTEST instruction can be used to activate the Boundary Scan Register.
Identification (ID) Register
The ID register is a 32-bit register that is loaded with a device and vender specific 32-bit code when the controllers put in the
Capture-DR state with the IDCODE Instruction loaded in the Instruction Register. The code is loaded from 32-bit on-chip ROM. It
describes various attributes of the SRAM (see page 25). The register is then placed between the TDI and TDO pins when the controller
is moved into the Shift-DR state. Bit 0 in the register is the LSB and the first to reach the TDO pin when shifting begins.
TAP Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; standard (Public) instructions, and device specific (Private)
instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in
prescribed ways. Although the TAP Controller in this device follows the 1149.1 conventions, it is not 1194.1-compliant because one of
the mandatory instructions, EXTEST, is uniquely implemented. The TAP on this device may be used to monitor all input and I/O pads.
This device will not perform INTEST but can perform the preload portion of the SAMPLE/PRELOAD command.
When the TAP controller is placed in the Capture-IR state, the two least significant bits of the instruction register are loaded with 01.
When the TAP controller is moved to the Shift-IR state, the Instruction Register is placed between the TDI and TDO pins. In this state
the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at the TDO output). For all
instructions, the TAP executes newly loaded instructions only when the controller is moved to the Update-IR state. The TAP Instruction
Set for this device is listed in the following table.
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register, the Bypass Register is placed between the TDI and TDO pins. This
occurs when the TAP Controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate
testing of other devices in the scan path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard1149.1 mandatory public instruction. When the SAMPLE/PRELOAD instruction is loaded in the
Instruction Register, moving the TAP Controller into the Capture-DR state loads the data in the SRAM's input and I/O buffers into the
Boundary Scan Register. Some Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the
default state identified in the BSDL file. Because the SRAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to
attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to
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sample metastable inputs will not harm the device, repeatable results cannot be expected. SRAM input signals must be stabilized for
long enough to meet the TAP's input data capture set-up plus hold time (tTS plus tTH). The SRAM's clock inputs need not be paused
for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to the
Shift-DR state then places the Boundary Scan Register between the TDI and TDO pins.
EXTEST-A
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the Instruction Register is loaded with all logic
0s. The EXTEST command dose not block or override the SRAM's input pins; therefore, the SRAM's internal state is still determined by
its input pins.
Typically, the Boundary Scan Register is loaded with the desired pattern with the SAMPLE/PRELOAD command. Then the EXTEST
command is used to output the Boundary Scan Register's contents, in parallel, on the SRAM's data output drivers on the falling edge of
TCK when the controller is in the Update-IR state.
Alternately, the Boundary Scan Register may loaded in parallel using the EXTEST command. When the EXTEST instruction is selected,
the state of all SRAM's input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are
transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the SRAM's output pins
drive out the value of the Boundary Scan Register location with which each output pin is associated.
The EXTEST implementation in this device dose not, without further user intervention, actually move the contents of the scan chain
onto the SRAM's output pins. Therefore this device is not strictly 1149.1-compliant. To push data from the Boundary Scan Registers, in
parallel, out onto the SRAM's I/O and output pins, the SRAM's main clock (CK) must be pulsed. A single CK transition is sufficient to
transfer the data, but more transitions will do no harm.
IDCODE
The IDCODE instruction cause the ID ROM to be loaded into the ID register when the controller is in the Capture-DR state and places
the ID Register between the TDI and TDO pins in the Shift-DR state. The IDCODE instruction is the default instruction loaded in at
power-up and any time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the Instruction Register, all SRAM outputs are forced to an inactive drive state (High-Z) and
the Boundary Scan Register is placed between the TDI and TDO pins when the TAP Controller is moved to the Shift-DR state.
RFU
These instructions are reserved for future use. Do not use these instructions.
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JTAG TAP BLOCK DIAGRAM
Bypass Register
0
Instruction Register
2 1 0
TDI
Identification Register
TDO
31 30 29 . . . . . . . . 2 1 0
Boundary Scan Register
.. .............. .. 2 1 0
TMS
TCK
Test Access Port (TAP) Controller
BOUNDARY SCAN ORDER
TBD
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JTAG TAP CONTROLLER STATE DIAGRAM
Test-Logic-Reset
1
0
Run-Test/Idle
1
Select-DR-Scan
0
1
Select-IR-Scan
0
1
0
1
Capture-DR
0
Capture-IR
0
Shift-DR
Shift-IR
0
1
1
0
1
1
Exit1-DR
Exit1-IR
0
0
Pause-DR
Pause-IR
0
1
Exit2-DR
0
0
1
Exit2-IR
1
0
1
Update-DR
1
1
Update-IR
0
1
0
TAP CONTROLLER DC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, VDD=1.70~1.95V, unless otherwise noted)
Symbol
Parameter
Condition
Limits
Unit
Min
Max
VIHT
Test Port Input High Voltage
0.65*VDDQ
VDDQ+0.3 **
V
VILT
Test Port Input Low Voltage
-0.3 **
0.35*VDDQ
V
VOHT
Test Port Output High Voltage
IOH=-100µA
VDDQ-0.1
V
VOLT
Test Port Output Low Voltage
IOL=+100µA
0.1
V
IINT
TMS, TCK and TDI Input Leakage Current
-10
10
µA
IOLT
TDO Output Leakage Current
Output Disable, VOUT=0V~VDDQ
-10
10
µA
Note37. **Input Undershoot/Overshoot voltage must be –1.0V<Vi<VDDQ+1V(max. 3.6V) with a pulse width not to exceed 20% tTCK.
23
MITSUBISHI
ELECTRIC
Advanced Information
M5M5Y5672TG REV.0.1
MITSUBISHI LSIs
M5M5Y5672TG – 25,22,20
18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
TAP CONTROLLER AC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, VDD=1.70~1.95V, unless otherwise noted)
(1)MEASUREMENT CONDITION
Input pulse levels · ······································· VIH=VDDQ, VIL=0V
Input rise and fall times · ······························ faster than or equal to 1V/ns
Input timing reference levels · ······················ VIH=VIL=VDDQ / 2
Output reference levels · ······························ VIH=VIL=VDDQ / 2
Output load · ················································· Fig.4
30pF
(Including wiring and JIG)
Q
ZO=50Ω
50Ω
VT =VDDQ / 2
Fig.4 Output load
(2)TIMING CHARACTERISTICS
Symbol
Limits
Min
Max
20
50
20
20
10
10
20
Parameter
tTF
tTKC
tTKH
tTKL
tTS
tTH
tTKQ
TCK Frequency
TCK Cycle Time
TCK High Pulse Width
TCK Low Pulse Width
TDI, TMS setup time
TDI, TMS hold time
TCK Low to TDO valid
Unit
MHz
ns
ns
ns
ns
ns
ns
(3) TIMING
tTKC
tTKH
tTKL
TCK
tTS tTH
TMS
tTS tTH
TDI
tTKQ
TDO
24
MITSUBISHI
ELECTRIC
Advanced Information
M5M5Y5672TG REV.0.1
MITSUBISHI LSIs
M5M5Y5672TG – 25,22,20
18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
JTAG TAP INSTRUCTION SET SUMMARY
Instruction
Code
EXTEST-A
000
IDCODE
001
SAMPLE-Z
010
RFU
SAMPLE/PRELOAD
RFU
RFU
BYPASS
011
100
101
110
111
Description
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
This SRAM implements an Clock Assisted EXTEST function. Not 1149.1 Compliant.
Preloads ID Register and places it between TDI and TDO
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
Forces all Data and Clock output drivers to High-Z
Do not use this instruction; Reserved for Future Use.
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
Do not use this instruction; Reserved for Future Use.
Do not use this instruction; Reserved for Future Use.
Places the BYPASS Register between TDI and TDO.
STRUCTURE OF IDENTIFICATION REGISTER
Revision
Bit No.
31
M5M5W5672
30
29
Device Information
Capacity
Function
VDD
28
27
26
0 0 0 0 0 1
25
24
23
22
21
20
0 0 1 0 1 0
19
18
17
Width
16
15
Gen.
14
1 0 0 1 0 1
MSB
13
12
JEDEC Vendor Code of MITSUBISHI
11
10
9
8
0 0 0 0 0 0
7
6
5
4
3
2
0 0 1 1 1 0
1
0
0 1
LSB
Note38. Bit of Device Information “Gen.(Generation)” means
Bit No.
st
1 Generation
nd
2 Generation
rd
3 Generation
13
0
0
1
12
0
1
0
Note39. Bit of Device Information ”Width” means
Bit No.
X16
X18
X32
X36
X64
X72
16
0
0
0
0
1
1
15
0
0
1
1
0
0
14
0
1
0
1
0
1
Note40. Bit of Device Information ”Function” means
Bit No.
Network SRAM
PB
20
0
0
19
1
0
18
0
0
17
0
1
Note41. Bit of Device Information ”Capacity” means
Bit No.
1M or 1.15M
2M or 2.3M
4M or 4.5M
8M or 9M
16M or 18M
32M or 36M
24
0
0
0
0
0
0
23
0
0
0
1
1
1
22
0
1
1
0
0
1
21
1
0
1
0
1
0
Note42. Bit of Device Information ”VDD” means
Bit No.
3.3V
2.5V
1.8V
1.5V
27
0
0
0
0
26
0
0
1
1
25
0
1
0
1
25
MITSUBISHI
ELECTRIC
Advanced Information
M5M5Y5672TG REV.0.1
MITSUBISHI LSIs
M5M5Y5672TG – 25,22,20
18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
PACKAGE OUTLINE
209(11x19) bump Ball Grid Array(BGA) Pin Pitch 1.0mm
Refer to JEDEC Standard MS-028, Variation BC,
which can be seen at:
http://www.jedec.org/download/search/MS-028C.pdf
26
MITSUBISHI
ELECTRIC
Advanced Information
M5M5Y5672TG REV.0.1
MITSUBISHI LSIs
M5M5Y5672TG – 25,22,20
18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM
REVISION HISTORY
• Apr/06/2001 REV.0.0
• May/16/2001 REV.0.1
First revision
Deleted VDDQ=2.5V
27
MITSUBISHI
ELECTRIC
Advanced Information
M5M5Y5672TG REV.0.1
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