IDT IDT70P3517S250RM 512k/256k x36 synchronous dual qdr-ii Datasheet

PRELIMINARY DATASHET
IDT70P3537
IDT70P3517
512K/256K x36
SYNCHRONOUS
DUAL QDR-IITM
®
Features
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18Mb Density (512K x 36)
– Also available 9Mb Density (256K x 36)
QDR-II x 36 Burst-of-2 Interface
– Commercial: 233MHz, 250MHz
Two independent ports
– True Dual-Port Access to common memory
Separate, Independent Read and Write Data Buses on each
Port
– Supports concurrent transactions
Two-Word Burst on all DPRAM accesses
DDR (Double Data Rate) Multiplexed Address Bus
– One Read and One Write request per clock cycle
DDR (Double Data Rate) Data Buses
– Four word burst data (Two Read and Two Write) per clock on
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each port
– Four word transfers each of Read & Write per clock cycle per
port (four word bursts on 2 ports)
Octal Data Rate
Port Enable pins (E0,E1) for depth expansion
Dual Echo Clock Output with DLL-based phase alignment
High Speed Transceiver Logic inputs
– scaled to receive signals from 1.4V to 1.9V
Scalable output drivers
– Drives HSTL, 1.8V TTL or any voltage level from 1.4V to 1.9V
– Output impedance adjustable from 35 ohms to 70 ohms
1.8V Core Voltage (VDD)
576-ball Flip Chip BGA (25mm x 25mm, 1.0mm ball pitch)
JTAG Interface - IEEE 1149.1 Compliant
Functional Block Diagram
VREFL
VREFR
EP[1:0]
ER[1:0]
A0L- A17L(2)
RL
WL
BW0 L - BW3 L
KL
LEFT PORT
ADDRESS
REGISTER
AND LOGIC
OR
CL, CL
KL, KL
OR
ADDRESS DECODE
CR, CR
KR, KR
D0 R - D3 5 R
KR
KR
KR
SELECT OUTPUT
KR
CR
RIGHT PORT
DATA
REGISTER
AND LOGIC
OUTPUT BUFFER
WRITE
REGISTER
KL
CL
OUTPUT REGISTER
MUX
CQL, CQL
512/256K x 36
MEMORY
ARRAY
SENSE AMPS
Q0 L - Q3 5 L
SENSE AMPS
OUTPUT BUFFER
ZQL (1)
MUX
KL
WRITE DRIVER
OUTPUT REGISTER
KL
KL
SELECT OUTPUT
D0 L - D3 5 L
LEFT PORT
DATA
REGISTER
AND LOGIC
WRITE
REGISTER
EL[1:0]
ZQR (1)
Q0 R - Q3 5 R
CQR, CQR
A0R- A17R(2)
RR
RIGHT PORT
ADDRESS
REGISTER
AND LOGIC
WR
BW0 R - BW3 R
KR
KR
KL
TDI
VREFL
JTAG
TDO
TCK
TMS
TRST
5677 drw01
VREFR
NOTES:
1. Input pin to adjust the device outputs to the system data bus impedance.
2. Address A17 is a INC for IDT70P3517. Disabled input pin (Diode tied to VDD and VSS).
July 16, 2007
©2007 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice. NOT AN OFFER FOR SALE The information
presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale
or an offer for sale that creates a contractual power of acceptance. "QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semicondor, IDT, and Micron Tecnology, Inc."
DSC-5677/1
Preliminary Datasheet
Commercial Temperatue Range
18/9Mb x36 IDT70P3537/70P3517
SYNCHRONOUS Dual QDR-IITM
Pin Configuration
70P3537
70P3517
RM-576 Ball Flip Chip BGA
Top View
A1 BALL PAD CORNER
1
2
3
4
VSS
5
6
7
8
9
10
11
12
13
14
15
16
17
18
VSS
ZQR
VSS
VSS
D17R
VSS
D16R
D15R VDDQR Q17R
VSS VDDQR
D14R
D13R
Q16R
D12R
D11R VDDQR Q13R
Q14R VDDQR VSS
VSS
D10R
VSS
Q11R
Q12R
VREFR
VSS
VDDQR
Q9R
Q10R VDDQR VSS
D9R
D8R
VSS
Q8R
CQR
D7R
D6R VDDQR
Q6R
Q7R VDDQR
D5R
D4R
Q4R
Q5R
D3R
D2R VDDQR
Q2R
Q3R VDDQR
D1R
D0R
Q0R
Q1R
D16L
D17L VDDQL
Q17L
Q16L VDDQL
D14L
D15L
Q15L
Q14L
D12L
D13L VDDQL
Q13L
Q12L VDDQL
D10L
D11L
VSS
Q11L
Q10L
VREFL
VSS
VDDQL
Q9L
CQL VDDQL
VSS
D9L
VSS
Q8L
Q7L
D7L
D8L
VDDQL
Q6L
Q5L
D5L
D6L
VSS
Q4L
Q3L
D3L
D4L
VDDQL
Q2L
Q1L VDDQL
D1L
D2L
VSS
Q0L
VSS
D0L
VDDQL
VSS
TDI
VSS
VSS
ZQL
VSS
TMS
1
2
3
4
5
19
20
21
22
23
24
VSS VDDQR A2R
A3R
RR
BW0R
E0R
VDD
VREFR
BW3R
A8R
A9R
A14R
A15R
VDDQR
VSS
VSS
VSS
EP0
A4R
A5R
BW1R
E1R
VSS
VDD
BW2R
WR
A12R
A13R
INC
VSS
VSS
A0R
A1R
A6R
A7R
KR
KR
CR
CR
A10R
A11R
A16R
A17R
VSS
VDDQR
VSS
VDDQR
VSS
VSS
VDDQR
VSS
VDDQR
VSS
VDDQR
VSS
Q34R
Q33R
VDDQR
VSS
VDD
VSS
VDD
VDD
VSS
VDD
VSS
VDDQR
VSS
VDDQR
Q32R
Q31R
VSS
VDD
VSS
VDD
VSS
VSS
VDD
VSS
VDD
VSS
VDDQR
VSS
Q30R
Q29R
VDDQR
VSS
VDD
VSS
VDD
VDD
VSS
VDD
VSS
VDDQR
VSS
VDDQR
Q28R
Q27R
VSS
D26R
VSS
VSS
VDD
VSS
VDD
VSS
VSS
VDD
VSS
VDD
VSS
VDDQR
VSS
CQR
Q26R
VDDQR
VSS
VREFR
VDDQR
VSS
VDD
VSS
VDD
VDD
VSS
VDD
VSS
VDDQR
VSS
VDDQR
Q25R
Q24R
VSS
D24R
D25R
VSS
VDD
VSS
VDD
VSS
VSS
VDD
VSS
VDD
VSS
VDDQR
VSS
Q23R
Q22R
VDDQR D22R
D23R
VSS
VDDQR
VSS
VDD
VSS
VDD
VDD
VSS
VDD
VSS
VDDQR
VSS
VDDQR
Q21R
Q20R
D20R
D21R
VDDQR
VSS
VDD
VSS
VDD
VSS
VSS
VDD
VSS
VDD
VSS
VDDQR
VSS
Q19R
Q18R
VDDQR D18R
D19R
VSS
VDDQL
VSS
VDD
VSS
VDD
VDD
VSS
VDD
VSS
VDDQL
VSS
VDDQL
Q34L
Q35L
D35L
D34L
VDDQL
VSS
VDD
VSS
VDD
VSS
VSS
VDD
VSS
VDD
VSS
VDDQL
VSS
Q32L
Q33L
VDDQL D33L
D32L
VSS
VDDQL
VSS
VDD
VSS
VDD
VDD
VSS
VDD
VSS
VDDQL
VSS
VDDQL
Q30L
Q31L
VDDQL
VSS
VDD
VSS
VDD
VSS
VSS
VDD
VSS
VDD
VSS
VDDQL
VSS
Q28L
Q29L
VSS
VDDQL
VSS
VDD
VSS
VDD
VDD
VSS
VDD
VSS
VDDQL
VSS
VDDQL
CQL
Q27L
VSS
D27L
D26L
VDDQL
VSS
VDD
VSS
VDD
VSS
VSS
VDD
VSS
VDD
VSS
VDDQL
VSS
Q25L
Q26L
VDDQL
VSS
VREFL
VDDQL
VSS
VDD
VSS
VDD
VDD
VSS
VDD
VSS
VDDQL
VSS
VDDQL
Q23L
Q24L
VSS
D25L
VSS
VDDQL
VSS
VDD
VSS
VDD
VSS
VSS
VDD
VSS
VDD
VSS
VDDQL
VSS
Q21L
Q22L
VSS
VDDQL
VSS
VDDQL VDDQL
VSS
VDDQL
VSS
VDDQL
Q19L
Q20L
A0L
A1L
A6L
A7L
VDDQL EP1
A4L
A5L
VSS
A2L
A3L
6
7
8
A
A
MRST DOFFR
B
B
VDDQR DEPTH
VSS
VSS
VDDQR D35R
VSS
C
C
VDDQR VDDQR
Q35R
VSS
D33R
D34R
VDDQR D31R
D32R
D
D
VSS
Q15R
VSS VDDQR
E
E
VSS
D29R
D30R
VDDQR D27R
D28R
F
F
VSS
VDDQR
G
G
H
H
VSS VDDQR
J
J
VSS
K
K
VSS
VSS VDDQR
L
L
VSS
M
M
VSS
VSS
N
N
VSS
P
P
VSS
VSS
R
R
VSS
D31L
D30L
VDDQL D29L
D28L
T
T
VSS
U
U
V
V
VSS
W
W
VDDQL VSS
Y
Y
VSS
VDDQL D24L
D23L
AA
AA
VDDQL VDDQL
VSS
VSS
KL
KL
CL
CL
A10L
A11L
A16L
A17L
VSS
VDDQL
BW1L
E1L
VDD
VSS
BW2L
WL
A12L
A13L
INC
VDDQL
RL
BW0L
E0L
VREFL
VDD
BW3L
A8L
A9L
A14L
A15L
9
10
11
12
13
14
15
16
17
18
AB
VDDQL VSS
VSS
D22L
D21L
Q18L
VDDQL D20L
D19L
VSS
VDDQL
DOFFL D18L
VSS
VSS
TRST
TCK
TDO
VSS
19
20
21
22
23
AB
AC
AC
AD
AD
VSS
24
5677 drw
NOTE:
1. The package is 25mm x 25mm x 2.55mm with 1.0mm ball pitch; the customer will have to provide external airflow of 100LFM (0.5m/s) or higher at 250MHz.
2
July 16, 2007
Preliminary Datasheet
Commercial Temperatue Range
18/9Mb x36 IDT70P3537/70P3517
SYNCHRONOUS Dual QDR-IITM
Functional Description
As a memory standard, the (Quad Data Rate) QDR-II SRAM
interface has become increasingly common in high performance
networking systems. With the QDR-II interface/configuration, memory
throughput is increased without increasing the clock rate via the use
of two unidirectional buses on each of providing 2 ports of QDR-II
makes this a Dual-QDRII Static Ram two ports to transfer data without
the need for bus turnaround.
Dual QDR-II Static RAMs are high speed synchronous memories supporting two independent double-data-rate (DDR) read and
write data ports. This scheme allows simultaneous read and write
access for the maximum device throughput - two data items are
passed with each read or write. Four data word transfers occur per
clock cycle, providing quad-data-rate (QDR) performance on each
port. Comparing this with standard SRAM common I/O single data
rate (SDR) devices, a four to one increase in data access is achieved
at equivalent clock speeds. IDT70P3537/70P3517 Dual QDR-II Static
RAM devices, are capable of sustaining full bandwidth on both the
input and output buses simultaneously. Using independent buses for
read and write data access simplifies design by eliminating the need
for bidirectional buses. And all data are in two word bursts, (with
addressing capability to the burst level).
Devices with QDR-II interfaces include network processor units
(NPUs) and field programmable gate arrays (FPGAs).
IDT70P3537/70P3517 Dual QDR-II Static RAMs support unidirectional 36-bit read and write interfaces. These data inputs and
outputs operate simultaneously, thus eliminating the need for highspeed bus turnarounds (i.e. no dead cycles are present). Access to
each port is accomplished using a common 18-bit address bus (17
bits for IDT70P3517). Addresses for reads and writes are latched on
rising edges of the K and K input clocks, respectively.The K and K
clocks are offset by 90 degrees or half a clock cycle. Each address
location is associated with two 36-bit data words that burst sequentially
into or out of the device. Since data can be transferred into and out
of the device on every rising edge of the K and K clocks, memory
bandwidth is maximized while simplifying overall design through the
elimination of bus turnaround(s). IDT70P3537/70P3517 Dual QDR-II
Static RAMs can support devices in a multi-drop configuration (i.e.
multiple devices connected to the same interface). Through this
capability, system designers can support compatible devices such as
NPUs and FPGAs on the same bus at the same time.
Using independent ports for read and write access simplifies
design by eliminating the need for bidirectional buses. All buses
associated with Dual QDR-II Static RAMs are unidirectional and can
be optimized for signal integrity at very high bus speeds. The Dual
QDR-II Static RAM has scalable output impedance on its data output
bus and echo clocks allowing the user to tune the bus for low noise
and high performance.
IDT70P3537/70P3517 Dual QDR-II Static RAMs have a single
DDR address bus per port with multiplexed read and write addresses.
All read addresses are received on the first half of the clock cycle and
all write addresses are received on the second half of the clock cycle.
The byte write signals are received on both halves of the clock cycle
simultaneously with the data they are controlling on the data input bus.
The Dual QDR-II Static RAM device has echo clocks, which
provide the user with a clock that is precisely timed to the data output
3
and tuned with matching impedance and signal quality. The user
can use the echo clock for downstream clocking of the data. For
the user, echo clocks eliminate the need to produce alternate clocks
with precise timing, positioning, and signal qualities to guarantee
data capture. Since the echo clocks are generated by the same
source that drives the data output, the relationship to the data is
NOT significantly affected by external parameters such as voltage,
temperature, and process as would be the case if the clock were
generated by an outside source.Thus the echo clocks are guaranteed to be synchronized with the data.
All interfaces of Dual QDR-II Static RAMs are HSTL, allowing speeds beyond SRAM devices that use any form of TTL
interface. The interface can be scaled to higher voltages (up to
1.9V) to interface with 1.8V systems, if necessary. The device has
VDDQ pins and a separate Vref, allowing the user to designate the
interface operational voltage independent of the device core voltage of 1.8V VDD. Output impedance control pins allow the user to
adjust the drive strength to adapt to a wide range of loads and
transmission lines.
Clocking
The IDT70P3537/3517 has two sets of input clocks for both
the input and output, the K, K clocks and the C, C clocks. In addition,
the IDT70P3537/3517 has an output “echo” clock pair, CQ and CQ.
The K and K clocks are the primary device input clocks.
The K clock is used to clock in the control signals (R, W, E[1:0],
BW0-3), the read address, and the first word of the data burst
(D[35:0]) during a write operation. The K clock is used to clock in
the control signals (BW0-3, E[1:0]), write address and the second
word of the data burst during a write operation (D[35:0]). In the
event that the user disables the C and C clocks, the K and K clocks
will also be used to clock the data out of the output register and
generate the echo clocks. The K and K, C and C,CQ and CQ, pairs
are offset by half a clock cycle from each other.
The C and C clocks may be used to clock the data out of
the output register during read operations and to generate the echo
clocks. C and C must be presented to the memory within the timing
tolerances as shown in the AC Electrical Characteristics Table
(Page 12). The output data from the IDT70P3537/70P3517 will be
closely aligned to the C and C input, through the use of an internal
DLL. When C is presented to the IDT70P3537/70P3517 the DLL
will have already internally clocked the data to arrive at the device
output simultaneously with the arrival of the C clock. The C and
second data item of the burst will also correspond.
Single Clock Mode
The IDT70P3537/70P3517 may be operated with a single
clock pair. C and C may be disabled by tying both signals high,
forcing the outputs and echo clocks to be controlled instead by the
K and K clocks.
DLL Operation
The DLL in the output structure of the IDT70P3537/70P3517
can be used to closely align the incoming clocks C and C with the
output of the data, generating very tight tolerances between the
July 16, 2007
Preliminary Datasheet
Commercial Temperatue Range
18/9Mb x36 IDT70P3537/70P3517
SYNCHRONOUS Dual QDR-IITM
two. The user may disable the DLL by holding DOFF low. With the DLL
off, the C and C (or K and K, if C and C are not used) will directly clock
the output register of the IDT70P3537/70P3517. With the DLL off,
there will be a propagation delay from the time the clock enters the
device until the data appears at the output. QDR-II becomes QDRITM
with DLL off. First data out is referenced to C instead of C.
Echo Clock
The echo clocks, CQ and CQ, are generated by the C and C
clocks (or K, K if C, C are disabled). The rising edge of C generates
the rising edge of CQ, and the falling edge of CQ. The rising edge of
C generates the rising edge of CQ and the falling edge of CQ. This
scheme improves the correlation of the rising and falling edges of the
echo clock and will improve the duty cycle of the individual signals.
The echo clock is very closely aligned with the data, guaranteeing
that the echo clock will remain closely correlated with the data, within
the tolerances designated.
Normal QDR-II Read and Write Operations
The IDT70P3537/70P3517 Dual QDR-II Static RAM supports
QDR-II burst-of-two read/write operations. Read operations are initiated by holding the read port select (R) low, and presenting the read
address to the address port during the rising edge of K which will latch
the address. Data is delivered after the next rising edge of the next K
(t + 1), using C and C as the output timing references; or K and K, if
C and C are tied high.
The write operation is a standard QDR-II burst-of-two write
operation, except the data is not available to be read until the next
clock cycle (this is one cycle later than standard QDR-II SRAM).
4
Normal QDR write cycles are initiated by holding the write port select
(W) low at K rising edge. Also, the Byte Write inputs (BW0-3), designating which bytes are to be written, need to be held low for both the
K and K clocks. On the rising edge of K the first word of the data must
also be present on the data input bus D[35:0] observing the designated
set up times. Upon the rising edge of K the first word of the burst will
be latched into the input register. After K has risen, and the designated
hold times observed, the second half of the clock cycle is initiated by
presenting the write address to the address bus A[X:0], the BW0-3
inputs for the second data word of the burst, and the second data item
of the burst to the data bus D[35:0]. Upon the rising edge of K, the
second word of the burst will be latched, along with the designated
address. Both the first and second words of the burst will be written
into memory as designated by the address and byte write enables.
The addresses for the write cycles is provided at the K rising edge,
and data is expected at the rising edge of K and K, beginning at the
same K that initiated the cycle.
Programmable Impedance
An external resistor, RQ, must be connected between the
ZQ pin on the IDT70P3537/70P3517 and tied to VSS to allow the
IDT70P3537/70P3517 to adjust its output drive impedance. The value
of RQ must be 5X the value of the intended drive impedance of the
IDT70P3537/70P3517. The allowable range of RQ to guarantee
impedance matching with a tolerance of +/- 15% is 175 ohms to 350
ohms. The output impedance is adjusted every 1024 clock cycles to
correct for drifts in supply voltage and temperature. If the user wishes
to drive the output impedance of the IDT70P3537/70P3517 to its
lowest value, the ZQ pin may be tied to VDDQ.
July 16, 2007
Preliminary Datasheet
Commercial Temperatue Range
18/9Mb x36 IDT70P3537/70P3517
SYNCHRONOUS Dual QDR-IITM
Pin Definitions
Symbol(1)
Pin Function
D[35:0]X
Input
Synchronous
BW0X, BW1X,
BW2X, BW3X
Input
Synchronous
A[17:0] X(2)
Input
Synchronous
Address Inputs. Read addresses are sampled on the rising edge of K clock during active read operations. Write addresses are sampled on the rising edge of K
clock during active write operations. These address inputs are multiplxed, so that both a read and write operation can occur on the same clock cycle. These inputs
are ignored when the appropriate port is deselected.
Q[35:0]X
Output
Synchronous
Data Output signals. These pins drive out the requested data during a Read operation. Valid data is driven out on the rising edge of both the C and C clocks during
Read operations or K and K when operating in single clock mode. When the Read port is deselected, Q[35:0] are automatically tri-stated.
WX
Input
Synchronous
Write Control Logic, active LOW. Sampled on the rising edge of the positive input clock (K). When asserted active, a write operation in initiated. Deasserting will
deselect the Write port. Deselecting the Write port will cause D[35:0] to be ignored.
RX
Input
Synchronous
Read Control Logic, active LOW. Sampled on the rising edge of Positive Input Clock (K). When active, a Read operation is initiated. Deasserting will cause the
Read port to be deselected. When deselected, the pending access is allowed to complete and the output drivers are automatically tri-stated following the next
rising edge of the C clock. (DOFFX = 1). Each read access consists of a burst of two sequential transfers.
CX
Input Clock
Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of
various devices on the board back to the controller. See application example for further details.
CX
Input Clock
Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times
of various devices on the board back to the controller. See application example for further details.
KX
Input Clock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device. Drives out data through Q[35:0] when in single clock mode.
All accesses are initiated on the rising edge of K.
KX
Input Clock
CQX
Output Clock
CQX
Output Clock
ZQX
Input
EP[1:0]
Input
EX[1:0]
Input
Syncronous
DOFFX
Input
MRST
Description
Data input signals, sampled on the rising edge of K and K clocks during valid write operations
Byte Write Selects active LOW. Sampled on the rising edge of the K and again on the rising edge of K clocks during write operations. Used to select which byte is
written into the device during the current portion of the write operations. Bytes not written remain unaltered. All byte writes are sampled on the same edge as the
data. Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored and not written in to the device.
BW0 controls D[8:0], BW1 controls D[17:9], BW2 controls D[26:18], and BW3 controls D[35:27].
Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device. Drives out data through Q[35:0] when in single clock mode.
Synchronous Echo clock output. The rising edge of CQ is tightly matched to the synchronous data outputs and can be used as a data valid indication. CQ is free
running and does not stop when the output data is tri-stated.
Synchronous Echo Clock output. The rising edge of CQ is tightly matched to the synchronous data outputs and can be used as a data valid indication. CQ is free
running and does not stop wehen the output data is tri-stated.
Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. Q[35:0] output impedance is set to 0.2 x RQ,
where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be connected directly to V DDQ, which enables the minimum impedance mode.
This pin cannot be connected directly to GND or left unconnected.
EP[1:0] are used to program the Port Enable pins E[1:0]. EP[1:0] are programmed by tying the pins high or low on the board. If a customer does not want to use
Pins EP[1:0], then these pins should be tied low. Refer to Truth Table III for Port Enable pins.
Two Port Enable pins E[1:0] are provided to connect to the two MSB bits on the memory controller in order to cascade up to four IDT70P3537 devices. If a customer
does not want to use Pins E[1:0], then these pins should be tied low. Refer to Truth Table III for Port Enable pins. Also refer to Figure 1 showing cascade/multi-drop
using port-enable (E[1:0]) pins. E[1:0] are sampled on the rising edge of K for read operations and again on rising edge of K for write operations.
DLL Turn Off. When low this input will turn off the DLL inside the device. The AC timings with the DLL turned off will be different from those listed in this data sheet.
There will be an increased propagation delay from the incidence of C and C to Q, or K and K to Q as configured.
Input
Master Reset pin. When held low will reset the device.
Asynchronous
DEPTH
Input
TDO
Output
TCK
Input
TCK pin for JTAG.
TDI
Input
TDI pin for JTAG.
Input
TMS pin for JTAG.
TMS
TRST
VDD
VSS
VDDQX
TDO pin for JTAG.
Input
Reset pin for JTAG.
Asynchronous
Should be tied to V CC or VSS only, or can be left as a floating pin.
INC
VREFX
Connect to VDDQ for 9Mb. Connect to VSS for 18Mb.
Input
Reference
Reference Voltage input. Static input used to set the reference level for HSTL inputs as well as AC measurement points.
Power Supply Power supply inputs to the core of the device. Should be connected to a 1.8V power supply.
Ground
Ground for the device. Should be connected to ground of the system.
Power Supply Power supply for the outputs of the device. Should be connected to a 1.5V power supply for HSTL or scaled to the desired output voltage.
5677 tbl 01
NOTE:
1. "X" = "L" for the Left Port pins and "X" = "R" for the Right Port pins.
2. A[16:0]x for IDT70P3517.
5
July 16, 2007
Preliminary Datasheet
Commercial Temperatue Range
18/9Mb x36 IDT70P3537/70P3517
SYNCHRONOUS Dual QDR-IITM
Truth Table I - Synchronous Port Control(1)
D(3,4)
K
K
Stopped
R
W
X
X
Stopped
H
Ç
H
Ç
X
Ç
X
Ç
X
Ç
X
Ç
L
Ç
X
Ç
X
Ç
L
Ç
EO(2) E1(2)
X
X
X
X
X
X
X
X
F
X
F
X
X
F
X
F
T
T
X
X
X
X
T
T
Q(3,4)
D(A+0)
D(A+1)
X
C
C
Stopped
X
X
High - Z
Ç
High - Z
Ç
DOUT at C (t+1)
Ç
DIN at K(t)
Read
X
Ç
No operation
DOUT at C (t+2) Read
Ç
DIN at K(t)
No operation
No operation
High - Z
Ç
X
No operation
No operation
High - Z
Ç
X
X
No operation
High - Z
Ç
X
X
Clock stopped
Previous state Clock stopped
High - Z
Ç
OPERATION
Q(A+1)
Previous state
Stopped
X
X
Q(A+0)
Write
X
Ç
Write
5677 tbl 03
NOTES:
1. x = "Don’t Care", H = Logic High, L = Logic Low, Ç represents rising edge.
2. T (True) = E and EP have some polarity (device selected) on the rising edge of the appropriate clock. F (False) =E and EP have
opposite polarity (device de-selected) on the rising edge of the appropriate clock. See Truth Table III.
3. "A" represents address location latched by the device when operation was initiated. A+0, A+1 represents the internal address sequence
in the burst.
4. "t" represents the cycle at which a read/write operation is started. t+1 and t+2 are the first and second clock cycles respectively
following clock cycle t.
Truth Table II - Write Port Enable Control(2,3)
K
K
BW0(1)
BW1(1)
BW2(1)
BW3(1)
Input
Input
Input
Input
Input
Input
H
H
H
H
Write function disabled all bytes
H
H
H
H
Write function disabled all bytes
L
H
H
H
Write data inputs to Byte 0 Only
L
H
H
H
Write data inputs to Byte 0 Only
H
L
H
H
Write data inputs to Byte 1 Only
H
L
H
H
Write data inputs to Byte 1 Only
H
H
L
H
Write data inputs to Byte 2 Only
H
H
L
H
Write data inputs to Byte 2 Only
H
H
H
L
Write data inputs to Byte 3 Only
H
H
H
L
Write data inputs to Byte 3 Only
L
L
L
L
Write data inputs to all Bytes
L
L
L
L
Write data inputs to all Bytes
Ç
Ç
Ç
Ç
Ç
Ç
Ç
Ç
Ç
Ç
Ç
Ç
Mode
5677 tbl 03a
NOTES:
1. BW0 controls D[8:0], BW1 controls D[17:9], BW2 controls D[26:18], BW3 controls D[35:27].
2. For this table: W is Low on the rising edge of K; E0 and E1 are true on the rising edge of K. See Truth Tables I and III.
Addresses for Writes are qualified on rising edge of K.
3. This table represents a subset of the potential write scenarios based upon BW0 - BW3 inputs and is meant to illustrate
basic device functionality.
6
July 16, 2007
Preliminary Datasheet
Commercial Temperatue Range
18/9Mb x36 IDT70P3537/70P3517
SYNCHRONOUS Dual QDR-IITM
Truth Table III - Port Enable Pins(1)
Normal Read and Writes
Device Selected
EP[0]
EP[1]
E[0]
E[1]
Bank 0
VSS
VSS
L
L
Bank 1
VDD
VSS
H
L
Bank 2
VSS
VDD
L
H
Bank 3
VDD
VDD
H
H
5677 tbl05
NOTES:
1. EP [1:0] - Port Enable Programming Polarity (see pin description for the entire device).
2. Ex[1:0] - Port Enable (see pin description assigned for each port).
Cascade/Multi-Drop using Port Enable (E0 & E1) Pins
As shown below in Figure 1 upto four devices can be cascaded using the Port Enable (E0,E1) pins scheme. The port enable pins
are subject to the same DC characteristics as the QDR interface. Refer to Pin Definitions table for pin descriptions. This diagram illustrates
one port of a QDR-II dual port
Figure 1. Multi-drop Cascading using the Chip Enable E[1:0] Pins
7
July 16, 2007
Preliminary Datasheet
Commercial Temperatue Range
18/9Mb x36 IDT70P3537/70P3517
SYNCHRONOUS Dual QDR-IITM
Absolute Maximum Ratings(1,2,3)
Symbol
Rating
Value
Unit
Symbol
CIN
CO
VDD
Supply Voltage on VDD with
Respect to GND
–0.5 to +2.2
V
VDDQ
Supply Voltage on VDDQ with
Respect to GND
–0.5 to VDD
V
VTERM
Voltage on Input, Output and I/O
terminals with respect to GND
TBIAS
Capacitance
(TA = +25°C, f = 1.0MHz)(1)
Conditions(2)
Max.
Unit
Input Capacitance
VIN = 0V
5
pF
Output Capacitance
VOUT = 0V
7
pF
Parameter
5677 tbl 08
–0.3 to VDD+0.3
V
Temperature Under Bias
–55 to +125
°C
TSTG
Storage Temperature
–65 to +150
°C
IOUT
Continuous Current into Outputs
+ 20
NOTE:
1. Tested at characterization and retested after any design or process change that
may affect these parameters.
2. VDD = 1.8V, VDDQ = 1.5V
mA
5677 tbl 07
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDDQ must not exceed VDD during normal operation.
3. VTerm(MAX) = minimum of VDD +0.3V and 2.2V.
Thermal Resistance
Recommended DC Operating
and Temperature Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
Power Supply
Voltage
1.7
1.8
1.9
V
VDDQ
I/O Supply Voltage
1.4
1.5
1.9
V
VSS
Ground
0
0
0
V
VREF
Input Reference
Voltage
0.68
VDDQ/2
0.95
V
VIH
Input High Voltage
VREF+0.1
–
VDDQ+0.3
V
Parameter
Symbol
Typ.
Unit
VIL
Input Low Voltage
–0.3
–
VREF–0.1
V
Junction to Ambient
θJA
12.5
°C/W
TA
Ambient
Temperature (1)
0
25
+70
Junction to Case
θJC
0.1
°C/W
o
c
5677 tbl 09
NOTE:
1. During production testing, the case temperature equals the ambient temperature.
5677 tbl 10
NOTE:
1. Junction temperature is a function of on-chip power dissipation, package
thermal impedance, mounting site temperature and mounting site thermal
impedance. TJ = TA + PD x θJA.
Recommended Operating
Temperature and Supply Voltage
Grade
Commercial
Industrial
Ambient
Temperature
GND
VDD
0OC to +70OC
0V
1.8V + 100mV
-40OC to +85OC
0V
1.8V + 100mV
5677 tbl06
8
July 16, 2007
Preliminary Datasheet
Commercial Temperatue Range
18/9Mb x36 IDT70P3537/70P3517
SYNCHRONOUS Dual QDR-IITM
DC Electrical Characteristics Over the Operating Temperature
and Supply Voltage (VDD = 1.8V ±100mV, VDDQ = 1.4V to 1.9V, TA = 0 to 70°C)
Parameter
Symbol
Test Conditions
Min
Max
Unit
Note
-10
+10
µA
8
-10
+10
µA
8
-
1636
233MHZ
-
1542
mA
1
VDD = Max,
IOUT = 0mA (outputs open),
Cycle Time > tKHKH Min
250MHZ
-
1432
233MHZ
-
1351
mA
1
VDD = Max,
IOUT = 0mA (outputs open),
Cycle Time > tKHKH Min
250MHZ
-
1212
IDD2
233MHZ
-
1147
mA
1
250MHZ
-
1007
ISB
Device Deselected
IOUT = 0mA (outputs open),
f=Max,
All Inputs < 0.2V or > VDD - 0.2V
WEN=REN=High
233MHZ
-
956
mA
2
Input Leakage Current
IIL
VDD = Max VIN = VSS to VDDQ
Output Leakage Current
IOL
Output Disabled
250MHZ
Active Operating Current
IDD
VDD = Max,
IOUT = 0mA (outputs open),
Cycle Time > tKHKH Min
2 Port Read
IDD1
2 Port Write
Standby Current
Output High Voltage
VOH1
ZQ = 250Ω, IOH = -(VDDQ/2)/(RQ/5)
VDDQ/2 -0.12
VDDQ/2 +0.12
V
3,7
Output Low Voltage
VOL1
ZQ = 250Ω, IOL = (VDDQ/2)/(RQ/5)
VDDQ/2 -0.12
VDDQ/2 +0.12
V
4,7
Output High Voltage
VOH2
IOH = -0.1mA
VDDQ -0.2
VDDQ
V
5
Output Low Voltage
VOL2
IOL = 0.1mA
VSS
0.2
V
6
Output Impedance Control
| IOH |
| IOL |
VOUT = VDDQ/2
VOUT = VDDQ/2
-(IOHo-15%)
(IOLo-15%)
-(IOHo+15%)
(IOLo+15%)
V
3
4
5677 tbl12
NOTES:
1. Operating Current is measured at 100% bus utilization on the active port.
2. Standby Current is only after all pending read and write burst operations are completed.
3. Outputs are impedance-controlled. IOHO = (VDDQ/2)/(RQ/5) = @Vout = VDDQ/2 and is guaranteed by device characterization for 175Ω < ZQ < 350Ω. This parameter is tes
at ZQ = 250Ω, which gives a nominal 50Ω output impedance.
4. Outputs are impedance-controlled. IOLO = (VDDQ/2)/(RQ/5) = @Vout = VDDQ/2 and is guaranteed by device characterization for 175Ω < ZQ < 350Ω. This parameter is tes
at ZQ = 250Ω, which gives a nominal 50Ω output impedance.
5. This measurement is taken to ensure that the output has the capability of pullling to the V DDQ rail, and is not intended to be used as an impedance
measurement point.
6. This measurement is taken to ensure that the output has the capability of pulling to VSS, and is not intended to be used as an impedance measure point.
7. Programmable Impedance Mode.
8. ± 30µA for JTAG input pins.
Input Electrical Characteristics Over the Operating Temperature
and Supply Voltage (VDD = 1.8V ±100mV, VDDQ = 1.4V to 1.9V, TA = 0 to 70°C)
Parameter
Symbol
Min
Max
Unit
Notes
Input High Voltage, DC
VIH (DC)
VREF +0.1
VDDQ +0.3
V
1,2
Input Low Voltage, DC
VIL (DC)
-0.3
VREF -0.1
V
1,3
Input High Voltage, AC
VIH (AC)
VREF +0.2
-
V
4,5
Input Low Voltage, AC
VIL (AC)
-
VREF -0.2
V
4,5
5677 tbl 13
NOTES:
1. These are DC test criteria. DC design criteria is VREF + 50mV. The AC VIH/VIL levels are defined separately for measuring timing parameters.
2. VIH (Max) DC = VDDQ +0.3V, VIH (Max) AC = VDDQ +0.5V (pulse width < 20% tKHKH (min)).
3. VIL (MIN) DC = -0.3V, VIL (MIN) AC = -0.5V (pulse width < 20% tKHKH (min)).
4. This condition is for AC function test only, not for AC parameter test.
5. To maintain a valid level, the transitioning edge of the input must:
Sustain a constant slew rate from the current AC level through the target AC level, VIL (AC) or VIH (AC)
Reach at least the target AC level
After the AC target level is reached, continue to maintain at least the target DC level, VIL (DC) or VIH (DC)
9
July 16, 2007
Preliminary Datasheet
Commercial Temperatue Range
18/9Mb x36 IDT70P3537/70P3517
SYNCHRONOUS Dual QDR-IITM
Overshoot Timing
Undershoot Timing
VIL
VSS
VSS -0.25V
VSS -0.5V
20% tKHKH (MIN)
5677 drw 06
AC Test Loads
VREF
AC Test Conditions
VDDQ/2
Parameter
OUTPUT
Device
Under
Test
ZQ
Z0 = 50 Ω
RL = 50 Ω
RQ = 250 Ω
VDDQ/2
5677 drw 07
Symbol
Value
Unit
Core Power Supply Voltage
VDD
1.7-1.9
V
Output Power Supply Voltage
VDDQ
1.4-1.9
V
Input High Level
VIH
(VDDQ/2) +0.5
V
Input Low Level
VIL
(VDDQ/2) -0.5
V
Input Reference Level
VREF
VDDQ/2
V
Input Rise/Fall Time
TR/TF
0.3/0.3
ns
VDDQ/2
V
Output Timing Reference Level
5677 tbl 14
NOTE:
1. Parameters are tested with RQ=250Ω.
(VDDQ/2) +0.5V
VDDQ/2
(VDDQ/2) -0.5V
10
5677 drw08
July 16, 2007
Preliminary Datasheet
Commercial Temperatue Range
18/9Mb x36 IDT70P3537/70P3517
SYNCHRONOUS Dual QDR-IITM
AC Electrical Characteristics
(VDD = 1.8V ±100mV, VDDQ = 1.4V to 1.9V, TA(8) = 0 to 70°C)
Symbol
Parameter
Commercial
Com'l & Ind'l
250MHz
233MHz
Min.
Max.
Min.
Max.
Unit
4.00
6.30
4.30
7.20
ns
__
Notes
Clock Parameters
tKHKH
Average clock cycle time (K,K,C,C)
tKC var
Clock Phase Jitter (K,K,C,C)
0.20
__
0.20
ns
1,5
tKHKL
Clock High Time (K,K,C,C)
1.60
__
1.80
__
ns
9
tKLKH
Clock LOW Time (K,K,C,C)
1.60
__
1.80
__
ns
9
tKHKH
Clock to clock (K→K,C→C)
1.80
__
2.00
__
ns
10
tKHKH
Clock to clock (K→K,C→C)
1.80
__
2.00
__
ns
10
tKHCH
Clock to data clock (K→C,K→C)
0.00
1.80
0.00
2.00
ns
tKC lock
DLL lock time (K, C)
1024
__
1024
__
cycles
tKC reset
K static to DLL reset
30
__
30
__
ns
ns
2
Output Parameters
tCHQV
C,C HIGH to output valid
__
0.45
__
0.45
3
ns
3
ns
3
3
tCHQX
C,C HIGH to output hold
-0.45
__
-0.45
__
tCHCQV
C,C HIGH to echo clock valid
__
0.45
__
0.45
tCHCQX
C,C HIGH to echo clock hold
-0.45
__
-0.45
__
ns
tCQHQV
CQ,CQ HIGH to output valid
__
0.30
__
0.32
ns
tCQHQX
CQ,CQ HIGH to output hold
-0.30
__
-0.32
__
ns
tCHQZ
C HIGH to output High-Z
__
0.45
__
0.45
ns
3,4,5
tCHQX1
C HIGH to output Low-Z
-0.45
__
-0.45
__
ns
3,4,5
Set-Up Times
tAVKH
Address valid to K,K rising edge
0.35
__
0.37
__
ns
6
tIVKH
Control inputs valid to K,K rising edge
0.35
__
0.37
__
ns
7
tDVKH
Date-in valid to K, K rising edge
0.35
__
0.37
__
ns
Hold Times
tKHAX
K,K rising edge to address hold
0.35
__
0.37
__
ns
6
tKHIX
K,K rising edge to control inputs hold
0.35
__
0.37
__
ns
7
tKHDX
K,K rising edge to data-in hold
0.35
__
0.37
__
ns
4.00
—
4.30
—
ns
Port-to-Port Delay
tCO
Clock-to-Clock Offset
6725 tbl15
NOTES:
1. Cycle to cycle period jitter is the variance from clock rising edge to the next expected clock rising edge, as defined per JEDEC Standard No. 65 (EIA/JESD65)
page.
2. VDD slew rate must be less than 0.1V DC per 50ns for DLL lock retention. DLL lock time begins once VDD, VDDQ and input clock are stable.
3. If C, C are tied High, K, K become the references for C, C timing parameters.
4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ.
The specs as shown do not imply bus contention because tCHQX1 is a MIN parameter that is worst case at 0°C and 1.9V tCHQZ, is a MAX parameter that is
worst case at 70°C and 1.7V.
5. This parameter is guaranteed by device characterization, but not production tested.
6. All address inputs must meet the specified setup and hold times for all latching clock edges.
7. Control signals are R, W, BW0, BW1, BW2, BW3,E0, E1.
8. During production testing, the case temperature equals TA.
9. Clock High Time (tKHKL) and Clock Low Time (tKLKH) should be within 40% to 60%of the cycle time (tKHKH).
10. Clock to Clock time (tKHKH) and Clock to Clock time (tKHKH) should be within 45% to 55% of the cycle time (tKHKH).
11
July 16, 2007
Preliminary Datasheet
Commercial Temperatue Range
18/9Mb x36 IDT70P3537/70P3517
SYNCHRONOUS Dual QDR-IITM
Timing Waveform for Alternating Read and Write Operations(1,2)
Read
0
Read
2
Write
1
Write
3
Read
4
Write
5
Write
7
NOP
6
NOP
8
NOP
9
Q40
Q41
K
tKHKL
tKLKH
tKHKH
tKHKH
tKHKH
K
R
tIVKH
tKHIX
W
tAVKH
A
tKHAX
A4
A7
A2
tAVKH tKHAX
tAVKH tKHAX
BWx(3) B10
B11
B30
B31
B50
B51
B70
B71
D10
D11
D30
D31
D50
D51
D70
D71
D
A3
A5
A1
A0
tIVKH
tKHIX
tDVKH tKHDX
Q00(4)
Q
tKHIX
tIVKH
tDVKH tKHDX
Q01
Q20
Q21
tCHQX1
tCHQX
tCHQX
tCHQV
tKLKH
tCQHQV
tCHQV
tCHQZ
tKHKH
C
tKHKH
tKHKL
tKHKH
C
tCHCQV
tCQHQX
tCQHQV
tCHCQX
CQ
tCHCQV
tCQHQV
tCQHQX
tCHCQX
CQ
5677 drw 09
NOTES:
1. Device is selected per E[0] and E[1] as defined in Truth Table II, and MRST = VIH.
2. This waveform represents operation when DLL is ON.
3. To perform a valid write operation, both W and the appropriate BW0-3 must be low.
4. Q00 refers to the output from A0, and Q01 refers to the output from the next internal address following A0.
12
July 16, 2007
Preliminary Datasheet
Commercial Temperatue Range
18/9Mb x36 IDT70P3537/70P3517
SYNCHRONOUS Dual QDR-IITM
Timing Waveform of Back-to-Back Read-Write-Read to Same
Address(1,2)
NOTES:
1. Device is selected per E[0] and E[1] as defined in Truth Table II, and MRST = VIH.
2. This waveform represents operation when DLL is ON.
3. To perform a valid write operation, both W and the appropriate BW0-3 must be low.
4. ORIG Q00 represents the existing data in the memory. New Q00 represents the data written into the memory in the first cycle of the waveform.
13
July 16, 2007
Preliminary Datasheet
Commercial Temperatue Range
18/9Mb x36 IDT70P3537/70P3517
SYNCHRONOUS Dual QDR-IITM
Timing Waveform for Left Port Write to Right Port Read(1)
0
1
2
3
4
5
6
7
8
9
11
10
12
13
14
tCO(2)
KL
tKHKH
KL
WL
DINL
A1
A0
Address_L
D00
D01
D11
D10
KR
KR
RR
Address_R
A0
A2
QR
Q00
Q01
Q20
Q21
tCHQX1
CR
tCHQV
CR
CQR
CQR
5677 drw 11
NOTES:
1. Device is selected per E[0] and E[1] as defined inTruth Table III. MRST = VIH. BW0L, BW1L, BW2L, and BW3L = VIL
2. If tco < specified minimum, data read from right port is not valid until the next KR cycle. If tco > specified minimum, data read from right port is available on the first KR cycle
as shown.
14
July 16, 2007
Preliminary Datasheet
Commercial Temperatue Range
18/9Mb x36 IDT70P3537/70P3517
SYNCHRONOUS Dual QDR-IITM
Timing Waveforms for DLL Operation (On/Off)(1,2)
Read
0
Read
2
Write
1
Write
3
Read
4
Write
5
Write
7
NOP
6
NOP
8
NOP
9
K
tKHKL
tKLKH
tKHKH
tKHKH
tKHKH
K
R
tIVKH
tKHIX
W
tKHAX
tAVKH
A
BWX(3)
D
A0
A4
A3
A5
A1
A2
tAVKH tKHAX
tAVKH tKHAX
B10
B11
B30
B31
B50
B51
B70
B71
D10
D11
D30
D31
D50
D51
D70
D71
tIVKH
A7
tKHIX
tIVKH
tDVKH tKHDX
tDVKH tKHDX
tCHQV
Case 1: Q
DLL OFF (QDRI)(5)
Q00(4)
tCHQX1
Q01
tCHQX
tKHIX
Q20
Q21
tCHQZ
Q40
Q41
tCHQX
tCHQV
Case 2: Q
DLL ON (QDRII)
Q00(4)
Q01
Q20
Q40
Q21
Q41
tCHQX1
tCHQX
tKLKH
tCHQV
tCHQV
tCHQX
tCHQZ
tKHKH
C
tKHKL
tKHKH
tKHKH
C
5677 drw 12
NOTES:
1. Device is selected per E[0] and E[1] as defined in Truth Table II, and MRST = VIH.
2. With DLL OFF (DOFFX < VIL) device behaves as a QDRI device. With DLL ON (DOFFX > VIH) device behaves as a QDR-II device.
3. To perform a valid write operation, both W and the appropriate BW0-3 must be low on the rising edge of K.
4. Q00 refers to the output from A0, and Q01 refers to the output from the next internal address following A0.
5. With DLL off (DOFF = VIL) the propagation delays will be increased and the AC timing parameters will be different values from those specified in this data sheet.
15
July 16, 2007
Preliminary Datasheet
Commercial Temperatue Range
18/9Mb x36 IDT70P3537/70P3517
SYNCHRONOUS Dual QDR-IITM
Master Reset Timing Waveform
K
(5ns)
MRST(1)
5677 drw13
NOTE:
1. MRST must be held LOW for a minimum of (5ns) after power supply is stable.
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July 16, 2007
Preliminary Datasheet
Commercial Temperatue Range
18/9Mb x36 IDT70P3537/70P3517
SYNCHRONOUS Dual QDR-IITM
IEEE 1149.1 Test Access Port and Boundary SCAN-JTAG
This part contains an IEEE standard 1149.1 Compatible Test Access Port (TAP). The package pads are monitored by the Serial
Scan circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. In conformance with
IEEE 1149.1, the QDR-II Dual-Port Static RAM contains a TAP controller, Instruction Register, Bypass Register and ID Register. The TAP
controller has a standard 16-state machine that resets internally upon power-up. It is possible to use this device without utilizing the TAP. To
disable the TAP controller without interfacing with normal operation of the QDR-II Dual-Port Static RAM TCK must be tied to VSS to preclude
a mid level input. TMS and TDI are designed so an undriven input will produce a response identical to the application of a logic 1, and may
be left unconnected, but they may also be tied to Vdd through a resistor. TDO should be left unconnected.
JTAG Block Diagram
TAP Controller State Diagram
1
0
Test Logic Reset
0
Run Test Idle
1
Select DR
1
Select IR
1
1
Capture DR
0
1
1
Exit 2 DR
1
Update DR
0
1
1
Exit 1 DR
Pause DR
Shift IR
0
0
1
Capture IR
0
Shift DR
1
1
0
0
0
Exit 1 IR
0
0
0
Pause IR
1
Exit 2 IR
0
0
1
Update IR
0
1
5677 drw 15
17
July 16, 2007
Preliminary Datasheet
Commercial Temperatue Range
18/9Mb x36 IDT70P3537/70P3517
SYNCHRONOUS Dual QDR-IITM
Identification Register Definitions
Instruction Field
Value
Revision Number (31:28)
Description
0x0
IDT Device ID (27:12)
0x355(1)
IDT JEDEC ID (11:1)
0x33
ID Register Indicator Bit (Bit 0)
Reserved for version number
Defines IDT part number (IDT70P3537)
Allows unique identification of device vendor as IDT
1
Indicates the presence of an ID register
5677 tbl 16
NOTE:
1. Device ID for IDT70P3517 is 0x356.
Scan Register Sizes
Register Name
Bit Size
Instruction (IR)
4
Bypass (BYR)
1
Identification (IDR)
Boundary Scan (BSR)
32
Note 1
5677 tbl 17
NOTE:
1. The Boundary Scan Descriptive Language (BSDL) file for this device is available
on the IDT website (www.idt.com), or by contacting your local IDT sales representative.
System Interface Parameters
Instruction
Code
Description
EXTEST
0000
Forces contents of the boundary scan cells onto the device outputs (1).
Places the boundary scan register (BSR) between TDI and TDO.
BYPASS
1111
Places the bypass register (BYR) between TDI and TDO.
IDCODE
0010
Loads the ID register (IDR) with the vendor ID code and places the
register between TDI and TDO.
0100
Places the bypass register (BYR) between TDI and TDO. Forces all
device output drivers to a High-Z state except COLx & INTx outputs.
HIGHZ
Uses BYR. Forces contents of the boundary scan cells onto the device
outputs. Places the bypass register (BYR) between TDI and TDO.
CLAMP
0011
SAMPLE/PRELOAD
0001
Places the boundary scan register (BSR) between TDI and TDO.
SAMPLE allows data from device inputs (2) to be captured in the
boundary scan cells and shifted serially through TDO. PRELOAD allows
data to be input serially into the boundary scan cells via the TDI.
0101, 0111, 1000, 1001,
1010, 1011, 1100
Several combinations are reserved. Do not use codes other than those
identified above.
RESERVED
PRIVATE
0110,1110,1101
For internal use only.
5677 tbl 18
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST.
18
July 16, 2007
Preliminary Datasheet
Commercial Temperatue Range
18/9Mb x36 IDT70P3537/70P3517
SYNCHRONOUS Dual QDR-IITM
JTAG DC Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Power Supply Voltage (I/P + O/P)
VDD
1.7
1.8
1.9
V
Input High Level
VIH
1.3
-
VDD+0.3
V
Input Low Level
VIL
-0.3
-
0.5
V
Output High Voltage (IOH = -1mA)
VOH
VDD - 0.2
-
VDD
V
Output Low Voltage (IOL = 1mA)
VOL
VSS
-
0.2
V
Note
5677 tbl 19
JTAG AC Test Conditions
Parameter
Symbol
Value
Unit
Input High/Low Level
VIH/VIL
1.8/0
V
Input Rise/Fall Time
TR/TF
1.0/1.0
ns
VDD/2
V
Input and Output Timing Reference Level
Note
1
5677 tbl 20
NOTE:
1. For outputs see AC test loads on page 10.
JTAG AC Characteristics
Symbol
Min
Max
Unit
TCK Cycle Time
Parameter
tCHCH
100
-
ns
TCK High Pulse Width
tCHCL
40
-
ns
TCK Low Pulse Width
tCLCH
40
-
ns
TMS Input Setup Time
tMVCH
10
-
ns
TMS Input Hold Time
tCHMX
10
-
ns
TDI Input Setup Time
tDVCH
10
-
ns
TDI Input Hold Time
tCHDX
10
-
ns
Input Setup Time
tSVCH
10
-
ns
Input Hold Time
tCHSX
10
-
ns
Clock Low to Output Valid
tCLQV
0
20
ns
TRST Low to Reset JTAG
tJRST
50
-
ns
TRST High to TCK HIGH
tJRSR
50
-
ns
Note
5677 tbl 21
JTAG Timing Diagram
TCK
tCHCL
tCHCH
tMVCH
tCHMX
tDVCH
tCHDX
tSVCH
tCHSX
tCLCH
TMS
TDI
Outputs
tCLQV
TDO
TRST
tJRST
tJRSR
5677 drw 16
19
July 16, 2007
Preliminary Datasheet
Commercial Temperatue Range
18/9Mb x36 IDT70P3537/70P3517
SYNCHRONOUS Dual QDR-IITM
Ordering Information
Preliminary Datasheet: Description
"PRELIMINARY" datasheets contain descriptions for products that are in early release.
Datasheet Document History
7/11/2007: Initial release of Preliminary Datasheet
®
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800-345-7015 or 408-284-8200
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[email protected]
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
20
July 16, 2007
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