NSC DS25CP152TSQ 3.125 gbps lvds 2x2 crosspoint switch Datasheet

DS25CP152
3.125 Gbps LVDS 2x2 Crosspoint Switch
General Description
Features
The DS25CP152 is a 3.125 Gbps 2x2 LVDS crosspoint switch
optimized for high-speed signal routing and switching over
lossy FR-4 printed circuit board backplanes and balanced cables. Fully differential signal paths ensure exceptional signal
integrity and noise immunity. The non-blocking architecture
allows connections of any input to any output or outputs.
Wide input common mode range allows the switch to accept
signals with LVDS, CML and LVPECL levels; the output levels
are LVDS. A very small package footprint requires a minimal
space on the board while the flow-through pinout allows easy
board layout. Each differential input and output is internally
terminated with a 100Ω resistor to lower device return losses,
reduce component count and further minimize board space.
■ DC - 3.125 Gbps low jitter, low skew, low power operation
■ Pin configurable, fully differential, non-blocking
architecture
■ On-chip 100Ω input and output terminations minimize
return losses, reduce component count and minimize
board space
■ 8 kV ESD on LVDS I/O pins protects adjoining
components
■ Small 4 mm x 4 mm LLP-16 space saving package
Applications
■
■
■
■
High-speed channel select applications
Clock and data buffering and muxing
OC-48 / STM-16
SD/HD/3G HD SDI Routers
Typical Application
30021803
© 2008 National Semiconductor Corporation
300218
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DS25CP152 3.125 Gbps LVDS 2x2 Crosspoint Switch
January 17, 2008
DS25CP152
Ordering Code
NSID
Function
DS25CP152TSQ
2x2 LVDS Crosspoint Switch
Block Diagram
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Connection Diagram
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DS25CP152 Pin Diagram
Pin Descriptions
Pin Name
Pin
Number
I/O, Type
Pin Description
IN0+, IN0- ,
IN1+, IN1-
1, 2,
3, 4
I, LVDS
Inverting and non-inverting high speed LVDS input pins.
OUT0+, OUT0-,
OUT1+, OUT1-
12, 11,
10, 9
O, LVDS
Inverting and non-inverting high speed LVDS output pins.
SEL0, SEL1
7, 8
I, LVCMOS
Switch configuration pins. There is a 20 kΩ pulldown resistor on
each pin.
EN0, EN1
14, 13
I, LVCMOS
Output enable pins. There is a 20 kΩ pulldown resistor on each
pin.
NC
6, 15
I, LVCMOS
"NO CONNECT" pins.
VDD
16
Power
Power supply pin.
GND
5, DAP
Power
Ground pin and Device Attach Pad (DAP) ground.
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2
θJA
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
+41.8°C/W
θJC
ESD Susceptibility
HBM (Note 1)
Supply Voltage
−0.3V to +4V
LVCMOS Input Voltage
−0.3V to (VCC + 0.3V)
LVDS Input Voltage
−0.3V to +4V
LVDS Differential Input Voltage
0V to 1.0V
LVDS Output Voltage
−0.3V to (VCC + 0.3V)
LVDS Differential Output Voltage
0V to 1.0V
LVDS Output Short Circuit Current
5 ms
Duration
Junction Temperature
+150°C
Storage Temperature Range
−65°C to +150°C
Lead Temperature Range
Soldering (4 sec.)
+260°C
Maximum Package Power Dissipation at 25°C
SQA Package
2.99W
Derate SQA Package
23.9 mW/°C above +25°C
+6.9°C/W
≥8 kV
≥250V
≥1250V
MM (Note 2)
CDM (Note 3)
Note 1: Human Body Model, applicable std. JESD22-A114C
Note 2: Machine Model, applicable std. JESD22-A115-A
Note 3: Field Induced Charge Device Model, applicable std.
JESD22-C101-C
Recommended Operating
Conditions
Supply Voltage (VCC)
Receiver Differential Input
Voltage (VID)
Operating Free Air
Temperature (TA)
Min
3.0
0
Typ
3.3
Max
3.6
1
Units
V
V
−40
+25
+85
°C
DC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 5, 6, 7)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VCC
V
LVCMOS DC SPECIFICATIONS
VIH
High Level Input Voltage
2.0
VIL
Low Level Input Voltage
IIH
High Level Input Current
VIN = 3.6V
VCC = 3.6V
IIL
Low Level Input Current
VIN = GND
VCC = 3.6V
VCL
Input Clamp Voltage
ICL = −18 mA, VCC = 0V
GND
40
0.8
V
175
250
μA
0
±10
μA
−0.9
−1.5
V
1
V
+100
mV
LVDS INPUT DC SPECIFICATIONS
VID
Input Differential Voltage
0
VTH
Differential Input High Threshold
VTL
Differential Input Low Threshold
VCMR
Common Mode Voltage Range
VID = 100 mV
IIN
Input Current
VIN = +3.6V or 0V
VCC = 3.6V or 0V
CIN
Input Capacitance
Any LVDS Input Pin to GND
1.7
pF
RIN
Input Termination Resistor
Between IN+ and IN-
100
Ω
VCM = +0.05V or VCC-0.05V
0
−100
3
0
0.05
±1
mV
VCC 0.05
V
±10
μA
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DS25CP152
Package Thermal Resistance
Absolute Maximum Ratings (Note 4)
DS25CP152
Symbol
Parameter
Conditions
Min
Typ
Max
Units
250
350
450
mV
35
mV
1.375
V
35
mV
LVDS OUTPUT DC SPECIFICATIONS
VOD
Differential Output Voltage
ΔVOD
Change in Magnitude of VOD for Complimentary
Output States
VOS
Offset Voltage
ΔVOS
Change in Magnitude of VOS for Complimentary
Output States
RL = 100Ω
IOS
Output Short Circuit Current (Note 8)
OUT to GND
-35
-55
mA
OUT to VCC
7
55
mA
RL = 100Ω
-35
1.05
1.2
-35
COUT
Output Capacitance
Any LVDS Output Pin to GND
1.2
pF
ROUT
Output Termination Resistor
Between OUT+ and OUT-
100
Ω
SUPPLY CURRENT
ICC
Supply Current
EN0 = EN1 = High
64
77
mA
ICCZ
Supply Current with Outputs Disabled
EN0 = EN1 = Low
23
29
mA
Note 4: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions.
Note 5: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 6: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD and
ΔVOD.
Note 7: Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not guaranteed.
Note 8: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
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4
Over recommended operating supply and temperature ranges unless otherwise specified (Notes 9, 10)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
340
500
ps
344
500
ps
LVDS OUTPUT AC SPECIFICATIONS
tPLHD
Differential Propagation Delay Low to
High (Note 11)
tPHLD
Differential Propagation Delay High to
Low (Note 11)
tSKD1
Pulse Skew |tPLHD − tPHLD|
(Notes 11, 12)
4
35
ps
tSKD2
Channel to Channel Skew
(Notes 11, 13)
12
40
ps
tSKD3
Part to Part Skew
(Notes 11, 14)
50
150
ps
tLHT
Rise Time (Note 11)
65
120
ps
tHLT
Fall Time (Note 11)
65
120
ps
tON
Output Enable Time
ENn = LH to output active
7
20
μs
tOFF
Output Disable Time
ENn = HL to output inactive
5
12
ns
tSEL
Select Time
SELn LH or HL to output
3.5
12
ns
Random Jitter (RMS Value)
(Note 15)
VID = 350 mV
VCM = 1.2V
Clock (RZ)
2.5 Gbps
0.5
1
ps
3.125 Gbps
0.5
1
ps
Deterministic Jitter (Peak to Peak)
(Note 16)
VID = 350 mV
VCM = 1.2V
K28.5 (NRZ)
2.5 Gbps
8
25
ps
3.125 Gbps
3
19
ps
Total Jitter (Peak to Peak)
(Note 17)
VID = 350 mV
VCM = 1.2V
PRBS-23 (NRZ)
2.5 Gbps
0.04
0.08
UIP-P
3.125 Gbps
0.03
0.09
UIP-P
RL = 100Ω
RL = 100Ω
JITTER PERFORMANCE (Note 11)
tRJ1
tRJ2
tDJ1
tDJ2
tTJ1
tTJ2
Note 9: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 10: Typical values represent most likely parametric norms for VCC = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not guaranteed.
Note 11: Specification is guaranteed by characterization and is not tested in production.
Note 12: tSKD1, |tPLHD − tPHLD|, Pulse Skew, is the magnitude difference in differential propagation delay time between the positive going edge and the negative
going edge of the same channel.
Note 13: tSKD2, Channel to Channel Skew, is the difference in propagation delay (tPLHD or tPHLD) among all output channels in Broadcast mode (any one input to
all outputs).
Note 14: tSKD3, Part to Part Skew, is defined as the difference between the minimum and maximum differential propagation delays. This specification applies to
devices at the same VCC and within 5°C of each other within the operating temperature range.
Note 15: Measured on a clock edge with a histogram and an acummulation of 1500 histogram hits. Input stimulus jitter is subtracted geometrically.
Note 16: Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is subtracted
algebraically.
Note 17: Measured on an eye diagram with a histogram and an acummulation of 3500 histogram hits. Input stimulus jitter is subtracted.
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DS25CP152
AC Electrical Characteristics
DS25CP152
DC Test Circuits
30021820
FIGURE 1. Differential Driver DC Test Circuit
AC Test Circuits and Timing Diagrams
30021821
FIGURE 2. Differential Driver AC Test Circuit
30021822
FIGURE 3. Propagation Delay Timing Diagram
30021823
FIGURE 4. LVDS Output Transition Times
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The DS25CP152 is a 3.125 Gbps 2x2 LVDS digital crosspoint
switch optimized for high-speed signal routing and switching
over lossy FR-4 printed circuit board backplanes and balanced cables.
TABLE 1. Switch Configuration Truth Table
S1
S0
OUT1
OUT0
0
0
IN0
IN0
0
1
IN0
IN1
1
0
IN1
IN0
1
1
IN1
IN1
TABLE 2. Output Enable Truth Table
EN1
EN0
OUT1
OUT0
0
0
Disabled
Disabled
0
1
Disabled
Enabled
1
0
Enabled
Disabled
1
1
Enabled
Enabled
7
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DS25CP152
Functional Description
DS25CP152
drivers (i.e. LVPECL, LVDS, CML). The following three figures illustrate typical DC-coupled interface to common differential drivers. Note that the DS25CP152 inputs are internally
terminated with a 100Ω resistor.
Input Interfacing
The DS25CP152 accepts differential signals and allows simple AC or DC coupling. With a wide common mode range, the
DS25CP152 can be DC-coupled with all common differential
30021831
Typical LVDS Driver DC-Coupled Interface to DS25CP152 Input
30021832
Typical CML Driver DC-Coupled Interface to DS25CP152 Input
30021833
Typical LVPECL Driver DC-Coupled Interface to DS25CP152 Input
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8
The DS25CP152 outputs signals that are compliant to the
LVDS standard. Its outputs can be DC-coupled to most common differential receivers. The following figure illustrates typical DC-coupled interface to common differential receivers
30021834
Typical DS25CP152 Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver
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DS25CP152
and assumes that the receivers have high impedance inputs.
While most differential receivers have a common mode input
range that can accomodate LVDS compliant signals, it is recommended to check respective receiver's data sheet prior to
implementing the suggested interface implementation.
Output Interfacing
DS25CP152
Typical Performance
30021851
30021850
A 3.125 Gbps NRZ PRBS-7 After 2"
Differential FR-4 Stripline
V:100 mV / DIV, H:50 ps / DIV
A 2.5 Gbps NRZ PRBS-7 After 2"
Differential FR-4 Stripline
V:100 mV / DIV, H:75 ps / DIV
30021854
30021855
Total Jitter as a Function of Input Common Mode Voltage
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Total Jitter as a Function of Data Rate
10
DS25CP152
Physical Dimensions inches (millimeters) unless otherwise noted
Order Number DS25CP152TSQ
NS Package Number SQA16A
(See AN-1187 for PCB Design and Assembly Recommendations)
11
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DS25CP152 3.125 Gbps LVDS 2x2 Crosspoint Switch
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