Cypress CY7C1041DV33 4-mbit (256 k ã 16) static ram Datasheet

CY7C1041DV33
4-Mbit (256 K × 16) Static RAM
4-Mbit (256 K × 16) Static RAM
Features
Functional Description
■
Temperature ranges
❐ Industrial: –40 °C to 85 °C
[1]
❐ Automotive-A
: –40 °C to 85 °C
[1]
❐ Automotive-E
: –40 °C to 125 °C
The CY7C1041DV33 is a high performance CMOS Static RAM
organized as 256 K words by 16-bits. To write to the device, take
chip enable (CE) and write enable (WE) inputs LOW. If byte low
enable (BLE) is LOW, then data from I/O pins (I/O0 to I/O7) is
written into the location specified on the address pins (A0 to A17).
If byte high enable (BHE) is LOW, then data from I/O pins (I/O8
to I/O15) is written into the location specified on the address pins
(A0 to A17).
■
Pin and function compatible with CY7C1041CV33
■
High speed
❐ tAA = 10 ns
■
Low active power
❐ ICC = 90 mA at 10 ns (industrial)
■
Low CMOS standby power
❐ ISB2 = 10 mA
■
2.0 V data retention
■
Automatic power-down when deselected
■
TTL compatible inputs and outputs
■
Easy memory expansion with CE and OE features
■
Available in Pb-free 48-ball VFBGA, 44-pin (400-mil) molded
SOJ, and 44-pin TSOP II Packages
To read from the device, take chip enable (CE) and output enable
(OE) LOW while forcing the write enable (WE) HIGH. If BLE is
LOW, then data from the memory location specified by the
address pins appears on I/O0 to I/O7. If BHE is LOW, then data
from memory appears on I/O8 to I/O15. See the Truth Table on
page 10 for a complete description of read and write modes.
The input and output pins (I/O0 to I/O15) are placed in a high
impedance state when the device is deselected (CE HIGH),
outputs are disabled (OE HIGH), BHE and BLE are disabled
(BHE, BLE HIGH), or during a write operation (CE LOW and WE
LOW).
The CY7C1041DV33 is available in a standard 44-pin 400-mil
wide SOJ and 44-pin TSOP II package with center power and
ground (revolutionary) pinout and a 48-ball fine-pitch ball grid
array (FBGA) package.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
Logic Block Diagram
256K × 16
SENSE AMPS
A0
A1
A2
A3
A4
A5
A6
A7
A8
ROW DECODER
INPUT BUFFER
IO0–IO7
IO8–IO15
A9
A10
A 11
A 12
A 13
A14
A15
A16
A17
COLUMN
DECODER
BHE
WE
CE
OE
BLE
Note
1. Automotive product information is preliminary.
Cypress Semiconductor Corporation
Document Number: 38-05473 Rev. *I
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 24, 2011
[+] Feedback
CY7C1041DV33
Contents
Selection Guide ................................................................ 3
Pin Configuration ............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
DC Electrical Characteristics .......................................... 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
AC Switching Characteristics ......................................... 6
Data Retention Characteristics ....................................... 7
Data Retention Waveform ................................................ 7
Switching Waveforms ...................................................... 7
Truth Table ...................................................................... 10
Document Number: 38-05473 Rev. *I
Ordering Information ...................................................... 11
Ordering Code Definitions ......................................... 11
Package Diagrams .......................................................... 12
Acronyms ........................................................................ 15
Document Conventions ................................................. 15
Units of Measure ....................................................... 15
Document History Page ................................................. 16
Sales, Solutions, and Legal Information ...................... 17
Worldwide Sales and Design Support ....................... 17
Products .................................................................... 17
PSoC Solutions ......................................................... 17
Page 2 of 17
[+] Feedback
CY7C1041DV33
Selection Guide
Description
Maximum access time
Maximum operating current
–10 (Industrial)
10
90
Maximum CMOS standby current
–10 (Automotive-A) [2]
10
–12 (Automotive-E) [2]
12
Unit
ns
90
10
95
15
mA
mA
10
Pin Configuration
Figure 1. 48-ball VFBGA (Pinout 1) [3, 4]
1
2
3
4
5
6
BLE
OE
A0
A1
A2
NC
IO 0
BHE
A3
A4
CE
IO 1
IO2
A5
A6
IO10
VSS
IO3
A17
VCC
IO4
IO 6
Figure 2. 48-ball VFBGA (Pinout 2) [3, 4]
1
2
3
4
5
6
A
BLE
OE
A0
A1
A2
NC
A
IO 8
B
IO 8
BHE
A3
A4
CE
IO 0
B
IO 9
C
IO 9
IO10
A5
A6
IO 1
IO 2
C
A7
IO11 VCC
D
VSS
IO11
A17
A7
IO3
VCC
D
NC
A16
IO12
VSS
E
VCC
IO 12
NC
A16
IO 4
VSS
E
IO 5
A14
A15
IO13
IO14
F
IO 14
IO 13
A14
A15
IO 5
IO 6
F
IO 7
NC
A12
A13
WE
IO15
G
IO 15
NC
A12
A13
WE
IO 7
G
NC
A8
A9
A10
A11
NC
H
NC
A8
A9
A10
A11
NC
H
Figure 3. 44-pin SOJ/TSOP II
A0
A1
A2
A3
A4
CE
IO0
IO1
IO2
IO3
VCC
VSS
IO4
IO5
IO6
IO7
WE
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
OE
BHE
BLE
IO15
IO14
IO13
IO12
VSS
VCC
IO11
IO10
IO9
IO8
NC
A14
A13
A12
A11
A10
Notes
2. Automotive product information is preliminary.
3. NC pins are not connected on the die.
4. Pinout 1 is compliant with CY7C1041CV33 and pinout 2 is JEDEC compliant. The difference between the two is that the higher and lower byte I/Os (I/O[7:0] and I/O[15:8]
balls) are swapped.
Document Number: 38-05473 Rev. *I
Page 3 of 17
[+] Feedback
CY7C1041DV33
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature with
power applied ........................................... –55 °C to +125 °C
Static discharge voltage............ ...............................> 2001 V
(MIL-STD-883, method 3015)
Latch-up current ..................................................... > 200 mA
Operating Range
Supply voltage on VCC relative to GND [5] ....–0.3 V to +4.6 V
DC voltage applied to outputs
in high Z State[5] ................................... –0.3 V to VCC +0.3 V
Ambient
Temperature
Range
VCC
Speed
DC input voltage[5] ................................ –0.3 V to VCC +0.3 V
Industrial
–40 °C to +85 °C 3.3 V ± 0.3 V
10 ns
Automotive-A [1]
–40 °C to +85 °C 3.3 V ± 0.3 V
10 ns
Current into outputs (LOW) ......................................... 20 mA
Automotive-E [1]
–40 °C to +125 °C 3.3 V ± 0.3 V
12 ns
DC Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
–10
(Industrial)
Min
VOH
Output HIGH voltage VCC = Min, IOH = –4.0 mA
VOL
Output LOW voltage
2.4
–
2.4
–
2.4
–
V
–
0.4
–
0.4
–
0.4
V
[5]
Input HIGH voltage
2.0
VCC + 0.3
2.0
VCC + 0.3
2.0
VCC + 0.3
V
[5]
Input LOW voltage
–0.3
0.8
–0.3
0.8
–0.3
0.8
V
VIH
VIL
VCC = Min, IOL = 8.0 mA
Max
–10
–12
(Automotive-A) [6] (Automotive-E) [6] Unit
Min
Max
Min
Max
IIX
Input leakage current GND < VI < VCC
–1
+1
–1
+1
–1
+1
μA
IOZ
Output leakage
current
GND < VOUT < VCC, output
disabled
–1
+1
–1
+1
–1
+1
μA
ICC
VCC operating
supply current
VCC = Max,
f = fMAX = 1/tRC
100 MHz
–
90
–
90
–
–
mA
83 MHz
–
80
–
80
–
95
mA
66 MHz
–
70
–
70
–
85
mA
40 MHz
–
60
–
60
–
75
mA
ISB1
Automatic CE
power-down current
—TTL inputs
Max VCC, CE > VIH
VIN > VIH or
VIN < VIL, f = fMAX
–
20
–
20
–
15
mA
ISB2
Automatic CE
power-down current
—CMOS inputs
Max VCC,
CE > VCC – 0.3 V,
VIN > VCC – 0.3 V,
or VIN < 0.3 V, f = 0
–
10
–
10
–
15
mA
Notes
5. Minimum voltage is –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns.
6. Automotive product information is preliminary.
Document Number: 38-05473 Rev. *I
Page 4 of 17
[+] Feedback
CY7C1041DV33
Capacitance[7]
Parameter
Description
CIN
Input capacitance
COUT
I/O capacitance
Test Conditions
Max
Unit
8
pF
8
pF
TA = 25 °C, f = 1 MHz, VCC = 3.3 V
Thermal Resistance[7]
Parameter
Description
ΘJA
Thermal resistance
(junction to ambient)
ΘJC
Thermal resistance
(junction to case)
Test Conditions
Still Air, soldered on a 3 × 4.5 inch,
four layer printed circuit board
FBGA
Package
SOJ
Package
TSOP II
Package
Unit
27.89
57.91
50.66
°C/W
14.74
36.73
17.17
°C/W
AC Test Loads and Waveforms
The AC test loads and waveform diagram follows.[8]
10 ns device
Z = 50 Ω
50 Ω
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
ALL INPUT PULSES
3.0V
OUTPUT
30 pF*
GND
90%
90%
10%
10%
1.5V
Rise Time: 1 V/ns
(b)
Fall Time: 1 V/ns
(a)
High-Z Characteristics
R 317Ω
3.3V
OUTPUT
R2
351Ω
5 pF
(c)
Notes
7. Tested initially and after any design or process changes that may affect these parameters.
8. AC characteristics (except high Z) are tested using the load conditions shown in AC Test Loads and Waveforms (a). High Z characteristics are tested for all speeds
using the test load shown in (c).
Document Number: 38-05473 Rev. *I
Page 5 of 17
[+] Feedback
CY7C1041DV33
AC Switching Characteristics
Over the Operating Range[9]
Parameter
Description
–10
(Industrial)
–10
(Automotive-A) [10]
–12
(Automotive-E) [10]
Min
Max
Min
Max
Min
Max
Unit
Read Cycle
tpower[11]
VCC(Typical) to the first access
100
–
100
–
100
–
μs
tRC
Read cycle time
10
–
10
–
12
–
ns
tAA
Address to data valid
–
10
–
10
–
12
ns
tOHA
Data hold from address change
3
–
3
–
3
–
ns
tACE
CE LOW to data valid
–
10
–
10
–
12
ns
tDOE
OE LOW to data valid
–
5
–
5
–
7
ns
tLZOE
OE LOW to low Z
0
–
0
–
0
–
ns
–
5
–
5
–
6
ns
3
–
3
–
3
–
ns
–
5
–
5
–
6
ns
Z[12, 13]
tHZOE
OE HIGH to high
tLZCE
CE LOW to low Z[13]
Z[12, 13]
tHZCE
CE HIGH to high
tPU
CE LOW to power-up
0
–
0
–
0
–
ns
tPD
CE HIGH to power-down
–
10
–
10
–
12
ns
tDBE
Byte enable to data valid
–
5
–
5
–
7
ns
tLZBE
Byte enable to low Z
0
–
0
–
0
–
ns
Byte disable to high Z
–
6
–
6
–
6
ns
tHZBE
Write Cycle
[14, 15]
tWC
Write cycle time
10
–
10
–
12
–
ns
tSCE
CE LOW to write end
7
–
7
–
8
–
ns
tAW
Address setup to write end
7
–
7
–
8
–
ns
tHA
Address hold from write end
0
–
0
–
0
–
ns
tSA
Address setup to write start
0
–
0
–
0
–
ns
tPWE
WE pulse width
7
–
7
–
8
–
ns
tSD
Data setup to write end
5
–
5
–
6
–
ns
tHD
Data hold from write end
0
–
0
–
0
–
ns
tLZWE
WE HIGH to low Z[13]
3
–
3
–
3
–
ns
–
5
–
5
–
6
ns
7
–
7
–
8
–
ns
Z[12, 13]
tHZWE
WE LOW to high
tBW
Byte enable to end of write
Notes
9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH
and 30-pF load capacitance.
10. Automotive product information is preliminary.
11. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access is performed.
12. tHZOE, tHZCE, tHZBE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of AC Test Loads and Waveforms. Transition is measured when the outputs enter
a high impedance state.
13. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, tHZBE is less than tLZBE, and tHZWE is less than tLZWE for any given
device.
14. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write and the transition of either of
these signals can terminate the write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the write.
15. The minimum write cycle time for Write Cycle No. 4 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document Number: 38-05473 Rev. *I
Page 6 of 17
[+] Feedback
CY7C1041DV33
Data Retention Characteristics
Over the Operating Range
Parameter
VDR
VCC for data retention
ICCDR
Data retention current
tCDR
tR
[18]
Conditions[16]
Description
Max
Unit
2.0
–
V
VCC = VDR = 2.0 V, CE > VCC – 0.3 V, Industrial
VIN > VCC – 0.3 V or VIN < 0.3 V
Auto-A [17]
–
10
mA
–
10
mA
Auto-E [17]
–
15
mA
0
–
ns
tRC
–
ns
Chip deselect to data retention time
[19]
Min
Operation recovery time
Data Retention Waveform
DATA RETENTION MODE
3.0 V
VCC
VDR > 2 V
tCDR
3.0 V
tR
CE
Switching Waveforms
Figure 4. Read Cycle No. 1[20, 21]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Notes
16. No input may exceed VCC + 0.3 V.
17. Automotive product information is preliminary.
18. Tested initially and after any design or process changes that may affect these parameters.
19. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 μs or stable at VCC(min.) > 50 μs.
20. Device is continuously selected. OE, CE, BHE, and BLE = VIL.
21. WE is HIGH for read cycle.
Document Number: 38-05473 Rev. *I
Page 7 of 17
[+] Feedback
CY7C1041DV33
Switching Waveforms
(continued)
Figure 5. Read Cycle No. 2 (OE Controlled)[22, 23]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
BHE, BLE
tLZOE
tHZCE
tDBE
tLZBE
DATA OUT
tHZBE
HIGH IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
tPD
tPU
50%
50%
IICC
CC
IISB
SB
Figure 6. Write Cycle No. 1 (CE Controlled)[24, 25]
tWC
ADDRESS
CE
tSA
tSCE
tAW
tHA
tPWE
WE
tBW
BHE, BLE
tSD
tHD
DATAI/O
Notes
22. WE is HIGH for read cycle.
23. Address valid prior to or coincident with CE transition LOW.
24. Data I/O is high impedance if OE or BHE and BLE = VIH.
25. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
Document Number: 38-05473 Rev. *I
Page 8 of 17
[+] Feedback
CY7C1041DV33
Switching Waveforms
(continued)
Figure 7. Write Cycle No. 2 (BLE or BHE Controlled)
tWC
ADDRESS
tSA
BHE, BLE
tBW
tAW
tHA
tPWE
WE
tSCE
CE
tSD
tHD
DATAI/O
Figure 8. Write Cycle No. 3 (WE Controlled, OE HIGH During Write)[26, 27]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tPWE
WE
OE
BHE, BLE
t
SD
DATA I/O
NOTE
28
tHD
DATAIN VALID
t
HZOE
Notes
26. Data I/O is high impedance if OE or BHE and BLE = VIH.
27. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
28. During this period the I/Os are in the output state and input signals should not be applied.
Document Number: 38-05473 Rev. *I
Page 9 of 17
[+] Feedback
CY7C1041DV33
Switching Waveforms
(continued)
Figure 9. Write Cycle No. 4 (WE Controlled, OE LOW)
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE, BLE
tHZWE
tSD
tHD
NOTE 29
DATA I/O
tLZWE
Truth Table
I/O0–I/O7
I/O8–I/O15
Mode
Power
CE
H
OE
X
WE
X
BLE
X
BHE
X
High Z
High Z
Power-down
Standby (ISB)
L
L
H
L
L
Data out
Data out
Read all bits
Active (ICC)
L
L
H
L
H
Data out
High Z
Read lower bits only
Active (ICC)
L
L
H
H
L
High Z
Data out
Read upper bits only
Active (ICC)
L
X
L
L
L
Data in
Data in
Write all bits
Active (ICC)
L
X
L
L
H
Data in
High Z
Write lower bits only
Active (ICC)
L
X
L
H
L
High Z
Data in
Write upper bits only
Active (ICC)
L
H
H
X
X
High Z
High Z
Selected, outputs disabled
Active (ICC)
Note
29. During this period the I/Os are in the output state and input signals should not be applied.
Document Number: 38-05473 Rev. *I
Page 10 of 17
[+] Feedback
CY7C1041DV33
Ordering Information
Speed
(ns)
10
Ordering Code
CY7C1041DV33-10BVI
12
51-85150
Package Type
48-ball VFBGA
CY7C1041DV33-10BVXI
48-ball VFBGA (Pb-free) Pinout - 1[4]
CY7C1041DV33-10BVJXI
48-ball VFBGA (Pb-free) Pinout - 2[4]
CY7C1041DV33-10VXI
10
Package
Diagram
51-85082
Operating
Range
Industrial
44-pin (400-mil) Molded SOJ (Pb-free)
CY7C1041DV33-10ZSXI
51-85087
44-pin TSOP II (Pb-free)
CY7C1041DV33-10BVXA
51-85150
48-ball VFBGA (Pb-free) Pinout - 1[4]
CY7C1041DV33-10ZSXA
51-85087
44-pin TSOP II (Pb-free)
CY7C1041DV33-12BVXE
51-85150
48-ball VFBGA (Pb-free) Pinout - 1[4]
Automotive-A [1]
Automotive-E[1]
48-ball VFBGA (Pb-free) Pinout - 2[4]
CY7C1041DV33-12BVJXE
CY7C1041DV33-12VXE
51-85082
44-pin (400-mil) Molded SOJ (Pb-free)
CY7C1041DV33-12ZSXE
51-85087
44-pin TSOP II (Pb-free)
Please contact your local Cypress sales representative for availability of these parts
Ordering Code Definitions
CY 7 C 1 04 1
D V33 - xx xxx x
Temperature Range: x = I or A or E
I = Industrial
A = Automotive-A
E = Automotive-E
Package Type: xxx = BV or BVX or BVJX or VX or ZSX
BV = 48-ball VFBGA
BVX = 48-ball VFBGA (Pb-free) Pinout - 1
BVJX = 48-ball VFBGA (Pb-free) Pinout - 2
VX = 44-pin (400-mil) Molded SOJ (Pb-free)
ZSX = 44-pin TSOP II (Pb-free)
Speed: xx = 10 ns / 12 ns
V33 = Voltage range (3 V to 3.6 V)
D = C9, 90 nm Technology
1 = Data width × 16-bits
04 = 4-Mbit density
1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
7 = SRAM
CY = Cypress
Document Number: 38-05473 Rev. *I
Page 11 of 17
[+] Feedback
CY7C1041DV33
Package Diagrams
Figure 1. 48-ball VFBGA (6 × 8 × 1 mm), 51-85150
51-85150 *F
a
Document Number: 38-05473 Rev. *I
Page 12 of 17
[+] Feedback
CY7C1041DV33
Package Diagrams (continued)
Figure 2. 44-pin (400-mil) Molded SOJ, 51-85082
51-85082 *C
Document Number: 38-05473 Rev. *I
Page 13 of 17
[+] Feedback
CY7C1041DV33
Package Diagrams (continued)
Figure 3. 44-pin TSOP II, 51-85087
51-85087 *C
Document Number: 38-05473 Rev. *I
Page 14 of 17
[+] Feedback
CY7C1041DV33
Acronyms
Document Conventions
Acronym
Description
CE
chip enable
CMOS
Complementary metal oxide semiconductor
I/O
Input/output
OE
output enable
SRAM
Static random access memory
SOJ
Small Outline J-Lead
TSOP
Thin Small Outline Package
VFBGA
Very Fine-Pitch Ball Grid Array
Document Number: 38-05473 Rev. *I
Units of Measure
Symbol
Unit of Measure
ns
nano seconds
V
Volts
µA
micro Amperes
mA
milli Amperes
mV
milli Volts
mW
milli Watts
MHz
Mega Hertz
pF
pico Farad
°C
degree Celcius
W
Watts
Page 15 of 17
[+] Feedback
CY7C1041DV33
Document History Page
Document Title: CY7C1041DV33 4-Mbit (256 K × 16) Static RAM
Document Number: 38-05473
Rev.
ECN No.
Orig. of
Change
Submission
Date
Description of Change
**
201560
SWI
See ECN
Advance Data sheet for C9 IPP
*A
233729
RKF
See ECN
1.AC, DC parameters are modified as per EROS(Spec # 01-2165)
2.Pb-free offering in the ‘Ordering information’
*B
351117
PCI
See ECN
Changed from Advance to Preliminary
Removed 15 and 20 ns Speed bin
Corrected DC voltage (min) value in maximum ratings section from - 0.5 to
- 0.3V
Redefined ICC values for Com’l and Ind’l temperature ranges
ICC (Com’l): Changed from 100, 80 and 67 mA to 90, 80 and 75 mA for 8, 10
and 12ns speed bins respectively
ICC (Ind’l): Changed from 80 and 67 mA to 90 and 85 mA for 10 and 12ns speed
bins respectively
Added Static Discharge Voltage and latch-up current spec
Added VIH(max) spec in Note# 2
Changed Note# 4 on AC Test Loads
Changed reference voltage level for measurement of Hi-Z parameters from
±500 mV to ±200 mV
Added Data Retention Characteristics/Waveform and footnote # 11, 12
Added Write Cycle (WE Controlled, OE HIGH During Write) Timing Diagram
Changed Package Diagram name from 44-Pin TSOP II Z44 to 44-Pin TSOP II
ZS44 and from 44-Pin (400-mil) Molded SOJ V34 to 44-Pin (400-mil) Molded
SOJ V44
Changed part names from Z to ZS in the Ordering Information Table
Added 8 ns Product Information
Added Pin-Free Ordering Information
Shaded Ordering Information Table
*C
446328
NXR
See ECN
Converted from Preliminary to Final
Removed -8 speed bin
Removed Commercial Operating Range product information
Included Automotive Operating Range product information
Updated Thermal Resistance table
Updated footnote #8 on High-Z parameter measurement
Updated the ordering information and replaced Package Name column with
Package Diagram in the Ordering Information Table
*D
480177
VKN
See ECN
Added -10BVI product ordering code in the Ordering Information table
*E
2541850
VKN/PYRS
07/22/08
Added -10BVJXI part
*F
2752971
VKN
08/18/2009
Added Automotive-A information
For 12 ns speed, changed ISB1 spec from 25 mA to 15 mA
For 12 ns speed, changed tDOE and tDBE specs from 6 ns to 7 ns
Updated ordering information table
*G
3034079
PRAS
09/20/2010
Added Ordering Code Definitions.
Added Acronyms and Units of Measure.
Minor edits
*H
3082285
HRP
11/09/2010
Corrected typo in Note 20.
*I
3149096
AJU
01/24/2011
No technical updates
Document Number: 38-05473 Rev. *I
Page 16 of 17
[+] Feedback
CY7C1041DV33
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC Solutions
cypress.com/go/automotive
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
cypress.com/go/memory
Optical & Image Sensing
cypress.com/go/image
PSoC
cypress.com/go/psoc
Touch Sensing
cypress.com/go/touch
USB Controllers
Wireless/RF
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2004-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05473 Rev. *I
Revised January 24, 2011
Page 17 of 17
All products and company names mentioned in this document may be the trademarks of their respective holders.
[+] Feedback
Similar pages