Integral IZD1521OA Cmos dot matrix lcd driver Datasheet

CMOS DOT MATRIX LCD DRIVER
IZD1520
FEATURES
• CMOS LSI chips
• Many command set
• Connection with CPU
• Total 80 (segment+common) drive sets
• Low power consumption - 30µW maximum at 2kHz
Can be directly coupled with 80-port or 68-port system
• Available in chip form or in 100-pin plastic QFP
external clock
• Power supply VDD - VSS : 2.4 to -7.0V
• Pin-to-Pin Replacement for SED1520 Series
VDD - V5 : 3.5 to -13.0V
DESCRIPTION
The IZD1520 family of dot matrix LCD (Liquid Crystal Display) drivers are designed for the display of characters and graphics.
The drivers generate LCD drive signals derived from bit mapped data stored in an internal RAM.
The IZD1520 family drivers incorporate innovative circuit design strategies to achieve very low power dissipation at a wide range of operating voltages.
These features give the designer a flexible means of implementing small to medium size LCD displays for compact, low power systems.
The IZD1520 which is able to drive two lines of twelve characters each.
The IZD1521 which is able to drive 80 segments for extension.
ABSOLUTE MAXIMUM RATINGS
Characteristic
Symbol
Value
Unit
VSS
- 8.0 ~ 0.3
V
Supply Voltage (2)
V5
- 16.5 ~ 0.3
V
Supply Voltage (3)
V1, V2, V3, V4
V5 ~ 0.3
V
Input Voltage
VI
VSS - 0.3 ~ 0.3
V
Output Voltage
VO
VSS - 0.3 ~ 0.3
V
Power Dissipation
PD
250
mW
Operating Temperature
Ta
- 10 ~ + 75
o
Storage Temperature
Tstg
- 65 ~ + 150
o
260
o
Supply Voltage (1)
Soldering temperature time (10 sec max)
Notes:
1.
2.
3.
Tsol
C
C
C
All voltages are specified relative to VDD = 0V.
The following relation must be always hold
VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥V5.
Exceeding the absolute maximum ratings may cause permanent damage to the device. Functional operating under these
conditions is not implied.
LINE-UP
Product
Clock Frequency
Applicable Driver
Name
On-chip
Number of
SEGMENT
Drivers
Number of
COMMON
Drivers
Duty
External
IZD1520OA
18kHz
18kHz
IZD1520OA , IZD1521OA
61
16
1/16, 1/32
IZD1521OA
-
18kHz
IZD1520OA
80
0
1/8 ~ 1/32
IZD1520AA
-
2kHz
IZD1520AA , IZD1521AA
61
16
1/16, 1/32
IZD1521AA
-
2kHz
IZD1520AA
80
0
1/8 ~ 1/32
1
CMOS DOT MATRIX LCD DRIVER
IZD1520
60
V SS
V DD
SEG
COM
0
0
to S E G
to C O M
V 1 ,V 2 ,V 3 ,V 4 ,V 5
15
BLOCK DIAGRAM IZD1520AA
L C D d rive circu it
D isp lay d ata R A M
(2560-b it)
I/O b u ffer
D isp lay d ata latch circu it
L in e ad d ress d ecod er
L in e cou nter
D isp lay start line register
C om m on cou n ter
C olu m n add ress register
C om m an d
d ecod er
S tatu s
B us
h old er
C olu m n add ress cou n ter
RES
R D ,R W
(E ,R W )
M /S
M P U in terface
A 0,C S
FR
D isp lay
tim ing
generator
circu it
D 0 -D 7
CL
L ow -add ress
register
C olu m n add ress d ecod er
2
CMOS DOT MATRIX LCD DRIVER
IZD1520
60
V SS
V DD
SEG
COM
0
0
to S E G
to C O M
V 1 ,V 2 ,V 3 ,V 4 ,V 5
15
BLOCK DIAGRAM IZD1520OA
L C D d rive circu it
D isp lay d ata R A M
(2560-b it)
I/O b u ffer
D isp lay d ata latch circu it
L in e ad d ress d ecod er
L in e cou nter
D isp lay start line register
C om m on cou n ter
C olu m n add ress register
C om m an d
d ecod er
S tatu s
B us
h old er
C olu m n add ress cou n ter
RES
R D ,R W
(E ,R W )
M /S
M P U in terface
O SC 1
FR
D isp lay
tim ing
generator
circu it
D 0 -D 7
O SC 2
L ow -add ress
register
C olu m n add ress d ecod er
3
CMOS DOT MATRIX LCD DRIVER
IZD1520
V SS
SEG
V DD
0
V 2 ,V 3 ,V
5
to S E G
79
BLOCK DIAGRAM IZD1521AA, IZD1521OA
L C D d rive circu it
D isp lay d ata R A M
(2560-b it)
I/O b u ffer
L in e ad d ress d ecod er
L in e cou nter
D isp lay start line register
D isp lay d ata latch circu it
C olu m n add ress register
C om m an d
d ecod er
S tatu s
B us
h old er
C olu m n add ress cou n ter
RES
R D ,R W
(E ,R W )
M P U in terface
A 0,C S
FR
D isp lay
tim ing
generator
circu it
D 0 -D 7
CL
L ow -add ress
register
C olu m n add ress d ecod er
4
CMOS DOT MATRIX LCD DRIVER
IZD1520
ELECTRICAL CHARACTERISTICS
(Ta = 25oC, VDD = 0V, VSS = -5.0V unless otherwise specified)
Characteristic
Operating
Symbo
l
Test Condition
Applicable Terminals
Recommended
Voltage(1)
VSS
VSS
V5
V5
Min
Typ
Max
-5.5
-5.0
-4.5
-7.0
-2.4
-13.0
-3.5
Unit
V
Note 1
Recommended
Operating
Voltage(2)
-13.0
V
Permitted
V1, V2
V1, V2
Permitted
V3, V4
V3, V4
VIH
A0,Di, E, R/W, CS
VSS+2.0
VDD
CL, FR, M/S, RES
0.2 x VSS
VDD
HIGH Input Voltage
LOW Input Voltage
HIGH Output Voltage
LOW Output Voltage
VIL
VOH
VOL
Input Leakage Current
ILI
Output Leakage Current
ILO
LCD Driver ON Resistance
Supply Current, Dynamic
VDD
V5
0.4xV5
A0, Di, E, R/W, CS
VSS
VSS+0.8
CL, FR, M/S, RES
VSS
0.8+VSS
IOH = -3.0 mA
D0 ÷ D7
VSS+2.4
IOH = -2.0 mA
FR
VSS+2.4
IOH = -120 µA
OSC2
0.2 x VSS
IOL = 3.0 mA
D0 ÷ D7
VSS+0.4
IOL = 2.0 mA
FR
VSS+0.4
IOL = 120µA
OSC2
0.8xVSS
A0, E, R/W, CS, CL,
M/S, RES
-1.0
Outputs are high impedance
D0 ÷ D7, FR
-3.0
RON
V5=-5.0V
SEG0 ~ SEG79
IDDQ
CS = CL = VDD
Note 2
Supply Current, Static
0.6 x V5
V
V
V
1.0
V
µA
3.0
µA
5.0
7.5
KΩ
0.05
1.0
µA
2.0
5.0
9.5
15.0
5.0
10.0
300
500
µA
5.0
8.0
pF
21
KHz
1000
µs
COM0 ~ COM15
IDD
During
fCL=2kHz
Note 3
display
Rf =1MΩ
V5=-5.0V
Note 4
VDD
VDD
fCL=18KHz
µA
Note 5
During access fcyc=200KHz
Input Terminal Capacity
CIN
f = 1 MHz
Oscillator Frequency
fOSC
Rf =1MΩ±2%
Reset Time
tR
All inputs
15
RES
18
1.0
Notes: 1. Operating over the specified voltage range is guaranteed, except where the supply voltage changes suddenly during
CPU access.
2. For a voltage differential of 0.1V between input (V1, …, V4) and output (COM, SEC) pins. All voltages within specified
operating voltage range.
3.
IZD1520AA and IZD1521AA only. Does not include transient currents due to stray and panel capacitances.
4.
IZD1521OA only. Does not include transient currents due to stray and panel capacitances.
5.
IZD1520OA only. Does not include transient currents due to stray and panel capacitances.
5
CMOS DOT MATRIX LCD DRIVER
IZD1520
• Read/Write timing for the 80-port MPU
Characteristic
Symbol
Signal
Condition
Address hold time
tAH8
A0, CS
Address setup time
tAW8
System cycle time
tCYC8
1000
ns
Control pulse width
tCC8
200
ns
Data setup time
tDS8
80
ns
Data hold time
tDH8
10
VDD access time
tACC8
Output Disable time
tOH8
Low-level pulsewidth
tWLCL
High-level pulsewidth
tWHCL
WR, RD
Min
Typ
10
ns
ns
ns
10
90
ns
60
ns
µs
35
CL
Unit
20
D0 ÷ D7
CL = 100pF
Max
µs
35
Rise time
tr
30
150
Fall time
tf
30
150
ns
0.2
2.0
µs
0.2
2.0
µs
Typ
Max
Unit
FR delay time
Note 1
tFDR
FR (Input)
FR delay time
Note 2
tFDR
FR (Input)
-2.0
ns
• Read/Write timing for the 68-port MPU
Characteristic
Symbol
Signal
Condition
Min
System cycle time
tCYC6
A0
1000
Address setup time
tAW6
R/W
20
ns
Address hold time
tAH6
10
ns
Data setup time
tDS6
80
ns
Data hold time
tDH6
10
Output disable time
tOH6
Access time
tACC6
Enable
READ
pulse width
WRITE
tEW
Low-level pulsewidth
tWLCL
High-level pulsewidth
tWHCL
D0 ÷ D7
ns
ns
10
CL = 100pF
E
CL
60
ns
90
ns
100
ns
80
ns
35
µs
µs
35
Rise time
tr
30
150
Fall time
tf
30
150
ns
0.2
2.0
µs
0.2
2.0
µs
FR delay time
Note 1
tFDR
FR (Input)
FR delay time
Note 2
tFDR
FR (Input)
-2.0
* The rating when VSS = -3.0V are approximately 100% higher that when VSS = -5.0V
Notes: 1. The listed input tFDR applies to IZD1520 and IZD1521 in slave mode.
2. The listed input tFDR applies to IZD1520 and IZD1521 in master mode.
6
ns
CMOS DOT MATRIX LCD DRIVER
IZD1520
• Timing Chart
• Read/Write timing for the 80-port MPU
tA H 8
A O , CS
tA W
tC Y C 8
8
W R, RD
tC C 8
tD S 8
tD H 8
D 0~D 7
(W R IT E )
tO H 8
tA C C 8
D 0~D 7
(R E A D )
• Read/Write timing for the 68-port MPU
• Read/Write timing for the 80-port/68-port display
CL
tW
tW
H CL
tf
LCL
tr
tD F R
FR
7
CMOS DOT MATRIX LCD DRIVER
IZD1520
TERMINAL DESCRIPTION
Terminal Name
D0 ÷ D7
A0
Function
Data I/O
Select display data or functions.
HIGH: Display data
LOW : Instructions
Resets the system and selects the interface type for a 68-port/80-port MPU
RES
HIGH: 68-port MPU interface
LOW : 80-port MPU interface
CS
Input. Active low. Effective for an external clock operation model only.
Chip Select input
OSC1
E
(RD)
LOW : Active level sensing
Read/Write Enable signal when a 68-port MPU is connected.
(Active LOW Read Enable signal when an 80-port MPU is connected)
Read/Write Select signal when a 68-port MPU is connected.
R/W
HIGH: Read Select
LOW : Write Select
(WR)
CL
OSC2
FR
SEGn
COMn
(Active LOW Write Enable input when an 80-port MPU is connected Rising edge sensing)
Input. Effective for an external clock operation model only.
External clock input (only effective with external clock types)
LCD Frame (AC- conversion) signal input/output
Segment output for driving the LCD
Common output for driving the LCD
M/S
Master/Slave Select signal
VDD
5V power supply
VSS
0V power supply (GND level)
V1, V2, V3, V4, V5
Power supplies for driving the LCD. VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5
8
CMOS DOT MATRIX LCD DRIVER
IZD1520
DISPLAY COMMANDS
(Based on the 80-port MPU; the RD and WR commands differ for the 68-port MPU)
Command
RD WR A0
D7 D6 D5 D4 D3 D2 D1 D0
1
Display ON/OFF
1
0
0
1
0
1
0
1
1
1
0/1
2
Display START Line
1
0
0
1
1
0
Display START
3
Page Address Set
1
0
0
1
0
1
4
Column (Segment)
Address Set
1
0
0
0
Column address
5
Status Read
0
1
0
1
0
Switches the entire display ON or OFF regardless of
the Display RAM’s data or the internal status. *Note
Determines the line of RAM data to be displayed at the
display’s top line (COM0)
address (0 ÷ 31)
1
Function
Page
Sets the page of the Display RAM in the page address
register
Sets the column address of the Display RAM in the
column address register
(0 ÷ 79)
Reads the status.
BUSY 1: Busy (internal processing) 0: READY
status
ADC
1: Rightward (forward) output
0: Leftward (reverse) output
0
0
0
0
ON/OFF 1: Display OFF
0: Display ON
RESET 1: Resetting
0: Normal
6
Write Display Data
1
0
1
Write Data
Writes the data on the
data bus to RAM
These commands access a
previously specified
address
7
Read Display Data
0
1
1
Read Data
Reads data from the
Display RAM onto the
data bus
of the Display RAM,
after which the column
address is incremented
one
8
ADC Select
1
0
0
1
0
1
0
0
0
0
0/1
Used to reverse the correspondence between the
Display RAM’s column addresses and segment driver
output ports
0: Rightward (forward) output 1: Leftward (reverse)
9
Static Drive ON/OFF
1
0
0
1
0
1
0
0
1
0
0/1
Selects normal display operation or static all-fit drive
display operation
10
Duty Select
1
0
0
1
0
1
0
1
0
0
0/1
Selects the duty factor for driving LCD cells
11
Read Modify Write
1
0
0
1
1
1
0
0
0
0
0
Increments the column address counter by one only
when display data is written but not when it is read
12
End
1
0
0
1
1
1
0
1
1
1
0
Cancels the Ready Modify Write mode
13
Reset
1
0
0
1
1
1
0
0
0
1
0
Resets the Display START line to the 1-st line in the
register.
1: Static drive (Power Save) 0: Normal display
1: 1/32 duty
0: 1/16 duty
Resets the column address counter and page address
register to 0.
Note: Power Save mode is entered by selecting static drive in the Display OFF status.
9
CMOS DOT MATRIX LCD DRIVER
IZD1520
REFERENCE CIRCUITRY EXAMPLES
• 16 x 61 dots
• 16 x 141 dots
1 /1 6 d u ty
1 /1 6 d u ty
1
LC D C e ll
1 6 x 6 1 d o ts
1 - 61
16
1
LC D C e ll
1 6 x 1 4 1 d o ts
16 1 -61
62 -141
SEG
SEG
SEG
COM
COM
VD D
VD D
M /S
M /S
M /S
O SC 1
A0
D
O SC 2
D
A 0 O SC 1 O SC 2 FR
Rf
M PU
DB
A0
CL
Rf
M PU
CB
CB
FR
DB
A0
A0
• 32 x 202 dots
1
16
1 /3 2 D u ty
LC D C e ll
3 2 x 2 0 2 d o ts
1 - 16
6 2 -1 4 1
SEG
SEG
17
32
142 - 202
SEG
COM
COM
VDD
M /S
M /S
D
A 0 O SC 1 O SC 2 FR
FR
D
A0
CL
FR
M /S
D
A0
CL
FR
M PU
CB
DB
A0
Note: If a system has two or more slave drivers a CMOS buffer will be required for clock signal.
10
D
CMOS DOT MATRIX LCD DRIVER
IZD1520
PAD LAYOUT
(6 5 0 0 , 5 0 0 0 )
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
81
50
82
49
83
48
84
47
85
46
86
45
87
44
Y
88
43
89
42
90
41
(0 ,0 )
X
91
40
92
PA D
D IA G
C h ip size :
Pa d size :
U nit
:
93
94
39
R A M IZD 1 5 2 0
6 50 0 x 5 00 0
1 20 x 1 2 0
µm
38
37
95
36
96
35
97
34
98
33
99
32
100
1
31
2
3
4
5
6
7
8
9
10
11
12
13
14
PAD LOCATION
Pad
No.
Pad Name
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
( Unit: µm)
X
Y
Pad
No.
Pad Name
X
Y
Pad
No.
Pad Name
1
COM5
-2994
-2243
35
SEG37
3010
-1100
69
SEG3
2
COM6
-2717
-2244
36
SEG36
3010
-892
70
SEG2
3
COM7
-2510
-2244
37
SEG35
3010
-722
71
SEG1
4
COM8
-2302
-2244
38
SEG34
3010
-515
72
SEG0
5
COM9
-2132
-2244
39
SEG33
3010
-344
73
A0
6
COM10
-1924
-2244
40
SEG32
3010
-136
74
OSC1 [CS]
7
COM11
-1754
-2244
41
SEG31
3010
33
75
OSC2 [CL]
8
COM12
-1547
-2244
42
SEG30
3010
241
76
E [RD]
9
COM13
-1377
-2244
43
SEG29
3010
412
77
R/W (WR)
10
COM14
-1167
-2244
44
SEG28
3010
620
78
GND
11
COM15
-998
-2244
45
SEG27
3010
790
79
DB0
12
SEG60
-790
-2244
46
SEG26
3010
998
80
DB1
13
SEG59
-620
-2244
47
SEG25
3010
1170
81
DB2
14
SEG58
-413
-2244
48
SEG24
3010
1376
82
DB3
15
SEG57
-242
-2244
49
SEG23
3010
1544
83
DB4
16
SEG56
-35
-2244
50
SEG22
3010
1754
84
DB5
17
SEG55
135
-2244
51
SEG21
3010
2242
85
DB6
18
SEG54
344
-2244
52
SEG20
1494
2242
86
DB7
19
SEG53
514
-2244
53
SEG19
2434
2242
87
VCC
20
SEG52
722
-2244
54
SEG18
2226
2242
88
RES
21
SEG51
892
-2244
55
SEG17
2056
2242
89
FR
22
SEG50
1100
-2244
56
SEG16
1848
2242
90
V5
23
SEG49
1270
-2244
57
SEG15
1678
2242
91
V3
24
SEG48
1478
-2244
58
SEG14
1470
2242
92
V2
25
SEG47
1607
-2244
59
SEG13
1300
2242
93
M/S
26
SEG46
1856
-2244
60
SEG12
1012
2242
94
V4
27
SEG45
2026
-2244
61
SEG11
922
2242
95
V1
28
SEG44
2234
-2244
62
SEG10
714
2242
96
COM0
29
SEG43
2477
-2244
63
SEG9
544
2242
97
COM1
30
SEG42
3020
-2244
64
SEG8
336
2242
98
COM2
31
SEG41
3010
-1857
65
SEG7
166
2242
99
COM3
32
SEG40
3010
-1648
66
SEG6
-42
2242
100
COM4
33
SEG39
3010
-1474
67
SEG5
-213
2242
34
SEG38
3010
-1270
68
SEG4
-420
2242
Note: Pads 74,75 are OSC1, OSC2 for BT5150OA and CS, CL for IZ1520AA respectively. All other pad names are identical.
X
Y
-650
-798
-968
-1177
-1368
-1569
-1761
-1953
-2142
-2348
-2646
-3009
-3009
-3009
-3009
-3009
-3009
-3009
-3009
-3009
-3009
-3009
-3009
-3009
-3009
-3009
-3009
-2994
-2994
-2994
-2994
-2994
2242
2242
2242
2242
2242
2242
2242
2242
2242
2242
2242
2242
1895
1695
1497
1297
1097
916
737
542
342
162
-18
-198
-398
-603
-806
-996
-1166
-1375
-1544
-1753
11
CMOS DOT MATRIX LCD DRIVER
IZD1520
PAD LAYOUT
(6 5 0 0 , 5 0 0 0 )
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
81
50
82
49
83
48
84
47
85
46
86
45
87
44
Y
88
43
89
42
90
41
(0 ,0 )
X
91
40
92
PA D
D IA G
C h ip size :
Pa d size :
U nit
:
93
94
95
39
R A M IZD 1 52 1
6 50 0 x 5 00 0
1 20 x 1 2 0
µm
38
37
36
96
35
97
34
98
33
99
32
100
1
31
2
3
4
5
6
7
8
9
10
11
12
13
14
PAD LOCATION
Pad
No.
Pad Name
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
( Unit: µm)
X
Y
Pad
No.
Pad Name
X
Y
Pad
No.
Pad Name
X
Y
1
2
3
4
5
SEG71
SEG70
SEG69
SEG68
SEG67
-2994
-2717
-2510
-2302
-2132
-2243
-2244
-2244
-2244
-2244
35
36
37
38
39
SEG37
SEG36
SEG35
SEG34
SEG33
3010
3010
3010
3010
3010
-1100
-892
-722
-515
-344
69
70
71
72
73
SEG3
SEG2
SEG1
SEG0
A0
-650
-798
-968
-1177
-1368
2242
2242
2242
2242
2242
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
SEG66
SEG65
SEG64
SEG63
SEG62
SEG61
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
SEG41
SEG40
SEG39
SEG38
-1924
-1754
-1547
-1377
-1167
-998
-790
-620
-413
-242
-35
135
344
514
722
892
1100
1270
1478
1607
1856
2026
2234
2477
3020
3010
3010
3010
3010
-2244
-2244
-2244
-2244
-2244
-2244
-2244
-2244
-2244
-2244
-2244
-2244
-2244
-2244
-2244
-2244
-2244
-2244
-2244
-2244
-2244
-2244
-2244
-2244
-2244
-1857
-1648
-1474
-1270
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
3010
3010
3010
3010
3010
3010
3010
3010
3010
3010
3010
3010
1494
2434
2226
2056
1848
1678
1470
1300
1012
922
714
544
336
166
-42
-213
-420
-136
33
241
412
620
790
998
1170
1376
1544
1754
2242
2242
2242
2242
2242
2242
2242
2242
2242
2242
2242
2242
2242
2242
2242
2242
2242
2242
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
CS
CL
E RD
R/W (WR)
GND
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
VCC
RES
FR
V5
V3
V2
SEG79
SEG78
SEG77
SEG76
SEG75
SEG74
SEG73
SEG72
-1569
-1761
-1953
-2142
-2348
-2646
-3009
-3009
-3009
-3009
-3009
-3009
-3009
-3009
-3009
-3009
-3009
-3009
-3009
-3009
-3009
-3009
-2994
-2994
-2994
-2994
-2994
2242
2242
2242
2242
2242
2242
2242
1895
1695
1497
1297
1097
916
737
542
342
162
-18
-198
-398
-603
-806
-996
-1166
-1375
-1544
-1753
12
CMOS DOT MATRIX LCD DRIVER
IZD1520
13
Similar pages