Renesas HD74HC193FPEL Synchronous up/down decade counter (dual clock lines) Datasheet

HD74HC192, HD74HC193
Synchronous Up/Down Decade Counter (Dual Clock Lines)
Synchronous Up/Down 4-bit Binary Counter (Dual Clock Lines)
REJ03D0588-0300
Rev.3.00
Jan 31, 2006
Description
The HD74HC192 is a decade counter, and the HD74HC193 is a binary counter. Both counters have two separate clock
inputs, an up count input and a down count input. All outputs of the flip-flops are simultaneously triggered on the low
to high transition of either clock while the other input is held high. The direction of counting is determined by which
input is clocked.
These counters may be preset by entering the desired data on the data A, data B, data C, and data D inputs. When the
load input is taken low the data is loaded independently of either clock input. This feature allows the counters to be
used as divide-by-n counters by modifying the count length with the preset inputs.
In addition both counters can also be cleared. This is accomplished by inputting a high on the clear input. All 4 internal
stages are set to a low level independently of either count input.
Both a borrow and carry output are provided to enable cascading of both up and down counting functions. The borrow
output produces a negative going pulse when the counter underflows and the carry outputs a pulse when the counter
overflows. The counters can be cascaded by connecting the carry and borrow outputs of one device to the count up and
count down inputs, respectively, of the next device.
Features
•
•
•
•
•
•
High Speed Operation: tpd (Clock Up or Count Down to Q) = 21 ns typ (CL = 50 pF)
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: VCC = 2 to 6 V
Low Input Current: 1 µA max
Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
HD74HC192P
PRDP0016AE-B
DILP-16 pin
P
(DP-16FV)
HD74HC193P
HD74HC192FPEL
PRSP0016DH-B
SOP-16 pin (JEITA)
FP
(FP-16DAV)
HD74HC193FPEL
Note: Please consult the sales office for the above package availability.
Rev.3.00, Jan 31, 2006 page 1 of 13
Taping Abbreviation
(Quantity)
—
EL (2,000 pcs/reel)
HD74HC192, HD74HC193
Pin Arrangement
Data B
1
Input
QB 2
QB
QA 3
QA
B
A
15 Data A
Inputs
Outputs
Inputs
16 VCC
Clear
14 Clear
Count
Down
4
Count
Borrow
Down
13 Borrow
Count
Up
5
Count
Up
Carry
12 Carry
QC 6
QC
Load
11 Load
QD 7
QD
Outputs
Outputs
D
C
9 Data D
GND 8
(Top view)
Rev.3.00, Jan 31, 2006 page 2 of 13
10 Data C
Inputs
HD74HC192, HD74HC193
Timing Chart
HD74HC192
Illustrated below is the following sequence:
1.
2.
3.
4.
Clear outputs to zero.
Load (preset) to binary seven.
Count up to eight, nine, zero, one and two.
Count down to one, zero, borrow, nine, eight and seven.
Clear
Load
A
Data
Inputs
B
C
D
Count Up
Count Down
QA
QB
QC
QD
Carry
Borrow
8
Sequence
Illustrated
0
7
Clear
Preset
Rev.3.00, Jan 31, 2006 page 3 of 13
9
0
Count Up
1
2
1
0
9
Count Down
8
7
HD74HC192, HD74HC193
Timing Chart
HD74HC193
Illustrated below is the following sequence:
1.
2.
3.
4.
Clear outputs to zero.
Load (preset) to binary thirteen.
Count up to fourteen, fifteen, zero, one and two.
Count down to one, zero, borrow, fifteen and thirteen.
Clear
Load
A
Data
Inputs
B
C
D
Count Up
Count Down
QA
QB
Outputs
QC
QD
Carry
Borrow
0
13
Clear
Preset
14
15
0
Count Up
Rev.3.00, Jan 31, 2006 page 4 of 13
1
2
1
0
15
14
Count Down
13
HD74HC192, HD74HC193
Logic Diagram
HD74HC192
Count
Down
Borrow
Count
Up
Carry
CK
R
Q
CK
S
Q
QA
Data A
CK
R
Q
CK
S
Q
QB
Data B
CK
R
Q
CK
S
Q
QC
Data C
CK
R
Q
CK
S
Q
QD
Data D
Load
Clear
HD74HC193
Count
Down
Borrow
Count
Up
Carry
CK
R
Q
CK
S
Q
QA
Data A
CK
R
Q
CK
S
Q
QB
Data B
CK
R
Q
CK
S
Q
QC
Data C
CK
R
Q
CK
S
Q
QD
Data D
Load
Clear
Rev.3.00, Jan 31, 2006 page 5 of 13
HD74HC192, HD74HC193
Absolute Maximum Ratings
Item
Supply voltage range
Input / Output voltage
Input / Output diode current
Output current
VCC, GND current
Power dissipation
Storage temperature
Symbol
VCC
Vin, Vout
IIK, IOK
IO
ICC or IGND
PT
Tstg
Ratings
–0.5 to 7.0
–0.5 to VCC +0.5
±20
±25
±50
500
–65 to +150
Unit
V
V
mA
mA
mA
mW
°C
Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of
which may be realized at the same time.
Recommended Operating Conditions
Item
Supply voltage
Input / Output voltage
Operating temperature
Symbol
VCC
VIN, VOUT
Ta
Input rise / fall time*1
Ratings
2 to 6
0 to VCC
–40 to 85
0 to 1000
0 to 500
tr, tf
Unit
V
V
°C
ns
0 to 400
Note:
Conditions
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
1. This item guarantees maximum limit when one input switches.
Waveform: Refer to test circuit of switching characteristics.
Electrical Characteristics
Item
Input voltage
Symbol VCC (V)
VIH
VIL
Output voltage
VOH
VOL
Input current
Quiescent supply
current
Iin
ICC
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
Rev.3.00, Jan 31, 2006 page 6 of 13
Min
1.5
3.15
4.2
—
—
—
1.9
4.4
5.9
4.18
5.68
—
—
—
—
—
—
—
Ta = 25°C
Typ Max
—
—
—
—
—
—
2.0
4.5
6.0
—
—
0.0
0.0
0.0
—
—
—
—
—
—
—
0.5
1.35
1.8
—
—
—
—
—
0.1
0.1
0.1
0.26
0.26
±0.1
4.0
Ta = –40 to+85°C
Unit
Min
Max
1.5
3.15
4.2
—
—
—
1.9
4.4
5.9
4.13
5.63
—
—
—
—
—
—
—
—
—
—
0.5
1.35
1.8
—
—
—
—
—
0.1
0.1
0.1
0.33
0.33
±1.0
40
Test Conditions
V
V
V
V
Vin = VIH or VIL IOH = –20 µA
Vin = VIH or VIL
IOH = –4 mA
IOH = –5.2 mA
IOL = 20 µA
IOL = 4 mA
IOL = 5.2 mA
µA Vin = VCC or GND
µA Vin = VCC or GND, Iout = 0 µA
HD74HC192, HD74HC193
Switching Characteristics
(CL = 50 pF, Input tr = tf = 6 ns)
Item
Symbol VCC (V)
Maximum clock
frequency
fmax
Propagation delay
time
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPHL
Pulse width
tw
Hold time
th
Setup time
tsu
Removal time
trem
Output rise/fall
time
tTLH, tTHL
Input capacitance
Cin
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
—
Rev.3.00, Jan 31, 2006 page 7 of 13
Ta = 25°C
Ta = –40 to +85°C
Unit
Min
Typ Max
Min
Max
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
80
16
14
5
5
5
100
20
17
50
10
9
—
—
—
—
—
—
—
—
14
—
—
15
—
—
14
—
—
15
—
—
21
—
—
21
—
—
17
—
—
23
—
—
24
—
—
8
–
—
–3
—
—
4
—
—
–1
—
—
5
—
5
4
20
24
140
28
24
130
26
22
130
26
22
130
26
22
215
43
37
275
55
47
230
46
39
290
58
49
265
53
45
—
—
—
—
—
—
—
—
—
—
—
—
75
15
13
10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
100
20
17
5
5
5
125
25
21
65
13
11
—
—
—
—
3
16
19
175
35
30
165
33
28
165
33
28
165
33
28
270
54
46
345
69
59
290
58
49
365
73
62
335
66
56
—
—
—
—
—
—
—
—
—
—
—
—
95
19
16
10
Test Conditions
MHz
ns
Count up to Carry
ns
Count down to Borrow
ns
Count up or down to Q
ns
Load to Q
ns
Clear to Q
ns
ns
Data to Load
ns
Data to Load
ns
Clear to Clock
ns
pF
HD74HC192, HD74HC193
Test Circuit
VCC
VCC
Load
See Function Table
Input
Pulse Generator
Zout = 50 Ω
Output
Borrow
Up
Output
CL = 50 pF
Down
Carry
Clear
Output
A
CL = 50 pF
B
QA to QD
C
D
CL = 50 pF
Note : 1. CL includes probe and jig capacitance.
Waveforms
• Waveform – 1 (HD74HC192)
tr
tf
VCC
Count
Up
50%
50%
tw (H)
(Measure at tn+1)
QA
50%
50%
0V
tw (L)
tPLH
tPHL (Measure at tn+2)
90%
50%
10%
VOH
90%
50%
10%
tTLH
tTHL
tPHL (Measure at tn+4)
VOL
tPLH (Measure at tn+2)
90%
50%
10%
90%
50%
10%
QB
tTHL
tPHL (Measure at tn+8)
tTHL
tPHL (Measure at tn+10)
90%
50%
10%
QD
(Measure before
1 clock of tn+10)
tTHL
tPHL
tPLH
90%
50%
10%
Carry
tTHL
tPLH (Measure at tn+4)
90%
50%
10%
VOH
VOL
tTLH
tPLH
(Measure at tn+8)
90%
50%
10%
VOH
VOL
tTLH
(Measure at tn+10)
90%
50%
VOH
VOL
tTLH
Notes : 1. Input pulse : PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns
2. tn is reference bit time when all outputs are low.
Rev.3.00, Jan 31, 2006 page 8 of 13
VOL
tTLH
90%
50%
10%
QC
VOH
HD74HC192, HD74HC193
• Waveform – 2 (HD74HC192)
tr
Count
Down
tf
VCC
50%
50%
tw (H)
tw (L)
50%
50%
0V
tPLH (Measure at tn+0)
tPHL (Measure at tn+1)
VOH
QA
50%
50%
VOL
tPLH (Measure at tn+2)
tPHL (Measure at tn+4)
VOH
50%
50%
QB
VOL
tPLH (Measure at tn+2)
tPHL (Measure at tn+6)
VOH
50%
QC
50%
VOL
tPLH (Measure at tn+0)
tPHL (Measure at tn+2)
VOH
50%
QD
50%
VOL
(Measure before
1 clock of tn+0)
Borrow
tPHL
tPLH (Measure at tn+0)
90%
50%
90%
50%
10%
tTHL
VOL
tTLH
Notes : 1. Input pulse : PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns
2. tn is reference bit time when outputs are H, L, L, H
Rev.3.00, Jan 31, 2006 page 9 of 13
VOH
HD74HC192, HD74HC193
• Waveform – 3 (HD74HC193)
tr
tf
VCC
Count
Up
50%
50%
tw (H)
(Measure at tn+1)
QA
50%
50%
0V
tw (L)
tPLH
tPHL (Measure at tn+2)
90%
50%
10%
VOH
90%
50%
10%
tTLH
tTHL
tPHL (Measure at tn+4)
VOL
tPLH (Measure at tn+2)
90%
50%
10%
90%
50%
10%
QB
tTHL
tPHL (Measure at tn+8)
tTHL
tPHL (Measure at tn+16)
90%
50%
10%
QD
(Measure before
1 clock of tn+16)
tTHL
tPHL
tPLH
90%
50%
10%
Carry
tTHL
tPLH (Measure at tn+4)
90%
50%
10%
VOH
VOL
tTLH
tPLH
(Measure at tn+8)
90%
50%
10%
VOH
VOL
tTLH
(Measure at tn+16)
90%
50%
VOH
VOL
tTLH
Notes : 1. Input pulse : PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns
2. tn is reference bit time when all outputs are low.
Rev.3.00, Jan 31, 2006 page 10 of 13
VOL
tTLH
90%
50%
10%
QC
VOH
HD74HC192, HD74HC193
• Waveform – 4 (HD74HC193)
tr
Count
Down
tf
VCC
50%
50%
tw (H)
tw (L)
50%
50%
0V
tPLH (Measure at tn+0)
tPHL (Measure at tn+1)
VOH
QA
50%
50%
VOL
tPLH (Measure at tn+0)
tPHL (Measure at tn+2)
VOH
50%
50%
QB
VOL
tPLH (Measure at tn+0)
tPHL (Measure at tn+4)
VOH
50%
QC
50%
VOL
tPLH (Measure at tn+0)
tPHL (Measure at tn+8)
VOH
50%
QD
50%
VOL
(Measure before
1 clock of tn+0)
Borrow
tPHL
tPLH (Measure at tn+0)
90%
50%
90%
50%
10%
tTHL
VOL
tTLH
Notes : 1. Input pulse : PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns
2. tn is reference bit time when outputs are H, L, L, H
Rev.3.00, Jan 31, 2006 page 11 of 13
VOH
HD74HC192, HD74HC193
• Waveform – 5
tr
Clear
tf
90 %
50 % 50 %
10 %
VCC
10 %
0V
tW
tr
tf
90 %
50 %
Data
(A to D)
VCC
90 %
50 %
10 %
50 %
10 %
t su
th
t su
th
0V
tf
Load
t PHL
50 %
10 %
50 %
90 %
50 %
10 %
t THL
50 %
10 %
t TLH
50 %
0V
tr
t PLH
90 %
Q
VCC
90 %
90 %
50 %
10 %
t PHL
VOH
90 %
50 %
10 %
t THL
Notes : 1. Load Input Pulse : PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns
2. Data Input Pulse : PRR ≤ 500 kHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns
Rev.3.00, Jan 31, 2006 page 12 of 13
VOL
HD74HC192, HD74HC193
Package Dimensions
JEITA Package Code
P-DIP16-6.3x19.2-2.54
RENESAS Code
PRDP0016AE-B
MASS[Typ.]
1.05g
Previous Code
DP-16FV
D
9
E
16
1
8
b3
0.89
Z
A1
A
Reference
Symbol
L
e
Nom
θ
c
e1
D
19.2
E
6.3
JEITA Package Code
P-SOP16-5.5x10.06-1.27
RENESAS Code
PRSP0016DH-B
*1
Previous Code
FP-16DAV
7.4
A1
0.51
b
p
0.40
b
3
0.48
0.56
1.30
c
0.19
θ
0°
e
2.29
0.25
0.31
2.54
2.79
15°
1.12
L
2.54
MASS[Typ.]
0.24g
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
D
F
16
20.32
5.06
Z
( Ni/Pd/Au plating )
Max
7.62
1
A
bp
e
Dimension in Millimeters
Min
9
c
HE
*2
E
bp
Index mark
Reference
Symbol
Terminal cross section
( Ni/Pd/Au plating )
1
Z
*3
bp
Nom
D
10.06
E
5.50
Max
10.5
A2
8
e
Dimension in Millimeters
Min
x
A1
M
0.00
0.10
0.20
0.34
0.40
0.46
0.15
0.20
0.25
7.80
8.00
A
L1
2.20
bp
b1
c
A
c
A1
θ
y
L
Detail F
1
θ
0°
HE
7.50
e
1.27
x
0.12
y
0.15
0.80
Z
L
L
Rev.3.00, Jan 31, 2006 page 13 of 13
8°
0.50
1
0.70
1.15
0.90
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Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
Renesas Technology Malaysia Sdn. Bhd
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: <603> 7955-9390, Fax: <603> 7955-9510
© 2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
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