Holt HI-3586PQT Arinc 429 terminal ic with spi interface Datasheet

HI-3585, HI-3586
ARINC 429
Terminal IC with SPI Interface
July 2013
FEATURES
The HI-3585 from Holt Integrated Circuits is a silicon gate
CMOS device for interfacing a Serial Peripheral Interface
(SPI) enabled microcontroller to the ARINC 429 serial bus.
The device provides one receiver with user-programmable
label recognition for any combination of 256 possible
labels, 32 x 32 Receive FIFO and analog line receiver.
The independent transmitter has a 32 x 32 Transmit FIFO
and built-in line driver. The status of the transmit and
receive FIFOs can be monitored using the programmable
external interrupt pin, or by polling the HI-3585 Status
Register. Other features include a programmable option
of data or parity in the 32nd bit, and the ability to switch the
bit-signifiance of ARINC 429 labels. Pins are available
with different input resistance and output resistance
values which provides flexibility when using external
lightning protection circuitry.
·
·
·
·
·
·
·
·
·
ARINC specification 429 compliant
3.3V or 5.0V logic supply operation
On-chip analog line driver and receiver connect
directly to ARINC 429 bus
Programmable label recognition for 256 labels
32 x 32 Receive FIFO and 32 x 32 Transmit FIFO
Independent data rates for Transmit and Receive
High-speed, four-wire Serial Peripheral Interface
Label bit-order control
32nd transmit bit can be data or parity
Self test mode
Low power
Industrial & extended temperature ranges
PIN CONFIGURATIONS (Top View)
HI-3585PCI
HI-3585PCT
33
32
31
30
29
28
27
26
25
24
23
-
BOUT27
BOUT37
N/C
VN/C
TFLAG
N/C
N/C
RFLAG
N/C
N/C
12
13
14
15
16
17
18
19
20
21
22
- 1
- 2
- 3
- 4
- 5
- 6
- 7
- 8
- 9
- 10
- 11
-
The HI-3586 is functionally identical to the HI-3585 except
it includes digital transmitter output pins 429D1 and 429D0
instead of a built-in line driver. This allows the designer to
take advantage of Holt’s single supply rail line drivers,
such as the 5V HI-8592 or 3.3V HI-8596.
N/C
RINB-40
RINB
N/C
N/C
N/C
MR
SI
CS
N/C
N/C
N/C
N/C
N/C
SCK
N/C
GND
N/C
ACLK
SO
N/C
N/C
The HI-3585 applies the ARINC 429 protocol to the
receiver and transmitter. ARINC 429 databus timing
comes from a 1 MHz clock input, or an internal counter can
derive it from higher clock frequencies having certain fixed
values, possibly the external host processor clock.
44
43
42
41
40
39
38
37
36
35
34
-
The Serial Peripheral Interface minimizes the number of
host interface signals resulting in a small footprint device
that can be interfaced to a wide range of industry-standard
microcontrollers supporting SPI. Alternatively, the SPI
signals may be controlled using just four general purpose
I/O port pins from a microcontroller or custom FPGA. The
SPI and all control signals are CMOS and TTL compatible
and support 3.3V or 5V operation.
·
·
·
N/C
RINA
RINA-40
N/C
VDD
N/C
V+
N/C
AOUT27
AOUT37
N/C
GENERAL DESCRIPTION
44 - Pin Plastic 7mm x 7mm
Chip-Scale Package (QFN)
(DS3585 Rev. J)
HOLT INTEGRATED CIRCUITS
www.holtic.com
07/13
HI-3585, HI-3586
BLOCK DIAGRAM
VDD
ARINC 429
Line Driver
(HI-3585 only)
ARINC
Clock
Divider
ACLK
V+
10 Ohm
ARINC 429
Transmit
Data FIFO
ARINC 429
Transmit
Formatter
27 Ohm
AOUT37
AOUT27
27 Ohm
BOUT27
10 Ohm
BOUT37
V429D1(HI-3586 only)
429D0 (HI-3586 only)
SCK
CS
SI
TFLAG
SPI
Interface
SO
Control Register
RINA-40
ARINC 429
Line Receiver
RINB-40
RINA
RINB
Label
Filter
Bit Map
Memory
Status Register
ARINC 429
Valid word
Checker
40 Kohm
40 Kohm
Label
Filter
ARINC 429
Received
Data FIFO
RFLAG
GND
PIN DESCRIPTIONS
SIGNAL FUNCTION
RINB
RINB-40
MR
SI
CS
SCK
GND
ACLK
SO
RFLAG
TFLAG
VBOUT37
BOUT27
AOUT27
AOUT37
V+
VDD
RINA-40
RINA
429D1
429D0
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
POWER
INPUT
OUTPUT
OUTPUT
OUTPUT
POWER
OUTPUT
OUTPUT
OUTPUT
OUTPUT
POWER
POWER
INPUT
INPUT
OUTPUT
OUTPUT
DESCRIPTION
ARINC receiver negative input. Direct connection to ARINC 429 bus
Alternate ARINC receiver negative input. Requires external 40K ohm resistor
Master Reset. A positive pulse clears Receive and Transmit data FIFOs and flags
SPI interface serial data input
Chip select. Data is shifted into SI and out of SO when CS is low.
SPI Clock. Data is shifted into or out of the SPI interface using SCK
Chip 0V supply
Master timing source for the ARINC 429 receiver and transmitter
SPI interface serial data output
Goes high when ARINC 429 Receive FIFO is empty (CR15=0), or full (CR15=1)
Goes high when ARINC 429 Transmit FIFO is empty (CR14=0), or full (CR14=1)
Minus 5V power supply to ARINC 429 Line Driver
ARINC line driver negative output. Direct connection to ARINC 429 bus
Alternate ARINC line driver negative output. Requires external 10 ohm resistor
Alternate ARINC line driver positive output. Requires external 10 ohm resistor
ARINC line driver positive output. Direct connection to ARINC 429 bus
Positive 5V power supply to ARINC 429 Line Driver
3.3V or 5.0V logic power
Alternate ARINC receiver positive input. Requires external 40K ohm resistor
ARINC receiver positive input. Direct connection to ARINC 429 bus
Digital positive output to external line driver
Digital negative output to external line driver
* Internal Pull-up or Pull-down
HOLT INTEGRATED CIRCUITS
2
NOTE
10K ohm pull-down*
10K ohm pull-down*
10K ohm pull-up*
10K ohm pull-down*
10K ohm pull-down*
(HI-3585 only)
(HI-3585 only)
(HI-3585 only)
(HI-3585 only)
(HI-3585 only)
(HI-3585 only)
(HI-3586 only)
(HI-3586 only)
HI-3585, HI-3586
INSTRUCTIONS
Instruction op codes are used to read, write and configure the HI3585. When CS goes low, the next 8 clocks at the SCK pin shift an
instruction op code into the decoder, starting with the first positive
edge. The op code is fed into the SI pin most significant bit first.
For write instructions, the most significant bit of the data word must
immediately follow the instruction op code and is clocked into its
register on the next rising SCK edge. Data word length varies
depending on word type written: 16-bit writes to Control Register,
32-bit ARINC word writes to transmit FIFO or 256-bit writes to the
label-matching enable/disable table.
For read instructions, the most significant bit of the requested data
word appears at the SO pin after the last op code bit is clocked into
the decoder, at the next falling SCK edge. As with write
instructions, data field bit-length varies with read instruction type.
Table 1 lists all instructions. Instructions that perform a reset or set,
or enable transmission are executed after the last SI bit is received
while CS is still low.
Example:
one SPI Instruction
CS
SCK
SI
op code 07hex
MSB
data field 02hex
LSB MSB
LSB
TABLE 1. DEFINED INSTRUCTION OP CODES
OP CODE
Hex
DATA FIELD
00
None
No instruction implemented
01
None
After the 8th op code bit is received, perform Master Reset (MR)
02
None
After the 8th op code bit is received, reset all label selections
03
None
After the 8th op code bit is received, set all the label selections
04
8 bits
Reset the label at the address specified in the data field
05
8 bits
Set the label at the address specified in the data field
06
256 bits
07
8 bits
Programs a division of the ACLK input. If the divided ACLK frequency is 1 MHz and Control
Register bit CR1 is set, the ARINC receiver and transmitter operate from the divided ACLK clock.
Allowable values for division rate are X1, X2, X4, X8, or XA hex. Any other programmed value
results in no clock. Note: ACLK input frequency and division ratio must yield 1 MHz clock.
08
32 bits
Read the next word in the Receive FIFO. If the FIFO is empty, it will read zeros
09
None
No Instruction Implemented
0A
8 bits
Read the Status Register
0B
16 bits
Read the Control Register
0C
8 bits
Read the ACLK divide value programmed previously using op code 07 hex
0D
256 bits
0E
N x 32 Bits
0F
None
No instruction implemented
10
16 bits
Write the Control Register
11
None
Reset the Transmit FIFO. After the 8th op code bit is received, the transmit FIFO will be empty
12
None
Transmission enabled by this instruction only if Control Register bit 13 is zero
DESCRIPTION
Starting with label FF hex, consecutively set or reset each label in descending order
For example, a Data Field pattern starting with 1011 will set labels FF, FD, and FC
hex and reset label FE hex
Read the Label look-up memory table consecutively starting with address FF hex.
Write up to 32 words into the next empty positions of the Transmit FIFO
HOLT INTEGRATED CIRCUITS
3
HI-3585, HI-3586
FUNCTIONAL DESCRIPTION
CONTROL WORD REGISTER
STATUS REGISTER
The HI-3585 contains a 16-bit Control Register which is used to
configure the device. Control Register bits CR15 - CR0 are loaded
from a 16-bit data value appended to SPI instruction 10 hex. The
Control Register contents may be read using SPI instruction 0B
hex. Each bit of the Control Register has the following function:
The HI-3585 contains an 8-bit Status Register which can be
interrogated to determine the status of the ARINC receiver, data
FIFOs and transmitter. The contents of the Status Register are
output using SPI instruction 0A hex. Unused bits are output as
Zeros. The following table defines the Status Register bits.
CR
Bit
Cr0
(LSB)
CR1
CR2
FUNCTION STATE
DESCRIPTION
Receiver
Data Rate
Select
0
Data rate = CLK/10 (ARINC 429 High-Speed)
1
Data rate = CLK/80 (ARINC 429 Low-Speed)
ARINC Clock
Source Select
0
ARINC CLK = ACLK input frequency
1
ARINC CLK = ACLK divided by the value
programmed with SPI Instruction 07 hex
Enable Label
Recognition
0
Label recognition disabled
1
Label recognition enabled
Transmitter 32nd bit is data
CR3
Transmitter
Parity Bit
Enable
0
1
Transmitter 32nd bit is parity
CR4
Receiver
Parity Check
Enable
0
Receiver parity check disabled
1
Receiver odd parity check enabled
Self Test
0
The transmitter’s digital outputs are internally
connected to the receiver logic inputs
1
Normal operation
0
Receiver decoder disabled
1
ARINC bits 10 and 9 must match CR7 and CR8
CR5
CR6
Receiver
Decoder
SR
Bit
FUNCTION
STATE
SR0
(LSB)
Receive FIFO
Empty
0
Receiver FIFO contains valid data
Sets to One when all data has
been read. RFLAG pin reflects the
state of this bit when CR15=0
1
Receiver FIFO is empty
0
Receiver FIFO holds less than 16
words
1
Receiver FIFO holds at least 16
words
0
Receiver FIFO not full. RFLAG pin
reflects the state of this bit when
CR15=1
1
Receiver FIFO full. To avoid data
loss, the FIFO must be read within
one ARINC word period
0
Transmit FIFO not empty.
Sets to One when all data has
been sent. TFLAG pin reflects the
state of this bit when CR14=0
1
Transmit FIFO is empty.
0
Transmit FIFO contains less than 16
words
1
Transmit FIFO contains at least 16
words
0
Transmit FIFO not full. TFLAG pin
reflects the state of this bit when
CR14=1
1
Transmit FIFO full.
SR1
SR2
SR3
SR4
Receive FIFO
Half Full
Receive FIFO
Full
Transmit FIFO
Empty
Transmit FIFO
Half Full
DESCRIPTION
CR7
-
-
If receiver decoder is enabled,
the ARINC bit 10 must match this bit
CR8
-
-
If receiver decoder is enabled,
the ARINC bit 9 must match this bit
CR9
Transmitter
Parity
Select
0
Transmitter 32nd bit is Odd parity
1
Transmitter 32nd bit is Even parity
Transmitter
Data Rate
0
Data rate = CLK/10, O/P slope = 1.5us
SR6
Not used
0
Always “0”
1
Data rate = CLK/80, O/P slope = 10us
SR7
(MSB)
Not used
0
Always “0”
0
Label bit order reversed (See Table 2)
1
Label bit order same as transmitted /
received (See Table 2)
0
Line Driver enabled
1
Line Driver disabled (force outputs to Null state)
0
Start transmission by SPI
instruction12 hex
1
Transmit whenever data is available
in the Transmit FIFO
0
TFLAG goes high when transmit FIFO is empty
1
TFLAG goes high when transmit FIFO is full
0
RFLAG goes high when receive FIFO is empty
1
RFLAG goes high when receive FIFO is full
CR10
CR11
CR12
CR13
CR14
CR15
(MSB)
ARINC Label
Bit Order
Disable
Line Driver
Transmission
Enable Mode
TFLAG
Definition
RFLAG
Definition
SR5
Transmit FIFO
Full
HOLT INTEGRATED CIRCUITS
4
HI-3585, HI-3586
FUNCTIONAL DESCRIPTION (cont.)
ARINC 429 DATA FORMAT
RECEIVER LOGIC OPERATION
Control Register bit CR11 controls how individual bits in the
received or transmitted ARINC word are mapped to the HI-3585 SPI
data word bits during data read or write operations. The following
table describes this mapping:
Figure 2 is a block diagram showing receiver logic.
The ARINC 429 specification defines the following timing tolerances for received data:
Table 2. SPI / ARINC bit-mapping
8
Data
31 - 11
Data
Label (LSB)
5
Label
6
4
3
2
1
Label
7
Label (MSB)
8
Label
9
Label
10
Label
7
Label
6
Label
5
Label
4
Label
3
Label
2
Label
1
Label
9
SDI
10
Label (MSB)
31 - 11
SDI
CR11=1
Parity
ARINC bit 32
23 24 25 26 27 28 29 30 31 32
Label (LSB)
CR11=0
Parity
. ARINC bit 32
2 - 22
SDI
1
SDI
SPI
Order
ARINC 429 RECEIVER
ARINC BUS INTERFACE
Figure 1 shows the input circuit for the on-chip ARINC 429 line
receiver. The ARINC 429 specification requires the following
detection levels:
STATE
ONE
NULL
ZERO
RINA-40
DIFFERENTIAL VOLTAGE
+6.5 Volts to +13 Volts
+2.5 Volts to -2.5 Volts
-6.5 Volts to -13 Volts
VDD
BIT TIMING
DIFFERENTIAL
AMPLIFIERS
GND
HIGH SPEED
100K BPS ± 1%
1.5 ± 0.5 µsec
1.5 ± 0.5 µsec
5 µsec ± 5%
LOW SPEED
12K -14.5K BPS
10 ± 5 µsec
10 ± 5 µsec
34.5 to 41.7 µsec
The HI-3585 accepts signals within these tolerances and rejects
signals outside these tolerances. Receiver logic achieves this as
described below:
1. An accurate 1MHz clock source is required to validate the
receive signal timing. Less than 1% error is recommended.
2. The receiver uses three separate 10-bit sampling shift registers for Ones detection, Zeros detection and Null detection.
When the input signal is within the differential voltage range
for any shift register’s state (One Zero or Null) sampling
clocks a high bit into that register. When the receive signal is
outside the differential voltage range defined for any shift register, a low bit is clocked. Only one shift register can clock a
high bit for any given sample. All three registers clock low
bits if the differential input voltage is between defined state
voltage bands.
Valid data bits require at least three consecutive One or Zero
samples (three high bits) in the upper half of the Ones or
Zeros sampling shift register, and at least three consecutive
Null samples (three high bits) in the lower half of the Null sampling shift register within the data bit interval.
COMPARATORS
ONE
RINA
BIT RATE
PULSE RISE TIME
PULSE FALL TIME
PULSE WIDTH
NULL
VDD
ZERO
RINB
RINB-40
A word gap Null requires at least three consecutive Null samples (three high bits) in the upper half of the Null sampling
shift register and at least three consecutive Null samples
(three high bits) in the lower half of the Null sampling shift register. This guarantees the minimum pulse width.
3. To validate the receive data bit rate, each bit must follow
its preceding bit by not less than 8 samples and not more
than 12 samples. With exactly 1MHz input clock frequency,
the acceptable data bit rates are:
GND
FIGURE 1. ARINC RECEIVER INPUT
DATA BIT RATE MIN
DATA BIT RATE MAX
The HI-3585 guarantees recognition of these levels with a common
mode voltage with respect to GND less than ±30V for the worst case
condition (3.15V supply and 13V signal level).
Design tolerances guarantee detection of the above levels, so the
actual acceptance ranges are slightly larger. If the ARINC signal
(including nulls) is outside the differential voltage ranges, the HI3585 receiver rejects the data.
HIGH SPEED
LOW SPEED
83K BPS
125K BPS
10.4K BPS
15.6K BPS
4. Following the last data bit of a valid reception, the Word
Gap timer samples the Null shift register every 10 input
clocks (every 80 clocks for low speed). If a Null is present,
the Word Gap counter is incremented. A Word Gap count of
3 enables the next reception.
HOLT INTEGRATED CIRCUITS
5
HI-3585, HI-3586
FUNCTIONAL DESCRIPTION (cont.)
SCK
CS
SPI INTERFACE
SI
SO
32 X 32
RFLAG
FIFO
LOAD
CONTROL
FIFO
/
CONTROL BITS
CR2, CR6-8
LABEL /
DECODE
COMPARE
CLOCK
OPTION
CONTROLBITS
CR0, CR1
ACLK
CLOCK
256-BIT
LABEL
LOOK-UP
TABLE
32 BIT SHIFT REGISTER
DATA
PARITY
CHECK
32ND
BIT
BIT
COUNTER
AND
END OF
SEQUENCE
BIT CLOCK
EOS
ONES
WORD GAP
SHIFT REGISTER
WORD GAP
TIMER
BIT CLOCK
END
START
NULL
SHIFT REGISTER
ZEROS
SHIFT REGISTER
SEQUENCE
CONTROL
ERROR
ERROR
DETECTION
FIGURE 2.
RECEIVER BLOCK DIAGRAM
HOLT INTEGRATED CIRCUITS
6
CLOCK
HI-3585, HI-3586
FUNCTIONAL DESCRIPTION (cont.)
RETRIEVING DATA
RECEIVER PARITY
Once 32 valid bits are recognized, the receiver logic generates an
End of Sequence (EOS). Depending on the state of Control
Register bits CR2, CR6, CR7 and CR8, the received 32-bit ARINC
word is then checked for correct decoding and label match before
it is loaded into the 32 x 32 Receive FIFO. ARINC words that do
not match required 9th and 10th ARINC bit and do not have a label
match are ignored and are not loaded into the Receive FIFO. The
adjacent table describes this operation.
The Receiver Parity Check Enable bit (Control Register bit 4,
CR4) controls how the 32nd bit of the received ARINC word is
interpreted by the HI-3585 receiver.
Once a valid ARINC word is loaded into the FIFO, the EOS signal
clocks the Data Ready flip-flop to a "1" and Status Register bit 0
(SR0) to a “0”. The SR0 bit remains low until the Receive FIFO is
empty. Each received ARINC word is retrieved via the SPI
interface using SPI instruction 08 hex to read a single word.
Up to 32 ARINC words may be held in the Receive FIFO. Status
register bit 2 (SR2) goes high when the Receive FIFO is full.
Failure to unload the Receive FIFO when full causes additional
received valid ARINC words to overwrite Receive FIFO location 32.
A FIFO half-full flag (SR1) is high when the Receive FIFO contains
16 or more ARINC words. SR1 may be interrogated by the
system’s external microprocessor, allowing a 16 word data
retrieval routine to be performed.
When CR4 is set to a “1”, the 32nd bit is treated as a parity
error bit.
Odd Parity Received
The receiver expects the 32nd bit of the received word to
indicate odd parity. If this is the case, the parity bit is reset to
indicate correct parity was received and resulting word is
written to the receive FIFO.
Even Parity Received
If the received word is even parity, the receiver sets the 32nd
bit to a “1”, indicating a parity error. The resulting word is then
written to the receive FIFO.
Therefore, when CR4 is set to “1”, the 32nd bit retrieved from the
receiver FIFO will always be “0” when valid (odd parity) ARINC 429
words are received.
CR4
TABLE 3. FIFO LOADING CONTROL
CR2
When CR4 is set to a “0”, the 32nd bit is treated as data and
transferred as received from the ARINC bus to the receive FIFO.
ARINC word
matches
Enabled
label
CR6
ARINC word
bits 10, 9
match
CR7, 8
FIFO
0
X
0
X
Load FIFO
1
No
0
X
Ignore data
1
Yes
0
X
Load FIFO
0
X
1
No
Ignore data
0
X
1
Yes
Load FIFO
1
Yes
1
No
Ignore data
1
No
1
Yes
Ignore data
1
No
1
No
Ignore data
1
Yes
1
Yes
Load FIFO
ARINC BUS
32nd bit
FIFO
32nd bit
0
data
data
1
parity bit
Error Bit:
0 = odd parity
1= odd parity error (even parity)
LABEL RECOGNITION
The user loads the 256-bit label look-up table to specify which 8-bit
incoming ARINC labels are captured by the receiver, and which are
discarded. Setting a “1” in the look-up table enables processing of
received ARINC words containing the corresponding label. A “0”
in the look-up table causes discard of received ARINC words
containing the label. The 256-bit look-up table is loaded using SPI
op codes 02 hex, 03 hex or 06 hex, as described in Table 1. After
the look-up table is initialized, set Control Register bit CR2 to
enable label recognition.
If label recognition is enabled, the receiver compares the label in
each new ARINC word against the stored look-up table. If a label
match is found, the received word is processed. If no match
occurs, the new ARINC word is discarded and no indicators of
received ARINC data are presented.
READING THE LABEL LOOK-UP TABLE
The contents of the Label Look-up table may be read via the SPI
interface using instruction 0D hex as described in Table 1.
HOLT INTEGRATED CIRCUITS
7
HI-3585, HI-3586
FUNCTIONAL DESCRIPTION (cont.)
TRANSMITTER
FIFO OPERATION
The Transmit FIFO is loaded with ARINC 429 words awaiting
transmission. SPI op code 0E hex writes up to 32 ARINC words
into the FIFO, starting at the next available FIFO location. If Status
Register bit SR3 equals “1” (FIFO empty), then up to 32 words (32
bits each) may be loaded. If Status Register bit SR3 equals “0”
then only the available positions may be loaded. If all 32 positions
are full, Status Register bit SR5 is asserted. Further attempts to
load the Transmit FIFO are ignored until at least one ARINC word is
transmitted.
In normal operation (Control Register bit CR3 = ”1”), the 32nd bit
transmitted is a word parity bit. Odd or even parity is selected by
programming Control Register bit CR9 to a “0” or “1” respectively. If
Control Register bit CR3 equals “0”, all 32 bits loaded into the
Transmit FIFO are treated as data and are transmitted.
SPI op code 11 hex asynchronously clears all data in the Transmit
FIFO. The Transmit FIFO should be cleared after a self-test before
starting normal operation to avoid inadvertent transmission of test
data.
The Transmit FIFO half-full flag (Status Register bit SR4) equals “0”
when the Transmit FIFO contains less than 16 words. When SR4
equals “0”, the system microprocessor can safely initiate a 16-word
ARINC block-write sequence.
CR3, CR9
32 BIT PARALLEL
LOAD SHIFT REGISTER
BIT CLOCK
DATA AND
NULL TIMER
SEQUENCER
PARITY
GENERATOR
LINE DRIVER
AOUT
BOUT
CR12
BIT
AND
WORD GAP
COUNTER
WORD CLOCK
START
SEQUENCE
32 x 32 FIFO
ADDRESS
SR3
WORD COUNTER
AND
FIFO CONTROL
LOAD
SR4
SR5
INCREMENT
WORD COUNT
FIFO
LOADING
SEQUENCER
SCK
SPI COMMANDS
CS
SI
SPI INTERFACE
SPI COMMANDS
DATA
CLOCK
SO
CR10, CR1
FIGURE 3.
DATA CLOCK
DIVIDER
ACLK
TRANSMITTER BLOCK DIAGRAM
HI-3586 OPTION
The HI-3586 is functionally identical to the HI-3585 except
it does not include an on-chip ARINC 429 Line Driver.
Instead, digital output pins 429D1 and 429D0 may be used
to drive an external ARINC 429 line driver. This
configuration is useful if the desiger wishes to take
advantage of Holt’s single supply rail line drivers, such as
the 5V Hi-8592 or 3.3V HI-8596.
3.3V
HI-3586
429D1
TX1IN
429D0
TX0IN
HI-8596
TXAOUT
32.5 Ohm
TXBOUT
32.5 Ohm
GND
HI-3586 / HI-8596 3.3V-only Design Example
HOLT INTEGRATED CIRCUITS
8
ARINC 429 Bus
HI-3585, HI-3586
FUNCTIONAL DESCRIPTION (cont.)
DATA TRANSMISSION
If Control Register bit CR13 equals “1”, ARINC 429 data is
transmitted immediately following the CS rising edge of the SPI
instruction that loaded data into the Transmit FIFO. Loading
Control Register bit CR13 to “0” allows the software to control
transmission timing; each time an SPI op code 12 hex is executed,
all loaded Transmit FIFO words are transmitted. If new words are
loaded into the Transmit FIFO before transmission stops, the new
words will also be output. Once the Transmit FIFO is empty and
transmission of the last word is complete, the FIFO can be loaded
with new data which is held until the next SPI 12 hex instruction is
executed. Once transmission is enabled, the FIFO positions are
incremented with the top register loading into the data transmission
shift register. Within 2.5 data clocks the first data bit appears at
AOUT and BOUT. The 31 or 32 bits in the data transmission shift
register are presented sequentially to the outputs in the ARINC 429
format with the following timing:
ARINC DATA BIT TIME
DATA BIT TIME
NULL BIT TIME
WORD GAP TIME
HIGH SPEED
10 Clocks
5 Clocks
5 Clocks
40 Clocks
LOW SPEED
80 Clocks
40 Clocks
40 Clocks
320 Clocks
Transmit timing is derived from a 1 MHZ reference clock. Control
Register bit CR1 determines the reference clock source. If CR1
equals ”0,” a 50% duty cycle 1 MHZ clock should be applied to the
ACLK input pin. If CR1 equals ”1,” the ACLK input is divided to
generate the 1 MHZ ARINC clock. SPI op code 07 hex provides
the HI-3585 with the correct division ratio to generate a 1 MHZ
reference from ACLK.
Loading Control Register bit CR10 to “0” causes a 100 Kbit/s data
rate and a slope of 1.5 µs on the ARINC outputs. Loading CR10 to
“1” causes a 12.5 Kbit/s data rate and a slope of 10 µs. Timing is
set by an on-chip resistor and capacitor and tested to be within
ARINC 429 requirements.
LINE DRIVER OUTPUT PINS
The HI-3585 AOUT37 and BOUT37 pins have 37.5 Ohms in
series with each line driver output, and may be directly connected
to an ARINC 429 bus. The alternate AOUT27 and BOUT27 pins
have 27 ohms of internal series resistance and require external 10
ohm resistors at each pin. AOUT27 and BOUT27 are for
applications where external series resistance is applied, typically
for lightning protection devices.
LINE RECEIVER INPUT PINS
The word counter detects when all loaded positions have been
transmitted and sets the transmitter ready flag, SR3, high.
TRANSMITTER PARITY
The parity generator counts the Ones in the 31-bit word. If control
register bit CR9 is set to a “0”, the 32nd bit transmitted will make
parity odd. If the control bit is a “1”, the parity is even. Setting CR3
to “0” bypasses the parity generator, and allows 32 bits of data to be
transmitted.
SELF TEST
If Control Register bits CR5 and CR12 equal ”0”, the transmitter
serial output data is internally looped-back into the receiver. Data
passes unmodified from transmitter to receiver. Setting Control
register bit CR12 to ”1” forces AOUT and BOUT to the Null state
regardless of CR5 state.
SYSTEM OPERATION
The receiver is independent of the transmitter. Therefore, control
of data exchanges is strictly at the option of the user. The only
restrictions are:
1. The received data will be overwritten if the Receive FIFO is
full and at least one location is not retrieved before the next
complete ARINC word is received.
2. The Transmit FIFO can store 32 words maximum and
ignores attempts to load additional data when full.
The HI-3585 has two sets of Line Receiver input pins, RINA/B
and RINA/B-40. Only one pair may be used to connect to the
ARINC 429 bus. The unused pair must be left floating. The
RINA/B pins may be connected directly to the ARINC 429 bus.
The RINA/B-40 pins require external 40K ohm resistors in series
with each ARINC input. These do not affect the ARINC receiver
thresholds. By keeping excessive voltage outside the device, this
option is helpful in applications where lightning protection is required.
When using the RINA/B-40 pins, each side of the ARINC bus
must be connected through a 40K ohm series resistor in order for
the chip to detect the correct ARINC levels. The typical 10 Volt differential signal is translated and input to a window comparator
and latch. The comparator levels are set so that with the external
40K ohm resistors, they are just below the standard 6.5 volt minimum ARINC data threshold and just above the standard 2.5 volt
maximum ARINC null threshold.
Please refer to the Holt AN-300 Application Note for additional
information and recommendations on lightning protection of Holt
line drivers and line receivers.
POWER SUPPLY SEQUENCING
Power supply sequencing should be controlled to prevent large
currents during supply turn-on and turn-off. The recommended
sequence is V+ followed by VDD, always ensuring that V+ is the
most positive supply. The V- supply is not critical and can be
applied at any time.
LINE DRIVER OPERATION
MASTER RESET (MR)
The line driver in the HI-3585 directly drives the ARINC 429 bus.
The two ARINC outputs (AOUT37 and BOUT37) provide a
differential voltage to produce a +10V One, a -10V Zero, and a
0 Volt Null. Control Register bit CR10 controls both the transmitter
data rate and the slope of the differential output signal. No
additional hardware is required to control the slope.
Application of a Master Reset causes immediate termination of
data transmission and data reception. The transmit and receive
FIFOs are cleared. Status Register FIFO flags and FIFO status
output signals RFLAG and TFLAG are also cleared. The Control
Register is not affected by a Master Reset.
HOLT INTEGRATED CIRCUITS
9
HI-3585, HI-3586
SERIAL PERIPHERAL INTERFACE
As seen in Figure 4, SPI Mode 0 holds SCK in the low state when
idle. The SPI protocol transfers serial data as 8-bit bytes. Once
CS chip select is asserted, the next 8 rising edges on SCK latch
input data into the master and slave devices, starting with each
byte’s most-significant bit.
SERIAL PERIPHERAL INTERFACE (SPI) BASICS
The HI-3585 uses an SPI synchronous serial interface for host
access to internal registers and data FIFOs. Host serial
communication is enabled through the Chip Select (CS) pin, and
is accessed via a three-wire interface consisting of Serial Data
Input (SI) from the host, Serial Data Output (SO) to the host and
Serial Clock (SCK). All read / write cycles are completely selftimed.
Multiple bytes may be transferred when the host holds CS low
after the first byte transferred, and continues to clock SCK in
multiples of 8 clocks. A rising edge on CS chip select terminates
the serial transfer and reinitializes the HI-3585 SPI for the next
transfer. If CS goes high before a full byte is clocked by SCK, the
incomplete byte clocked into the device SI pin is discarded.
The SPI (Serial Peripheral Interface) protocol specifies master
and slave operation; the HI-3585 operates as an SPI slave.
In the general case, both master and slave simultaneously send
and receive serial data (full duplex), per Figure 4 below. However
the HI-3585 operates half duplex, maintaining high impedance
on the SO output, except when actually transmitting serial data.
When the HI-3110 is sending data on SO during read operations,
activity on its SI input is ignored. Figures 5 and 6 show actual
behavior for the HI-3585 SO output.
The SPI protocol defines two parameters, CPOL (clock polarity)
and CPHA (clock phase). The possible CPOL-CPHA
combinations define four possible "SPI Modes". Without
describing details of the SPI modes, the HI-3585 operates in
mode 0 where input data for each device (master and slave) is
clocked on the rising edge of SCK, and output data for each
device changes on the falling edge (CPHA = 0, CPOL = 0). Be
sure to set the host SPI logic for mode 0.
SCK (SPI Mode 0)
SI
SO
High Z
0
1
2
3
4
5
6
7
MSB
LSB
MSB
LSB
CS
Figure 4. Generalized Single-Byte Transfer Using SPI Protocol Mode 0
HOLT INTEGRATED CIRCUITS
10
High Z
HI-3585, HI-3586
HOST SERIAL PERIPHERAL INTERFACE (cont.)
HI-3585 SPI COMMANDS
Multiple byte read or write cycles may be performed by
transferring more than one byte before CS is negated. Table 1
defines the required number of bytes for each instruction.
For the HI-3585, each SPI read or write operation begins with an
8-bit command byte transferred from the host to the device after
assertion of CS. Since HI-3585 command byte reception is halfduplex, the host discards the dummy byte it receives while
serially transmitting the command byte.
Note: SPI Instruction op-codes not shown in Tables 1 are
“reserved” and must not be used. Further, these op-codes will
not provide meaningful data in response to read commands.
Figures 5 and 6 show read and write timing as it appears for a
single-byte and dual-byte register operation. The command byte
is immediately followed by a data byte comprising the 8-bit data
word read or written. For a single register read or write, CS is
negated after the data byte is transferred.
0
1
2
3
4
5
6
Two instruction bytes cannot be “chained”; CS must be
negated after the command, then reasserted for the following
Read or Write command.
7
0
1
2
3
4
5
6
7
SCK
MSB
LSB
SI
Op-Code Byte
LSB MSB
MSB
High Z
SO
High Z
Data Byte
CS
Host may continue to assert CS
here to read sequential word(s)
when allowed by the instruction.
Each word needs 8 SCK clocks.
Figure 5. Single-Byte Read From a Register
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
SPI Mode 0
MSB
LSB MSB
LSB
LSB MSB
SI
Op-Code Byte
SO
Data Byte 0
Data Byte 1
High Z
CS
Host may continue to assert CS
here to write sequential byte(s)
when allowed by the SPI instruction.
Each byte needs 8 SCK clocks.
Figure 6. 2-Byte Write example
HOLT INTEGRATED CIRCUITS
11
HI-3585, HI-3586
TIMING DIAGRAMS
SERIAL INPUT TIMING DIAGRAM
t CPH
t CYC
CS
tCHH
t SCKF
t CES
t CEH
SCK
t DS
t SCKR
t DH
SI
MSB
LSB
SERIAL OUTPUT TIMING DIAGRAM
t CPH
t CYC
CS
SCK
t CHZ
t DV
SO
MSB
Hi Impedance
LSB
Hi Impedance
* Above diagram does not apply for op code instruction 09hex
DATA RATE - EXAMPLE PATTERN
TXAOUT
ARINC BIT
TXBOUT
NULL
DATA
DATA
DATA
NULL
WORD GAP
BIT 32
BIT 31
BIT 30
NULL
BIT 1
NEXT WORD
RECEIVER OPERATION
ARINC DATA
BIT 31
BIT 32
RFLAG
tRFLG
tRXR
tSPIF
CS
SPI INSTRUCTION 08h
SI
ARINC
BIT 32
ARINC
BIT 31
ARINC
BIT 30
SO
HOLT INTEGRATED CIRCUITS
12
ARINC
BIT 1
HI-3585, HI-3586
TIMING DIAGRAMS (cont.)
TRANSMITTING DATA
CS
SPI INSTRUCTION 0Eh, (or 12h)
SI
t TFLG
tDATT
TFLAG (CR14=0)
ARINC BIT
DATA
BIT 1
t SDAT
ARINC BIT
DATA
BIT 2
ARINC BIT
DATA
BIT 32
+5V
+5V
AOUT
-5V
+5V
BOUT
-5V
-5V
tfx
+10V
+10V
90%
V
DIFF
(AOUT - BOUT)
tfx
10%
trx
one level
trx
10%
zero level
90%
null level
-10V
ABSOLUTE MAXIMUM RATINGS
Supply Voltages VDD ......................................... -0.3V to +7.0V
V+ ......................................................... +7.0V
V- ......................................................... -7.0V
Power Dissipation at 25°C
Plastic Quad Flat Pack ..................1.5 W, derate 10mW/°C
Voltage at pins RINA, RINB ............................... -120V to +120V
DC Current Drain per pin .............................................. ±10mA
Voltage at any other pin ............................... -0.3V to VDD +0.3V
Storage Temperature Range ........................ -65°C to +150°C
Solder temperature (Leads) .................... 280°C for 10 seconds
(Package) .......................................... 220°C
Operating Temperature Range (Industrial): ..... -40°C to +85°C
(Hi-Temp): ..... -55°C to +125°C
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
HOLT INTEGRATED CIRCUITS
13
HI-3585, HI-3586
DC ELECTRICAL CHARACTERISTICS
VDD = 3.3V or 5.0V , V+ = +5V, V- = -5V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
LIMITS
PARAMETER
ARINC INPUTS
-
SYMBOL
CONDITIONS
UNIT
MIN
TYP
MAX
6.5
-13.0
-2.5
10.0
-10.0
0
13.0
-6.5
2.5
V
V
V
140
140
100
-
KW
KW
KW
200
µA
µA
20
20
20
pF
pF
pF
20% VDD
V
V
Pins RINA, RINB, RINA-40 (with external 40KOhms), RINB-40 (with external 40KOhms)
Differential Input Voltage:
(RINA to RINB)
ONE
ZERO
NULL
Input Resistance:
VIH
VIL
VNUL
Common mode voltages
less than ±30V with
respect to GND
Differential
To GND
To VDD
RI
RG
RH
-
Input Sink
Input Source
IIH
IIL
-450
Differential
To GND
To VDD
CI
CG
CH
Input Voltage HI
Input Voltage LO
VIH
VIL
Input Sink
Input Source
Pull-down Current (MR, SI, SCK, ACLK pins)
Pull-up current (CS pin)
IIH
IIL
IPD
IPU
Input Current:
Input Capacitance:
(Guaranteed but not tested)
(RINA to RINB)
LOGIC INPUTS
Input Voltage:
Input Current:
80% VDD
1.5
-1.5
250
-600
600
-300
µA
µA
µA
µA
ARINC OUTPUTS - Pins AOUT37, BOUT37, (or AOUT27, BOUT27 with external 10 Ohms)
ARINC output voltage (Ref. To GND)
One or zero
Null
VDOUT
VNOUT
No load and magnitude at pin,
4.50
-0.25
5.00
5.50
0.25
V
V
ARINC output voltage (Differential)
One or zero
Null
VDDIF
VNDIF
No load and magnitude at pin,
9.0
-0.5
10.0
11.0
0.5
V
V
IOUT
Momentary current
80
Logic "1" Output Voltage
Logic "0" Output Voltage
VOH
VOL
IOH = -100µA
IOL = 1.0mA
90%VDD
Output Sink
Output Source
IOL
IOH
VOUT = 0.4V
VOUT = VDD - 0.4V
1.6
ARINC output current
mA
LOGIC OUTPUTS
Output Voltage:
Output Current:
Output Capacitance:
CO
10% VDD
V
V
-1.0
mA
mA
15
pF
Operating Voltage Range
VDD
3.15
5.25
V
V+
4.75
5.5
V
V-
-4.75
-5.5
V
Operating Supply Current
VDD
IDD1
2.5
7
mA
V+
IDD2
4
14
mA
V-
IEE1
4
12
mA
HOLT INTEGRATED CIRCUITS
14
HI-3585, HI-3586
AC ELECTRICAL CHARACTERISTICS
VDD = 3.3V or 5.0V, V+=+5V, V-=-5V, GND = 0V, TA = Operating Temperature Range and fclk=1MHz +0.1% with 50/50 duty cycle
LIMITS
PARAMETER
SYMBOL
UNITS
MIN
TYP
MAX
SPI INTERFACE TIMING - 5.0V
SCK clock period
CS active after last SCK rising edge
CS setup time to first SCK rising edge
CS hold time after last SCK falling edge
CS inactive between SPI instructions
SPI SI Data set-up time to SCK rising edge
SPI SI Data hold time after SCK rising edge
SCK rise time
SCK fall ime
SO valid after SCK falling edge
SO high-impedance after SCK falling edge
Master Reset pulse width
tCYC
tCHH
tCES
tCEH
tCPH
tDS
tDH
tSCKR
tSCKF
tDV
tCHZ
tMR
250
10
10
40
20
25
15
10
10
125
100
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SPI INTERFACE TIMING - 3.3V
SCK clock period
CS active after last SCK rising edge
CS setup time to first SCK rising edge
CS hold time after last SCK falling edge
CS inactive between SPI instructions
SPI SI Data set-up time to SCK rising edge
SPI SI Data hold time after SCK rising edge
SCK rise time
SCK fall ime
SO valid after SCK falling edge
SO high-impedance after SCK falling edge
Master Reset pulse width
tCYC
tCHH
tCES
tCEH
tCPH
tDS
tDH
tSCKR
tSCKF
tDV
tCHZ
tMR
390
10
10
40
35
30
30
10
10
195
100
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RECEIVER TIMING
Delay - Last bit of received ARINC word to RFLAG(Full or Empty) - Hi Speed
Delay - Last bit of received ARINC word to RFLAG(Full or Empty) - Lo Speed
Received data available to SPI interface. RFLAG to CS active
SPI receiver read or clear FIFO instruction to RFLAG
tRFLG
tRFLG
tRXR
tSPIF
16
126
155
µs
µs
ns
ns
120
17
118
14
114
ns
µs
µs
µs
µs
2.0
2.0
15
15
µs
µs
µs
µs
0
TRANSMITTER TIMING
SPI transmit data write or FIFO clear instruction to TFLAG (Empty or Full)
SPI instruction to ARINC 429 data output - Hi Speed
SPI instruction to ARINC 429 data output - Lo Speed
Delay TFLAG high after enable transmit - Hi Speed
Delay TFLAG high after enable transmit - Lo Speed
Line driver transition differential times:
high to low
(High Speed, control register CR10 = Logic 0)
low to high
(Low Speed, control register CR10 = Logic 1)
high to low
low to high
tTFLG
tSDAT
tSDAT
tDATT
tDATT
tfx
trx
tfx
trx
HOLT INTEGRATED CIRCUITS
15
1.0
1.0
5.0
5.0
1.5
1.5
10
10
HI-3585, HI-3586
44
43
42
41
40
39
38
37
36
35
34
- N/C
- RINA
- RINA-40
- N/C
- VDD
- N/C
- V+
- N/C
- AOUT27
- AOUT37
- N/C
ADDITIONAL HI-3585 & HI-3586 PIN CONFIGURATIONS (Top View)
N/C - 1
RINB-40 - 2
RINB - 3
N/C - 4
N/C - 5
N/C - 6
MR - 7
SI - 8
CS - 9
N/C - 10
N/C - 11
33 - BOUT27
32 - BOUT37
31 - N/C
30 - V29 - N/C
28 - TFLAG
27 - N/C
26 - N/C
25 - RFLAG
24 - N/C
23 - N/C
N/C - 12
N/C - 13
N/C - 14
SCK - 15
N/C - 16
GND - 17
N/C - 18
ACLK - 19
SO - 20
N/C - 21
N/C - 22
HI-3585PQI
HI-3585PQT
HI-3585PQM
44
43
42
41
40
39
38
37
36
35
34
-
44
43
42
41
40
39
38
37
36
35
34
N/C
RINA
RINA-40
N/C
VDD
429D1
429D0
VDD
N/C
N/C
N/C
- N/C
- RINA
- RINA-40
- N/C
- VDD
- 429D1
- 429D0
- VDD
- N/C
- N/C
- N/C
44 - Pin Plastic Quad Flat Pack (PQFP)
HI-3586PQI
HI-3586PQT
HI-3586PQM
33 - N/C
32 - N/C
31 - N/C
30 - GND
29 - N/C
28 - TFLAG
27 - N/C
26 - N/C
25 - RFLAG
24 - N/C
23 - N/C
N/C
RINB-40
RINB
N/C
N/C
N/C
MR
SI
CS
N/C
N/C
- 1
- 2
- 3
- 4
- 5
- 6
- 7
- 8
- 9
- 10
- 11
HI-3586PCI
HI-3586PCT
33
32
31
30
29
28
27
26
25
24
23
-
N/C - 12
N/C - 13
N/C - 14
SCK - 15
N/C - 16
GND - 17
N/C - 18
ACLK - 19
SO - 20
N/C - 21
N/C - 22
N/C
N/C
N/C
SCK
N/C
GND
N/C
ACLK
SO
N/C
N/C
-
12
13
14
15
16
17
18
19
20
21
22
N/C - 1
RINB-40 - 2
RINB - 3
N/C - 4
N/C - 5
N/C - 6
MR - 7
SI - 8
CS - 9
N/C - 10
N/C - 11
44 - Pin Plastic Quad Flat Pack (PQFP)
44 - Pin Plastic 7mm x 7mm
Chip-Scale Package (QFN)
HOLT INTEGRATED CIRCUITS
16
N/C
N/C
N/C
GND
N/C
TFLAG
N/C
N/C
RFLAG
N/C
N/C
HI-3585, HI-3586
ORDERING INFORMATION
HI - 358x xx x x
PART
NUMBER
Blank
F
PART
NUMBER
LEAD
FINISH
Tin / Lead (Sn / Pb) Solder
100% Matte Tin (Pb-free, RoHS compliant)
TEMPERATURE
RANGE
FLOW
I
-40°C TO +85°C
I
No
T
-55°C TO +125°C
T
No
M
-55°C TO +125°C
M
YES
PART
NUMBER
PACKAGE
DESCRIPTION
PC
44 PIN PLASTIC CHIP-SCALE, QFN (44PCS) Not Avaiable in “M” Flow
PQ
44 PIN PLASTIC QUAD FLAT PACK, PQFP (44PTQS)
PART
NUMBER
PACKAGE
DESCRIPTION
3585
On-chip ARINC 429 Line Driver
3586
External ARINC 429 Line Driver
HOLT INTEGRATED CIRCUITS
17
HI-3585, HI-3586
REVISION HISTORY
P/N
Rev
DS3585 NEW
A
B
C
D
E
F
G
Date
05/08/08
10/10/08
05/22/09
02/03/10
04/20/10
05/19/10
09/03/10
11/02/10
H
06/04/12
I
J
07/02/12
07/25/13
Description of Change
Initial Release
Revised AC Electrical Characteristics table and description of “T” process.
Clarified relationship between SPI bit order and the ARINC 429 bit order.
Clarified op code 09 hex description.
Removed op code 09 hex.
Corrected ARINC receiver nomenclature.
Added HI-3586 digital-only product option
Enhanced description of HI-3586 digital-only product option, added basics of SPI
communications and added M flow for QFP package.
Clarified the description of receiver parity. Updated PQFP package drawing. Corrected typo
in clock source tolerance on p. 5 from 0.1% to 1%.
Update SPI Interface Timing at 5.0V and 3.3V
Update QFN package drawing. Remove note on heat sink connection for QFN package.
HOLT INTEGRATED CIRCUITS
18
HI-3585, HI-3586 PACKAGE DIMENSIONS
inches (millimeters)
44-PIN PLASTIC CHIP-SCALE PACKAGE (QFN)
Package Type: 44PCS
.276
BSC
(7.00)
.216 ± .002
(5.50 ± .05)
.020 BSC
(0.50)
.276
BSC
(7.00)
.216 ± .002
(5.50 ± .05)
Top View
Bottom
View
.010
(0.25) typ
.039
max
(1.00)
.008 typ
(0.2)
.016 ± .002
(0.40 ± .05)
Electrically isolated heat
sink pad on bottom of
package
Connect to any ground or
power plane for optimum
thermal dissipation
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
inches (millimeters)
44-PIN PLASTIC QUAD FLAT PACK (PQFP)
44PMQS
.009 MAX.
(.23)
.0315
BSC
(.80)
.394 ± .004
(10.0 ± .10)
SQ.
.520 ± .010
(13.20 ± .25)
SQ.
.014 ± .003
(.37 ± .08)
.035 ± .006
(.88 ± .15)
.012
R MAX.
(.30)
See Detail A
.096
MAX.
(2.45)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
.079 ± .008
(2.0 ± .20)
.005
R MIN. Detail A
(.13)
HOLT INTEGRATED CIRCUITS
19
0° £ Q £ 7°
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