Intersil HFA3663IA96 2.3ghz upconverter with gain control Datasheet

HFA3663
Data Sheet
January 1999
File Number
4241.3
2.3GHz UpConverter with Gain Control
Features
The HFA3663 UpConverter with Gain
Control is a monolithic bipolar device
for up conversion applications in the
2.0GHz to 2.3GHz range.
Manufactured in the Intersil UHF1X
process, the device consists of a double balanced mixer
followed by a variable gain power preamp. An energy saving,
TTL Compatible, power enable input provides on/off bias
current control to the mixer and amplifier. The device
requires low drive levels from the local oscillator and is
housed in a small outline 20 lead SSOP package ideally
suited for PCMCIA card applications.
• RF Frequency Range . . . . . . . . . . . . . . 2.0GHz to 2.3GHz
Ordering Information
• PCMCIA Wireless Transceiver
™
PART NUMBER
TEMP.
RANGE (oC)
PACKAGE
HFA3663IA
-40 to 85
20 Ld SSOP
HFA3663IA96
-40 to 85
Tape and Reel
PKG.
NO.
M20.15
• IF Operation . . . . . . . . . . . . . . . . . . . . . 10MHz to 400MHz
• Gain Control Range . . . . . . . . . . . . . . . . . . . . . . . . . .20dB
• Single Supply Operation. . . . . . . . . . . . . . . . . 2.7V to 5.5V
• High Output 1dB Compression. . . . . . . . . . . . . . . . . 6dBm
• High Power Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . .18dB
• Power Enable/Disable Control
Applications
• Wireless Local Loop Systems
• Wireless Local Area Network Modems
• CDMA/TDMA Packet Protocol Radios
• Full Duplex Transceivers
• Portable Battery Powered Equipment
Pinout
Block Diagram
HFA3663
TOP VIEW
BIAS_VCC
PRE_VCC3
1
20 TX_PE
GND
2
19 LO_BY
PRE_OUT
3
18 LO_IN
GND
4
17 GND
PRE_VCC2
5
16 IF_IN
LO_IN
PRE_VCC3
GND
6
15 IF_BY
7
14 GND
GND
8
13 TXM_RF
PRE_IN
9
12 MIX_VCC
TX_PE
LO_BY
PRE_OUT
BIAS_VCC
PRE_VCC1 10
BIAS
IF_IN
IF_BY
PRE_VCC2
PRE_VCC1
PRE_IN
TXM_RF
11 AGC_CTRL
AGC CONTROL
AGC_CTRL
POWER CONTROL TRUTH TABLE
STATE
2-201
TX_PE
Power Down - Energy Saving Mode
Low
Transmit Mode
High
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
PRISM® is a registered trademark of Intersil Corporation. PRISM logo is a trademark of Intersil Corporation.
HFA3663
Typical Application Diagram
PRISM™ FULL DUPLEX CHIP SET
HFA3661
(FILE #4240)
HFA3424/21
(FILE #4131)
D
U
P
L
E
X
E
R
LNA
LNA
RF/IF
CONVERTER
BPF
HFA3761 (FILE #4236)
FILTER
LPF
IF AGC
A/D
QMODEM
LPF
RF LO1
HFA3524
(FILE #4062)
SYNTHESIZER
IF LO1
BASEBAND
HFA3524
(FILE #4062)
HFA3925
(FILE #4132)
PA
SYNTHESIZER
HFA3763
(FILE #4237)
RF LO2
AGC
IF/RF
CONVERTER
BPF
IF LO2
LPF
AGC
D/A
QMODEM
LPF
HFA3663 (FILE #4241)
HFA3664 (FILE #4242)
OPTIONAL WHEN IN
ANALOG MODE
PRISM™ FULL DUPLEX RADIO
CHIP SET, FILE #4238
Pin Description
NAME
DESCRIPTION
LO_IN
Local Oscillator Input.
LO_BY
Local Oscillator Input Bypass (AC coupled to GND).
PRE_IN
Power Pre-Amplifier Input.
PRE_OUT
Power Pre-Amplifier Output.
PRE_VCC1
Power Pre-Amplifier 1st Stage Positive Power Supply. Use high quality RF decoupling capacitors.
PRE_VCC2
Power Pre-Amplifier 2nd Stage Positive Power Supply. Use high quality RF decoupling capacitors.
PRE_VCC3
Power Pre-Amplifier 3rd Stage Positive Power Supply. Use high quality RF decoupling capacitors.
BIAS_VCC
LO Buffer, Bias, Mixer and AGC Control Positive Power Supply. Requires an isolation coil to VCC.
MIX_VCC
Transmit Mixer Output Stage Positive Power Supply. Use high quality RF decoupling capacitors.
RX_PE
TXM_RF
Power Enable Control Input. Refer to the Power Control Truth Table.
Transmit Mixer RF Output.
IF_IN
Transmit Mixer Positive IF Input. Requires external bias resistor to VCC.
IF_BY
Transmit Mixer Negative IF Input (AC coupled to GND).
GND
Circuit Ground Pins (Qty 6). Internally connected with the exception of pin 17.
2-202
HFA3663
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 6.0V
Voltage on Any Other Pin. . . . . . . . . . . . . . . . . . . . -0.3 to VCC 0.3V
Operating Conditions
Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
20 Lead SSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
110
Package Power Dissipation at 70oC
20 Lead SSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.7W
Maximum Junction Temperature (Plastic Package) . . . . . . . . .150oC
Maximum Temperature Range. . . . . . . . . . . . . . . -40oC ≤ TA ≤ 85oC
Maximum Storage Temperature Range . . . . . . . -65oC ≤ TA ≤ 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
(Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
VCC = 5.5V, LO = 2050MHz, IF = 100MHz, RF = 2150MHz, ZO = 50Ω,
Unless Otherwise Specified
PARAMETER
SYMBOL
(NOTE 2)
TEST
LEVEL
TEMP
(oC)
MIN
TYP
MAX
UNITS
CASCADED CHARACTERISTICS (-3dB Loss RF Image Filter with 35dB LO Suppression,
LO_IN = 2050MHz/-6dBm, IF_IN = 100MHz/-30dBm, AGC_CTRL = 0.7V (Max Gain))
Cascaded Output 1dB Compression
CTX_P1D
B
25
6
7.5
-
dBm
Cascaded Output Third Order Intercept
CTX_IP3
C
25
-
14
-
dBm
Cascaded Power Gain
CTX_PG
B
25
18
22
-
dB
Cascaded Power Gain Flatness
(2.0GHz to 2.3GHz)
CTX_PGF
C
25
-2.5
0
+2.5
dB
Cascaded LO Leakage
CTX_LEAK
B
25
-
-20
-
dBm
LO INPUT CHARACTERISTICS (LO_IN = 2050MHz/-6dBm, all unused inputs and outputs are terminated into 50Ω)
LO Input Frequency Range
LO Input Drive Level
LO Input VSWR
LO Input Return Loss
LO_f
B
25
1.6
-
2.29
GHz
LO_dr
A
25
-
-6
-
dBm
LO_SWR
A
25, 85
-
1.62:1
2.0:1
-
LO_IRL
A
25, 85
9.4
12.5
-
dB
TRANSMIT MIXER CHARACTERISTICS (LO_IN = 2050MHz/-6dBm, TXM_IF = 100MHz/-30dBm)
IF Input Frequency Range
TXM_IFf
B
25
10
-
400
MHz
TXM_SWR
A
25, 85
-
1.22:1
2.0:1
-
TXM_IRL
A
25, 85
9.4
23
-
dB
TXM_PGH
A
25, 85
3.0
5.6
TBD
dB
Transmit Mixer LO Leakage
TXM_LEAK
A
25, 85
-
-20
-10
dBm
RF Output Frequency Range
TXM_RFf
B
25
2.0
-
2.3
GHz
TXM_OSWR
A
25, 85
-
1.68:1
2.0:1
-
TXM_ORL
A
25, 85
9.4
17.4
-
dB
TXM_P1DH
A
25
-7.8
-6.5
-
dBm
RF Output Third Order Intercept
TXM_IP3
C
25
-
2.7
-
dBm
Transmit Mixer Noise Figure
TXM_NF
B
25
-
18
-
dB
IF Input VSWR
IF Input Return Loss
Power Conversion Gain
(Note 3)
VCC = 5.5V
RF Output VSWR
RF Output Return Loss
RF Output 1dB Compression
(Note 3)
VCC = 5.5V
2-203
HFA3663
Electrical Specifications
VCC = 5.5V, LO = 2050MHz, IF = 100MHz, RF = 2150MHz, ZO = 50Ω,
Unless Otherwise Specified (Continued)
PARAMETER
SYMBOL
(NOTE 2)
TEST
LEVEL
TEMP
(oC)
MIN
TYP
MAX
UNITS
TRANSMIT POWER PREAMP CHARACTERISTICS (PRE_IN = 2150MHz/-30dBm, AGC_CTRL = 0.7V (Max Gain))
Frequency Range
PRE_f
B
25
2.0
-
2.3
GHz
PRE_PGH
A
25, 85
18
24
-
dB
PRE_NF
B
25
-
8
-
dB
PRE_AGC
A
25
20
30
-
dB
AGC_V
A
25
0.7
-
1.7
V
AGC Control Linearity
AGC_LIN
B
25
-
5:1
-
-
AGC Settling Time (Min to Max Gain)
AGC_T1
B
25
-
8.0
-
µS
AGC Settling Time (Max to Min Gain)
AGC_T2
B
25
-
0.1
-
µS
PRE_P1DH
A
25
8
10
-
dBm
PRE_IP3
C
25
-
17
-
dBm
PRE_ISWR
A
25, 85
-
2.7:1
3.0:1
-
PRE_IRL
A
25, 85
6.02
9.0
-
dB
PRE_OSWR
A
25, 85
1.0
1.17:1
2.0:1
-
PRE_ORL
A
25, 85
9.4
15.4
-
dB
VCC
A
25
4.5
-
5.5
V
ICC HI
A
25, 85
9.0
100
110
mA
ICC HIT
C
Full
-
-
110
mA
ICC_PD
A
25
0.004
2.8
4
mA
Logic Input Low Level
VIL
A
25
-0.2
-
0.8
V
Logic Input High Level
VIH
A
25
2.0
-
VCC
V
Logic Low Input Bias Current
(VPE = 0V, VCC = 5.5V)
IB_LO
A
25
-
-5.0
5.0
µA
Logic High Input Bias Current
(VPE = 5.5V, VCC = 5.5V)
IB_HI
A
25
-
-5.0
5.0
µA
Vagc High Input Bias Current
(Vagc = 2.1V, VCC = 5.5V)
Ivagc_HI
A
25
-
10
400
µA
Vagc Low Input Bias Current
(Vagc = 0.7V, VCC = 5.5V)
Ivagc_LO
A
25
-400
-10
-
µA
Power Enable Time (50% VPE to 90% ICC)
PEt
B
25
-
5
10
µs
Power Disable Time (50% VPE to 10% ICC)
PDt
B
25
-
0.1
10
µs
Power Gain
(AGC_CTRL = 0.7V)
VCC = 5.5V
Pre-Amp Noise Figure (Max Gain)
Pre-Amp AGC Range (Max - Min Gain)
AGC Control Voltage Range
Pre-Amp RF Output 1dB
Compression
VCC = 5.5V
RF Output Third Order Intercept
Input VSWR
Input Return Loss
Output VSWR
Output Return Loss
POWER SUPPLY AND LOGIC CHARACTERISTICS
Voltage Supply Range
Supply Current (VCC = 5.5V)
Power Down Supply Current (VCC = 5.5V)
NOTES:
2. Test Level: A = 100% production tested, B = Typical or Limit based on characterization data, C = Design information, goal or condition.
3. Bias Resistor at pin 16 changes according to the relationship mentioned in Note 4 of the Typical Applications Circuit.
2-204
HFA3663
Typical Application Circuit
VCC = 5.0V
C1
2.2µF
TRANSMIT
ENABLE
C2
3300pF
7pF
C3
330pF
RF OUTPUT
50Ω
GND
C4
7pF
1
20
2
19
3
18
LO_BY C9
LO_IN 7pF
PRE_OUT
7pF
GND
C5
PRE_VCC2
22pF
GND
17
4
C7
5
16
6
15
7
14
8
13
9
12
IF_BY
PRE_VCC1
C8
330pF
GND
AGC CONTROL
C10
C11
3300pF
LO INPUT
50Ω
IF INPUT
50Ω
3300pF
C13
7pF
MIX_VCC
AGC_CTRL
10
7pF
C12
TXM_RF
PRE_IN
7pF
NOTE
4
1.69K
GND
IF_IN
BIAS_VCC
4.7nH
GND
330pF
TX_PE
PRE_VCC3
C14
7pF
11
C15
3300pF
330pF
7pF
AGC
CONTROL
NOTE 5
50Ω BPF
LO REJECT
FILTER
NOTE 5
NOTES:
4. Required external resistor for Mixer biasing. Value optimized for 2.7mA bias current with R = (VCC - 0.93)/2.7mA. Most Mixer cell characteristics
like Gain, NF etc., can be affected when biasing is outside the optimum value.
5. The combination of these attenuator pads and the Band Pass Filter insertion loss shall bring the overall Cascaded Gain at the desired frequency
of operation from 21dB to 22dB for best performance. The selection of these values is optional. The total gain, LO feedthru, Mixer and Preamplifier interaction (stability) and output compression point performances can be manipulated according to the user needs.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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2-205
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