AD AD7264BSTZ-5-RL7 1 msps, 14-bit, simultaneous sampling sar adc with pga and four comparator Datasheet

1 MSPS, 14-Bit, Simultaneous Sampling
SAR ADC with PGA and Four Comparators
AD7264
FEATURES
GENERAL DESCRIPTION
The AD7264 is a dual, 14-bit, high speed, low power, successive
approximation ADC that operates from a single 5 V power supply
and features throughput rates of up to 1 MSPS per on-chip
ADC (500 kSPS for the AD7264-5). Two complete ADC functions allow simultaneous sampling and conversion of two
channels. Each ADC is preceded by a true differential analog
input with a PGA. There are 14 gain settings available: ×1, ×2,
×3, ×4, ×6, ×8, ×12, ×16, ×24, ×32, ×48, ×64, ×96, and ×128.
The AD7264 contains four comparators. Comparator A and
Comparator B are optimized for low power, whereas Comparator C
and Comparator D have fast propagation delays. The AD7264
features a calibration function to remove any device offset error
and programmable gain adjust registers to allow for input path
(for example, sensor) offset and gain compensation. The AD7264
has an on-chip 2.5 V reference that can be disabled if an external
reference is preferred. The AD7264 is available in 48-lead LFCSP
and LQFP packages.
The AD7264 is ideally suited for monitoring small amplitude
signals from a variety of sensors. The parts include all the
functionality needed for monitoring the position feedback signals
from a variety of analog encoders used in motor control systems.
FUNCTIONAL BLOCK DIAGRAM
VREFA
AVCC
REF
VA+
VA–
AD7264
BUF
PGA
14-BIT
SUCCESSIVE
APPROXIMATION
ADC
T/H
OUTPUT
DRIVERS
DOUTA
SCLK
CAL
CS
REFSEL
G0
G1
G2
G3
CONTROL
LOGIC
VDRIVE
VB+
VB–
PGA
14-BIT
SUCCESSIVE
APPROXIMATION
ADC
T/H
OUTPUT
DRIVERS
BUF
DOUTB
PD0/DIN
PD1
PD2
VREFB
CA_CBVCC
CA+
CA–
CB+
COMP
CB–
CA_CB_GND
COMP
CC_CDVCC
CC+
CC–
CD+
CD–
CC_CD_GND
OUTPUT
DRIVERS
COMP
COUTA
OUTPUT
DRIVERS
OUTPUT
DRIVERS
COMP
COUTB
COUTC
OUTPUT
DRIVERS
AGND
COUTD
DGND
06732-001
Dual, simultaneous sampling, 14-bit, 2-channel ADC
True differential analog inputs
Programmable gain stage: ×1, ×2, ×3, ×4, ×6, ×8, ×12, ×16,
×24, ×32, ×48, ×64, ×96, ×128
Throughput rate per ADC
1 MSPS for AD7264
500 kSPS for AD7264-5
Analog input impedance: >1 GΩ
Wide input bandwidth
−3 dB bandwidth: 1.7 MHz at gain = 2
4 on-chip comparators
SNR: 78 dB typical at gain = 2, 71 dB typical at gain = 32
Device offset calibration
System gain calibration
On-chip reference: 2.5 V
−40°C to +105°C operation
High speed serial interface
Compatible with SPI, QSPI™, MICROWIRE™, and DSP
48-lead LFCSP and LQFP packages
Figure 1.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
Integrated PGA with a variety of flexible gain settings to
allow detection and conversion of low level analog signals.
Each PGA is followed by a dual simultaneous sampling
ADC, featuring throughput rates of 1 MSPS per ADC
(500 kSPS for the AD7264-5). The conversion result of
both ADCs is simultaneously available on separate data
lines or in succession on one data line if only one serial
port is available.
Four integrated comparators that can be used to count
signals from pole sensors in motor control applications.
Internal 2.5 V reference.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
AD7264
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Connection Diagrams .................................................. 17
General Description ......................................................................... 1
Application Details ..................................................................... 19
Functional Block Diagram .............................................................. 1
Modes of Operation ....................................................................... 20
Product Highlights ........................................................................... 1
Pin Driven Mode ........................................................................ 20
Revision History ............................................................................... 2
Gain Selection ............................................................................. 20
Specifications..................................................................................... 3
Power-Down Modes .................................................................. 20
Timing Specifications .................................................................. 6
Control Register ......................................................................... 21
Absolute Maximum Ratings............................................................ 7
On-Chip Registers ...................................................................... 22
ESD Caution .................................................................................. 7
Serial Interface ................................................................................ 23
Pin Configuration and Function Descriptions ............................. 8
Calibration ....................................................................................... 25
Typical Performance Characteristics ........................................... 10
Internal Offset Calibration ........................................................ 25
Terminology .................................................................................... 14
Adjusting the Offset Calibration Register ............................... 26
Theory of Operation ...................................................................... 15
System Gain Calibration............................................................ 26
Circuit Information .................................................................... 15
Application Hints ........................................................................... 27
Comparators................................................................................ 15
Grounding and Layout .............................................................. 27
Operation..................................................................................... 15
PCB Design Guidelines for LFCSP .......................................... 27
Analog Inputs .............................................................................. 15
Outline Dimensions ....................................................................... 28
VDRIVE ............................................................................................ 16
Ordering Guide .......................................................................... 29
Reference ..................................................................................... 16
REVISION HISTORY
7/08—Rev. 0 to Rev. A
Added AD7264-5 ................................................................ Universal
Added LQFP Package......................................................... Universal
Changes to Figure 1 .......................................................................... 1
Changes to Common-Mode Voltage Range, VCM Parameter ..... 3
Changes to Table 3 ............................................................................ 7
Changes to Pin Configuration and Function
Description Section .......................................................................... 8
Changes to Figure 29 ...................................................................... 19
Updated Outline Dimensions ....................................................... 28
Changes to Ordering Guide .......................................................... 29
5/08—Revision 0: Initial Version
Rev. A | Page 2 of 32
AD7264
SPECIFICATIONS
AVCC = 4.75 V to 5.25 V, CA_CBVCC = CC_CDVCC = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, fS = 1 MSPS and fSCLK = 34 MHz for
the AD7264, fS = 500 kSPS and fSCLK = 20 MHz for the AD7264-5, VREF = 2.5 V internal/external; TA = −40°C to +105°C, unless otherwise
noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE 1
Signal-to-Noise Ratio (SNR) 2
Signal-to-(Noise + Distortion) Ratio
(SINAD)2
Total Harmonic Distortion (THD)2
Spurious-Free Dynamic Range (SFDR)
Common-Mode Rejection Ratio (CMRR)
Min
Typ
76
74
78
77
±1.5
±0.5
±0.122
±0.018
±0.061
±0.092
±0.012
±0.061
±0.122
±0.018
±0.061
2.5
Positive Full-Scale Error Match2
Zero Code Error2
Zero Code Error Match2
Negative Full-Scale Error2
Negative Full-Scale Error Match2
Zero Code Error Drift
ANALOG INPUT
Input Voltage Range, VIN+ and VIN−
Common-Mode Voltage Range, VCM
DC Leakage Current
Input Capacitance3
Input Impedance3
REFERENCE INPUT/OUTPUT
Reference Output Voltage 5
Reference Input Voltage
DC Leakage Current
Input Capacitance3
VREFA, VREFB Output Impedance3
Reference Temperature Coefficient
VREF Noise3
−77
−90
1.2
1.7
DC ACCURACY
Resolution
Integral Nonlinearity2
Differential Nonlinearity2
Positive Full-Scale Error2
VCM ±
Unit
dB
dB
−85
−97
−76
ADC-to-ADC Isolation2
Bandwidth 3
Max
dB
dB
dB
dB
MHz
MHz
14
±3
±0.99
±0.305
±0.244
±0.305
VREF
2 × Gain
Bits
LSB
LSB
% FSR
% FSR
% FSR
% FSR
% FSR
% FSR
% FSR
% FSR
% FSR
μV/°C
(VCC/2) − 0.4
(VCC/2) − 0.4
(VCC/2) − 0.6
(VCC/2) + 0.2
(VCC/2) + 0.4
(VCC/2) + 0.8
±1
V
V
V
μA
pF
GΩ
2.505
V
V
μA
±1
20
4
20
20
Rev. A | Page 3 of 32
Guaranteed no missed codes to 14 bits
Precalibration
Postcalibration
Precalibration
Postcalibration
Precalibration
Postcalibration
VCM = 2 V; PGA gain setting = 1;
see Figure 19 4
VCM = AVCC/2; PGA gain setting = 2
VCM = AVCC/2; 3 ≤ PGA gain setting ≤ 32
VCM = AVCC/2; PGA gain setting ≥ 48
V
2.5
2.5
±0.3
@ −3 dB; PGA gain setting = 128
@ −3 dB; PGA gain setting = 2
VCM = AVCC/2; PGA gain setting ≥ 2
VCM + 100 mV
2.495
For PGA gain setting = 2, ripple
frequency of 50 Hz/60 Hz; see
Figure 17 and Figure 18
V
VCM − 100 mV
±0.001
5
1
Test Conditions/Comments
fIN = 100 kHz sine wave
PGA gain setting = 2
pF
Ω
ppm/°C
μV rms
2.5 V ± 5 mV max @ 25°C
External reference applied to
Pin VREFA/Pin VREFB
AD7264
Parameter
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN3
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating State Leakage Current
Floating State Output Capacitance3
Output Coding
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time2
Throughput Rate
COMPARATORS
Input Offset
Comparator A and Comparator B
Comparator C and Comparator D
Offset Voltage Drift
Input Common-Mode Range3
Input Capacitance3
Input Impedance3
IDD Normal Mode (Static) 6
Comparator A and Comparator B
Comparator C and Comparator D
Min
Typ
Max
Unit
0.8
±1
V
V
μA
pF
0.4
±1
V
V
μA
pF
0.7 × VDRIVE
4
VDRIVE − 0.2
5
Twos complement
19 × tSCLK
400
1
500
±2
±2
0.5
0 to 4
0 to 1.7
4
1
3
6
60
120
±4
±4
8.5
170
ns
ns
MSPS
kSPS
Comparator C and Comparator D
Low to High, tPLH
Comparator A and Comparator B
Comparator C and Comparator D
1.4
0.95
0.20
0.13
3.5
2
0.93
0.18
0.12
4
0.32
0.28
±250
±10
Rev. A | Page 4 of 32
AD7264
AD7264-5
All comparators
CA_CBVCC = 5 V
CA_CBVCC = 2.7 V
μA
μA
μA
μA
25 pF load, COUTx = 0 V, VCM = AVCC/2,
VOVERDRIVE = 200 mV differential
CA_CBVCC = 3.3 V
CA_CBVCC = 5.25 V
CC_CDVCC = 3.3 V
CC_CDVCC = 5.25 V
VCM = AVCC/2, VOVERDRIVE = 200 mV
differential
μs
μs
μs
μs
CA_CBVCC = 2.7 V
CA_CBVCC = 5 V
CC_CDVCC = 2.7 V
CC_CDVCC = 5 V
μs
μs
μs
μs
CA_CBVCC = 2.7 V
CA_CBVCC = 5 V
CC_CDVCC = 2.7 V
CC_CDVCC = 5 V
VCM = AVCC/2, VOVERDRIVE = 200 mV
differential
Delay Matching
Comparator A and Comparator B
Comparator C and Comparator D
VIN = 0 V or VDRIVE
mV
mV
μV/°C
V
V
pF
GΩ
Propagation Delay Time2
High to Low, tPHL
Comparator A and Comparator B
Test Conditions/Comments
ns
ns
TA = 25°C to 105°C only
AD7264
Parameter
POWER REQUIREMENTS
AVCC
CA_CBVCC, CC_CDVCC
VDRIVE
IDD
ADC Normal Mode (Static)
ADC Normal Mode (Dynamic)
Shutdown Mode
Power Dissipation
ADC Normal Mode (Static)
ADC Normal Mode (Dynamic)
Shutdown Mode
Min
Typ
Max
Unit
5.25
5.25
5.25
V
V
V
20
23
0.5
31.5
33.3
1
mA
mA
μA
105
120
2.625
165
175
5.25
mW
mW
μW
4.75
2.7
2.7
1
Test Conditions/Comments
Digital inputs = 0 V or VDRIVE
AVCC = 5.25 V
fS = 1 MSPS, AVCC = 5.25 V
AVCC = 5.25 V, ADCs and comparators
powered down
These specifications were determined without the use of the gain calibration feature.
See the Terminology section.
Samples are tested during initial release to ensure compliance; they are not subject to production testing.
4
For PGA gain = 1, to utilize the full analog input range (VCM ± VREF/2) of the AD7264, the VCM voltage should be dropped to lie within a range from 1.95 V to 2.05 V.
5
Refers to Pin VREFA or Pin VREFB.
6
This specification includes the IDD for both comparators. The IDD per comparator is the specified value divided by 2.
2
3
Rev. A | Page 5 of 32
AD7264
TIMING SPECIFICATIONS
AVCC = 4.75 V to 5.25 V, CA_CBVCC = CC_CDVCC = 2.7 V to 5.25 V, VREF = 2.5 V internal/external; TA = TMIN to TMAX, unless otherwise noted. 1
Table 2.
tQUIET
Limit at TMIN , TMAX
2.7 V ≤ VDRIVE ≤ 3.6 V
4.75 V ≤ VDRIVE ≤ 5.25 V
200
200
34
34 2
20
20
19 × tSCLK
19 × tSCLK
560
560
950
950
13
13
Unit
kHz min
MHz max
MHz max
ns max
ns max
ns max
ns min
t2
t3 3
10
15
10
15
ns min
ns max
t4
t5
t6
t7
t8
t9
29
15
0.4 × tSCLK
0.4 × tSCLK
13
13
23
13
0.4 × tSCLK
0.4 × tSCLK
13
13
ns max
ns min
ns min
ns min
ns min
ns max
t10
5
35
2
2
5
35
2
2
ns min
ns max
μs min
μs min
3
3
240
15
3
3
240
15
ns min
ns min
μs max
μs max
Parameter
fSCLK
tCONVERT
t11
t12
t13
t14
tPOWER-UP
Description
AD7264
AD7264-5
tSCLK = 1/fSCLK
AD7264
AD7264-5
Minimum time between end of serial read/bus relinquish
and next falling edge of CS
CS to SCLK setup time
Delay from 19th SCLK falling edge until DOUTA and DOUTB are
three-state disabled
Data access time after SCLK falling edge
SCLK to data valid hold time
SCLK high pulse width
SCLK low pulse width
CS rising edge to falling edge pulse width
CS rising edge to DOUTA, DOUTB high impedance/bus
relinquish
SCLK falling edge to DOUTA, DOUTB high impedance
SCLK falling edge to DOUTA, DOUTB high impedance
Minimum CAL pin high time
Minimum time between the CAL pin high and the CS
falling edge
DIN setup time prior to SCLK falling edge
DIN hold time after SCLK falling edge
Internal reference, with a 1 μF decoupling capacitor
With an external reference, 10 μs typical
1
Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. See the
Terminology section.
2
The AD7264 is functional with a 40 MHz SCLK at 25°C, but specified performance is not guaranteed with SCLK frequencies greater than 34 MHz.
3
The time required for the output to cross 0.4 V or 2.4 V.
CS
t8
t2
1
2
3
4
5
18
20
19
t7
t3
DOUTA
THREE-STATE
DOUTB
THREE-STATE
21
t4
31
32
33
t9
t5
DB13 A
DB12 A DB11A
DB1A
DB0 A
DB13 B
DB12 B DB11B
DB1B
DB0 B
Figure 2. Serial Interface Timing Diagram
Rev. A | Page 6 of 32
tQUIET
THREESTATE
THREESTATE
06732-002
SCLK
t6
AD7264
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VDRIVE to DGND
VDRIVE to AGND
AVCC to AGND, DGND
CA_CBVCC to CA_CB_GND
CC_CDVCC to CC_CD_GND
AGND to DGND
CA_CB_GND, CC_CD_GND to DGND
Analog Input Voltage to AGND
Digital Input Voltage to DGND
Digital Output Voltage to GND
VREFA, VREFB Input to AGND
COUTA, COUTB, COUTC, COUTD to GND
CA±, CB±, CC±, CD± to
CA_CB_GND, CC_CD_GND
Operating Temperature Range
Storage Temperature Range
Junction Temperature
LQFP Package
θJA Thermal Impedance
θJC Thermal Impedance
LFCSP Package
θJA Thermal Impedance
θJC Thermal Impedance
Pb-Free Temperature, Soldering
Reflow
ESD
Rating
−0.3 V to AVCC
−0.3 V to AVCC
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to AVCC + 0.3 V
−0.3 V to +7 V
−0.3 V to VDRIVE + 0.3 V
−0.3 V to AVCC + 0.3 V
−0.3 V to VDRIVE + 0.3 V
−0.3 V to
CA_CBVCC/CC_CDVCC + 0.3 V
−40°C to +105°C
−65°C to +150°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
55°C/W
16°C/W
30°C/W
3°C/W
255°C
2 kV
Rev. A | Page 7 of 32
AD7264
48 47 46 45 44 43 42 41 40 39 38 37
TOP VIEW
(Not to Scale)
CS
SCLK
33
AVCC
32
DOUTA
31
DOUTB
AGND
AGND
AVCC
AGND
VB+
VB–
AVCC
CC_CDVCC
COUTA
29 COUTB
30
AGND 8
VB+ 9
VB– 10
AVCC 11
CC_CDVCC 12
28
DGND
27
VDRIVE
26
COUTC
25
COUTD
3
4
5
6
7
8
9
10
11
12
G0
G1
G2
G3
36
35
34
33
PIN 1
INDICATOR
32
31
30
29
28
27
26
25
AD7264
TOP VIEW
(Not to Scale)
CC+
CC–
CD+
CD–
CC_CD_GND
VREFB
06732-003
REFSEL
PD0/DIN
PD1
PD2
AVCC
AGND
CC_CD_GND
VREF B
CD–
CD+
CC–
13 14 15 16 17 18 19 20 21 22 23 24
CC+
1
2
CAL
CS
SCLK
AVCC
DOUTA
DOUTB
COUTA
COUTB
DGND
VDRIVE
COUTC
COUTD
NOTES
1. THE EXPOSED METAL PADDLE ON THE BOTTOM OF THE LFCSP PACKAGE MUST
BE SOLDERED TO PCB GROUND FOR PROPER HEAT DISSIPATION AND ALSO FOR
NOISE AND MECHANICAL STRENGTH BENEFITS.
06732-004
AD7264
AGND 6
AVCC 7
35
34
CA_CBVCC
AVCC
VA–
VA+
REFSEL
AGND 5
CAL
PD2
PD1
PD0/DIN
AVCC 2
VA– 3
VA+ 4
36
AGND
AVCC
PIN 1
INDICATOR
13
14
15
16
17
18
19
20
21
22
23
24
CA_CBVCC 1
AGND
AVCC
CA+
CA–
CB+
CB–
CA_CB_GND
VREFA
48
47
46
45
44
43
42
41
40
39
38
37
G3
G2
G1
G0
AVCC
AGND
CB–
CA_CB_GND
VREF A
CB+
CA–
CA+
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 4. 48-Lead LFCSP Pin Configuration
Figure 3. 48-Lead LQFP Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
2, 7, 11, 20, 33, 41
Mnemonic
AVCC
1
CA_CBVCC
12
CC_CDVCC
4, 3
9, 10
43, 18
VA+, VA−
VB+, VB−
VREFA, VREFB
34
SCLK
35
36
21
CS
CAL
PD2
22
PD1
23
PD0/DIN
Description
Analog Supply Voltage, 4.75 V to 5.25 V. This is the supply voltage for the analog circuitry on the
AD7264. All AVCC pins can be tied together. This supply should be decoupled to AGND with a 100 nF
ceramic capacitor per supply and a 10 μF tantalum capacitor.
Comparator Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for Comparator A and
Comparator B. This supply should be decoupled to CA_CB_GND. AVCC, CC_CDVCC, and CA_CBVCC can be
tied together.
Comparator Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for Comparator C and
Comparator D. This supply should be decoupled to CC_CD_GND. AVCC, CC_CDVCC, and CA_CBVCC can be
tied together.
Analog Inputs of ADC A. True differential input pair.
Analog Inputs of ADC B. True differential input pair.
Reference Input/Output. Decoupling capacitors are connected to these pins to decouple the
internal reference buffer for each respective ADC. Typically, 1 μF capacitors are required to decouple
the reference. Provided the output is buffered, the on-chip reference can be taken from these pins
and applied externally to the rest of a system.
Serial Clock. Logic input. A serial clock input provides the SCLK for accessing the data from the
AD7264. This clock is also used as the clock source for the conversion process. A minimum of
33 clocks are required to perform the conversion and access the 14-bit result.
Chip Select. Active low logic input. This input initiates conversions on the AD7264.
Logic Input. Initiates an internal offset calibration.
Logic Input. Places the AD7264 in the selected shutdown mode in conjunction with the PD1 and
PD0 pins. See Table 7.
Logic Input. Places the AD7264 in the selected shutdown mode in conjunction with the PD2 and
PD0 pins. See Table 7.
Logic Input/Data Input. Places the AD7264 in the selected shutdown mode in conjunction with the
PD2 and PD1 pins. See Table 7. If all gain selection pins, G0 to G3, are tied low, this pin acts as the
data input pin and all programming is via the control register (see Table 8). Data to be written to the
AD7264 control register is provided on this input and is clocked into the register on the falling edge
of SCLK.
Rev. A | Page 8 of 32
AD7264
Pin No.
48, 47, 46, 45
5, 6, 8, 19, 42
Mnemonic
CA+, CA−,
CB+, CB−
CC+, CC−,
CD+, CD−
AGND
28
DGND
30, 29, 26, 25
32, 31
COUTA, COUTB,
COUTC, COUTD
DOUTA, DOUTB
40, 39, 38, 37
G0, G1, G2, G3
27
VDRIVE
44, 17
CA_CB_GND,
CC_CD_GND
24
REFSEL
13, 14, 15, 16
Description
Comparator Inputs. These pins are the inverting and noninverting analog inputs for Comparator A
and Comparator B. These two comparators have very low power consumption.
Comparator Inputs. These pins are the inverting and noninverting analog inputs for Comparator C
and Comparator D. These two comparators offer very fast propagation delays.
Analog Ground. Ground reference point for all analog circuitry on the AD7264. All analog input
signals and any external reference signal should be referred to this AGND voltage. All AGND pins
should be connected to the AGND plane of a system. The AGND, DGND, CA_CB_GND, and
CC_CD_GND voltages should ideally be at the same potential and must not be more than 0.3 V apart,
even on a transient basis. CA_CB_GND and CC_CD_GND can be tied to AGND.
Digital Ground. Ground reference point for all digital circuitry on the AD7264. The DGND pin should
be connected to the DGND plane of a system. The DGND and AGND voltages should ideally be at
the same potential and must not be more than 0.3 V apart, even on a transient basis.
Comparator Outputs. These pins provide a CMOS (push-pull) output from each respective
comparator. These are digital output pins with logic levels determined by the VDRIVE supply.
Serial Data Outputs. The data output from the AD7264 is supplied to each pin as a serial data stream
in twos complement format. The bits are clocked out on the falling edge of the SCLK input. A total of
33 SCLK cycles are required to perform the conversion and access the 14-bit data. During the
conversion process, the data output pins are in three-state and, when the conversion is completed,
the 19th SCLK edge clocks out the MSB. The data appears simultaneously on both pins from the
simultaneous conversions of both ADCs. The data is provided MSB first. If CS is held low for a further
14 SCLK cycles on either DOUTA or DOUTB following the initial 33 SCLK cycles, the data from the other
ADC follows on the DOUT pin. This allows data from a simultaneous conversion on both ADCs to be
gathered in serial format on either DOUTA or DOUTB using only one serial port.
Logic Inputs. These pins are used to program the gain setting of the front-end amplifiers. If all four
pins are tied low, the PD0/DIN pin acts as a data input pin, DIN, and all programming is made via the
control register. See Table 6.
Logic Power Supply Input, 2.7 V to 5.25 V. The voltage supplied at this pin determines at what
voltage the interface operates, including the comparator outputs. This pin should be decoupled
to DGND.
Comparator Ground. Ground reference point for all comparator circuitry on the AD7264. Both the
CA_CB_GND and CC_CD_GND pins should connect to the GND plane of a system and can be tied to
AGND. The DGND, AGND, CA_CB_GND, and CC_CD_GND voltages should ideally be at the same
potential and must not be more than 0.3 V apart, even on a transient basis.
Internal/External Reference Selection. Logic input. If this pin is tied to a logic high voltage, the
on-chip 2.5 V reference is used as the reference source for both ADC A and ADC B. If the REFSEL
pin is tied to GND, an external reference can be supplied to the AD7264 through the VREFA and/or
VREFB pins.
Rev. A | Page 9 of 32
AD7264
1.0
0.8
0.8
0.6
0.6
0.4
0.4
DNL ERROR (LSB)
1.0
0.2
0
–0.2
–0.8
–1.0
0
2000
4000
6000
8000
10,000 12,000 14,000 16,000
CODE
0
–0.2
–0.4
–0.6
TA = 25°C
AVCC = 5V
VDRIVE = 5V INTERNAL REFERENCE
fS = 1MSPS GAIN = 32
–0.8
–1.0
0
2000
–1.5
1.0
–1.0
INL ERROR (LSB)
1.5
0.5
0
–0.5
AVCC = 5V
VDRIVE = 5V
fS = 1MSPS
TA = 25°C
INTERNAL REFERENCE
GAIN = 2
0
2000
4000
6000
8000
AVCC = 5V
VDRIVE = 5V
fS = 1MSPS
TA = 25°C
INTERNAL REFERENCE
GAIN = 32
–0.5
0
–0.5
–1.5
10,000 12,000 14,000 16,000
CODE
–2.0
0
2000
–40
8000
0
10,000 12,000 14,000 16,000
AVCC = 5V
VDRIVE = 2.7V
fS = 1MSPS
TA = 25°C
fIN = 100kHz
INTERNAL REFERENCE
SNR = 72dB
THD = –87dB
GAIN = 32
–20
–40
–60
–80
–100
–100
–120
–120
–140
0
50
100
150
200
250
300
350
FREQUENCY (kHz)
400
450
06732-009
–80
Figure 7. Typical FFT at Gain of 2
–140
0
50
100
150
200
250
300
350
400
FREQUENCY (kHz)
Figure 10. Typical FFT at Gain of 32
Rev. A | Page 10 of 32
450
500
06732-010
(dB)
(dB)
–60
6000
Figure 9. Typical INL at Gain of 32
AVCC = 5V
VDRIVE = 2.7V
fS = 1MSPS
TA = 25°C
fIN = 100kHz
INTERNAL REFERENCE
SNR = 79dB
THD = –96dB
GAIN = 2
–20
4000
CODE
Figure 6. Typical INL at Gain of 2
0
10,000 12,000 14,000 16,000
–1.0
06732-006
INL ERROR (LSB)
2.0
–2.0
8000
Figure 8. Typical DNL at Gain of 32
2.0
–1.5
6000
CODE
Figure 5. Typical DNL at Gain of 2
–1.0
4000
06732-007
AVCC = 5V
VDRIVE = 5V
fS = 1MSPS
TA = 25°C
INTERNAL REFERENCE
GAIN = 2
–0.6
0.2
06732-008
–0.4
06732-005
DNL ERROR (LSB)
TYPICAL PERFORMANCE CHARACTERISTICS
AD7264
2.4968
8000
7793
7000
2.4967
2.4966
5000
VREF (V)
4000
2.4965
2.4964
3000
2.4963
2000
1117
1084
1000
0
6
8189
8190
0
8191
8192
8193
8194
CODE
2.4961
06732-011
0
AVCC = 5V
VDRIVE = 3V
fS = 1MSPS
INTERNAL REFERENCE
2.4962
0
20
40
60
80
100
120
140
160
180
200
CURRENT LOAD (µA)
Figure 11. Histogram of Codes for 10k Samples at Gain of 2
Figure 14. VREF vs. Reference Output Current Drive
3000
1900
1800
2486
1700
3dB BANDWIDTH (kHz)
2000
1600
1861
1500
1222
1081
1000
498
0
1400
1300
1200
1100
1000
900
381
500
1500
800
22
2
8186
8187
132
8188
82
8189
8190
700
16
8192
8194
8196
8191
8193
8195
8197
CODE
600
06732-012
NUMBER OF HITS
2180
AVCC = 5V
VDRIVE = 5V
fS = 1MSPS
INTERNAL REFERENCE
1
2
–70
6
8
12
16
24
32
48
64
96 128
Figure 15. 3 dB Bandwidth vs. Gain
80
AVCC = 5V
VDRIVE = 5V
fS = 1MSPS
INTERNAL REFERENCE
75
70
GAIN = 32
65
–75
SNR (dB)
THD (dB)
4
GAIN
Figure 12. Histogram of Codes for 10k Samples at Gain of 32
–65
3
06732-016
2500
GAIN = 2
–80
60
55
50
45
AVCC = 5V
VDRIVE = 5V
fS = 1MSPS
INTERNAL REFERENCE
fIN = 100kHz
40
–90
10
110
210
310
410
510
610
710
810
ANALOG INPUT FREQUENCY (kHz)
910
06732-014
35
Figure 13. THD vs. Analog Input Frequency up to 1 MHz at Gain of 2 and 32
Rev. A | Page 11 of 32
30
1
2
3
4
6
8
12
16
24
32
48
64
96 128
PGA GAIN
Figure 16. SNR vs. PGA Gain for an Analog Input Tone of 100 kHz
06732-017
–85
06732-015
NUMBER OF HITS
6000
AD7264
10
–88
9
–86
8
PROPAGATION DELAY (µs)
–90
–82
–80
–78
–76
AVCC = 5V
VDRIVE = 5V
fS = 1MSPS
INTERNAL REFERENCE
fRIPPLE = 50kHz
1
2
3
4
6
8
12
16
24
32
48
64
96 128
GAIN
3
2
0
–79
1.8
–78
1.6
PROPAGATION DELAY (µs)
2.0
–76
–75
–74
AVCC = 5V
VDRIVE = 5V
fS = 1MSPS
VRIPPLE = 700mV p-p
GAIN = 2
INTERNAL REFERENCE
–71
–70
0
20
40
60
80
100
120
140
160
180
200
RIPPLE FREQUENCY (kHz)
Figure 18. Common-Mode Rejection vs. Common-Mode Ripple Frequency
–20
–30
0.8
0.6
G=4
G=6
G ≥ 32
= 2.7V
= 3.6V
= 4.5V
= 5V
= 2.7V
= 3.6V
= 5V
= 4.5V
0
10
20
30
40
50
60
70
80
90
100
VDRIVE = 5V
GAIN = 2
TA = 25°C
INTERNAL REFERENCE
100mV p-p SINE WAVE ON AVCC
AVCC DECOUPLED WITH
10µF AND 100nF CAPACITORS
–90
–95
–100
–110
G = 24
G=8
1.9
2.1
2.3
2.5
2.7
2.9
3.1
3.3
3.5
3.7
VCM RANGE (V)
06732-020
1.7
100
–115
G = 12
1.5
90
–105
G = 16
1.3
80
0.4
–85
–60
–100
1.0
–80
–50
–90
70
L TO H, CC_CDVCC
L TO H, CC_CDVCC
L TO H, CC_CDVCC
L TO H, CC_CDVCC
H TO L, CC_CDVCC
H TO L, CC_CDVCC
H TO L, CC_CDVCC
H TO L, CC_CDVCC
1.2
–75
G=3
–80
60
Figure 21. Propagation Delay for Comparator C and Comparator D
vs. Overdrive Voltage for Various Supply Voltages
G=2
–70
50
OVERDRIVE VOLTAGE (mV)
G=1
–40
40
AVCC = 5V
VDRIVE = 3.3V
TA = 25°C
–70
AVCC = 5V
VDRIVE = 5V
fS = 1MSPS
fIN = 100kHz
INTERNAL REFERENCE
30
1.4
0
PSRR (dB)
–10
20
0.2
06732-019
–72
10
Figure 20. Propagation Delay for Comparator A and Comparator B
vs. Overdrive Voltage for Various Supply Voltages
–80
–73
0
OVERDRIVE VOLTAGE (mV)
–77
CMR (dB)
4
1
Figure 17. Common-Mode Rejection vs. Gain
THD (dB)
5
= 3.6V
= 4.5V
= 2.7V
= 5V
= 2.7V
= 3.6V
= 4.5V
= 5V
06732-021
–70
6
CA_CBVCC
CA_CBVCC
CA_CBVCC
CA_CBVCC
CA_CBVCC
CA_CBVCC
CA_CBVCC
CA_CBVCC
06732-022
–72
06732-018
–74
H TO L,
H TO L,
H TO L,
H TO L,
L TO H,
L TO H,
L TO H,
L TO H,
7
–120
0
200
400
600
800
SUPPLY RIPPLE FREQUENCY (kHz)
Figure 22. Power Supply Rejection Ratio
Figure 19. THD vs. Common-Mode Voltage Range for Various
PGA Gain Settings
Rev. A | Page 12 of 32
1000
06732-036
CMR (dB)
–84
AVCC = 5V
VDRIVE = 3.3V
TA = 25°C
AD7264
300
COUTA/COUTB SINK CURRENT
COUTC/COUTD SINK CURRENT
DOUT SINK CURRENT
100
0
–100
DOUT SOURCE CURRENT
–200
COUTA/COUTB SOURCE CURRENT
COUTC/COUTD SOURCE CURRENT
–300
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5
CURRENT (mA)
06732-037
VOUT (V) OR VDD – VOUT (mV)
200
Figure 23. DOUT and COUT Source and Sink Current
Rev. A | Page 13 of 32
AD7264
TERMINOLOGY
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
and the ideal 1 LSB change between any two adjacent codes in
the ADC.
Integral Nonlinearity (INL)
Integral nonlinearity is the maximum deviation from a straight
line passing through the endpoints of the ADC transfer function.
The endpoints of the transfer function are zero scale, a single
(1) LSB point below the first code transition, and full scale, a
point 1 LSB above the last code transition.
Zero Code Error
This is the deviation of the midscale transition (all 1s to all 0s)
from the ideal VIN voltage, that is, VCM − ½ LSB.
Positive Full-Scale Error
This is the deviation of the last code transition (011 … 110 to
011 … 111) from the ideal, that is,
⎛ VREF ⎞
VCM + ⎜
⎟ − 1 LSB
⎝ 2 × Gain ⎠
after the zero code error has been adjusted out.
Negative Full-Scale Error
This is the deviation of the first code transition (10 … 000 to
10 … 001) from the ideal, that is,
⎛ VREF ⎞
VCM − ⎜
⎟ + 1 LSB
⎝ 2 × Gain ⎠
after the zero code error has been adjusted out.
Zero Code Error Match
This is the difference in zero code error across both ADCs.
Positive Full-Scale Error Match
This is the difference in positive full-scale error across both ADCs.
Negative Full-Scale Error Match
This is the difference in negative full-scale error across both ADCs.
Track-and-Hold Acquisition Time
The track-and-hold amplifier returns to track mode at the end
of conversion. Track-and-hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach
its final value, within ±1/2 LSB, after the end of conversion.
Signal-to-(Noise + Distortion) Ratio
This ratio is the measured ratio of signal-to-(noise + distortion)
at the output of the analog-to-digital converter. The signal is the
rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2),
excluding dc. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the
smaller the quantization noise.
The theoretical signal-to-(noise + distortion) ratio for an ideal
N-bit converter with a sine wave input is given by
Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB
Thus, for a 14-bit converter, this is 86 dB.
Total Harmonic Distortion (THD)
Total harmonic distortion is the ratio of the rms sum of
harmonics to the fundamental. For the AD7264, it is defined as
THD(dB) = 20 log
V 2 2 + V 3 2 + V 4 2 + V 5 2 + V6 2
V1
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic, or spurious noise, is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2, excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined
by the largest harmonic in the spectrum, but for ADCs where
the harmonics are buried in the noise floor, it is a noise peak.
ADC-to-ADC Isolation
ADC-to-ADC isolation is a measure of the level of crosstalk
between ADC A and ADC B. It is measured by applying a fullscale, 100 kHz sine wave signal to all unselected input channels and
determining how much that signal is attenuated in the selected
channel with a 40 kHz signal. The figure given is the worst-case.
Power Supply Rejection Ration (PSRR)
Variations in power supply affect the full-scale transition but
not the linearity of the converter. PSRR is the maximum change
in the full-scale transition point due to a change in power
supply voltage from the nominal value (see Figure 22).
Propagation Delay Time, Low to High (tPLH)
Propagation delay time from low to high is defined as the time
taken from the 50% point on a low to high input signal until the
digital output signal reaches 50% of its final low value.
Propagation Delay Time, High to Low (tPHL)
Propagation delay time from high to low is defined as the time
taken from the 50% point on a high to low input signal until the
digital output signal reaches 50% of its final high value.
Comparator Offset
Comparator offset is the measure of the density of digital 1s
and 0s in the comparator output when the negative analog
terminal of the comparator input is held at a static potential,
and the analog input to the positive terminal of the comparators
is varied proportionally about the static negative terminal voltage.
Rev. A | Page 14 of 32
AD7264
THEORY OF OPERATION
CIRCUIT INFORMATION
The AD7264 is a fast, dual, simultaneous sampling, differential,
14-bit, serial ADCs. The AD7264 contains two on-chip differential programmable gain amplifiers, two track-and-hold
amplifiers, and two successive approximation analog-to-digital
converters with a serial interface with two separate data output
pins. The AD7264 also includes four on-chip comparators. The
part is housed in a 48-lead LFCSP or 48-lead LQFP package,
offering the user considerable space-saving advantages over
alternative solutions. The AD7264 requires a low voltage 5 V ±
5% AVCC to power the ADC core and supply the digital power, a
2.7 V to 5.25 V CA_CBVCC, CC_CDVCC supply for the comparators,
and a 2.7 V to 5.25 V VDRIVE supply for interface power.
The on-board PGA allows the user to select from 14 programmable gain stages: ×1, ×2, ×3, ×4, ×6, ×8, ×12, ×16, ×24, ×32,
×48, ×64, ×96, and ×128. The PGA accepts fully differential
analog signals. The gain can be selected either by setting the
logic state of the G0 to G3 pins or by programming the control
register.
The serial clock input accesses data from the part while also
providing the clock source for each successive approximation
ADC. The AD7264 has an on-chip 2.5 V reference that can be
disabled when an external reference is preferred. If the internal
reference is used elsewhere in a system, the output from VREFA
and VREFB must first be buffered. If the internal reference is the
preferred option, the user must tie the REFSEL pin to a logic
high voltage. Alternatively, if REFSEL is tied to GND, an
external reference can be supplied to both ADCs through the
VREFA and VREFB pins (see the Reference section).
The AD7264 also features a range of power-down options to
allow the user great flexibility with the independent circuit
components while allowing for power savings between conversions. The power-down feature is implemented via the control
register or the PD0 to PD2 pins, as described in the Control
Register section.
COMPARATORS
The AD7264 has four on-chip comparators. Comparator A and
Comparator B have ultralow power consumption, with static
power consumption typically less than 10 μW with a 3.3 V
supply. Comparator C and Comparator D feature very fast
propagation delays of 130 ns for a 200 mV differential overdrive.
These comparators have push-pull output stages that operate
from the VDRIVE supply. This feature allows operation with a
minimum amount of power consumption.
Each pair of comparators operates from its own independent
supply, CA_CBVCC or CC_CDVCC. The comparators are specified
for supply voltages from 2.7 V to 5.25 V. If desired, CA_CBVCC
and CC_CDVCC can be tied to the AVCC supply. The four comparators on the AD7264 are functional with CA_CBVCC, CC_CDVCC
greater than or equal to 1.8 V. However, no specifications are
guaranteed for comparator supplies less than 2.7 V. The wide
range of supply voltages ensures that the comparators can be
used in a variety of battery backup modes.
The four on-chip comparators on the AD7264 are ideally suited
for monitoring signals from pole sensors in motor control
systems. The comparators can be used to monitor signals from
Hall effect sensors or the inner tracks from an optical encoder.
One of the comparators can be used to count the index marker
or z marker, which is used on startup to place the motor in a
known position.
OPERATION
The AD7264 has two successive approximation ADCs, each
based around two capacitive DACs and two programmable gain
amplifiers.
The ADC itself comprises control logic, a SAR, and two capacitive
DACs. The control logic and the charge redistribution DACs are
used to add and subtract fixed amounts of charge from the sampling capacitor amplifiers to bring the comparator back into a
balanced condition. When the comparator is rebalanced, the
conversion is complete. The control logic generates the ADC
output code.
Each ADC is preceded by its own programmable gain stage.
The PGA features high analog input impedance, true differential
analog inputs that allow the output from any source or sensor to
be connected directly to the PGA inputs without any requirement
for additional external buffering. The variable gain settings ensure
that the device can be used for amplifying signals from a variety
of sources. The AD7264 offers the flexibility to choose the most
appropriate gain setting to utilize the wide dynamic range of
the device.
ANALOG INPUTS
Each ADC in the AD7264 has two high impedance differential
analog inputs. Figure 24 shows the equivalent circuit of the
analog input structure of the AD7264. It consists of a fully
differential input amplifier that buffers the analog input signal
and provides the gain selected by using the gain pins.
The two diodes provide ESD protection. Care must be taken
to ensure that the analog input signals never exceed the supply
rails by more than 300 mV. This causes these diodes to become
forward-biased and to start conducting current into the substrate. These diodes can conduct up to 10 mA without causing
irreversible damage to the part. The C1 capacitors in Figure 24
are typically 5 pF and can primarily be attributed to pin
capacitance.
Rev. A | Page 15 of 32
AD7264
VDD
AMP
C1
VOUT+
011...111
VDD
011...110
VOUT –
06732-024
C1
ADC CODE
AMP
VIN–
Figure 24. Analog Input Structure
The AD7264 can accept differential analog inputs from
⎛ VREF ⎞
⎛ VREF ⎞
VCM − ⎜
⎟ to VCM + ⎜
⎟.
⎝ 2 × Gain ⎠
⎝ 2 × Gain ⎠
100...000
0V
(VCM – (FSR/2)) + 1LSB
(VCM + (FSR/2)) – 1LSB
ANALOG INPUT
NOTES
1. FULL-SCALE RANGE (FSR) = VIN+ – VIN–.
Analog Input Range for VIN+ and VIN−
0.75 V to 3.25 V1
1.875 V to 3.125 V
2.083 V to 2.916 V
2.187 V to 2.813 V
2.292 V to 2.708 V
2.344 V to 2.656 V
2.396 V to 2.604 V
2.422 V to 2.578 V
2.448 V to 2.552 V
2.461 V to 2.539 V
2.474 V to 2.526 V
2.480 V to 2.520 V
2.487 V to 2.513 V
2.490 V to 2.510 V
For VCM = 2 V. If VCM = AVCC/2, the analog input range for VIN+ and VIN− is 1.6 V
to 3.4 V.
When a full-scale step input is applied to either differential
input on the AD7264 while the other analog input is held at a
constant voltage, 3 μs of settling time is typically required prior
to capturing a stable digital output code.
Transfer Function
The AD7264 output is twos complement; the ideal transfer
function is shown in Figure 25. The designed code transitions
occur at successive integer LSB values (that is, 1 LSB, 2 LSB, and
so on). The LSB size is dependent on the analog input range
selected.
The LSB size for the AD7264 is
111...111
100...001
Figure 25. Twos Complement Transfer Function
Table 5. Analog Input Range for Various PGA Gain Settings
1
000...000
100...010
Table 5 details the analog input range for the AD7264 for the
various PGA gain settings. VREF = 2.5 V and VCM = 2.5 V
(AVCC/2, with AVCC = 5 V).
PGA Gain Setting
1
2
3
4
6
8
12
16
24
32
48
64
96
128
000...001
06732-025
VIN+
⎛⎛
V
V
⎞⎞
⎞ ⎛
⎜ ⎜⎜ VCM + ⎛⎜ REF ⎞⎟ ⎟⎟ − ⎜⎜ VCM − ⎛⎜ REF ⎞⎟ ⎟⎟ ⎟
⎜
⎝ 2 × Gain ⎠ ⎠ ⎟
⎝ 2 × Gain ⎠ ⎠ ⎝
2×⎜ ⎝
⎟
16
,
384
⎜
⎟
⎜
⎟
⎝
⎠
VDRIVE
The AD7264 has a VDRIVE feature to control the voltage at which
the serial interface operates. VDRIVE allows the ADC and the
comparators to easily interface to both 3 V and 5 V processors.
For example, when the AD7264 is operated with AVCC = 5 V, the
VDRIVE pin can be powered from a 3 V supply, allowing a large
analog input range with low voltage digital processors.
REFERENCE
The AD7264 can operate with either the internal 2.5 V on-chip
reference or an externally applied reference. The logic state of
the REFSEL pin determines whether the internal reference is
used. The internal reference is selected for both ADCs when the
REFSEL pin is tied to logic high. If the REFSEL pin is tied to
AGND, an external reference can be supplied through the VREFA
and/or VREFB pins. On power-up, the REFSEL pin must be tied to
either a low or high logic state for the part to operate. Suitable
reference sources for the AD7264 include the AD780, AD1582,
ADR431, REF193, and ADR391.
The internal reference circuitry consists of a 2.5 V band gap reference and a reference buffer. When operating the AD7264 in
internal reference mode, the 2.5 V internal reference is available at
the VREFA and VREFB pins, which should be decoupled to AGND
using a 1 μF capacitor. It is recommended that the internal reference be buffered before applying it elsewhere in the system. The
internal reference is capable of sourcing up to 90 μA of current
when the converter is static. If internal reference operation is
required for the ADC conversion, the REFSEL pin must be tied
to logic high on power-up. The reference buffer requires 240 μs
to power up and charge the 1 μF decoupling capacitor during
the power-up time.
Rev. A | Page 16 of 32
AD7264
pin driven mode. Both circuit configurations illustrate the use
of the internal 2.5 V reference.
TYPICAL CONNECTION DIAGRAMS
Figure 26 and Figure 27 are typical connection diagrams for the
AD7264. In these configurations, the AGND pin is connected
to the analog ground plane of the system, and the DGND pin is
connected to the digital ground plane of the system. The analog
inputs on the AD7264 are true differential and have an input
impedance in excess of 1 GΩ; thus, no driving op amps are
required. The AD7264 can operate with either an internal or an
external reference. In Figure 26, the AD7264 is configured to
operate in control register mode; thus, G0 to G3, PD1, and PD2
can be connected to ground (low logic state). Figure 27 has the
gain pins configured for a gain of 2 setup; thus, the device is in
ANALOG
SUPPLY
The CA_CBVCC and CC_CDVCC pins can be connected to either a
3 V or 5 V supply voltage. The AVCC pin must be connected to
a 5 V supply. All supplies should be decoupled with a 100 nF
capacitor at the device pin, and some supply sources may
require a 10 μF capacitor where the source is supplied to the
circuit board. The VDRIVE pin is connected to the supply voltage
of the microprocessor. The voltage applied to the VDRIVE input
controls the voltage of the serial interface. VDRIVE can be set to
3 V or 5 V.
+5V
100nF
10µF1
100nF
100nF
100nF
100nF
10µF1
COMPARATOR
SUPPLY 3V TO 5V2
100nF
100nF
3
1.875V
AVCC
CA–CBVCC
AVCC
CC–CDVCC
AVCC
AVCC
AVCC
AVCC
DGND
AGND
AGND
AGND
AGND
7 11 20 41 12 1 33
VDRIVE
VA–
GAIN 2
3.125V
4
2.500V
1.875V
8 19 42 28 2
G0
G1
G2
G3
VA+
THIS REFERENCE SIGNAL
MUST BE BUFFERED
BEFORE IT CAN BE
USED ELSEWHERE IN
THE CIRCUIT
VREF A
SCLK
AD7264
CS
DOUTA
VREF B
DOUTB
1µF
REFSEL
CAL
3.125V
9
2.500V
PD0/DIN
GAIN 2
PD1
13 14 15 16
45 46 47 48
FAST PROPAGATION DELAY
COMPARATOR INPUTS
10µF1
3V OR 5V
SUPPLY
34
35
MICROPROCESSOR/
MICROCONTROLLER
32
31
24
VDRIVE
36
23
22
21
COUTA
COUTB
COUTC
COUTD
CA+
CB+
CA–
PD2
CB–
GAIN 2
VB–
CD–
2.500V
CD+
10
CC–
3.125V
1.875V
VB+
CC+
1.875V
100nF
SERIAL
INTERFACE
1µF
18
VDRIVE
40
39
38
37
GAIN 2
43
VB– AND VB+
CONNECT
DIRECTLY
TO SENSOR
OUTPUTS
27
25 26 29 30
LOW POWER
COMPARATOR INPUTS
1THESE CAPACITORS ARE PLACED AT THE SUPPLY SOURCE AND MAY NOT BE REQUIRED
2THIS SUPPLY CAN BE CONNECTED TO THE ANALOG 5V SUPPLY IF REQUIRED.
IN ALL SYSTEMS.
Figure 26. Typical Connection Diagram for the AD7264 in Control Register Mode (All Gain Pins Tied to Ground) Configured for a PGA Gain of 2
Rev. A | Page 17 of 32
06732-026
VA– AND VA+
CONNECT
DIRECTLY
TO SENSOR
OUTPUTS
CA–CB–GND
CC–CD–GND
3.125V
2.500V
6
AGND
100nF
17 44 5
AD7264
ANALOG
SUPPLY
+5V
100nF
10µF1
100nF
100nF
100nF
100nF
10µF1
COMPARATOR
SUPPLY 3V TO 5V2
100nF
100nF
VA– AND VA+
CONNECT
DIRECTLY
TO SENSOR
OUTPUTS
3
2.500V
1.875V
AVCC
CA–CBVCC
AVCC
CC–CDVCC
AVCC
AVCC
AVCC
7 11 20 41 12 1 33
AVCC
DGND
AGND
AGND
AGND
AGND
8 19 42 28 2
VDRIVE
VA–
GAIN 2
3.125V
4
2.500V
1.875V
6
G0
G1
G2
G3
VA+
THIS REFERENCE SIGNAL
MUST BE BUFFERED
BEFORE IT CAN BE
USED ELSEWHERE IN
THE CIRCUIT
VREF A
SCLK
1µF
18
AD7264
CS
DOUTA
VREF B
DOUTB
REFSEL
CAL
3.125V
9
2.500V
PD0/DIN
PD1
VB–
13 14 15 16
45 46 47 48
FAST PROPAGATION DELAY
COMPARATOR INPUTS
100nF
10µF1
3V OR 5V
SUPPLY
VDRIVE
GAIN 2
SETUP
34
35
MICROPROCESSOR/
MICROCONTROLLER
32
31
24
VDRIVE
36
23
VDRIVE
22
21
VDRIVE
BOTH
COMPARATORS
AND ADCs
POWERED ON
COUTA
COUTB
COUTC
COUTD
CA+
CA–
CB+
CB–
CD–
CD+
CC+
GAIN 2
PD2
CC–
10
2.500V
1.875V
VB+
GAIN 2
3.125V
VDRIVE
SERIAL
INTERFACE
1µF
1.875V
40
39
38
37
GAIN 2
43
VB– AND VB+
CONNECT
DIRECTLY
TO SENSOR
OUTPUTS
27
25 26 29 30
LOW POWER
COMPARATOR INPUTS
1THESE CAPACITORS ARE PLACED AT THE SUPPLY SOURCE AND MAY NOT BE REQUIRED
2THIS SUPPLY CAN BE CONNECTED TO THE ANALOG 5V SUPPLY IF REQUIRED.
IN ALL SYSTEMS.
06732-027
3.125V
5
CA–CB–GND
CC–CD–GND
17 44
AGND
100nF
Figure 27. Typical Connection Diagram for the AD7264 in Pin Driven Mode with Gain of 2 and Both ADCs and Comparators Fully Powered On
Comparator Application Details
The comparators on the AD7264 have been designed with no
internal hysteresis, allowing users the flexibility to add external
hysteretic if required for systems operating in noisy environments.
If the comparators on the AD7264 are used with external hysteresis, some external resistors and capacitors are required, as
shown in Figure 28. The value of RF and RS, the external resistors,
can be determined using the following equation, depending on
the amount of hysteresis required in the application:
VHYS =
RS
× C X _C XVCC
RS + R F
The amount of hysteresis chosen must be sufficient to eliminate
the effects of analog noise at the comparator inputs, which may
affect the stability of the comparator outputs. The level of
hysteresis required in any system depends on the noise in the
system; thus, the value of RF and RS needs to be carefully selected
to eliminate any noise effects. To increase the level of hysteresis in
the system, increase the value of RS or RF. For example, RF = 10 MΩ,
RS = 1 kΩ gives 330 μV of hysteresis with a Cx_CxVCC of 3.3 V; if
hysteresis is increased to 1 mV, RS = 3.1 kΩ. In certain applications,
a load capacitor (100 pF) may be required on the comparator
outputs to suppress high frequency transient glitches.
where CX_CXVCC = CA_CBVCC or CC_CDVCC.
Rev. A | Page 18 of 32
AD7264
RF
Cx–
RS
Cx+
variety of sensors, which results in reduced design cycles and
costs.
COUTx
06732-028
The two simultaneous sampling ADCs are used to sample the
sine and cosine outputs from the sensor. No external buffering
is required between the sensor/transducer and the analog inputs
of the AD7264. The on-chip comparators can be used to
monitor the pole sensors, which can be Hall effect sensors or
the inner tracks from an optical encoder.
Figure 28. Recommended Comparator Connection Diagram
APPLICATION DETAILS
The AD7264 has been specifically designed to meet the requirements of any motor control shaft position feedback loop. The
device can interface directly to multiple sensor types, including
optical encoders, magnetoresistive sensors, and Hall effect sensors.
Its flexible analog inputs, which incorporate programmable
gain, ensure that identical board design can be utilized for a
Figure 29 shows how the AD7264 can be used in a typical
application. An optical encoder is shown in Figure 29, but other
sensor types could as easily be used. Figure 29 indicates a
typical application configuration only; there are several other
configurations that render equally effective results.
COMP
COMP
VREF A
AVCC
REF
14-BIT
SUCCESSIVE
APPROXIMATION
ADC
VA+
A
VA–
AD7264
BUF
PGA
T/H
OUTPUT
DRIVERS
SCLK
CAL
CS
REFSEL
G0
G1
G2
G3
VDRIVE
CONTROL
LOGIC
B
VB+
VB–
PGA
14-BIT
SUCCESSIVE
APPROXIMATION
ADC
T/H
DOUTA
OUTPUT
DRIVERS
BUF
DOUTB
PD0/DIN
PD1
PD2
VREF B
H.E.
CA_CBVCC
Z
CA+
CA–
U
CB+
COMP
CB–
CA_CB_GND
V
W
COMP
CC_CDVCC
CC+
CC–
CD+
CD–
CC_CD_GND
OUTPUT
DRIVERS
COMP
COUTA
OUTPUT
DRIVERS
OUTPUT
DRIVERS
COMP
AGND
COUTC
OUTPUT
DRIVERS
DGND
Figure 29. Typical System Connection Diagram with Optical Encoder
Rev. A | Page 19 of 32
COUTB
COUTD
06732-029
SENSOR
RS
AD7264
MODES OF OPERATION
The AD7264 allows the user to choose between two modes of
operation: pin driven mode and control register mode.
PIN DRIVEN MODE
Pin driven mode allows the user to select the gain of the PGA,
the power-down mode, internal or external reference, and to
initiate a calibration of the offset for both ADC A and ADC B.
These functions are implemented by setting the logic levels on
the gain pins (G3 to G0), the power-down pins (PD2 to PD0),
the REFSEL pin, and the CAL pin, respectively.
The logic state of the G3 to G0 pins determines which mode of
operation is selected. Pin driven mode is selected if at least one
of the gain pins is set to a logic high state. Alternatively, if all
four gain pins are connected to a logic low, the control register
mode of operation is selected.
GAIN SELECTION
The on-board PGA allows the user to select from 14 programmable gain stages: ×1, ×2, ×3, ×4, ×6, ×8, ×12, ×16, ×24, ×32,
×48, ×64, ×96, and ×128. The PGA accepts fully differential
analog signals and provides three key functions, which include
selecting gains for small amplitude input signals, driving the
ADCs switched capacitive load, and buffering the source from
the switching effects of the SAR ADCs. The AD7264 offers the
user great flexibility in user interface, offering gain selection via
the control register or by driving the gain pins to the desired
logic state. The AD7264 has four gain pins, G3, G2, G1 and G0,
as shown in Figure 3 and Figure 4. Each gain setting is selected
by setting up the appropriate logic state on each of the four gain
pins, as outlined in Table 6. If all four gain pins are connected to
a logic low level, the part is put in control register mode, and
the gain settings are selected via the control register.
Table 6. Gain Selection
G3
0
G2
0
G1
0
G0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Gain
Software control
via control register
1
2
3
4
6
8
12
16
24
32
48
64
96
128
POWER-DOWN MODES
The AD7264 offers the user several of power-down options to
enable individual device components to be powered down
independently. These options can be chosen to optimize power
dissipation for different application requirements. The powerdown modes can be selected by either programming the device
via the control register or by driving the PD pins to the
appropriate logic levels. By setting the PD pins to a logic low
level when in pin driven mode, all four comparators and both
ADCs can be powered down. The PD2 and PD0 pins must be
set to logic high and the PD1 pin set to logic low level to power
up all circuitry on the AD7264. The PD pin configurations for
the various power-down options are outlined in Table 7.
Table 7. Power-Down Modes
PD2
PD1
PD0
Comparator A,
Comparator B
Comparator C,
Comparator D
ADC A,
ADC B
0
0
0
0
1
1
11
0
0
1
1
0
0
11
0
1
0
1
0
1
11
Off
Off
Off
On
On
On
Off
Off
Off
On
Off
On
On
Off
Off
On
Off
Off
Off
On
Off
1
PD2 = PD1 = PD0 = 1; resets the AD7264 when in pin driven mode only.
The AVCC and VDRIVE supplies must continue to be supplied to
the AD7264 when the comparators are powered up but the
ADCs are powered down. External diodes can be used from the
CA_CBVCC and/or CC_CDVCC to both the AVCC and the VDRIVE
supplies to ensure that they retain a supply at all times.
The AD7264 can be reset in pin driven mode only by setting the
PD pins to a logic high state. When the device is reset, all the
registers are cleared and the four comparators and the two
ADCs are left powered down.
In the normal mode of operation with the ADCs and comparators powered on, the CA_CBVCC/CC_CDVCC supplies and the
AVCC supply can be at different voltage levels, as indicated in
Table 1. When the comparators on the AD7264 are in powerdown mode and the CA_CBVCC/CC_CDVCC supplies are at a
potential 0.3 V greater than or less than the AVCC supply, the
supplies consume more current than would be the case if both
sets of supplies were at the same potential. This configuration
does not damage the AD7264 but results in additional current
flowing in any or all of the AD7264 supply pins. This is due to
ESD protection diodes within the device. In applications where
power consumption in power-down mode is critical, it is
recommended that the CA_CBVCC/CC_CDVCC supply and the
AVCC supply be held at the same potential.
Rev. A | Page 20 of 32
AD7264
Power-Up Conditions
to a low logic state. These functions can also be implemented by
setting the logic levels on the gain pins, power-down pins, and
CAL pin, respectively. The control register can also be used to
read the offset and gain registers.
On power-up, the status of the gain pins determines which
mode of operation is selected, as outlined in the Gain Selection
section. All registers are set to 0.
Data is loaded from the PD0/DIN pin of the AD7264 on the
falling edge of SCLK when CS is in a logic low state. The control
register is selected by first writing the appropriate four WR bits,
as outlined in Table 10. The 12 data bits must then be clocked
into the control register of the device. Thus, on the 16th falling
SCLK edge, the LSB is clocked into the device. One more SCLK
cycle is then required to write to the internal device registers. In
total, 17 SCLK cycles are required to successfully write to the
AD7264. The data is transferred on the PD0/DIN line while the
conversion result is being processed. The data transferred on
the DIN line corresponds to the AD7264 configuration for the
next conversion.
If the AD7264 is powered up in pin driven mode, the gain pins
and the PD pins should be configured to the appropriate logic
states and a calibration initiated if required.
Alternatively, if the AD7264 is powered up in control register
mode, the comparators and ADCs are powered down and the
default gain is 1. Thus, powering up in control register mode
requires a write to the device to power up the comparators and
the ADCs.
It takes the AD7264 15 μs to power up when using an external
reference. When the internal reference is used, 240 μs are required
to power up the AD7264 with a 1 μF decoupling capacitor.
CONTROL REGISTER
Only the information provided on the 12 falling clock edges after
the CS falling edge and the initial four write address bits is loaded
to the control register. The PD0/DIN pin should have a logic low
state for the four bits RD3 to RD0 when using the control register
to select the power-down modes and gain setting, or when initializing a calibration. The RD bits should also be set to a logic low
level to access the ADC results from both DOUTA and DOUTB.
The control register on the AD7264 is a 12-bit read and write
register that is used to control the device when not in pin driven
mode. The PD0/DIN pin serves as the serial DIN pin for the
AD7264 when the gain pins are set to 0 (that is, the part is not in
pin driven mode). The control register can be used to select the
gain of the PGAs, the power-down modes, and the calibration
of the offset for both ADC A and ADC B. When in the control
register mode of operation, PD1 and PD2 should be connected
The power-up status of all bits is 0, and the MSB denotes the first
bit in the data stream. The bit functions are outlined in Table 9.
Table 8. Control Register Bits
MSB
Bit 11
RD3
Bit 10
RD2
Bit 9
RD1
Bit 8
RD0
Bit 7
CAL
Bit 6
PD2
Bit 5
PD1
Bit 4
PD0
Bit 3
G3
Bit 2
G2
LSB
Bit 0
G0
Bit 1
G1
Table 9. Control Register Bit Function Descriptions
Bits
11 to 8
7
Mnemonic
RD3 to RD0
CAL
6 to 4
3 to 0
PD2 to PD0
G3 to G0
Comment
Register address bits. These bits select which register the subsequent read is from. See Table 11.
Setting this bit high initiates an internal offset calibration. When the calibration is completed, this pin can be reset low,
and the internal offset that is stored in the on-chip offset registers is automatically removed from the ADCs results.
Power-down bits. These bits select which power-down mode is programmed. See Table 7.
Gain selection bits. These bits select which gain setting is used on the front-end PGA. See Table 6.
Table 10. Write Address Bits
WR3
0
WR2
0
WR1
0
WR0
1
Read Register Addressed
Control register
CS
t8
t2
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
32
33
DOUTA
PD0/DIN
t13
WR3
WR2
WR1
WR0
RD3
RD2
DB13
t14
RD1
RD0
CAL
PD2
PD1
PD0
G3
G2
G1
G0
Figure 30. Timing Diagram for a Write Operation to the Control Register
Rev. A | Page 21 of 32
DB12
THREE-STATE
DB0
THREESTATE
06732-030
tQUIET
THREE-STATE
AD7264
ON-CHIP REGISTERS
Table 11. Read and Write Register Addresses
The AD7264 contains a control register, two offset registers for
storing the offsets for each ADC, and two external gain registers
for storing the gain error. The control, offset, and gain registers
are read and write registers. On power-up, all registers in the
AD7264 are set to 0 by default.
RD3
0
0
0
0
0
0
Writing to a Register
Data is loaded from the PD0/DIN pin of the AD7264 on the
falling edge of SCLK when CS is in a logic low state. Four
address bits and 12 data bits must be clocked into the device.
Thus, on the 16th falling SCLK edge, the LSB is clocked into the
AD7264. One more SCLK cycle is then required to write to the
internal device registers. In total, 17 SCLK cycles are required to
successfully write to the AD7264. The control and offset
registers are 12-bits registers, and the gain registers are 7-bit
registers.
RD2
0
0
0
0
1
1
RD1
0
0
1
1
0
0
RD0
0
1
0
1
0
1
Comment
ADC result (default)
Control register
Offset ADC A internal
Offset ADC B internal
Gain ADC A external
Gain ADC B external
Reading from a Register
The internal offset of the device, which has been measured by
the AD7264 and stored in the on-chip registers during the
calibration, can be read back by the user. The contents of the
external gain registers can also be read. To read the contents of
any register, the user must first write to the control register by
writing 0001 to the WR3 to WR0 bits via the PD0/DIN pin (see
Table 10). The next four bits in the control register are the RD
bits, which are used to select the desired register from which to
read. The appropriate 4-bit addresses for each of the offset and
gain registers are listed in Table 11. The remaining eight SCLK
cycle bits are used to set the remaining bits in the control
register to the desired state for the next ADC conversion.
When writing to a register, the user must first write the address
bits corresponding to the selected register. Table 11 shows the
decoding of the address bits. The four RD bits are written MSB
first, that is, RD3 followed by RD2, RD1, and RD0. The AD7264
decodes these bits to determine which register is being addressed.
The subsequent 12 bits of data are written to the addressed register.
The 19th SCLK falling edge clocks out the first data bit of the
digital code corresponding to the value stored in the selected
internal device register on the DOUTA pin. DOUTB outputs the
conversion result from ADC B. When the selected register has
been read, the control register must be reset to output the ADC
results for future conversions. This is achieved by writing 0001
to the WR3 to WR0 bits, followed by 0000 to the RD bits. The
remaining eight bits in the control register should then be set to
the required configuration for the next ADC conversion.
When writing to the external gain registers, the seven bits of
data immediately after the four address bits are written to the
register. However, 17 SCLK cycles are still required, and the
PD0/DIN pin of the AD7264 should be tied low for the five
additional clock cycles.
CS
t8
t2
SCLK
2
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
t13
RD3
RD2
RD1
19
20
32
33
tQUIET
THREE-STATE
DOUTA
PD0/DIN
3
RD0
MSB
DB13A
t14
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB12A
DB0A
06732-031
1
THREESTATE
THREE-STATE
DB0
Figure 31. Timing Diagram for Writing to a Register
CS
t8
t2
1
SCLK
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
32
33
PD0/DIN
t13
0
0
0
1
RD3
RD2
DB13A
t14
RD1
RD0
0
0
0
0
0
0
0
0
Figure 32. Timing Diagram for a Read Operation with PD0/DIN as an Input
Rev. A | Page 22 of 32
DB12A
THREE-STATE
DB0A
THREESTATE
06732-032
tQUIET
THREE-STATE
DOUTA
AD7264
SERIAL INTERFACE
access time (t4) is 23 ns, which enables reading on the subsequent falling SCLK edge after the data has been clocked out, as
described previously. However, if a VDRIVE voltage of 3 V is used
for the AD7264 and the setup time of the microcontroller or
DSP is too large to enable reading on the falling SCLK edge, it
may be necessary to read on the SCLK rising edge. In this case,
the MSB of the conversion result is clocked out on the 19th SCLK
falling edge to be read on the 20th SCLK rising edge, as shown in
Figure 35. This is possible because the hold time (t5) is longer for
lower VDRIVE voltages. If the data access time is too long to accommodate the setup time of the chosen processor, an alternative to
reading on the rising SCLK edge is to use a slower SCLK frequency.
Figure 33 and Figure 34 show the detailed timing diagrams for
the serial interface on the AD7264. The serial clock provides the
conversion clock and controls the transfer of information from
the AD7264 after the conversion. The AD7264 has two output
pins corresponding to each ADC. Data can be read from the
AD7264 using both DOUTA and DOUTB. Alternatively, a single
output pin of the user’s choice can be used. The SCLK input
signal provides the clock source for the serial interface.
The falling edge of CS puts the track-and-hold into hold mode,
at which point the analog input is sampled. The conversion is
also initiated at this point and requires a minimum of 19 SCLK
cycles to complete. The DOUTx lines remain in three-state while
the conversion is taking place. On the 19th SCLK falling edge, the
AD7264 returns to track mode and the DOUTA and DOUTB lines
are enabled. The data stream consists of 14 bits of data, MSB first.
On the rising edge of CS, DOUTA and DOUTB go back into threestate. If CS is not brought high after 33 SCLK cycles but is instead
held low for an additional 14 SCLK cycles, the data from ADC B
is output on DOUTA after the ADC A result. Likewise, the data
from ADC A is output on DOUTB after the ADC B result. This is
illustrated in Figure 34, which shows the DOUTA example. In this
case, the DOUT line in use goes back into three-state on the 47th
SCLK falling edge or the rising edge of CS, whichever occurs first.
The MSB of the conversion result is clocked out on the 19th
SCLK falling edge to be read by the microcontroller or DSP on
the subsequent SCLK falling edge (the 20th falling edge). The
remaining data is then clocked out by subsequent SCLK falling
edges. Thus, the 20th falling clock edge on the serial clock has
the MSB provided and also clocks out the second data bit. The
remainder of the 14-bit result follows, with the final bit in the
data transfer being valid for reading on the 33rd falling edge.
The LSB is provided on the 32nd falling clock edge.
If the falling edge of SCLK coincides with the falling edge of CS,
the falling edge of SCLK is not acknowledged by the AD7264,
and the next falling edge of SCLK is the first one registered after
the falling edge of CS.
The AD7264-5, with its 20 MHz SCLK frequency, easily
facilitates reading on the SCLK falling edge. When using a
VDRIVE voltage of 5 V with the AD7264, the maximum specified
FIRST DATA BIT CLOCKED
OUT ON THIS EDGE
FIRST DATA BIT READ
ON THIS EDGE
CS
t8
t2
1
t6
2
3
5
4
19
18
20
t7
t3
DOUTA
THREE-STATE
DOUTB
THREE-STATE
21
31
32
33
t9
t5
t4
DB13 A
DB12 A DB11A
DB1A
DB0A
DB13 B
DB12 B DB11B
DB1B
DB0B
tQUIET
THREESTATE
THREESTATE
06732-033
SCLK
Figure 33. Normal Mode Operation
CS
SCLK
1
2
18
19
20
21
31
32
33
45
46
47
THREE-STATE
DB13 A
DB12 A
DB1 A
DB0 A
DB13 B
DB12 B
Figure 34. Reading Data from Both ADCs on One DOUT Line with 47 SCLK Cycles
Rev. A | Page 23 of 32
DB1 B
DB0B
THREESTATE
06732-034
t10
DOUTA
AD7264
FIRST DATA BIT CLOCKED
OUT ON THIS EDGE
FIRST DATA BIT READ
ON THIS EDGE
CS
t8
t2
1
2
3
4
5
18
20
19
21
22
t4
DOUTA
THREE-STATE
DOUTB
THREE-STATE
31
32
33
t5
DB13 A
DB12 A DB11A
DB1 A
DB0A
DB13 B
DB12 B DB11B
DB1 B
DB0B
Figure 35. Serial Interface Timing Diagram When Reading Data on the Rising SCLK Edge with VDRIVE = 3 V
Rev. A | Page 24 of 32
THREESTATE
THREESTATE
06732-039
SCLK
AD7264
CALIBRATION
The AD7264 registers store the offset value, which can easily be
accessed by the user (see the Reading from a Register section).
When the device is calibrating, the differential analog inputs
for each respective ADC are shorted together internally and a
conversion is performed. A digital code representing the offset is
stored internally in the offset registers, and subsequent conversion results have this measured offset removed.
INTERNAL OFFSET CALIBRATION
The AD7264 allows the user to calibrate the offset of the device
using the CAL pin. This is achieved by setting the CAL pin to a
high logic level, which initiates a calibration on the next CS
falling edge. The calibration requires one full conversion cycle,
which contains a CS falling edge followed by 19 SCLK cycles.
The CAL pin can remain high for more than one conversion, if
desired, and the AD7264 continues to calibrate.
When the AD7264 is calibrated, the calibration results stored in
the internal device registers are relevant only for the particular
PGA gain selected at the time of calibration. If the PGA gain is
changed, the AD7264 must be recalibrated. If the device is not
recalibrated when the PGA gain is changed, the offset for the
previous gain setting continues to be removed from the digital
output code, which may lead to inaccuracies.
The CAL pin should be driven high only when the CS pin is
high or after 19 SCLK cycles have elapsed when CS is low, that
is, between conversions. The CAL pin must be driven high t12
before CS goes low. If the CS pin goes low before t12 elapses, the
calibration result will be inaccurate for the current conversion;
if the CAL pin remains high, the subsequent calibration conversion is correct. If the CAL pin is set to a logic high state during a
conversion, that conversion result is corrupted.
The offset range that can be calibrated for is ±500 LSB at a gain
of 1. The maximum offset voltage that can be calibrated for is
reduced as the gain of the PGA is increased.
If the CAL pin has been held high for a minimum of one
conversion and when t12 and t11 have been adhered to, the
calibration is complete after the 19th SCLK cycle and the CAL
pin can be driven to a logic low state. The next CS falling edge
after the CAL pin has been driven to a low logic state initiates
a conversion of the differential analog input signal for both
ADC A and ADC B.
Table 12 details the maximum offset voltage that can be
removed by the AD7264 without compromising the available
digital output code range. The least significant bit size is
AVCC/2Bits, which is 5/16,384 or 305 μV for the AD7264. The
maximum removable offset voltage is given by
± 500 LSB ×
Alternatively, the control register can be used to initiate an
offset calibration. This is done by setting the CAL bit in the
control register to 1. The calibration is then initiated on the next
CS falling edge, but the current conversion is corrupted. The
ADCs on the AD7264 must remain fully powered up to
complete the internal calibration.
305 μV
Gain
Table 12. Offset Voltage Range
Gain
1
2
3
32
Maximum Removable Offset Voltage
±152.5 mV
±76.25 mV
±50.83 mV
±4.765 mV
t11
t12
CAL
t8
t6
t2
SCLK
1
2
3
19
20
21
32
33
1
2
t7
Figure 36. Calibration Timing Diagram
Rev. A | Page 25 of 32
3
19
20
21
06732-035
CS
AD7264
ADJUSTING THE OFFSET CALIBRATION REGISTER
SYSTEM GAIN CALIBRATION
The internal offset calibration register can be adjusted manually
to compensate for any signal path offset from the sensors to the
ADC. No internal calibration is required, and the CAL pin can
remain at a low logic state. By changing the contents of the
offset register, different amounts of offset on the analog input
signal can be compensated for. Use the following steps to
determine the digital code to be written to the offset register:
The AD7264 also allows the user to write to an external gain
register, thus enabling the removal of any overall system gain
error. Both ADC A and ADC B have independent external gain
registers, allowing the user to calibrate independently the gain
on both ADC A and ADC B signal paths. The gain calibration
feature can be used to implement accurate gain matching
between ADC A and ADC B.
Configure the sensor to its offset state.
Perform a number of conversions using the AD7264.
Take the mean digital output code from both DOUTA and
DOUTB. This is a 14-bit result but the offset register is only
12 bits; thus, the 14-bit result needs to be converted to a
12-bit result that can be stored in the offset register. This is
achieved by keeping the sign bit and removing the second
and third MSBs.
The resultant digital code can then be written to the offset
registers to calibrate the AD7264.
The system calibration function is used by setting the sensors to
which the AD7264 is connected to a 0 gain state. The AD7264
converts this analog input to a digital output code, which
corresponds to the system gain and is available on the DOUT pins,
This digital output code can then be stored in the appropriate
external register. For details on how to write to a register, see the
Writing to a Register section and Table 11.
1.
2.
3.
4.
The gain calibration register contains seven bits of data. By
changing the contents of the gain register, different amounts of
gain on the analog input signal can be compensated for. The
MSB is a sign bit, while the remaining six bits store the multiplication factor, which is used to adjust the analog input range. The
gain register value is effectively multiplied by the analog input
to scale the conversion result over the full range. Increasing the
gain register multiplication factor compensates for a larger
analog input range, and decreasing the gain register multiplier
compensates for a smaller analog input range. Each bit in the
gain calibration register has a resolution of 2.4 × 10−4 V (1/4096).
A maximum of 1.538% of the analog range can be calibrated for.
The multiplier factor stored in the gain register can be decoded
as outlined in Table 13.
Example:
Mean digital code from DOUTA = 8100 (01 1111 1010 0100)
Code written to offset register = 0111 1010 0100
If a +10 mV offset is present in the analog input signal and the
gain of the PGA is 2, the code that needs to be written to the
offset register to compensate for the offset is
+10 mV
= 65.57 = 0000 0100 0001
(305 μV/ 2)
If a −10 mV offset is present in the analog input signal and the
gain of the PGA is 2, the code that needs to be written to the
offset register to compensate for the offset is
The gain registers can be cleared by writing all 0s to each register,
as described in the Writing to a Register section. For accurate
gain calibration, both the positive and negative full-scale digital
output codes should be measured prior to determining the
multiplication factor that is written to the gain register.
−10 mV
= −65.57 = 1000 0100 0001
(305 μV/ 2)
Table 13. Decoding of Multiplication Factors for Gain Calibration
Analog Input (V)
VIN max
Digital Gain
Error (LSB)
0 LSB
Gain Register
Code
(Sign Bit + 6 Bits)
0 000000
Multiplier
Equation
(1 ± x/4096)
1 − 0/4096
Multiplier
Value
1
VIN max − 244 μV
−2 LSB
0 000001
1 − 1/4096
0.999755859
VIN max − (63 × 244 μV)
−126 LSB
0 111111
1 − 63/4096
0.98461914
VIN max
0 LSB
1 000000
1 + 0/4096
1
VIN max + 244 μV
+2 LSB
1 000001
1 + 1/4096
1.000244141
VIN max + (63 × 244 μV)
+126 LSB
1 111111
1 + 63/4096
1.015380859
Rev. A | Page 26 of 32
Comments
Sign bit = 0; negative sign in multiplier
equation
Sign bit = 0; negative sign in multiplier
equation
Sign bit = 0; negative sign in multiplier
equation
Sign bit = 1; plus sign in multiplier
equation
Sign bit = 1; plus sign in multiplier
equation
Sign bit = 1; plus sign in multiplier
equation
AD7264
APPLICATION HINTS
GROUNDING AND LAYOUT
The analog and digital supplies to the AD7264 are independent
and separately pinned out to minimize coupling between the
analog and digital sections of the device. The printed circuit
board (PCB) that houses the AD7264 should be designed so
that the analog and digital sections are separated and confined
to certain areas of the board. This design facilitates the use of
ground planes that can be easily separated.
To provide optimum shielding for ground planes, a minimum
etch technique is generally best. All five AGND pins of the
AD7264 should be sunk in the AGND plane. Digital and analog
ground planes should be joined in only one place. If the AD7264
is in a system where multiple devices require an AGND to
DGND connection, the connection should still be made at only
one point, a star ground point, that should be established as
close as possible to the ground pins on the AD7264.
Avoid running digital lines under the device because this
couples noise onto the die. However, the analog ground plane
should be allowed to run under the AD7264 to avoid noise
coupling. The power supply lines to the AD7264 should use as
large a trace as possible to provide low impedance paths and
reduce the effects of glitches on the power supply line.
To avoid radiating noise to other sections of the board, fast
switching signals, such as clocks, should be shielded with digital
ground, and clock signals should never run near the analog
inputs. Avoid crossover of digital and analog signals. To reduce
the effects of feedthrough within the board, traces on opposite
sides of the board should run at right angles to each other. A
microstrip technique is the best method but is not always possible
with a double-sided board. In this technique, the component
side of the board is dedicated to ground planes, while signals are
placed on the solder side.
Good decoupling is also important. All analog supplies should
be decoupled with 10 μF tantalum capacitors in parallel with
100 nF capacitors to GND. To achieve the best results from
these decoupling components, they must be placed as close as
possible to the device, ideally right up against the device. The
0.1 μF capacitors should have low effective series resistance
(ESR) and low effective series inductance (ESI), such as the
common ceramic types or surface-mount types. These low ESR
and low ESI capacitors provide a low impedance path to ground
at high frequencies to handle transient currents due to internal
logic switching.
PCB DESIGN GUIDELINES FOR LFCSP
The lands on the chip scale package (CP-48-1) are rectangular.
The PCB pad for these should be 0.1 mm longer than the
package land length, and 0.05 mm wider than the package land
width, leaving a portion of the pad exposed. To ensure that the
solder joint size is maximized, the land should be centered on
the pad.
The bottom of the chip scale package has a thermal pad. The
thermal pad on the PCB should be at least as large as the
exposed pad. On the PCB, there should be a clearance of at least
0.25 mm between the thermal pad and the inner edges of the
pad pattern to ensure that shorting is avoided.
To improve thermal performance of the package, use thermal
vias on the PCB, incorporating them in the thermal pad at 1.2 mm
pitch grid. The via diameter should be between 0.3 mm and
0.33 mm, and the via barrel should be plated with 1 oz copper
to plug the via. The user should connect the PCB thermal pad
to AGND.
Rev. A | Page 27 of 32
AD7264
OUTLINE DIMENSIONS
7.00
BSC SQ
0.60 MAX
37
36
PIN 1
INDICATOR
48
25
24
12
13
0.25 MIN
5.50
REF
THE EXPOSED METAL PADDLE ON THE
BOTTOM OF THE LFCSP PACKAGE
MUST BE SOLDERED TO PCB GROUND
FOR PROPER HEAT DISSIPATION AND
ALSO FOR NOISE AND MECHANICAL
STRENGTH BENEFITS.
0.05 MAX
0.02 NOM
0.50 BSC
5.25
5.10 SQ
4.95
(BOTTOM VIEW)
0.80 MAX
0.65 TYP
SEATING
PLANE
1
EXPOSED
PAD
6.75
BSC SQ
0.50
0.40
0.30
12° MAX
PIN 1
INDICATOR
0.20 REF
COPLANARITY
0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
061208-A
TOP
VIEW
Figure 37. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
7 mm × 7 mm Body, Very Thin Quad
(CP-48-1)
Dimensions shown in millimeters
0.75
0.60
0.45
9.20
9.00 SQ
8.80
1.60
MAX
37
48
36
1
PIN 1
0.15
0.05
7.20
7.00 SQ
6.80
TOP VIEW
1.45
1.40
1.35
SEATING
PLANE
VIEW A
0.20
0.09
7°
3.5°
0°
0.08
COPLANARITY
(PINS DOWN)
25
12
13
VIEW A
0.50
BSC
LEAD PITCH
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
Figure 38. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
Rev. A | Page 28 of 32
24
0.27
0.22
0.17
051706-A
1.00
0.85
0.80
0.30
0.23
0.18
0.60 MAX
AD7264
ORDERING GUIDE
Model
AD7264BCPZ 1
AD7264BCPZ-RL71
AD7264BCPZ-51
AD7264BCPZ-5-RL71
AD7264BSTZ1
AD7264BSTZ-RL71
AD7264BSTZ-51
AD7264BSTZ-5-RL71
EVAL-AD7264EDZ1
EVAL-CED1Z1
1
Temperature Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Package Description
48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
48-Lead Low Profile Quad Flat Package [LQFP]
48-Lead Low Profile Quad Flat Package [LQFP]
48-Lead Low Profile Quad Flat Package [LQFP]
48-Lead Low Profile Quad Flat Package [LQFP]
Evaluation Board
Development Board
Z = RoHS Compliant Part.
Rev. A | Page 29 of 32
Package Option
CP-48-1
CP-48-1
CP-48-1
CP-48-1
ST-48
ST-48
ST-48
ST-48
AD7264
NOTES
Rev. A | Page 30 of 32
AD7264
NOTES
Rev. A | Page 31 of 32
AD7264
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06732-0-7/08(A)
Rev. A | Page 32 of 32
Similar pages