Stereo FM Receiver Radio-on-a-Chip™ KT0830EG Features Fully compatible with KT0830E Excellent radio reception with short antenna 32.768KHz and 38KHz crystal support Variable reference clock support including 32.768 KHz/7.6MHz/12MHz/24MHz Excellent tuning experience with built in SNR meter and RSSI Low-cost true single-chip FM radio solution Single-Chip Low IF FM Receiver Direct band, volume, frequency selection Digital FM Demodulator Digital Stereo Processor Low-noise PLL with integrated VCO Extended FM band support (64-109MHz) Integrated Class AB headphone driver High Fidelity SNR: 64dB THD: <0.3% High Sensitivity: -106dBm Low supply current 19mA (operating), 1uA (power-down) High Driving capability Drive up to 16 ohm load (single-sided) Automatic Frequency Control (AFC) Automatic gain control (AGC) Anti-pop circuit 16-pin SOP package Applications Figure 1: System Diagram Description The KT0830EG is a high-quality Monolithic Digital FM Receiver designed to playback high-fidelity FM broadcasting signals under various conditions. The KT0830EG offers a true single-chip FM radio solution. There are no external filters or frequency-tuning devices thanks to a proprietary digital low-IF architecture, a fullyintegrated LNA, automatic gain control (AGC), highperformance ADCs, high-quality analog and digital filters, and an on-chip low-noise self-tuning VCO. The on-chip highfidelity Class-AB driver further eliminates the need for any external audio amplifiers and can drive stereo headphones directly. The on-chip LDO regulator allows the chip to operate with power supply ranging from 2.0V to 3.6V consuming merely 19mA in full operation mode and less than 10uA when standby – greatly extending the battery life. The small footprint, high integration level and great flexibility make KT0830EG for any standalone FM radio applications. Single chip FM radio used in PMP, boom box, sporting devices, medical devices and etc Rev. 1.2 Information furnished by KT Micro is believed to be accurate and reliable. However, no responsibility is assumed by KT Micro for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of KT Micro, Inc. Copyright ©2010, KT Micro, Inc. 深圳代理办事处：深圳市高智创电子有限公司 网址：www.sbdsemi.cn 联系：086-0755-81753689/83340989 移动：13642365547 杨斌(先生) 本信息资料皆为原设计公司所拥有及发布，如有详细疑问，请联系本公司及原厂。 1 EMAIL: [email protected] KT0830EG Table of Content Section ................................................................................................................................................. Page 1 Electrical specification ..........................................................................................................................3 2 Pin List ...................................................................................................................................................4 3 Functional Description ..........................................................................................................................6 3.1 Overview ............................................................................................................................... 6 3.2 FM Receiver .......................................................................................................................... 6 3.3 Digital Signal Processing ...................................................................................................... 6 3.4 Stereo DAC, Audio Filter and Driver .................................................................................... 7 3.5 SEEK/TUNE ......................................................................................................................... 7 3.6 Power on Sequence................................................................................................................ 8 3.7 Reference Clock .................................................................................................................... 8 4 Control Interface- I2C ..........................................................................................................................8 5 Register Map ........................................................................................................................................10 5.1 Device ID Register (Reg 0x00) ........................................................................................... 11 5.2 CHIP ID (Reg 0x01) ............................................................................................................ 11 5.3 Seek Configuration (Reg 0x02) ........................................................................................... 11 5.4 TUNE Register (Reg 0x03) ................................................................................................. 11 5.5 VOLUME Control Register (Reg 0x04).............................................................................. 12 5.6 DSP Configuration Register A (Reg 0x05) ......................................................................... 13 5.7 LO Synthesizer Configuration A (Reg 0x0A) ..................................................................... 13 5.8 System Configuration Register (Reg 0x0F) ........................................................................ 14 5.9 Status Register A (Reg 0x12) .............................................................................................. 15 5.10 Status Register B (Reg 0x13) .............................................................................................. 15 5.11 . Status Register C (Reg 0x14) ............................................................................................ 16 5.12 Status Register D (Reg 0x15) .............................................................................................. 16 5.13 SNR Register (Reg 0x1F) .................................................................................................... 16 5.14 SEEKTH Register (Reg 0x20) ............................................................................................ 16 5.15 Softmute Register (Reg 0x21) ............................................................................................. 16 5.16 Clock Register (Reg 0x23) .................................................................................................. 17 6 Application circuit ...............................................................................................................................18 7 Package.................................................................................................................................................20 8 Order Information ..............................................................................................................................20 9 Revision History ..................................................................................................................................21 10Contact Information ...........................................................................................................................21 Copyright ©2010, KT Micro, Inc. 深圳代理办事处：深圳市高智创电子有限公司 网址：www.sbdsemi.cn 联系：086-0755-81753689/83340989 移动：13642365547 杨斌(先生) 本信息资料皆为原设计公司所拥有及发布，如有详细疑问，请联系本公司及原厂。 2 EMAIL: [email protected] KT0830EG 1 Electrical specification Parameter Power Supply Operating Temp Parameter Current Consumption Standby Current Power-down Current Symbol VDD Tj Table 1: Operation Condition Operating Condition Min Relative to Vss 2.0 Junction Temperature -20 Table 2: DC Characteristics Symbol Test/Operating Min Condition IA IAPD IPD Typ 3.3 50 Max 3.6 110 Units V °C Typ Max Units 19 6 1 10 3 mA μA μA Table 3: FM Receiver Characteristics (Unless otherwise noted Tj = -20~110 oC, VDD =2.0V to 3.6V) Parameter Symbol Test/Operating Min Typ Max Condition FM Frequency Range Frx 64 109 Sensitivity1,2,3 Sen (S+N)/N=26dB 2.2 3.5 IIP3 Input referred 3rd Order 87 Intermodulation Production4,5 Adjacent Channel Selectivity 40 51 ±200KHz Alternate Channel Selectivity 50 70 ±400KHz Image Rejection Radio 35 AM suppression 50 RCLK frequency 32 32.768 26000 RCLK frequency Range8 -100 100 Audio Output Voltage1,2,3,4 32ohm load 68 70 72 Audio Band Limits1,2,4 30 15k ±3dB Audio Stereo Separation 1,4,6 35 Audio Stereo S/N1,4,6,7 64 Audio THD1,2,4,6 0.3 Audio Common Mode Voltage 0.7 Audio Output Load Resistance RL Single-ended 16 Seek/Tune Time 50 (effective channel) Power-up Time 380 Notes: 1. FMOD=1kHz, 75us de-emphasis 2. MONO=1 3. △F=22.5kHz 4. VEMF=1mV, Frx=70MHz~110MHz 5. AGCD=1 6. △F=75kHz 7. VOLUME<3:0>=1111 8. The supported RCLK frequency is not continuous. Please refer to application notes. Copyright ©2010, KT Micro, Inc. 深圳代理办事处：深圳市高智创电子有限公司 网址：www.sbdsemi.cn 联系：086-0755-81753689/83340989 移动：13642365547 杨斌(先生) 本信息资料皆为原设计公司所拥有及发布，如有详细疑问，请联系本公司及原厂。 Units MHz uVemf dBuVE MF dB dB dB dB KHz ppm mVRMS Hz dB dB % V Ω ms/ch ms 3 EMAIL: [email protected] KT0830EG 2 Pin List A 16-pin SOP package is used. The chip IO pin-out is listed in Table 4. Pin Index 1 2 3 4 5 6 Name VDD GND GND SCLK SDIO LOUT 7 ROUT 8 9 10 GND VDD XI/RCLK 11 12 XO POWER_ON 13 14 15 N.C. GND RFINP 16 GND Table 4 Pin-Out I/O Type Function Power 2.0V – 3.6V Power supply Ground Ground Ground Ground Digital Input I2C clock input. Digital IO I2C data input/output Analog output Left channel output with 16 ohm driving capability. Analog output Right channel output with 16 ohm driving capability. Ground Ground Power 2.0V – 3.6V power supply. Analog IO 32.768KHz crystal input or 32.768KHz external reference clock input. Analog IO 32.768KHz crystal input Digital Input High for normal operating mode and low for standby mode. N.C. No Connection Ground Ground Analog Input RF signal input. External AC coupling cap is not required Ground Ground Figure 2: Pin out Copyright ©2010, KT Micro, Inc. 深圳代理办事处：深圳市高智创电子有限公司 网址：www.sbdsemi.cn 联系：086-0755-81753689/83340989 移动：13642365547 杨斌(先生) 本信息资料皆为原设计公司所拥有及发布，如有详细疑问，请联系本公司及原厂。 4 EMAIL: [email protected] KT0830EG Table 5: I/O Pin Configuration PAD SCLK Schematic SDIO RFINP POWERON Copyright ©2010, KT Micro, Inc. 深圳代理办事处：深圳市高智创电子有限公司 网址：www.sbdsemi.cn 联系：086-0755-81753689/83340989 移动：13642365547 杨斌(先生) 本信息资料皆为原设计公司所拥有及发布，如有详细疑问，请联系本公司及原厂。 5 EMAIL: [email protected] KT0830EG 3 Functional Description 3.1 Overview The KT0830EG offers a true single-chip FM radio solution by virtually eliminating all the external components. There are no external filters or frequency-tuning devices thanks to a proprietary digital low-IF architecture, a fully-integrated LNA, automatic gain control (AGC), high-performance ADCs, high-quality analog and digital filters, and an on-chip low-noise self-tuning VCO. The on-chip high-fidelity Class-AB driver further eliminates the need for any external audio amplifiers and can drive stereo headphones directly. 3.2 FM Receiver A high performance digital-IF structure receiver is used in KT0830EG to convert RF signal to IF signal. The received IF signal is digitized by a high resolution analog to digital converter (ADC) and all of the following signal processing including channel filtering, FM demodulation and stereo decoding is performed digitally. In order to improve the dynamic range of the RF signal, an automatic gain control (AGC) loop is used together with the low noise amplifier (LNA). 3.3 Digital Signal Processing 3.3.1 Stereo Decoder The digitized IF signal is fed to the FM demodulator which demodulates the signal and outputs a digital multiplexed (MPX) signal consisting of L+R audio, L-R audio, 19kHz pilot tone. The left channel signal and the right channel signal can be extracted from the MPX signal by simply adding and subtracting the L+R signal and L-R signal. The spectrum diagram is shown in Figure 3. Figure 3: Spectrum diagram of the MPX signal Copyright ©2010, KT Micro, Inc. 深圳代理办事处：深圳市高智创电子有限公司 网址：www.sbdsemi.cn 联系：086-0755-81753689/83340989 移动：13642365547 杨斌(先生) 本信息资料皆为原设计公司所拥有及发布，如有详细疑问，请联系本公司及原厂。 6 EMAIL: [email protected] KT0830EG 3.3.2 Mute KT0830EG can be hard muted by setting VOLUME to 0 and the output of the audio signal is set to the common mode voltage. There is also a Soft Mute feature that is enabled by setting SMUTE_B to 0. In this mode, the audio volume is gradually attenuated when the signal reception is bad (i.e. when the RSSI or SNR, which is determined by reg SMMD, is below a certain level as defined by SMTH<2:0>.) The reg VOLUMET<3:0> sets the lowest volume that the internal state machine can reach. The attenuation attack rate and depth can be configured through SMUTER<1:0> and SMUTEA<1:0>, respectively. 3.3.3 Stereo / Mono Blending In order to provide a comfortable listening experience, KT0830EG blends the stereo signal with mono signal gradually when in weak reception. The signal level range over which the blending occurs is set by BLNDADJ<1:0>. The blending is disabled when DBLND is set to 1. MONO playback mode can also be forced by setting the MONO to 1. 3.3.4 Bass Boosting KT0830EG provides a digital audio enhancement feature, bass boosting. The gain of the bass boost can be programmed through BASS<1:0> (Reg0x04<9:8>). With BASS<1:0>=00, this feature is disabled. 3.4 Stereo DAC, Audio Filter and Driver Two high-quality single-bit ΔΣ audio digital to analog converters (DAC) are integrated along with high-fidelity analog audio filters and class AB drivers. Headphones or speakers with impedance as low as 16ohms can be directly driven without external audio drivers. An integrated anti-pop circuit eliminates the clickand-pop sound during power up and power down. 3.5 SEEK/TUNE The fully integrated LO synthesizer supports wide band operation from 64MHz to 110MHz. The chip begins to directly TUNE to a channel when the register TUNE is set to 1. The channel frequency can be programmed and tuned by setting CHAN<9:0> which is defined as Freq(MHz) = 50 kHz × CHAN<9:0> + 64 MHz The Seeking process is started by setting SEEK to “1”. Two built-in seek methods are available, which are distinguished by setting SEEK_SEL. Seeking direction is determined by SEEKDIR. The band edges are determined by BAND<1:0> and the seek step is set by SPACE<1:0>. KT0830EG automatically seeks and tunes to the first satisfying station. If no qualified channel is found, the FM receiver returns to the original channel and SF/BL bit is set to “1”. when SEEKMD is set to 0. Alternatively, if SEEKMD is set to 1 and no qualified channel is found, the chip stops at the band edge while setting SF/BL bit to 1. When AUTOTUNE bit is set to 1, the chip will automatically tune to the found channel, otherwise, the chip will remain mute after Copyright ©2010, KT Micro, Inc. 深圳代理办事处：深圳市高智创电子有限公司 网址：www.sbdsemi.cn 联系：086-0755-81753689/83340989 移动：13642365547 杨斌(先生) 本信息资料皆为原设计公司所拥有及发布，如有详细疑问，请联系本公司及原厂。 7 EMAIL: [email protected] KT0830EG seek is completed. During the seeking, the current channel can be read out from READCH<9:0> bits. Refer to application notes for more information. 3.6 Power on Sequence KT0830EG is powered up by pulling the POWER_ON pin to high. or leaving this pin not connection. No external power-on reset circuit is required. One needs to wait for 400ms before he/she can configure the chip through the serial interface. 3.7 Reference Clock The KT0810G support variable reference clock frequencies, such as 32.768KHz, 7.6MHz, 12MHz, 13MHz, 24MHz, 26MHz and etc. The built-in crystal oscillator also supports 32.768KHz and 38KHz crystal. Please refer to application notes for more information about setting different reference clock. 4 Control Interface- I2C I2C bus mode uses SCLK and SDIO to transfer data. The device always drives data to SDIO at the falling edge of SCLK and captures data from SDIO at the rising edge of SCLK. The device acknowledges the external controller by driving SDIO low at the falling edge of SCLK. Data transfer always begins with START condition and ends with STOP condition. The external controller can read/write one 16-bits data at the specified address or read/write desired number of registers data continuously from the specified address till when STOP condition is occurred. For write operations, external controller should send command & data in the following sequence: START condition -> 7 bit chip address and Write command (“0”) -> 8 bit register address n -> write data n [15:8] -> write data n [7:0] -> write data n+1 [15:8] -> write data n+1 [7:0] -> …… -> STOP condition. For read operations, external controller should send command & data in the following sequence: START condition -> 7 bit chip address and Write command (“0”) -> 8 bit register address n -> 7 bit chip address and Read command (“1”) , then device will send read data n [15:8] -> read data n [7:0] -> read data n+1 [15:8] -> read data n+1 [7:0] > …… till STOP condition. Table 6 : I2C Interface Protocol RANDOM REGISTER WRITE PROCEDURE S 0 1 1 x 1 1 1 WA A A AP 7 bit chip Register address write data [15:8] write data [7:0] address Acknowledge Acknowledg Acknowledge e START WRITE command STOP condition condition Copyright ©2010, KT Micro, Inc. 深圳代理办事处：深圳市高智创电子有限公司 网址：www.sbdsemi.cn 联系：086-0755-81753689/83340989 移动：13642365547 杨斌(先生) 本信息资料皆为原设计公司所拥有及发布，如有详细疑问，请联系本公司及原厂。 8 EMAIL: [email protected] KT0830EG RANDOM REGISTER READ PROCEDURE S 0 1 1 x 1 1 1 WA 7 bit chip register address address Acknowledge WRITE command START condition AS 0 1 1 x 1 1 1 RA … A … AP 7 bit chip address read read data data [15:8] [7:0] Acknowledge Acknowledge READ command NO Acknowledge STOP condition Note: The data bits in gray color are sent by KT0830EG SDIO CHIP ADDR R/W ACK SCLK 1-7 8 9 REG ADDR 1-7 ACK 8 ACK DATA 9 1-7 8 9 P S Figure 4: I2C interface timing diagram Copyright ©2010, KT Micro, Inc. 深圳代理办事处：深圳市高智创电子有限公司 网址：www.sbdsemi.cn 联系：086-0755-81753689/83340989 移动：13642365547 杨斌(先生) 本信息资料皆为原设计公司所拥有及发布，如有详细疑问，请联系本公司及原厂。 9 EMAIL: [email protected] RFCFG LOCFGA SYSCFG STATUSA STATUSB STATUSC STATUSD ANTENNA SNR SEEKTH SOFTMUTE CLOCK 09h 0Fh 12h 13h 14h 15h 1Dh 1Fh 20h 21h 23h DSPCFGA 05h 0Ah VOLUME SEEK 02h 04h CHIPID 01h TUNE DEVICE 00h 03h Name Reg SFTRST STC XTAL_OK E AUTOTUN D12 SF/BL STCIEN D10 DEV<15:0> D4 深圳代理办事处：深圳市高智创电子有限公司 网址：www.sbdsemi.cn 联系：086-0755-81753689/83340989 移动：13642365547 杨斌(先生) 本信息资料皆为原设计公司所拥有及发布，如有详细疑问，请联系本公司及原厂。 RCLK_EN LRSWAP D2 D1 E_EN ANT_TUN SMTH<2> AFC_DELTAF<5:0> GPIO2<1:0> D0 GPIO1<1:0> VOLUME<3:0> SPACE<1:0> D3 AFC_DELTAF<7:0> READCHANCHAN<9:0> RSSI<4:0> GPIO3<1:0> DBLND SMTH<1:0> CHAN<9>0> FM_BAND<1:0> D5 ADV_SEEKTH_LOW SMMD SEEK_SEL HLSI D6 ADV_SEEKTH_HIGH ST<1:0> AFCD ANTTYP<1:0> BLNDADJ<1:0> REF_CLK<3:0> LO_LD SEEKMD D7 MFGID<15:0> D8 BASS<1:0> SEEKTH<4:0> D9 SNR<7:0> PLL_LD DE SMUTEA<1:0> D11 SNRTH<7:0> STDBY SMUTER<1:0> D13 AFCRANGE<2:0> MUTE_B SEEKDIR D14 INTLVL MONO SMUTE_B TUNE SEEK D15 KT0830EG 5 Register Map Copyright ©2010, KT Micro, Inc. 10 EMAIL: [email protected] KT0830EG The register bank stores channel frequency codes, calibration parameters, operation status, mode and power controls, which can be accessed by the internal digital controller, state machines and external micro controllers through the serial interface. All registers are 16 bits wide. Control logics are active high unless specifically noted. All the registers are automatically set to default values after the chip is powered-on or reset. 5.1 Device ID Register (Reg 0x00) Bit 15:0 Symbol Access MFGID<15:0> R Default 0xb002 Functional Description Manufacturer ID Default 0x0440 Functional Description Part Number 0x0440=FM Receiver 5.2 CHIP ID (Reg 0x01) Bit 15:0 Symbol DEV<15:0> Access R 5.3 Seek Configuration (Reg 0x02) Bit 15 Symbol SEEK Access RW 14 SEEKDIR RW 13:12 11:7 Reserved SEEKTH<4:0> RW RW 6 5:4 Reserved FM_Band<1:0> RW 3:2 SPACE<1:0> RW 1:0 Reserved Default Functional Description 0 Seek enable 0 = Disable 1 = Enable 0 Seek direction 0 = Seek down 1 = Seek up 10 Reserved 00110 Seek Threshold 00000 = most sensitive 11111 = least sensitive 0 Reserved 00 Band Selection 00 = 87-108MHz (USA, Europe) 01 = 76-108MHz (Japan wide band) 10 = 76-90MHz (Japan). 11 = reserved 00 Channel spacing 00 = 200KHz (US, Europe) 01 = 100KHz (Europe, Japan) 10 = 50KHz 11 Reserved 5.4 TUNE Register (Reg 0x03) Bit Symbol Access Default Functional Description Copyright ©2010, KT Micro, Inc. 深圳代理办事处：深圳市高智创电子有限公司 网址：www.sbdsemi.cn 联系：086-0755-81753689/83340989 移动：13642365547 杨斌(先生) 本信息资料皆为原设计公司所拥有及发布，如有详细疑问，请联系本公司及原厂。 11 EMAIL: [email protected] KT0830EG 15 Tune RW 0 14:13 Reserved RW 00 12 AUTOTUNE RW 1 11:10 Reserved RW 10 9:0 Chan<9:0> RW 1CC Tune Enable 0 = Disable 1 = Enable Automatic tune control 0 = Will NOT tune after a successful seek until a separated Tune command is received from the control interface 1 = Automatically starts Tune process after Seek Tune Channel Value 5.5 VOLUME Control Register (Reg 0x04) Bit 15 Symbol SMUTE_B Access RW 14 MUTE_B RW 13:12 SMUTER<1:0> RW 11:10 SMUTEA<1:0> RW 9:8 BASS<1:0> RW 7:6 5:4 Reserved SMTH<1:0> RW Default Functional Description 1 Softmute Disable 0 = Softmute enable 1 = Softmute disable 0 Hard Mute Disable 0 = Mute enable 1 = Mute disable 00 Softmute Attack/Recover Rate 0 = Slowest 01 = Fastest (RSSI mode only) 10 = Fast 11 = Slow 00 Softmute Attenuation 00 = Strong 01 = Strongest 10 = Weak 11 = Weakest 00 Bass boost effect mode selection 00 = Disable 01 = Low 10 = Med 11 = High 00 10 Soft mute start level together with SMTH<2> in reg0x21 000 = Lowest …… 111 = Highest Copyright ©2010, KT Micro, Inc. 深圳代理办事处：深圳市高智创电子有限公司 网址：www.sbdsemi.cn 联系：086-0755-81753689/83340989 移动：13642365547 杨斌(先生) 本信息资料皆为原设计公司所拥有及发布，如有详细疑问，请联系本公司及原厂。 12 EMAIL: [email protected] KT0830EG 3:0 VOLUME<3:0> RW 0111 Volume Control 0000 = mute 0001 = -42dBFS 0010 = -39dBFS …… ……. 1110 = -3dBFS 1111 = FS 5.6 DSP Configuration Register A (Reg 0x05) Bit 15 Symbol MONO Access RW 14:12 11 Reserved DE RW RW 10 9:8 Reserved BLNDADJ<1:0> RW RW Default Functional Description 0 Mono Select 0 = Stereo 1 = Force mono 101 Reserved 0 De-emphasis 0 = 75us. Used in USA. 1 = 50us. Used in Europe, Australia, Japan. 0 00 Stereo/Mono Blend Start Level 00 = High 01 = Highest 10 = Lowest 11 = Low Note: Write 00 explicitly even if 00 is the default value. 7:6 5 Reserved DBLND 4:0 Reserved RW RW 00 0 00000 Reserved Blend disable 0 = blend enable 1 = blend disable Reserved 5.7 LO Synthesizer Configuration A (Reg 0x0A) Bit Symbol 15 Reserved 14:12 AFCRANGE<2:0> Access RW RW Default 0 000 11:9 RW 000 Reserved Functional Description AFC correction range 000 = 12KHz 001 = 15KHz 010 = 14KHz 011 = 17KHz 100 = 16KHz 101 = 19KHz 110 = 22KHz 111 = 25KHz Copyright ©2010, KT Micro, Inc. 深圳代理办事处：深圳市高智创电子有限公司 网址：www.sbdsemi.cn 联系：086-0755-81753689/83340989 移动：13642365547 杨斌(先生) 本信息资料皆为原设计公司所拥有及发布，如有详细疑问，请联系本公司及原厂。 13 EMAIL: [email protected] KT0830EG 8 AFCD RW 1 7 6 Reserved HLSI RW RW 0 0 5:0 Reserved R 000000 AFC disable control bit 0 = AFC enable 1 = AFC disable High side or low side injection 1 = high side injection 0 = low side injection Reserved 5.8 System Configuration Register (Reg 0x0F) Bit 15 Symbol INTLVL Access RW 14 SFTRST RW 13 STCIEN RW 12 STDBY RW 11 10 Reserved SEEKMD RW RW 9:7 6 Reserved SEEK_SEL RW RW 5:4 GPIO3<1:0> RW 3:2 GPIO2<1:0> RW Default Functional Description 1 Interrupt level control (GPIO2) 0 = low level interrupt 1 = high level interrupt 0 Soft reset bit 0 = normal operation 1 = soft reset 0 Seek/Tune Complete Interrupt Enable 0 = Disable Interrupt 1 = Enable Interrupt 0 Standby mode (See version notes) 0 = disable 1 = enable 1 Reserved 0 Seek mode selection 0 = cycling seek 1 = stop at the band edge. 100 0 SEEK Method Selection 0 = Traditional method 1 = Advanced method 00 General Purpose I/O 3 00 = high impedance 01 = Mono/Stereo indicator (ST). GPIO3 = High for Stereo GPIO3 = Low for Mono 10 = low 11 = high 00 General purpose I/O 2 00 = high impedance 01 = STC interrupt/RDS group synchronization interrupt/ 10 = low 11 = high Copyright ©2010, KT Micro, Inc. 深圳代理办事处：深圳市高智创电子有限公司 网址：www.sbdsemi.cn 联系：086-0755-81753689/83340989 移动：13642365547 杨斌(先生) 本信息资料皆为原设计公司所拥有及发布，如有详细疑问，请联系本公司及原厂。 14 EMAIL: [email protected] KT0830EG 1:0 GPIO1<1:0> 5.9 RW 00 Setting STCIEN=1 will generate a high level interrupt on GPIO2 when the STC bit is set. Setting RDSIEN=1 will generate a high level interrupt on GPIO2 when RDS is synchronized. General purpose I/O 1 00 = high impedance 01 = reserved 10 = low 11 = high Status Register A (Reg 0x12) Bit Symbol 15 XTAL_OK Access Default Functional Description R 0 Crystal ready indictor 0 = not ready 1= crystal is ok 14 STC RW 0 Seek/Tune Complete 0 = Not Complete 1 = Complete The status can be cleared manually 13 SF/BL RW 0 Seek Fail or Band Limit 0 = Seek successful 1 = Seek failure 12 Reserved R 0 11 PLL_LOCK R 1 System PLL ready indicator 0 = not ready 1 = System PLL ready 10 LO_LOCK R 1 LO Synthesizer ready indicator 0 = not ready 1 = ready 9:8 ST<1:0> R 00 Stereo indicator 11 = Stereo Other= Mono 7:3 RSSI<4:0> R 00000 RSSI value indicator RSSI indication range is from -100dBm to -7dBm with 3dB resolution, where 00000 means minimum level and 11111 means maximum level. 2:0 Reserved R 000 Reserved 5.10 Status Register B (Reg 0x13) Bit 15:10 9:0 Symbol Reserved READCHAN<9:0> Access Default Functional Description R 000000 Reserved R 0 The current Channel READCHAN<9:0> provides the Copyright ©2010, KT Micro, Inc. 深圳代理办事处：深圳市高智创电子有限公司 网址：www.sbdsemi.cn 联系：086-0755-81753689/83340989 移动：13642365547 杨斌(先生) 本信息资料皆为原设计公司所拥有及发布，如有详细疑问，请联系本公司及原厂。 15 EMAIL: [email protected] KT0830EG current channel during seek or after a seek or tune operation is completed 5.11 . Status Register C (Reg 0x14) Bit Symbol Access Default Functional Description 15:6 Reserved R 0000000000 Reserved Frequency difference between 5:0 AFC_DELTAF_5767<5:0> R 000000 CHAN and received signal, calculated by AFC block in two’s complement format. Range is -31 to +31. Unit is KHz. This register is valid when STC=1 5.12 Status Register D (Reg 0x15) Bit 15:8 7:0 Symbol Reserved AFC_DELTAF<7:0> Access Default Functional Description R 00000000 Reserved R 00000000 Frequency difference between CHAN and received signal, calculated by AFC block in two’s complement format. Range is -127 to +127. Unit is KHz. This register is valid when STC=1 5.13 Antenna Register (Reg 0x1D) Bit 15:0 Symbol Reserved Access Default Functional Description 5.14 SNR Register (Reg 0x1F) Bit 15:8 Symbol SNRTH<7:0> 7:0 SNR<7:0> Access Default Functional Description RW 0x00 SNR threshold for traditional seek mode SNR value of current channel R 0x00 0x00 = Worst …… 0xFF = Best 5.15 SEEKTH Register (Reg 0x20) Bit 15:8 Symbol ADV_SEEKTH_HIGH 7:0 ADV_SEEKTH_LOW Access Default Functional Description RW 0x14 High threshold for advanced seek mode Low threshold for advanced seek mode RW 0x19 5.16 Softmute Register (Reg 0x21) Bit Symbol Access Default Functional Description Copyright ©2010, KT Micro, Inc. 深圳代理办事处：深圳市高智创电子有限公司 网址：www.sbdsemi.cn 联系：086-0755-81753689/83340989 移动：13642365547 杨斌(先生) 本信息资料皆为原设计公司所拥有及发布，如有详细疑问，请联系本公司及原厂。 16 EMAIL: [email protected] KT0830EG 15:7 6 Reserved SMMD RW RW 5:4 3 Reserved SMTH<2> RW RW 2:0 Reserved RW 000100000 Reserved 0 Softmute Mode Selection 0 = RSSI 1 = SNR 01 Reserved 0 Softmute threshold MSB, together with SMTH<1:0> in Reg0x04 010 000 = Lowest 001 = … 111 = Highest Reserved 5.17 Clock Register (Reg 0x23) Bit Symbol 15:13 Reserved 12 RCLK_EN Access Default RW 000 RW 0 Functional Description Reserved Reference Clock Enable 0 = crystal 1 = reference clock 11:8 REF_CLK<3:0> RW 0000 7:5 4 Reserved LRSWAP RW RW 000 0 3:0 Reserved RW 0 Reference clock selection 0000 = 32.768KHz 0001 = 6.5MHz 0010 = 7.6MHz 0011 = 12MHz 0100 = 13MHz 0101 = 15.2MHz 0110 = 19.2MHz 0111 = 24MHz 1000 = 26MHz Reserved Swap Left and Right audio channels 0 = don’t swap 1 = swap Reserved Copyright ©2010, KT Micro, Inc. 深圳代理办事处：深圳市高智创电子有限公司 网址：www.sbdsemi.cn 联系：086-0755-81753689/83340989 移动：13642365547 杨斌(先生) 本信息资料皆为原设计公司所拥有及发布，如有详细疑问，请联系本公司及原厂。 17 EMAIL: [email protected] KT0830EG 6 Application circuit C3 1 16 GND 2 15 GND 3 14 SCLK 4 SDIO 5 LOUT 6 ROUT 7 10 GND 8 9 KT0830E G C2 VDD GND RFINP GND 13 N.C 12 POWER_ON 11 XO XI/RCLK VDD External clock input From Battery C1 Figure 5: Typical application circuit (Reference Clock) Note：The decoupling C1 should be close to Pin 8 and Pin 9。 Table 7: Bill of Material Components C1 C2,C3 Value/Description Supply decoupling capacitor, 0.1uF AC decoupling capacitor, 100uF Suppliers Copyright ©2010, KT Micro, Inc. 深圳代理办事处：深圳市高智创电子有限公司 网址：www.sbdsemi.cn 联系：086-0755-81753689/83340989 移动：13642365547 杨斌(先生) 本信息资料皆为原设计公司所拥有及发布，如有详细疑问，请联系本公司及原厂。 18 EMAIL: [email protected] KT0830EG C3 1 16 GND 2 15 GND 3 14 SCLK 4 SDIO 5 LOUT 6 KT0830EG C2 VDD GND RFINP GND 13 N.C POWER_ON 12 11 ROUT 7 10 GND 8 9 XO C4 Y1 C5 XI/ RCLK R1(Recommended) VDD C1 From Battery Figure 6: Typical application circuit (Crystal) Note：The decoupling C1 should be close to Pin 8 and Pin 9。 Table 8: Bill of Material Components C1 C2,C3 C4,C5 Y1 R1 Value/Description Supply decoupling capacitor, 0.1uF AC decoupling capacitor, 100uF Capacitor, 24pF Crystal, 32.768KHz Resistor, 10Mohm Suppliers Copyright ©2010, KT Micro, Inc. 深圳代理办事处：深圳市高智创电子有限公司 网址：www.sbdsemi.cn 联系：086-0755-81753689/83340989 移动：13642365547 杨斌(先生) 本信息资料皆为原设计公司所拥有及发布，如有详细疑问，请联系本公司及原厂。 19 EMAIL: [email protected] KT0830EG 7 Package 8 Order Information Part Number Description nd KT0830EG 2 gen Single-chip stereo FM receiver Package SOP-16 Copyright ©2010, KT Micro, Inc. 深圳代理办事处：深圳市高智创电子有限公司 网址：www.sbdsemi.cn 联系：086-0755-81753689/83340989 移动：13642365547 杨斌(先生) 本信息资料皆为原设计公司所拥有及发布，如有详细疑问，请联系本公司及原厂。 MOQ 5000 20 EMAIL: [email protected] KT0830EG 9 Revision History V1.0 V1.1 V1.2 Official Release Pin 14 and Pin 2 Added Figure 7 and Table 9 深圳代理办事处：深圳市高智创电子有限公司 联系：086-0755-81753689/83340989 网址：www.sbdsemi.cn 本信息资料皆为原设计公司所拥有及发布，如有详细疑问，请联系本公司及原厂。 Copyright ©2010, KT Micro, Inc. 深圳代理办事处：深圳市高智创电子有限公司 网址：www.sbdsemi.cn 联系：086-0755-81753689/83340989 移动：13642365547 杨斌(先生) 本信息资料皆为原设计公司所拥有及发布，如有详细疑问，请联系本公司及原厂。 21 EMAIL: [email protected]