FINAL COM’L: H-5/7/10/15/25, Q-10/15/25 IND: H-10/15/25, Q-20/25 PALCE16V8 Family EE CMOS 20-Pin Universal Programmable Array Logic DISTINCTIVE CHARACTERISTICS ■ Pin and function compatible with all 20-pin GAL devices ■ Programmable output polarity ■ Electrically erasable CMOS technology provides reconfigurable logic and full testability ■ Preloadable output registers for testability ■ High-speed CMOS technology ■ Cost-effective 20-pin plastic DIP, PLCC, and SOIC packages — 5-ns propagation delay for “-5” version — 7.5-ns propagation delay for “-7” version ■ Direct plug-in replacement for the PAL16R8 series and most of the PAL10H8 series ■ Outputs programmable as registered or combinatorial in any combination ■ Peripheral Component Interconnect (PCI) compliant ■ Programmable enable/disable control ■ Automatic register reset on power up ■ Extensive third-party software and programmer support through FusionPLD partners ■ Fully tested for 100% programming and functional yields and high reliability ■ 5 ns version utilizes a split leadframe for improved performance GENERAL DESCRIPTION The PALCE16V8 is an advanced PAL device built with low-power, high-speed, electrically-erasable CMOS technology. It is functionally compatible with all 20-pin GAL devices. The macrocells provide a universal device architecture. The PALCE16V8 will directly replace the PAL16R8 and PAL10H8 series devices, with the exception of the PAL16C1. The fixed OR array allows up to eight data product terms per output for logic functions. The sum of these products feeds the output macrocell. Each macrocell can be programmed as registered or combinatorial with an activehigh or active-low output. The output configuration is determined by two global bits and one local bit controlling four multiplexers in each macrocell. The PALCE16V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to implement complex logic functions easily and efficiently. Multiple levels of combinatorial logic can always be reduced to sum-of-products form, taking advantage of the very wide input gates available in PAL devices. The equations are programmed into the device through floatinggate cells in the AND logic array that can be erased electrically. AMD’s FusionPLD program allows PALCE16V8 designs to be implemented using a wide variety of popular industry-standard design tools. By working closely with the FusionPLD partners, AMD certifies that the tools provide accurate, quality support. By ensuring that thirdparty tools are available, costs are lowered because a designer does not have to buy a complete set of new tools for each device. The FusionPLD program also greatly reduces design time since a designer can use a tool that is already installed and familiar. 2-36 Publication# 16493 Rev. D Issue Date: February 1996 Amendment /0 AMD BLOCK DIAGRAM I1 – I 8 CLK/I0 8 Programmable AND Array 32 x 64 MACRO MACRO MACRO MACRO MACRO MACRO MACRO MACRO MC0 MC1 MC2 MC3 MC4 MC5 MC6 MC7 OE/I9 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 16493D-1 CONNECTION DIAGRAMS Top View DIP/SOIC 1 20 VCC I1 2 19 I/O7 I1 CLK/I0 VCC I2 3 18 I/O6 3 2 1 20 19 I3 4 17 I/O5 I4 5 16 I/O4 I3 4 18 I/O6 I5 6 15 I/O3 I4 5 17 I/O5 I6 7 14 I/O2 I5 6 16 I/O4 I7 8 13 I/O1 I/O0 I/O3 12 I6 15 9 7 I8 10 11 OE/I9 I7 8 14 I/O2 CLK GND I I/O OE VCC = = = = = = I/O1 I/O0 PIN DESIGNATIONS 10 11 12 13 OE/I9 Note: Pin 1 is marked for orientation. 9 GND 16493D-2 I8 GND I/O7 CLK/I0 I2 PLCC/LCC 16493D-3 Clock Ground Input Input/Output Output Enable Supply Voltage PALCE16V8 Family 2-37 AMD ORDERING INFORMATION Commercial and Industrial Products AMD programmable logic products for commercial and industrial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: PAL CE 16 V 8 H -5 P C /5 OPTIONAL PROCESSING Blank = Standard Processing FAMILY TYPE PAL = Programmable Array Logic TECHNOLOGY CE = CMOS Electrically Erasable PROGRAMMING DESIGNATOR Blank = Initial Algorithm /4 = First Revision /5 = Second Revision (Same Algorithm as /4) NUMBER OF ARRAY INPUTS OUTPUT TYPE V = Versatile NUMBER OF OUTPUTS POWER H = Half Power (90 – 125 mA ICC) Q = Quarter Power (55 mA ICC) OPERATING CONDITIONS C = Commercial (0°C to +75°C) I = Industrial (–40°C to +85°C) SPEED -5 = 5 ns tPD -7 = 7.5 ns tPD -10 = 10 ns tPD -15 = 15 ns tPD -20 = 20 ns tPD -25 = 25 ns tPD PACKAGE TYPE P = 20-Pin Plastic DIP (PD 020) J = 20-Pin Plastic Leaded Chip Carrier (PL 020) S = 20-Pin Plastic Gull-Wing Small Outline Package (SO 020) Valid Combinations PALCE16V8H-5 PALCE16V8H-7 PALCE16V8H-10 PALCE16V8Q-10 PALCE16V8H-15 PALCE16V8Q-15 PALCE16V8Q-20 PALCE16V8H-25 PALCE16V8Q-25 2-38 JC PC, JC PC, JC, SC, PI, JI PC, JC, SC PC, JC, SC, PI, JI PC, JC PI, JI PC, JC, SC, PI, JI PC, JC, PI, JI Valid Combinations /5 /4 /5 Valid Combinations lists configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Blank, /4 PALCE16V8H-5/7/10/15/25, Q-10/15/25 (Com’l) H-10/15/25, Q-20/25 (Ind) AMD specification. The design specification is processed by development software to verify the design and create a programming file (JEDEC). This file, once downloaded to a programmer, configures the device according to the user’s desired function. FUNCTIONAL DESCRIPTION The PALCE16V8 is a universal PAL device. It has eight independently configurable macrocells (MC0–MC7). Each macrocell can be configured as registered output, combinatorial output, combinatorial I/O or dedicated input. The programming matrix implements a programmable AND logic array, which drives a fixed OR logic array. Buffers for device inputs have complementary outputs to provide user-programmable input signal polarity. Pins 1 and 11 serve either as array inputs or as clock (CLK) and output enable (OE), respectively, for all flip-flops. The user is given two design options with the PALCE16V8. First, it can be programmed as a standard PAL device from the PAL16R8 and PAL10H8 series. The PAL programmer manufacturer will supply device codes for the standard PAL device architectures to be used with the PALCE16V8. The programmer will program the PALCE16V8 in the corresponding architecture. This allows the user to use existing standard PAL device JEDEC files without making any changes to them. Alternatively, the device can be programmed as a PALCE16V8. Here the user must use the PALCE16V8 device code. This option allows full utilization of the macrocell. Unused input pins should be tied directly to VCC or GND. Product terms with all bits unprogrammed (disconnected) assume the logical HIGH state and product terms with both true and complement of any input signal connected assume a logical LOW state. The programmable functions on the PALCE16V8 are automatically configured from the user’s design OE 11 VCC 0X 10 To Adjacent Macrocell 11 10 00 01 SL0 X SG1 11 0X D SL1X CLK I/OX 10 Q Q 10 11 0X * SG1 *In macrocells MC0 and MC7, SG1 is replaced by SG0 on the feedback multiplexer. SL0X From Adjacent Pin 16493D-4 PALCE16V8 Macrocell PALCE16V8 Family 2-39 AMD Configuration Options Each macrocell can be configured as one of the following: registered output, combinatorial output, combinatorial I/O, or dedicated input. In the registered output configuration, the output buffer is enabled by the OE pin. In the combinatorial configuration, the buffer is either controlled by a product term or always enabled. In the dedicated input configuration, it is always disabled. With the exception of MC0 and MC7, a macrocell configured as a dedicated input derives the input signal from an adjacent I/O. MC0 derives its input from pin 11 (OE) and MC7 from pin 1 (CLK). The macrocell configurations are controlled by the configuration control word. It contains 2 global bits (SG0 and SG1) and 16 local bits (SL00 through SL07 and SL10 through SL17). SG0 determines whether registers will be allowed. SG1 determines whether the PALCE16V8 will emulate a PAL16R8 family or a PAL10H8 family device. Within each macrocell, SL0x, in conjunction with SG1, selects the configuration of the macrocell, and SL1x sets the output as either active low or active high for the individual macrocell. The configuration bits work by acting as control inputs for the multiplexers in the macrocell. There are four multiplexers: a product term input, an enable select, an output select, and a feedback select multiplexer. SG1 and SL0x are the control signals for all four multiplexers. In MC0 and MC7, SG0 replaces SG1 on the feedback multiplexer. This accommodates CLK being the adjacent pin for MC7 and OE the adjacent pin for MC0. use the feedback path of MC7 and pin 11 will use the feedback path of MC0. Combinatorial I/O in a Non-Registered Device The control bit settings are SG0 = 1, SG1 = 1, and SL0x = 1. Only seven product terms are available to the OR gate. The eighth product term is used to enable the output buffer. The signal at the I/O pin is fed back to the AND array via the feedback multiplexer. This allows the pin to be used as an input. Because CLK and OE are not used in a non-registered device, pins 1 and 11 are available as inputs. Pin 1 will use the feedback path of MC7 and pin 11 will use the feedback path of MC0. Combinatorial I/O in a Registered Device The control bit settings are SG0 = 0, SG1 = 1 and SL0x = 1. Only seven product terms are available to the OR gate. The eighth product term is used as the output enable. The feedback signal is the corresponding I/O signal. Dedicated Input Configuration The control bit settings are SG0 = 1, SG1 = 0 and SL0x = 1. The output buffer is disabled. Except for MC0 and MC7 the feedback signal is an adjacent I/O. For MC0 and MC7 the feedback signals are pins 1 and 11. These configurations are summarized in Table 1 and illustrated in Figure 2. Table 1. Macrocell Configuration Registered Output Configuration The control bit settings are SG0 = 0, SG1 = 1 and SL0x = 0. There is only one registered configuration. All eight product terms are available as inputs to the OR gate. Data polarity is determined by SL1x. The flip-flop is loaded on the LOW-to-HIGH transition of CLK. The feedback path is from Q on the register. The output buffer is enabled by OE. Combinatorial Configurations The PALCE16V8 has three combinatorial output configurations: dedicated output in a non-registered device, I/O in a non-registered device and I/O in a registered device. Dedicated Output in a Non-Registered Device The control bit settings are SG0 = 1, SG1 = 0 and SL0x = 0. All eight product terms are available to the OR gate. Although the macrocell is a dedicated output, the feedback is used, with the exception of pins 15 and 16. Pins 15 and 16 do not use feedback in this mode. Because CLK and OE are not used in a non-registered device, pins 1 and 11 are available as input signals. Pin 1 will 2-40 SG0 SG1 SL0X Cell Configuration Devices Emulated Device Uses Registers 0 1 0 Registered Output PAL16R8, 16R6, 16R4 0 1 1 Combinatorial I/O PAL16R6, 16R4 Device Uses No Registers 1 0 0 Combinatorial PAL10H8, 12H6, Output 14H4, 16H2, 10L8, 12L6, 14L4, 16L2 1 0 1 Input PAL12H6, 14H4, 16H2, 12L6, 14L4, 16L2 1 1 1 Combinatorial I/O PAL16L8 Programmable Output Polarity The polarity of each macrocell can be active-high or active-low, either to match output signal needs or to reduce product terms. Programmable polarity allows Boolean expressions to be written in their most compact form (true or inverted), and the output can still be of the desired polarity. It can also save “DeMorganizing” efforts. Selection is through a programmable bit SL1x which controls an exclusive-OR gate at the output of the AND/ OR logic. The output is active high if SL1x is 1 and active low if SL1x is 0. PALCE16V8 Family AMD OE OE D CLK Q D Q Q CLK Registered Active Low Q Registered Active High Combinatorial I/O Active Low Combinatorial I/O Active High VCC VCC Note 1 Combinatorial Output Active Low Note 1 Combinatorial Output Active High Notes: 1. Feedback is not available on pins 15 and 16 in the combinatorial output mode. Adjacent I/O pin 2. This configuration is not available on pins 15 and 16. Note 2 Dedicated Input 16493D-5 Figure 2. Macrocell Configurations PALCE16V8 Family 2-41 AMD Power-Up Reset Programming and Erasing All flip-flops power up to a logic LOW for predictable system initialization. Outputs of the PALCE16V8 will depend on whether they are selected as registered or combinatorial. If registered is selected, the output will be HIGH. If combinatorial is selected, the output will be a function of the logic. The PALCE16V8 can be programmed on standard logic programmers. It also may be erased to reset a previously configured device back to its virgin state. Erasure is automatically performed by the programming hardware. No special erase operation is required. Register Preload The register on the PALCE16V8 can be preloaded from the output pins to facilitate functional testing of complex state machine designs. This feature allows direct loading of arbitrary states, making it unnecessary to cycle through long test vector sequences to reach a desired state. In addition, transitions from illegal states can be verified by loading illegal states and observing proper recovery. Security Bit A security bit is provided on the PALCE16V8 as a deterrent to unauthorized copying of the array configuration patterns. Once programmed, this bit defeats readback and verification of the programmed pattern by a device programmer, securing proprietary designs from competitors. The bit can only be erased in conjunction with the array during an erase cycle. Electronic Signature Word An electronic signature word is provided in the PALCE16V8 device. It consists of 64 bits of programmable memory that can contain user-defined data. The signature data is always available to the user independent of the security bit. 2-42 Quality and Testability The PALCE16V8 offers a very high level of built-in quality. The erasability of the device provides a direct means of verifying performance of all AC and DC parameters. In addition, this verifies complete programmability and functionality of the device to provide the highest programming yields and post-programming functional yields in the industry. Technology The high-speed PALCE16V8 is fabricated with AMD’s advanced electrically erasable (EE) CMOS process. The array connections are formed with proven EE cells. Inputs and outputs are designed to be compatible with TTL devices. This technology provides strong input clamp diodes, output slew-rate control, and a grounded substrate for clean switching. PCI Compliance The PALCE22V10H-7/10 is fully compliant with the PCI Local Bus Specification published by the PCI Special Interest Group. The PALCE22V10H-7/10’s predictable timing ensures compliance with the PCI AC specifications independent of the design. PALCE16V8 Family AMD LOGIC DIAGRAM 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 CLK/I 0 1 11 VCC 0X 10 20 V CC 11 10 00 01 SL0 7 0 SG1 11 0X D 7 Q 19 I/O7 10 Q SL1 7 10 11 0X I1 2 SG0 11 VCC 0X 10 SL0 7 11 10 00 01 SL0 6 8 SG1 11 0X D 15 Q 18 I/O6 10 Q SL16 10 11 0X I2 3 SG1 11 VCC 0X 10 SL0 6 11 10 00 01 SL0 5 16 SG1 11 0X D 23 Q 17 I/O5 10 Q SL1 5 10 11 0X I3 4 SG1 11 VCC 0X 10 SL0 5 11 10 00 01 SL0 4 24 SG1 11 0X D Q 16 I/O4 10 Q 31 SL1 4 10 11 0X I4 5 SG1 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 SL0 4 CLK OE 16493D-6 PALCE16V8 Family 2-43 AMD LOGIC DIAGRAM (continued) 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 CLK OE 11 VCC 0X 10 11 10 00 01 SL0 3 32 SG1 11 0X D 39 Q 15 I/O 3 10 Q SL1 3 10 11 0X I5 6 SG1 11 VCC 0X 10 SL0 3 11 10 00 01 SL0 2 40 SG1 11 0X D 47 I6 Q 14 I/O 2 10 Q SL1 2 10 11 0X 7 SG1 11 VCC 0X 10 SL0 2 11 10 00 01 SL0 1 48 SG1 11 0X D 55 Q 13 I/O1 10 Q SL1 1 10 11 0X I7 8 SG1 11 VCC 0X 10 SL0 1 11 10 00 01 SL0 0 56 SG1 11 0X D 63 SL1 0 Q 12 I/O 0 10 Q 10 11 0X I8 9 SG0 SL00 11 OE/I 9 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 GND 10 16493D-6 (concluded) 2-44 PALCE16V8 Family AMD ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . –65°C to +150°C Commercial (C) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . –55°C to +125°C Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . . . . . . . . . 0°C to +75°C Supply Voltage with Respect to Ground . . . . . . . . . . . . . –0.5 V to +7.0 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . . +4.75 V to +5.25 V DC Input Voltage . . . . . . . . . . . –0.5 V to VCC + 0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = 0°C to 75°C) . . . . . . . . . . . . . . . . . . . . . 100 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions VOH Output HIGH Voltage IOH = –3.2 mA VCC = Min VIN = VIH or VIL VOL Output LOW Voltage IOL = 24 mA VCC = Min VIN = VIH or VIL VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) 0.8 V IIH Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 2) 10 µA IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 2) –100 µA IOZH Off-State Output Leakage Current HIGH VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) 10 µA IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) –100 µA ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –150 mA Supply Current Outputs Open (IOUT = 0 mA), VIN = 0 V VCC = Max 125 mA ICC (Static) Min Max Unit 2.4 V 0.5 V 2.0 –30 V Notes: 1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. PALCE16V8H-5 (Com’l) 2-45 AMD CAPACITANCE (Note 1) Parameter Symbol CIN COUT Parameter Descriptions Test Conditions Input Capacitance VIN = 2.0 V Output Capacitance VOUT = 2.0 V Typ Unit VCC = 5.0 V, TA = 25°C, 5 pF f = 1 MHz 8 pF Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter Symbol Parameter Description Min (Note 5) Max Unit 5 ns tPD Input or Feedback to Combinatorial Output 1 tS Setup Time from Input or Feedback to Clock 3 ns tH Hold Time 0 ns Clock to Output 1 tCO tSKEWR Skew Between Registered Outputs (Note 4) tWL tWH fMAX Clock Width Maximum Frequency (Note 3) 4 ns 1 ns LOW 3 ns HIGH 3 ns 142.8 MHz External Feedback 1/(tS+tCO) Internal Feedback (fCNT), 1/(tS+tCF) (Note 6) 166 MHz No Feedback 1/(tWH+tWL) 166 MHz tPZX OE to Output Enable 1 6 ns tPXZ OE to Output Disable 1 5 ns tEA Input to Output Enable Using Product Term Control 2 6 ns tER Input to Output Disable Using Product Term Control 2 5 ns Notes: 2. See Switching Test Circuit for test conditions. 3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 4. Skew testing takes into account pattern and switching direction differences between outputs that have equal loading. 5. Output delay minimums for tPD, tCO, tPZX, tPXZ, tEA, and tER are defined under best case conditions. Future process improvements may alter these values therefore, minimum values are recommended for simulation purposes only. 6. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) – tS. 2-46 PALCE16V8H-5 (Com’l) AMD ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . –65°C to +150°C Commercial (C) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . –55°C to +125°C Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . 0°C to +75°C Supply Voltage with Respect to Ground . . . . . . . . . . . . . . . . . . . . –0.5 V to + 7.0 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . +4.75 V to +5.25 V DC Input Voltage . . . . . . . . . . . –0.5 V to VCC + 1.0 V DC Output or I/O Pin Voltage . . . . . . . . . . . . . . . –0.5 V to VCC + 1.0 V Operating Ranges define those limits between which the functionality of the device is guaranteed. Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = 0°C to +75°C) . . . . . . . . . . . . . . . . . . . . 100 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min VOH Output HIGH Voltage IOH = –3.2 mA VCC = Min VIN = VIH or VIL VOL Output LOW Voltage IOL = 24 mA VCC = Min VIN = VIH or VIL VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) 0.8 V IIH Input HIGH Leakage Current VIN = 5.5 V, VCC = Max (Note 2) 10 µA IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 2) IOZH Off-State Output Leakage Current HIGH VOUT = 5.5 V, VCC = Max, VIN = VIL or VIH (Note 2) IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max VIN = VIL or VIH (Note 2) ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) Supply Current Outputs Open, (IOUT = 0 mA), VCC = Max, f = 25 MHz ICC (Dynamic) Max 2.4 V 0.5 2.0 –30 Unit V V –100 µA 10 µA –100 µA –150 mA 115 mA Notes: 1. These are absolute values with respect to the device ground and all overshoots due to system and tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be tested at a time. Duration of the short-circuit test should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. PALCE16V8H-7 (Com’l) 2-47 AMD CAPACITANCE (Note 1) Parameter Symbol CIN COUT Parameter Descriptions Test Conditions Input Capacitance VIN = 2.0 V Output Capacitance VOUT = 2.0 V Typ Unit VCC = 5.0 V, TA = 25°C, 5 pF f = 1 MHz 8 pF Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter Symbol Parameter Description Min (Note 5) Max Unit 3 3 7.5 7 ns ns tPD Input or Feedback to Combinatorial Output tS Setup Time from Input or Feedback 5 ns tH Hold Time 0 ns Clock to Output 1 tCO tSKEWR tWL tWH fMAX 8 Outputs Switching 1 Output Switching Skew Between Registered Outputs (Note 4) Clock Width Maximum Frequency (Note 3) 5 ns 1 ns LOW 4 ns HIGH 4 ns 1/(tS + tCO) 100 MHz Internal Feedback (fCNT) 1/(tS + tCF) (Note 6) 125 MHz No Feedback 1/(tWH + tWL) 125 MHz External Feedback tPZX OE to Output Enable 1 6 ns tPXA OE to Output Disable 1 6 ns tEA Input to Output Enable Using Product Term Control 3 9 ns tER Input to Output Disable Using Product Term Control 3 9 ns Notes: 2. See Switching Test Circuit for test conditions. 3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 4. Skew testing takes into account pattern and switching direction differences between outputs that have equal loading. 5. Output delay minimums for tPD, tCO, tPZX, tPXZ, tEA, and tER are defined under best case conditions. Future process improvements may alter these values therefore, minimum values are recommended for simulation purposes only. 6. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) – tS. 2-48 PALCE16V8H-7 (Com’l) AMD ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . –65°C to +150°C Commercial (C) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . –55°C to +125°C Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . . . . . . . . . 0°C to +75°C Supply Voltage with Respect to Ground . . . . . . . . . . . . –0.5 V to + 7.0 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . . +4.75 V to +5.25 V DC Input Voltage . . . . . . . . . . . –0.5 V to VCC + 0.5 V Industrial (I) Devices DC Output or I/O Pin Voltage . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . . . . +4.5 V to +5.5 V Latchup Current (TA = –40°C to +85°C) . . . . . . . . . . . . . . . . . . 100 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. Operating ranges define those limits between which the functionality of the device is guaranteed. DC CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges Parameter Symbol Parameter Description Test Conditions Min VOH Output HIGH Voltage IOH = –3.2 mA VCC = Min VIN = VIH or VIL VOL Output LOW Voltage IOL = 24 mA VCC = Min VIN = VIH or VIL VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) 0.8 V IIH Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 2) 10 µA IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 2) –100 µA IOZH Off-State Output Leakage Current HIGH VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) 10 µA IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) –100 µA ISC Output Short-Circuit Current VOUT = 0.5 V –150 mA ICC (Dynamic) Commercial Supply Current Outputs Open (IOUT = 0 mA) VCC = Max, f = 15 MHz 115 mA 130 mA VCC = Max (Note 3) Industrial Supply Current Max Unit 2.4 V 0.5 V 2.0 –30 V Notes: 1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. PALCE16V8H-10 (Com’l, Ind) 2-49 AMD CAPACITANCE (Note 1) Parameter Symbol CIN COUT Parameter Descriptions Test Conditions Typ Unit Input Capacitance VIN = 2.0 V VCC = 5.0 V, TA = 25°C, 5 pF Output Capacitance VOUT = 2.0 V f = 1 MHz 8 pF Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges (Note 2) Parameter Symbol Parameter Description tPD Input or Feedback to Combinatorial Output tS Setup Time from Input or Feedback to Clock tH tCO fMAX Max Unit 3 10 ns 7.5 ns Hold Time 0 ns Clock to Output 3 tWL tWH Min (Note 4) Clock Width Maximum Frequency (Note 3) 7.5 ns LOW 6 ns HIGH 6 ns External Feedback 1/(tS + tCO) 66.7 MHz Internal Feedback (fCNT) 1/(tS + tCF) (Note 5) 71.4 MHz No Feedback 1/(tWH + tWL) 83.3 MHz tPZX OE to Output Enable 2 10 ns tPXZ OE to Output Disable 2 10 ns tEA Input to Output Enable Using Product Term Control 3 10 ns tER Input to Output Disable Using Product Term Control 3 10 ns Notes: 2. See Switching Test Circuit for test conditions. 3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 4. Output delay minimums for tPD, tCO, tPZX, tPXZ, tEA, and tER are defined under best case conditions. Future process improvements may alter these values therefore, minimum values are recommended for simulation purposes only. 5. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) – tS. 2-50 PALCE16V8H-10 (Com’l, Ind) AMD ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . –65°C to +150°C Commercial (C) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . –55°C to +125°C Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . . . . . . . . . 0°C to +75°C Supply Voltage with Respect to Ground . . . . . . . . . . . . . –0.5 V to +7.0 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . . +4.75 V to +5.25 V DC Input Voltage . . . . . . . . . . . –0.5 V to VCC + 0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = 0°C to 75°C) . . . . . . . . . . . . . . . . . . . . . 100 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min Max Unit VOH Output HIGH Voltage IOH = –3.2 mA VCC = Min VIN = VIH or VIL VOL Output LOW Voltage IOL = 24 mA VCC = Min VIN = VIH or VIL VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) 0.8 V IIH Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 2) 10 µA IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 2) –100 µA IOZH Off-State Output Leakage Current HIGH VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) 10 µA IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) –100 µA ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –150 mA ICC Supply Current (Dynamic) Outputs Open (IOUT = 0 mA) VCC = Max, f = 15 MHz 55 mA 2.4 V 0.5 V 2.0 –30 V Notes: 1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. PALCE16V8Q-10 (Com’l) 2-51 AMD CAPACITANCE (Note 1) Parameter Symbol CIN COUT Parameter Descriptions Test Conditions Input Capacitance VIN = 2.0 V Output Capacitance VOUT = 2.0 V Typ Unit VCC = 5.0 V, TA = 25°C, 5 pF f = 1 MHz 8 pF Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter Symbol Parameter Description tPD Input or Feedback to Combinatorial Output tS Setup Time from Input or Feedback to Clock tH tCO fMAX Max Unit 3 10 ns 7.5 ns Hold Time 0 ns Clock to Output 3 tWL tWH Min (Note 4) Clock Width Maximum Frequency (Note 3) 7.5 ns LOW 6 ns HIGH 6 ns External Feedback 1/(tS + tCO) 66.7 MHz Internal Feedback (fCNT) 1/(tS + tCF) (Note 5) 71.4 MHz No Feedback 1/(tWH + tWL) 83.3 MHz tPZX OE to Output Enable 2 10 ns tPXZ OE to Output Disable 2 10 ns tEA Input to Output Enable Using Product Term Control 3 10 ns tER Input to Output Disable Using Product Term Control 3 10 ns Notes: 2. See Switching Test Circuit for test conditions. 3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 4. Output delay minimums for tPD, tCO, tPZX, tPXZ, tEA, and tER are defined under best case conditions. Future process improvements may alter these values therefore, minimum values are recommended for simulation purposes only. 5. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) – tS. 2-52 PALCE16V8Q-10 (Com’l) AMD ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . –65°C to +150°C Commercial (C) Devices Ambient Temperature with Power Applied . . . . . . . . . . . . . –55°C to +125°C Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . . . . . . . . . 0°C to +75°C Supply Voltage with Respect to Ground . . . . . . . . . . . . –0.5 V to + 7.0 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . . +4.75 V to +5.25 V DC Input Voltage . . . . . . . . . . . –0.5 V to VCC + 0.5 V Industrial (I) Devices DC Output or I/O Pin Voltage . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Temperature (TA) Operating in Free Air . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . . . . +4.5 V to +5.5 V Latchup Current (TA = –40°C to +85°C) . . . . . . . . . . . . . . . . . . 100 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. Operating ranges define those limits between which the functionality of the device is guaranteed. DC CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges Parameter Symbol Parameter Description Test Conditions Min Max Unit VOH Output HIGH Voltage IOH = –3.2 mA VCC = Min VIN = VIH or VIL VOL Output LOW Voltage IOL = 24 mA VCC = Min VIN = VIH or VIL VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) 0.8 V IIH Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 2) 10 µA IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 2) –100 µA IOZH Off-State Output Leakage Current HIGH VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) 10 µA IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) –100 µA ISC Output Short-Circuit Current VOUT = 0.5 V, VCC = Max (Note 3) –150 mA ICC (Dynamic) Commercial Supply Current Outputs Open (IOUT = 0 mA) VCC = Max, f = 15 MHz H Q 90 55 mA ICC (Dynamic) Industrial Supply Current Outputs Open (IOUT = 0 mA) VCC = Max, f = 15 MHz H Q 130 65 mA 2.4 V 0.5 V 2.0 –30 V Notes: 1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. PALCE16V8H-15/25, Q-15/25 (Com’l, Ind), Q-20 (Ind) 2-53 AMD CAPACITANCE (Note 1) Parameter Symbol CIN COUT Parameter Descriptions Test Conditions Typ Unit Input Capacitance VIN = 2.0 V VCC = 5.0 V, TA = 25°C, 5 pF Output Capacitance VOUT = 2.0 V f = 1 MHz 8 pF Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges (Note 2) Parameter Symbol -15 Parameter Description Min Max -20 -25 Min Max Min Max Unit tPD Input or Feedback to Combinatorial Output tS Setup Time from Input or Feedback to Clock 12 13 15 ns tH Hold Time 0 0 0 ns tCO tWL 15 Clock to Output Clock Width tWH 20 10 25 11 12 ns ns LOW 8 10 12 ns HIGH 8 10 12 ns External Feedback 1/(tS + tCO) 45.5 41.6 37 MHz Internal Feedback (fCNT) 1/(tS + tCO) (Note 4) 50 45.4 40 MHz No Feedback 1/(tWH + tWL) fMAX Maximum Frequency (Note 3) tPZX OE to Output Enable 15 18 20 ns tPXZ OE to Output Disable 15 18 20 ns tEA Input to Output Enable Using Product Term Control 15 18 20 ns tER Input to Output Disable Using Product Term Control 15 18 20 ns 62.5 50.0 41.6 MHz Notes: 2. See Switching Test Circuit for test conditions. 3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 4. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation: tCF = 1/fMAX (internal feedback) – tS. 2-54 PALCE16V8H-15/25, Q-15/25 (Com’l, Ind), Q-20 (Ind) AMD SWITCHING WAVEFORMS Input or Feedback Input or Feedback VT VT tS tH tPD VT Combinatorial Output VT Clock 16493D-7 tCO Registered Output VT 16493D-8 Combinatorial Output Registered Output VT Input tWH tER Clock VT tEA VOH - 0.5V Output VOL + 0.5V tWL 16493D-9 VT 16493D-10 Clock Width Input to Output Disable/Enable VT OE tPXZ Output tPZX VOH - 0.5V VT VOL + 0.5V 16493D-11 OE to Output Disable/Enable Notes: 1. VT = 1.5 V 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns – 5 ns typical. PALCE16V8 Family 2-55 AMD KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Must be Steady Will be Steady May Change from H to L Will be Changing from H to L May Change from L to H Will be Changing from L to H Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is HighImpedance “Off” State KS000010-PAL SWITCHING TEST CIRCUIT 5V S1 R1 Output Test Point R2 CL 16493D-12 Commercial Specification tPD, tCO tEA tER S1 CL R1 Closed Measured Output Value 1.5 V Z → H: Open Z → L: Closed 50 pF H → Z: Open 5 pF 200 Ω L → Z: Closed 2-56 R2 PALCE16V8 Family 390 Ω 1.5 V H-5: H → Z: VOH – 0.5 V 200 Ω L → Z: VOL + 0.5 V AMD TYPICAL ICC CHARACTERISTICS VCC = 5 V, TA = 25°C 150 16V8H-5 125 100 16V8H-7 ICC (mA) 75 16V8H-10 16V8H-15/25 50 16V8Q-10/15/25 25 0 0 10 20 30 Frequency (MHz) 40 50 16493D-13 ICC vs. Frequency The selected “typical” pattern utilized 50% of the device resources. Half of the macrocells were programmed as registered, and the other half were programmed as combinatorial. Half of the available product terms were used for each macrocell. On any vector, half of the outputs were switching. By utilizing 50% of the device, a midpoint is defined for ICC. From this midpoint, a designer may scale the ICC graphs up or down to estimate the ICC requirements for a particular design. PALCE16V8 Family 2-57 AMD ENDURANCE CHARACTERISTICS The PALCE16V8 is manufactured using AMD’s advanced Electrically Erasable process. This technology uses an EE cell to replace the fuse link used in bipolar Symbol tDR N 2-58 parts. As a result, the device can be erased and reprogrammed—a feature which allows 100% testing at the factory. Parameter Test Conditions Min Pattern Data Retention Time Max Storage Temperature Min Reprogramming Cycles Min Unit 10 Years Max Operating Temperature 20 Years Normal Programming Conditions 100 Cycles PALCE16V8 Family AMD clocking caused by subsequent ringing. A special noise filter makes the programming circuitry completely insensitive to any positive overshoot that has a pulse width of less than about 100 ns for the /5 versions. Selected /4 devices are also being retrofitted with these robustness features. See chart below for device listings. ROBUSTNESS FEATURES PALCE16V8X-X/5 devices have some unique features that make them extremely robust, especially when operating in high-speed design environments. Pull-up resistors on inputs and I/O pins cause unconnected pins to default to a known state. Input clamping circuitry limits negative overshoot, eliminating the possibility of false INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR /5 VERSIONS AND SELECTED /4 VERSIONS* VCC VCC > 50 kΩ ESD Protection and Clamping Programming Pins only Programming Voltage Detection Positive Overshoot Filter Programming Circuitry Typical Input VCC VCC > 50 kΩ Provides ESD Protection and Clamping Preload Circuitry Typical Output Feedback Input 16493D-14 * Rev Letter Topside Marking: Filter Only Filter and Pullups AMD CMOS PLD’s are marked on the top of the package in the PALCE16V8H-10 E, F, K L following manner: PALCE16V8H-15 D, E, F, G, I, J, K L, M PALCEXXXX Date Code (3 numbers) Lot ID (4 characters)– –(Rev. Letter) PALCE16V8Q-15 D, G, J M The Lot ID and Rev Letter are separated by two spaces. PALCE16V8H-25 D, G, J M Device PALCE16V8Q-25 D, G, J M PALCE16V8 Family 2-59 AMD POWER-UP RESET The PALCE16V8 has been designed with the capability to reset during system power-up. Following power-up, all flip-flops will be reset to LOW. The output state will be HIGH independent of the logic polarity. This feature provides extra flexibility to the designer and is especially valuable in simplifying state machine initialization. A timing diagram and parameter table are shown below. Due to the synchronous operation of the power-up reset Parameter Symbol and the wide range of ways VCC can rise to its steady state, two conditions are required to insure a valid power-up reset. These conditions are: The VCC rise must be monotonic. Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met. Parameter Descriptions Min tPR Power-Up Reset Time tS Input or Feedback Setup Time Max Unit 1000 ns See Switching Characteristics Clock Width LOW tWL VCC 4V Power tPR Registered Output tS Clock tWL 16493D-15 Power-Up Reset Waveform 2-60 PALCE16V8 Family AMD TYPICAL THERMAL CHARACTERISTICS /4 Devices (PALCE16V8H-10/4) Measured at 25°C ambient. These parameters are not tested. Parameter Symbol Typ PDIP PLCC Unit θjc Parameter Description Thermal Impedance, Junction to Case 25 22 °C/W θja Thermal Impedance, Junction to Ambient 71 64 °C/W θjma Thermal Impedance, Junction to Ambient with Air Flow 200 Ifpm air 61 55 °C/W 400 Ifpm air 55 51 °C/W 600 Ifpm air 51 47 °C/W 800 Ifpm air 47 45 °C/W PLCC Unit °C/W /5 Devices (PALCE16V8H-7/5) Measured at 25°C ambient. These parameters are not tested. Parameter Symbol Typ Parameter Description PDIP θjc Thermal Impedance, Junction to Case 29 23 θja Thermal Impedance, Junction to Ambient 70 61 °C/W θjma Thermal Impedance, Junction to Ambient with Air Flow 200 Ifpm air 64 53 °C/W 400 Ifpm air 58 47 °C/W 600 Ifpm air 53 44 °C/W 800 Ifpm air X X °C/W Plastic θjc Considerations The data listed for plastic θjc are for reference only and are not recommended for use in calculating junction temperatures. The heat-flow paths in plastic-encapsulated devices are complex, making the θjc measurement relative to a specific location on the package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package. Furthermore, θjc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar environment. PALCE16V8 Family 2-61