AD AD5203AR10 4-channel, 64-position digital potentiometer Datasheet

a
FEATURES
64 Position
Replaces Four Potentiometers
10 k⍀, 100 k⍀
Power Shutdown—Less than 5 ␮A
3-Wire SPI-Compatible Serial Data Input
10 MHz Update Data Loading Rate
+2.7 V to +5.5 V Single Supply Operation
Midscale Preset
4-Channel, 64-Position
Digital Potentiometer
AD5203
FUNCTIONAL BLOCK DIAGRAM
DAC 1
AD5203
6-BIT
LATCH 6
VDD
CK RS
DGND
1
DAC 2
SELECT
3
APPLICATIONS
Mechanical Potentiometer Replacement
Programmable Filters, Delays, Time Constants
Volume Control, Panning
Line Impedance Matching
Power Supply Adjustment
DAC 2
6-BIT 6
LATCH
4
CK RS
A1, A0
8-BIT
SERIAL
LATCH
DAC 3
6-BIT
LATCH 6
6
D
CK RS
CK Q RS
The AD5203 provides a quad channel, 64-position digitallycontrolled variable resistor (VR) device. These parts perform the
same electronic adjustment function as a potentiometer or variable resistor. The AD5203 contains four independent variable
resistors in a 24-lead SOIC and the compact TSSOP-24 packages. Each part contains a fixed resistor with a wiper contact
that taps the fixed resistor value at a point determined by a digital code loaded into the controlling serial input register. The
resistance between the wiper and either endpoint of the fixed
resistor varies linearly with respect to the digital code transferred
into the VR latch. Each variable resistor offers a completely
programmable value of resistance, between the A terminal and
the wiper or the B terminal and the wiper. The fixed A-to-B
terminal resistance of 10 kΩ, or 100 kΩ has a ± 1% channel-tochannel matching tolerance with a nominal temperature coefficient of 700 ppm/°C.
Each VR has its own VR latch which holds its programmed
resistance value. These VR latches are updated from an internal
serial-to-parallel shift register that is loaded from a standard
3-wire serial-input digital interface. Eight data bits make up the
data word clocked into the serial input register. The data word is
decoded where the first two bits determine the address of the VR
latch to be loaded, the last 6-bits are data. A serial data output
pin at the opposite end of the serial register allows simple daisychaining in multiple VR applications without additional external
decoding logic.
SHDN
A2
W2
B2
AGND2
2
SDI
GENERAL DESCRIPTION
SHDN
A1
W1
B1
AGND1
SHDN
CLK
DAC 4
CS
6-BIT
LATCH
CK RS
SDO
RS
6
SHDN
A3
W3
B3
AGND3
A4
W4
B4
AGND4
SHDN
The reset RS pin forces the wiper to the midscale position by
loading 20H into the VR latch. The SHDN pin forces the resistor to an end-to-end open circuit condition on terminal A and
shorts the wiper to terminal B, achieving a microwatt power
shutdown state. When shutdown is returned to logic-high the
previous latch settings put the wiper in the same resistance setting prior to shutdown.
The AD5203 is available in a narrow body P-DIP-24, the
24-lead surface mount package, and the compact 1.1 mm thin
TSSOP-24 package. All parts are guaranteed to operate over the
extended industrial temperature range of –40°C to +85°C.
For pin compatible higher resolution applications, see the 256position AD8403 product.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998
AD5203–SPECIFICATIONS(V = +3 V ⴞ 10% or +5 V ⴞ 10%, V = +V , V = 0 V, –40ⴗC < T < +85ⴗC unless
DD
A
ELECTRICAL CHARACTERISTICS otherwise noted)
Parameter
Symbol
DD
Conditions
DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs
Resistor Differential NL 2
R-DNL
RWB , VA = No Connect
R-INL
RWB , VA = No Connect
Resistor Nonlinearity Error2
∆RAB
Nominal Resistor Tolerance 3
VAB = V DD, Wiper = No Connect
Resistance Temperature Coefficient
∆RAB/∆T
IW = 1 V/RAB
Wiper Resistance
RW
Nominal Resistance Match
∆R/RO
CH 1 to CH 2, V AB = VDD , TA = +25°C
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications Apply to All VRs
Resolution
N
DNL
Differential Nonlinearity Error4
INL
Integral Nonlinearity Error4
Code = 20H
Voltage Divider Temperature Coefficient ∆VW/∆T
Code = 3FH
Full-Scale Error
VWFSE
Zero-Scale Error
VWZSE
Code = 00H
RESISTOR TERMINALS
Voltage Range5
Capacitance6 Ax, Bx
Capacitance6 Wx
Shutdown Supply Current7
Shutdown Wiper Resistance
VA, VB, VW
CA, C B
CW
IA_SD
RW_SD
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
Output Logic High
Output Logic Low
Input Current
Input Capacitance6
VIH
VIL
VIH
VIL
VOH
VOL
IIL
CIL
POWER SUPPLIES
Power Supply Range
Supply Current (CMOS)
Supply Current (TTL)8
Power Dissipation (CMOS)9
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS6, 10
Bandwidth –3 dB
VDD Range
IDD
IDD
PDISS
PSS
PSS
Resistor Noise Voltage
BW_10K
BW_100K
THDW
tS _10K
tS _100K
e NWB
Crosstalk11
CT
Total Harmonic Distortion
VW Settling Time
A
Min
Typ1
Max
Units
–0.25
–0.5
–30
± 0.1
± 0.1
+0.25
+0.5
+30
LSB
LSB
%
ppm/°C
Ω
%
700
45
0.2
6
–0.25
–0.75
–0.75
0
± 0.1
± 0.1
20
–0.2
+0.1
0
f = 1 MHz, Measured to GND, Code = 20H
f = 1 MHz, Measured to GND, Code = 20H
VA = VDD, VB = 0 V, SHDN = 0
VA = VDD, VB = 0 V, SHDN = 0, VDD = +5 V
VDD = +5 V
VDD = +5 V
VDD = +3 V
VDD = +3 V
RL = 2.2 kΩ to VDD
IOL = 1.6 mA, VDD = +5 V
VIN = 0 V or +5 V, VDD = +5 V
100
1
+0.25
+0.75
0
+0.75
VDD
75
120
0.01
45
5
100
2.4
0.8
2.1
0.6
VDD –0.1
0.4
±1
5
2.7
VIH = V DD or VIL = 0 V
VIH = 2.4 V or VIL = 0.8 V, V DD = +5.5 V
VIH = V DD or VIL = 0 V, V DD = +5.5 V
∆VDD = +5 V ± 10%
∆VDD = +3 V ± 10%
0.0002
0.006
RAB = 10 kΩ
RAB = 100 kΩ
VA =1 V rms + 2 V dc, V B = 2 V dc, f = 1 kHz
VA = VDD, VB = 0 V, ±1 LSB Error Band
VA = VDD, VB = 0 V, ±1 LSB Error Band
RWB = 5 kΩ, f = 1 kHz, RS = 0
RWB = 50 kΩ, f = 1 kHz, RS = 0
VA = VDD, VB = 0 V
600
71
0.003
2
18
9
29
–65
INTERFACE TIMING CHARACTERISTICS Applies to All Parts 6, 12
Input Clock Pulsewidth
tCH , tCL
Clock Level High or Low
Data Setup Time
tDS
Data Hold Time
tDH
tPD
RL = 2.2 kΩ, CL < 20 pF
CLK to SDO Propagation Delay13
CS Setup Time
tCSS
CS High Pulsewidth
tCSW
Reset Pulsewidth
tRS
CLK Fall to CS Rise Hold Time
tCSH
CS Rise to Clock Rise Setup
B
tCS1
0.01
0.9
10
5
5
1
10
10
50
0
10
–2–
5.5
5
4
27.5
0.001
0.03
Bits
LSB
LSB
ppm/°C
LSB
LSB
V
pF
pF
µA
Ω
V
V
V
V
V
V
µA
pF
V
µA
mA
µW
%/%
%/%
kHz
kHz
%
µs
µs
nV/√Hz
nV/√Hz
dB
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
REV. 0
AD5203
NOTES
1
Typicals represent average readings at +25°C and VDD = +5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 27 test circuit. I W = VDD/R
for both VDD = +3 V or VDD = +5 V.
3
VAB = V DD, Wiper (VW ) = No connect.
4
INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and V B = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See Figure 26 test circuit.
5
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
Measured at the AX terminals. All AX terminals are open-circuited in shutdown mode.
8
Worst case supply current consumed when all logic-input levels set at 2.4 V, standard characteristic of CMOS logic. See Figure 19 for a plot of I DD vs. logic voltage
inputs result in minimum power dissipation.
9
PDISS is calculated from (I DD × V DD). CMOS logic level inputs result in minimum power dissipation.
10
All dynamic characteristics use V DD = +5 V.
11
Measured at a V W pin where an adjacent V W pin is making a full-scale voltage change.
12
See timing diagrams for location of measured values. All input control voltages are specified with t R = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level
of 1.6 V. Switching characteristics are measured using both V DD = +3 V or +5 V. Input logic should have a 1 V/ µs minimum slew rate.
13
Propagation delay depends on value of V DD, R L and C L. See Operation section.
ABSOLUTE MAXIMUM RATINGS*
1
SDI
(TA = +25°C, unless otherwise noted)
A1 A0 D5 D4 D3 D2 D1 D0
0
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V
VA, VB, V W to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, VDD
IAB, IAW, I BW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Digital Input and Output Voltage to GND . . . . . . . 0 V, +8 V
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Maximum Junction Temperature (TJ MAX) . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
Package Power Dissipation . . . . . . . . . . . . . . (T J max–TA)/θJA
Thermal Resistance θJA
P-DIP (N-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W
SOIC (SOL-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
TSSOP-24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143°C/W
1
CLK
0
DAC REGISTER LOAD
1
CS
0
VOUT
VDD
0V
Figure 1a. Timing Diagram
SDI
(DATA IN)
Ax OR Dx
Ax OR Dx
0
t DS
t DH
1
SDO
(DATA OUT)
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
1
A'x OR D'x
A'x OR D'x
0
t PD
t PD
MIN
t CH
1
MAX
t CS1
CLK
0
t CL
t CSS
t CSH
1
ADDR
B7
B6
DATA
B5
B4
A1
MSB
27
D5
MSB
25
A0
LSB
26
D4
t CSW
CS
Table I. Serial-Data Word Format
0
VOUT
B3
B2
B1
B0
D3
D2
D1
D0
LSB
20
tS
VDD
61 LSB
6 1 LSB ERROR BAND
0V
Figure 1b. Detail Timing Diagram
1
t RS
RS
0
tS
VDD
VOUT
0V
61 LSB
61 LSB ERROR BAND
Figure 1c. Reset Timing Diagram
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD5203 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. 0
–3–
WARNING!
ESD SENSITIVE DEVICE
AD5203
PIN CONFIGURATION
AGND2
1
24
B1
B2
2
23
A1
A2
3
22
W1
W2
4
21
AGND1
AGND4
5
20
B3
B4
6
AD5203
PIN FUNCTION DESCRIPTIONS
(Not to Scale) 19 A3
W3
A4
7
18
W4
8
17
AGND3
DGND
9
16
VDD
SHDN 10
15
RS
CS 11
14
CLK
SDI 12
13
SDO
Pin
No.
Name
Description
1
2
3
4
5
6
7
8
9
10
AGND2
B2
A2
W2
AGND4
B4
A4
W4
DGND
SHDN
11
CS
12
13
SDI
SDO
14
15
CLK
RS
16
VDD
17
18
19
20
21
22
23
24
AGND3
W3
A3
B3
AGND1
W1
A1
B1
Analog Ground #2*
B Terminal RDAC #2
A Terminal RDAC #2
Wiper RDAC #2, addr = 012
Analog Ground #4*
B Terminal RDAC #4
A Terminal RDAC #4
Wiper RDAC #4, addr = 112
Digital Ground*
Active Low Input. Terminal A open circuit.
Shutdown controls Variable Resistors #1
through #4.
Chip Select Input, Active Low. When CS
returns high data in the serial input register
is decoded based on the address bits and
loaded into the target DAC register.
Serial Data Input
Serial Data Output. Open drain transistor
requires pull-up resistor.
Serial Clock Input, positive edge triggered.
Active low reset to midscale; sets RDAC
registers to 20H .
Positive power supply, specified for operation at both +3 V and +5 V.
Analog Ground #3*
Wiper RDAC #3, addr =102
A Terminal RDAC #3
B Terminal RDAC #3
Analog Ground #1*
Wiper RDAC #1, addr = 002
A Terminal RDAC #1
B Terminal RDAC #1
*All AGNDs must be connected to DGND voltage potential.
ORDERING GUIDE
Model
k⍀
Temperature Range
Package Descriptions
Package Options
AD5203AN10
AD5203AR10
AD5203ARU10
AD5203AN100
AD5203AR100
AD5203ARU100
10
10
10
100
100
100
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
24-Lead Narrow Body Plastic DIP
24-Lead Wide Body (SOIC)
24-Lead Thin Surface Mount Package (TSSOP)
24-Lead Narrow Body Plastic DIP
24-Lead Wide Body (SOIC)
24-Lead Thin Surface Mount Package (TSSOP)
N-24
SOL-24
RU-24
N-24
SOL-24
RU-24
–4–
REV. 0
Typical Performance Characteristics– AD5203
10
5
VDD = +3V, OR +5V
RAB = 10kV
6
5
4
3
RWA
8
16
24
32
40 48
CODE – Decimal
56
02H
2
1.5
64
RAB = 10kV
VDD = +5V
TA = +258C
12
NOMINAL RESISTANCE – kV
60
40
20
0
Figure 5.␣ Wiper-Contact-Resistance
Histogram
VDD = +3.0V
TA = +258C, +858C, –408C
0.15
0.1
0.05
0
–0.05
–0.1
–0.15
–0.2
8
16
24
32
40
48
56
DIGITAL INPUT CODE – Decimal
64
Figure 8. Potentiometer Divider
Differential Nonlinearity Error vs.
Code
REV. 0
0
–0.1
6
7
8
6
RWB (WIPER-TO-END)
CODE = 20H
2
16
24 32
40 48
56
8
DIGITAL INPUT CODE – Decimal
64
100 125
VDD = +3.0V
0.2
0.15
0.1
0.05
+258C
0
–0.05
–558C
–0.1
–0.15
+858C
–0.2
–0.25
0
8
16
24
32
40
48
56
DIGITAL INPUT CODE – Decimal
64
␣ ␣ ␣ Figure 7. Potentiometer Divider
␣ ␣ Nonlinearity Error vs. Code
120
50
VDD = +3.0V
TA = –408C/+858C
VA = +2.0V
VB = 0V
40
30
20
10
0
0
0.25
RAB (END-TO-END)
4
TA = +258C
Figure 4. Resistance Step Position
␣ ␣ Nonlinearity Error vs. Code
AD5203-10K VERSION
10
TA = –558C
–0.2
␣ ␣ Figure 6.␣ Nominal Resistance vs.
␣ ␣ Temperature
POTENTIOMETER MODE TEMPCO – ppm/8C
0.25
0
2
3
4
5
IWA CURRENT – mA
TA = +858C
–0.05
–0.25
1
0
0
25
50 75
–75 –50 –25
TEMPERATURE – 8C
30 31 32 33 34 35 36 37 38 39
WIPER RESISTANCE – V
0.2
0
0.1
0.05
–0.15
Figure 3. Resistance Linearity vs.
␣ ␣ Conduction Current
SS = 544 UNITS
VDD = +4.5V
TA = +258C
FREQUENCY
05H
2.5
0
0
80
DNL ERROR – LSB
3
0.5
Figure 2. Wiper to End Terminal
␣ ␣ Resistance vs. Code
–0.25
08H
1
1
0
10H
3.5
INL NONLINEARITY ERROR – LSB
RWB
0.15
RINL ERROR – LSB
VWB VOLTAGE – V
RESISTANCE – kV
7
VDD = +3.0V
0.2
20H
4
8
2
0.25
3FH
4.5
RHEOSTAT MODE TEMPCO – ppm/8C
9
80
60
40
20
0
0
8
16
24
32 40
48
CODE – Decimal
56
64
Figure 9.␣ ∆VWB/ ∆T Potentiometer
Mode Tempco
–5–
VDD = +3.0V
TA = –408C/+858C
VA = NO CONNECT
RWB MEASURED
100
0
8
16
24
32 40
48
CODE – Decimal
56
64
Figure 10. ∆RWB/∆ T Rheostat Mode
Tempco
AD5203–Typical Performance Characteristics
0.75
0
CODE = 3FH
20H
0.5
DRWB RESISTANCE – %
–10
GAIN – dB
10H
RW
(20mV/DIV)
CS
(5V/DIV)
08H
–20
04H
–30
02H
01H
–40
–50
10
Figure 11. One Position Step Change
at Half-Scale (Code 1FH to 20H)
1k
10k
100k
FREQUENCY – Hz
AVG
0
AVG –2 S
–0.25
–0.75
100
AVG +2 S
0.25
–0.5
TA = +258C
SEE TEST CIRCUIT FIGURE 32
TIME 500ns/DIV
VDD = +5V
CODE = 3FH
SS = 77 UNITS
1M
10M
Figure 12. Gain vs. Frequency for
R = 10 kΩ
␣␣␣␣
200
300
400
500
100
HOURS OF OPERATION @ 1508C
0
600
Figure 13. Long-Term Drift
Accelerated by Burn-In
10
FILTER = 22kHz
VDD = +5V
TA = +258C
RAB = 10kV
THD + NOISE – %
1
OUTPUT
CS
VOUT
(20mV/DIV)
0.1
SEE TEST CIRCUIT FIGURE 31
0.01
SEE TEST CIRCUIT FIGURE 30
TIME 100ns/DIV
TIME 5ms/DIV
0.001
10
CODE = 3FH
20H
–10
GAIN – dB
10H
–20
08H
04H
–30
–40
–50
10
02H
VDD = +5V
TA = +258C
5dB/DIV
100
01H
1k
10k
100k
FREQUENCY – Hz
1M
Figure 17. 100 kΩ Gain vs. Frequency
vs. Code
100k
Figure 15.␣ Total Harmonic Distortion
Plus Noise vs. Frequency
NORMALIZED GAIN FLATNESS – 0.1dB/DIV
0
1k
10k
FREQUENCY – Hz
Figure 16. Digital Feedthrough vs.
Time
10
0
RAB = 10kV
–0.1
IDD SUPPLY CURRENT – mA
Figure 14. Large Signal Settling Time
100
–0.2
–0.3
RAB = 100kV
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
–1.0
10
VDD = +5V
CODE = 3FH
TA = +258C
SEE TEST CIRCUIT FIGURE 32
VDD = +5.0V
1
VDD = +3.0V
0.1
0.01
100
1k
10k
100k
FREQUENCY – Hz
1M
Figure 18. Normalized Gain Flatness vs. Frequency
–6–
0
0.5
1 1.5 2 2.5 3 3.5 4 4.5
INPUT LOGIC VOLTAGE – Volts
5
Figure 19. Supply Current vs. Logic
Input Voltage
REV. 0
AD5203
80
1200
0
–5
–10
60
GAIN – dB
40
VDD = +5V DC 61V p-p AC
20 TA = +258C
CODE = 80H
CL = 10pF
VA = 4V, VB = 0V
0
1k
–20
–25
–40
–45
1M
Figure 20. Power Supply Rejection
vs. Frequency
–50
10
VDD = +5V
VIN = 100mV rms
CODE = 20H
TA = +258C
100
1k
10k
FREQUENCY – Hz
100k
Figure 21. –3␣ dB Frequency at
Half-Scale
IA SHUTDOWN CURRENT – nA
80
VDD = +2.7V
60
40
VDD = +5.5V
20
0
1
2
3
4
VDD – Volts
5
6
Figure 23. Incremental Wiper ON
Resistance vs. VDD
REV. 0
TA = +258C
B – VDD = +3.3V
CODE = 15H
C – VDD = +5.5V
CODE = 3FH
D – VDD = +3.3V
CODE = 3FH
400
A
200
B
C
D
10k
100k
1M
FREQUENCY – Hz
10M
1
10
1
–55 –35 –15
600
A – VDD = +5.5V
CODE = 15H
Figure 22. Supply Current vs. Clock
Frequency
VDD = +5V
TA = +258C
800
0
1k
1M
100
100
RON – V
f–3dB = 625kHz,
R = 10kV
–30
–35
10k
100k
FREQUENCY – Hz
f–3dB = 65kHz,
R = 100kV
IDD – SUPPLY CURRENT – mA
PSRR – dB
–15
0
IDD – SUPPLY CURRENT – mA
1000
5 25 45 65 85 105 125
TEMPERATURE – 8C
␣ ␣ ␣ ␣ Figure 24. Shutdown Current vs.
␣ ␣ ␣ ␣ Temperature
–7–
LOGIC INPUT
VOLTAGE = 0, VDD
0.1
0.01
VDD = +5.5V
VDD = +3.3V
0.001
–55 –35 –15 5
25 45 65 85 105 125
TEMPERATURE – 8C
Figure 25. Supply Current vs.
Temperature
AD5203–Parametric Test Circuits
V+ = VDD
1LSB = V+/64
DUT
A
W
V+
VIN
A
DUT B
~
W
+5V
OP279
B
OFFSET
GND
VMS
Figure 26. Potentiometer Divider Nonlinearity Error Test
Circuit (INL, DNL)
VOUT
2.5V DC
Figure 30. Inverting Programmable Gain Test Circuit
+5V
NO CONNECT
DUT
A
W
IW
VIN
OFFSET
GND
B
2.5V
VMS
Figure 27. Resistor Position Nonlinearity Error (Rheostat
Operation; R-INL, R-DNL)
IMS
DUT
A
W
V+
VW
VIN
B
PSRR (dB) = 20 LOG
W
VMS
DVMS%
PSS (%/%) = –––––––
DVDD%
+15V
DUT
B
2.5V
OP42
VOUT
–15V
␣ Figure 32. Gain vs. Frequency Test Circuit
RSW = 0.1V
ISW
DUT
V+ = VDD ± 10%
A
B
W
~
OFFSET
GND
VA
~
DUT
A
VW2 – [VW1 + I W (RAW II R BW)]
RW = ––––––––––––––––––––––––––
IW
Figure 28.␣ Wiper Resistance Test Circuit
V+
A
VOUT
OP279
␣ Figure 31. Noninverting Programmable Gain Test Circuit
WHERE VW1 = VMS WHEN I W = 0
AND VW2 = VMS WHEN IW = 1/R
VMS
VDD
W
V+ < VDD
IW = 1V/RNOMINAL
B
␣␣
~
DV
CODE = ØØH
W
MS
( –––––
)
DV
B
DD
ISW
0.1V
0 TO VDD
Figure 29. Power Supply Sensitivity Test Circuit (PSS,
PSRR)
Figure 33. Incremental ON Resistance Test Circuit
–8–
REV. 0
AD5203
tap point located at 201 Ω [= RBA(nominal resistance)/64 + RW
= 156 Ω + 45 Ω)] for data 01 H. The third connection is the next
tap point representing 312 + 45 = 357 Ω for data 02H. Each
LSB data value increase moves the wiper up the resistor ladder
until the last tap point is reached at 9889 Ω. The wiper does not
directly connect to the B Terminal. See Figure 34 for a simplified diagram of the equivalent RDAC circuit.
OPERATION
The AD5203 provides a quad channel, 64-position digitallycontrolled variable resistor (VR) device. Changing the programmed VR settings is accomplished by clocking in an 8-bit
serial data word into the SDI (Serial Data Input) pin. The format of this data word is two address bits, MSB first, followed by
six data bits, MSB first. Table I provides the serial register data
word format. The AD5203 has the following address assignments for the ADDR decode, which determines the location of
VR latch receiving the serial register data in Bits B5 through B0:
The general transfer equation that determines the digitally programmed output resistance between Wx and Bx is:
R WB(Dx) = (Dx)/64 × R BA + RW
VR# = A1 × 2 + A0 + 1
where Dx is the data contained in the 6-bit RDACx latch and
RBA is the nominal end-to-end resistance.
VR outputs can be changed one at a time in random sequence.
The serial clock running at 10 MHz makes it possible to load all
four VRs in under 3.2 µs (8 × 4 × 100 ns) for the AD5203. The
exact timing requirements are shown in Figure 1.
For example, when VB = 0 V and A–terminal is open circuit the
following output resistance values will be set for the following
RDAC latch codes (applies to the 10K potentiometer):
The AD5203 resets to a midscale by asserting the RS pin, simplifying initial conditions at power-up. Both parts have a power
shutdown SHDN pin that places the RDAC in a zero power
consumption state where terminals Ax are open-circuited and
the wiper Wx is connected to Bx, resulting in only leakage currents being consumed in the VR structure. In shutdown mode
the VR latch settings are maintained so that, returning to operational mode from power shutdown, the VR settings return to
their previous resistance values.
RS
SHDN
Ax
Output State
63
32
1
0
Full-Scale
Midscale (RS = 0 Condition)
1 LSB
Zero-Scale (Wiper Contact Resistance)
9889
5045
201
45
Like the mechanical potentiometer the RDAC replaces, it is
totally symmetrical. The resistance between the wiper W and
terminal A also produces a digitally controlled resistance RWA.
When these terminals are used the B–terminal should be tied to
the wiper. Setting the resistance value for RWA starts at a maximum value of resistance and decreases as the data loaded in the
latch is increased in value. The general transfer equation for this
operation is:
RS
Wx
RDAC
LATCH
&
DECODER
R WA(Dx) = (64-Dx)/64 × R BA + R W
RS
RS = RAB /64
(2)
where Dx is the data contained in the 6-bit RDACx latch and
RBA is the nominal end-to-end resistance. For example, when
VA = 0 V and B–terminal is tied to the wiper W, the following
output resistance values will be set for the following RDAC
latch codes:
Bx
Figure 34. Equivalent RDAC Circuit
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistance of the RDAC between Terminals A and
B are available with values of 10 kΩ, and 100 kΩ. The final
digits of the part number determine the nominal resistance
value, e.g., 10 kΩ = 10; 100 kΩ = 100. The nominal resistance
(RAB) of the VR has 64 contact points accessed by the wiper
terminal, plus the B terminal contact. The 6-bit data word in
the RDAC latch is decoded to select one of the 64 possible
settings. The wiper’s first connection starts at the B terminal for
data 00H . This B–terminal connection has a wiper contact resistance of 45 Ω. The second connection (10 kΩ part) is the first
REV. 0
D (DEC) RWB (⍀)
Note that in the zero-scale condition a finite wiper resistance of
45 Ω is present. Care should be taken to limit the current flow
between W and B in this state to a maximum value of 5 mA to
avoid degradation or possible destruction of the internal switch
contact.
RS
D5
D4
D3
D2
D1
D0
(1)
D (DEC)
RWA (⍀)
Output State
63
32
1
0
201
5045
9889
10045
Full-Scale
Midscale (RS = 0 Condition)
1 LSB
Zero-Scale
The typical distribution of RBA from channel to channel matches
within ± 1%. However, device-to-device matching is process-lotdependent, having a ± 30% variation. The change in RBA with
temperature has a 700 ppm/°C temperature coefficient.
–9–
AD5203
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates an output voltage
proportional to the input voltage applied to a given terminal.
For example connecting A–terminal to +5 V and B–terminal to
ground produces an output voltage at the wiper which can be
any value starting at zero volts up to 1 LSB less than +5 V.
Each LSB of voltage is equal to the voltage applied across terminal AB divided by the 64 position resolution of the potentiometer divider. The general equation defining the output
voltage with respect to ground for any given input voltage applied to terminals AB is:
VW(Dx) = Dx/64 × VAB + VB
Operation of the digital potentiometer in the divider mode
results in more accurate operation over temperature. Here the
output voltage is dependent on the ratio of the internal resistors
not the absolute value, therefore the drift improves to 20 ppm/°C.
DIGITAL INTERFACING
The AD5203 contains a standard three-wire serial input control
interface. The three inputs are clock (CLK), CS and serial data
input (SDI). The positive-edge sensitive CLK input requires
clean transitions to avoid clocking incorrect data into the serial
input register. Standard logic families work well. If mechanical
switches are used for product evaluation they should be debounced by a flip-flop or other suitable means. The Figure 35
block diagram shows more detail of the internal digital circuitry. When CS is taken active low the clock loads data into
the serial register on each positive clock edge, see Table III.
AD5203
CS
CLK
SDO
D5
A1
DO A0
A1
EN
R
ADDR
DEC
DAC
LAT
#1
D0
VDD
The serial-data-output (SDO) pin contains an open drain
n-channel FET. This output requires a pull-up resistor in order
to transfer data to the next package’s SDI pin. The pull-up
resistor termination voltage may be larger than the VDD supply
of the AD5203 SDO output device, e.g., the AD5203 could
operate at VDD = 3.3 V and the pull-up for interface to the next
device could be set at +5 V. This allows for daisy chaining several RDACs from a single processor serial data line. Clock period needs to be increased when using a pull-up resistor to the
SDI pin of the following device in the series. Capacitive loading
at the daisy chain node SDO-SDI between devices must be
accounted for to successfully transfer data. When daisy chaining
is used, the CS should be kept low until all the bits of every
package are clocked into their respective serial registers insuring
that the address bits and data bits are in the proper decoding
location. This would require 16 bits of address and data complying to the word format provided in Table I if two AD5203 fourchannel RDACs are daisy chained. During shutdown, SHDN
the SDO output pin is forced to the off (logic high state) to
disable power dissipation in the pull-up resistor. See Figure 37
for equivalent SDO output circuit schematic.
Table II. Input Logic Control Truth Table
CLK CS
RS
SHDN Register Activity
L
P
L
L
H
H
H
H
X
P
H
H
X
X
H
X
H
L
H
H
X
X
H
H
P
H
H
L
No SR effect, enables SDO pin.
Shift one bit in from the SDI pin.
The eighth previously entered bit
is shifted out of the SDO pin.
Load SR data into RDAC latch
based on A1, A0 decode (Table III).
No Operation.
Sets all RDAC latches to midscale,
wiper centered and SDO latch
cleared.
Latches all RDAC latches to 20H .
Open circuits all Resistor A–terminals, connects W to B, turns off
SDO output transistor.
W1
B1
R
D5
SER
REG
D5
SDI
DI D0
D0
6
A4
R
NOTE: P = positive edge, X = don’t care, SR = shift register.
W4
DAC
LAT
#4
Table III. Address Decode Table
B4
R
SHDN
DGND
RS
AGND
Figure 35. Block Diagram
–10–
A1
A0
Latch Decoded
0
0
1
1
0
1
0
1
RDAC#1
RDAC#2
RDAC#3
RDAC#4
REV. 0
AD5203
The data setup and data hold times in the specification table
determine the data valid time requirements. The last eight bits
of the data word entered into the serial register are held when
CS returns high. At the same time CS goes high it gates the
address decoder which enables one of four positive edge triggered RDAC latches, see Figure 36 detail.
AD5203
CS
ADDR
DECODE
DYNAMIC CHARACTERISTICS
SERIAL
REGISTER
Figure 36. Equivalent Input Control Logic
The target RDAC latch is loaded with the last six bits of the
serial data word completing one RDAC update. Four separate
8-bit data words must be clocked in to change all four VR
settings.
SHDN
SDI
SDO
SERIAL
REGISTER
D
LOGIC
Figure 38. Equivalent ESD Protection Circuit
RDAC 4
CS
1kV
RDAC 1
RDAC 2
CLK
SDI
All digital inputs are protected with a series input resistor and
parallel Zener ESD structure shown in Figure 38. Applies to
digital input pins CS, SDI, SDO, RS, SHDN, CLK.
Q
CK RS
CLK
RS
The total harmonic distortion plus noise (THD+N) measures
0.003% using an offset ground with a rail-to-rail OP279 inverting op amp test circuit, see Figure 30. Figure 15 plots THD
versus frequency for both inverting and noninverting amplifier
topologies. Thermal noise is primarily Johnson noise, typically
9 nV/√Hz for the 10 kΩ version measured at 1 kHz. For the
100 kΩ device, thermal noise measures 29 nV/√Hz. Channel-tochannel crosstalk measures less than –65 dB at f = 100 kHz. To
achieve this isolation, the extra ground pins (AGND) located
between the potentiometer terminals (A, B, W) must be connected to circuit ground. The AGND and DGND pins should
be at the same voltage potential. Any unused potentiometers in
a package should be connected to ground. Power supply rejection is typically –50 dB at 10 kHz (care is needed to minimize
power supply ripple injection in high accuracy applications).
Figure 37. Detail, SDO Output Schematic of the AD5203
REV. 0
–11–
AD5203
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
C3364–8–7/98
24-Lead Narrow Body Plastic DIP
(N-24)
1.275 (32.30)
1.125 (28.60)
24
13
1
12
PIN 1
0.280 (7.11)
0.240 (6.10)
0.060 (1.52)
0.015 (0.38)
0.210
(5.33)
MAX
0.200 (5.05)
0.125 (3.18)
0.325 (8.25)
0.300 (7.62) 0.195 (4.95)
0.115 (2.93)
0.150
(3.81)
MIN
0.022 (0.558)
0.014 (0.356)
0.100 (2.54)
BSC
0.070 (1.77)
0.045 (1.15)
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
24-Lead SOIC
(SOL-24)
13
1
12
PIN 1
0.1043 (2.65)
0.0926 (2.35)
0.0500
(1.27)
BSC
0.0118 (0.30)
0.0040 (0.10)
0.4193 (10.65)
0.3937 (10.00)
24
0.2992 (7.60)
0.2914 (7.40)
0.6141 (15.60)
0.5985 (15.20)
0.0291 (0.74)
x 45°
0.0098 (0.25)
8°
0.0192 (0.49)
0°
SEATING
0.0125 (0.32)
0.0138 (0.35) PLANE
0.0091 (0.23)
0.0500 (1.27)
0.0157 (0.40)
24-Lead Thin Surface Mount TSSOP
(RU-24)
13
0.256 (6.50)
0.246 (6.25)
0.177 (4.50)
0.169 (4.30)
24
1
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
PRINTED IN U.S.A.
0.311 (7.90)
0.303 (7.70)
12
PIN 1
0.0433
(1.10)
MAX
0.0256 (0.65)
BSC
0.0118 (0.30)
0.0075 (0.19)
0.0079 (0.20)
0.0035 (0.090)
–12–
8°
0°
0.028 (0.70)
0.020 (0.50)
REV. 0
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