FINAL Am28F512 512 Kilobit (64 K x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory DISTINCTIVE CHARACTERISTICS ■ High performance — 70 ns maximum access time ■ CMOS Low power consumption — 30 mA maximum active current — 100 µA maximum standby current — No data retention power consumption ■ Compatible with JEDEC-standard byte-wide 32-Pin EPROM pinouts — 32-pin PDIP — 32-pin PLCC — 32-pin TSOP ■ Latch-up protected to 100 mA from -1 V to VCC +1 V ■ Flasherase Electrical Bulk Chip-Erase — One second typical chip-erase ■ Flashrite Programming — 10 µs typical byte-program — One second typical chip program ■ Command register architecture for microprocessor/microcontroller compatible write interface ■ On-chip address and data latches ■ Advanced CMOS flash memory technology ■ 10,000 write/erase cycles minimum — Low cost single transistor memory cell ■ Write and erase voltage 12.0 V ±5% ■ Automatic write/erase pulse stop timer GENERAL DESCRIPTION The Am28F512 is a 512 K bit Flash memory organized as 64 Kbytes of 8 bits each. AMD’s Flash memories offer the most cost-effective and reliable read/ write non-volatile random access memor y. The Am28F512 is packaged in 32-pin PDIP, PLCC, and TSOP versions. It is designed to be reprogrammed and erased in-system or in standard EPROM programmers. The Am28F512 is erased when shipped from the factory. The standard Am28F512 offers access times as fast as 70 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the Am28F512 has separate chip enable (CE#) and output enable (OE#) controls. AMD’s Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The Am28F512 uses a command register to manage this functionality, while maintaining a standard JEDEC Flash Standard 32-pin pinout. The command register allows for 100% TTL level control inputs and fixed power supply levels during erase and programming. AMD’s Flash technology reliably stores memory contents even after 10,000 erase and program cycles. The AMD cell is designed to optimize the erase and proPublication# 11561 Rev: G Amendment/+2 Issue Date: January 1998 gramming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. The Am28F512 uses a 12.0 V ± 5% V PP high voltage input to perform the Flasherase and Flashrite algorithms. The highest degree of latch-up protection is achieved with AMD’s proprietary non-epi process. Latch-up protection is provided for stresses up to 100 mA on address and data pins from -1 V to VCC +1 V. The Am28F512 is byte programmable using 10 ms programming pulses in accordance with AMD’s Flashrite programming algorithm. The typical room temperature programming time of the Am28F512 is one second. The entire chip is bulk erased using 10 ms erase pulses according to AMD’s Flasherase algorithm. Typical erasure at room temperature is accomplished in less than one second. The windowed package and the 15-20 minutes required for EPROM erasure using ultra-violet light are eliminated. Commands are written to the command register using standard microprocessor write timings. Register contents serve as inputs to an internal state-machine which controls the erase and programming circuitry. During write cycles, the command register internally latches address and data needed for the programming and erase operations. For system design simplification, the Am28F512 is designed to support either WE# or CE# controlled writes. During a system write cycle, addresses are latched on the falling edge of WE# or CE# whichever occurs last. Data is latched on the rising edge of WE# or CE# whichever occurs first. To simplify the following discussion, the WE# pin is used as the write cycle control pin throughout the rest of this text. All setup and hold times are with respect to the WE# signal. AMD’s Flash technology combines years of EPROM and EEPROM experience to produce the highest levels of quality, reliability, and cost effectiveness. The Am28F512 electrically erases all bits simultaneously using Fowler-Nordheim tunneling. The bytes are programmed one byte at a time using the EPROM programming mechanism of hot electron injection. BLOCK DIAGRAM DQ0–DQ7 VCC VSS Erase Voltage Switch VPP WE# Input/Output Buffers To Array State Control Command Register Program Voltage Switch Chip Enable Output Enable Logic CE# OE# Low VCC Detector Data Latch Y-Decoder Y-Gating X-Decoder 524,288 Bit Cell Matrix Program/Erase Pulse Timer A0–A15 Address Latch 11561G-1 PRODUCT SELECTOR GUIDE Am28F512 Family Part Number Speed Options (VCC = 5.0 V ± 10%) -70 -90 -120 -150 -200 Max Access Time (ns) 70 90 120 150 200 CE# (E#) Access (ns) 70 90 120 150 200 OE# (G#) Access (ns) 35 35 50 55 55 2 Am28F512 VCC NC 2 31 WE# (W#) 4 3 2 VCC 32 NC 1 A12 A15 VPP VPP PLCC PDIP WE# (W#) NC CONNECTION DIAGRAMS 1 32 31 30 A7 5 29 A14 A6 6 28 A13 A5 27 A8 A4 7 8 26 A9 3 30 NC A12 4 29 A14 A7 5 28 A13 A6 6 27 A8 A3 9 25 A11 A5 7 26 A9 A2 10 24 OE# (G#) A4 8 25 A1 11 23 A10 A3 9 24 A11 OE# (G#) A0 12 22 DQ0 13 CE# (E#) DQ7 A2 10 23 A10 A1 11 22 CE# (E#) 14 15 16 17 18 19 20 A0 12 21 DQ7 DQ0 13 20 DQ6 DQ1 DQ2 A15 DQ1 14 19 DQ5 DQ2 15 18 DQ4 VSS 16 17 DQ3 DQ5 DQ6 DQ4 VSS DQ3 21 11561G-3 11561G-2 Note: Pin 1 is marked for orientation. Am28F512 3 CONNECTION DIAGRAMS (continued) A11 A9 A8 A13 A14 NC WE# VCC VPP NC A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE# A10 CE# D7 D6 D5 D4 D3 VSS D2 D1 D0 A0 A1 A2 A3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A11 A9 A8 A13 A14 NC WE# VCC VPP NC A15 A12 A7 A6 A5 A4 32-Pin — Standard Pinout OE# A10 CE# D7 D6 D5 D4 D3 VSS D2 D1 D0 A0 A1 A2 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 11561G-4 32-Pin — Reverse Pinout LOGIC SYMBOL 16 A0–A15 8 DQ0–DQ7 CE# (E#) OE# (G#) WE# (W#) 11561G-5 4 Am28F512 ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM28F512 -70 J C B OPTIONAL PROCESSING Blank = Standard Processing B = Burn-In Contact an AMD representative for more information. TEMPERATURE RANGE C = Commercial (0°C to +70°C) I = Industrial (–40°C to +85°C) E = Extended (–55°C to +125°C) PACKAGE TYPE P = 32-Pin Plastic DIP (PD 032) J = 32-Pin Rectangular Plastic Leaded Chip Carrier (PL 032) E = 32-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 032) F = 32-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR032) SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER/DESCRIPTION Am28F512 512 Kilobit (64 K x 8-Bit) CMOS Flash Memory Valid Combinations Valid Combinations AM28F256-70 AM28F256-90 AM28F256-120 AM28F256-150 PC, PI, PE, JC, JI, JE, EC, EI, EE, FC, FI, FE Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. AM28F256-200 Am28F512 5 PIN DESCRIPTION VCC A0–A15 Power supply for device operation. (5.0 V ± 5% or 10%) Address Inputs for memory locations. Internal latches hold addresses during write cycles. VPP Chip Enable active low input activates the chip’s control logic and input buffers. Chip Enable high will deselect the device and operates the chip in stand-by mode. Program voltage input. VPP must be at high voltage in order to write to the command register. The command register controls all functions required to alter the memory array contents. Memory contents cannot be altered when VPP ≤ VCC +2 V. DQ0–DQ7 VSS CE# (E#) Data Inputs during memory write cycles. Internal latches hold data during write cycles. Data Outputs during memory read cycles. NC No Connect-corresponding pin is not connected internally to the die. OE# (G#) Ground WE# (W#) Write Enable active low input controls the write function of the command register to the memory array. The target address is latched on the falling edge of the Write Enable pulse and the appropriate data is latched on the rising edge of the pulse. Write Enable high inhibits writing to the device. Output Enable active low input gates the outputs of the device through the data buffers during memory read cycles. Output Enable is high during command sequencing and program/erase operations. 6 Am28F512 BASIC PRINCIPLES The device uses 100% TTL-level control inputs to manage the command register. Erase and reprogramming operations use a fixed 12.0 V ± 5% high voltage input. formation must be supplied with the Erase-verify command. This command verifies the margin and outputs the addressed byte in order to compare the array data with FFh data (Byte erased). After successful data verification the Erase-verify command is written again with new address information. Each byte of the array is sequentially verified in this manner. Read Only Memory Without high V PP voltage, the device functions as a read only memory and operates like a standard EPROM. The control inputs still manage traditional read, standby, output disable, and Auto select modes. Command Register The command register is enabled only when high voltage is applied to the V PP pin. The erase and reprogramming operations are only accessed via the register. In addition, two-cycle commands are required for erase and reprogramming operations. The traditional read, standby, output disable, and Auto select modes are available via the register. The device’s command register is written using standard microprocessor write timings. The register controls an internal state machine that manages all device operations. For system design simplification, the device is designed to support either WE# or CE# controlled writes. During a system write cycle, addresses are latched on the falling edge of WE# or CE# whichever occurs last. Data is latched on the rising edge of WE# or CE# whichever occur first. To simplify the following discussion, the WE# pin is used as the write cycle control pin throughout the rest of this text. All setup and hold times are with respect to the WE# signal. Overview of Erase/Program Operations Flasherase™ Sequence A multiple step command sequence is required to erase the Flash device (a two-cycle Erase command and repeated one cycle verify commands). Note: The Flash memory array must be completely programmed to 0’s prior to erasure. Refer to the Flashrite™ Programming Algorithm. 1. Erase Setup: Write the Setup Erase command to the command register. 2. Erase: Write the Erase command (same as Setup Erase command) to the command register again. The second command initiates the erase operation. The system software routines must now time-out the erase pulse width (10 ms) prior to issuing the Erase-verify command. An integrated stop timer prevents any possibility of overerasure. 3. Erase-Verify: Write the Erase-verify command to the command register. This command terminates the erase operation. After the erase operation, each byte of the array must be verified. Address in- If data of the addressed location is not verified, the Erase sequence is repeated until the entire array is successfully verified or the sequence is repeated 1000 times. Flashrite Programming Sequence A three step command sequence (a two-cycle Program command and one cycle Verify command) is required to program a byte of the Flash array. Refer to the Flashrite Algorithm. 1. Program Setup: Write the Setup Program command to the command register. 2. Program: Write the Program command to the command register with the appropriate Address and Data. The system software routines must now timeout the program pulse width (10 µs) prior to issuing the Program-verify command. An integrated stop timer prevents any possibility of overprogramming. 3. Program-Verify: Write the Program-verify command to the command register. This command terminates the programming operation. In addition, this command verifies the margin and outputs the byte just programmed in order to compare the array data with the original data programmed. After successful data verification, the programming sequence is initiated again for the next byte address to be programmed. If data is not verified successfully, the Program sequence is repeated until a successful comparison is verified or the sequence is repeated 25 times. Data Protection The device is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. The device powers up in its read only state. Also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting fromVCC powerup and power-down transitions or system noise. Low VCC Write Inhibit To avoid initiation of a write cycle during VCC power-up and power-down, the device locks out write cycles for Am28F512 7 V CC < V LKO (see DC Characteristics section for voltages). When V CC < VLKO, the command register is disabled, all internal program/erase circuits are disabled, and the device resets to the read mode. The device ignores all writes until V CC > V LKO. The user must ensure that the control pins are in the correct logic state when VCC > VLKO to prevent uninitentional writes. Write Pulse “Glitch” Protection Noise pulses of less than 10 ns (typical) on OE#, CE# or WE# will not initiate a write cycle. Logical Inhibit Writing is inhibited by holding any one of OE# = VIL, CE# = V IH or WE# = VIH. To initiate a write cycle CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit Power-up of the device with WE# = CE# = V IL and OE# = V IH will not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up. FUNCTIONAL DESCRIPTION Description of User Modes Table 1. Am28F512 User Bus Operations (Notes 7 and 8) Operation Read-Only CE# (E#) VPP OE# (G#) WE# (W#) (Note 1) A0 A9 I/O Read VIL VIL X VPPL A0 A9 DOUT Standby VIH X X VPPL X X HIGH Z Output Disable VIL VIH VIH VPPL X X HIGH Z Auto-select Manufacturer Code (Note 2) VIL VIL VIH VPPL VIL VID (Note 3) CODE (01H) Auto-select Device Code (Note 2) VIL VIL VIH VPPL VIH VID (Note 3) CODE (25H) Read VIL VIL VIH VPPH A0 A9 DOUT (Note 4) Standby (Note 5) VIH X X VPPH X X HIGH Z Output Disable VIL VIH VIH VPPH X X HIGH Z Write VIL VIH VIL VPPH A0 A9 DIN (Note 6) Read/Write Legend: X = Don’t care, where Don’t Care is either VIL or VIH levels. VPPL = VPP < VCC + 2 V. See DC Characteristics for voltage levels of VPPH. 0 V < An < VCC + 2 V, (normal TTL or CMOS input levels, where n = 0 or 9). Notes: 1. VPPL may be grounded, connected with a resistor to ground, or < VCC +2.0 V. VPPH is the programming voltage specified for the device. Refer to the DC characteristics. When VPP = VPPL, memory contents can be read but not written or erased. 2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 2. 3. 11.5 < VID < 13.0 V. Minimum V ID rise time and fall time (between 0 and VID voltages) is 500 ns. 4. Read operation with VPP = VPPH may access array data or the Auto select codes. 5. With VPP at high voltage, the standby current is ICC + IPP (standby). 6. Refer to Table 3 for valid DIN during a write operation. 7. All inputs are Don’t Care unless otherwise stated, where Don’t Care is either VIL or VIH levels. In the Auto select mode all addresses except A9 and A0 must be held at VIL. 8. If VCC ≤ 1.0 Volt, the voltage difference between V PP and VCC should not exceed 10.0 Volts. Also, the Am28F512 has a V PP rise time and fall time specification of 500 ns minimum. 8 Am28F512 READ ONLY MODE When V PP is less than VCC + 2 V, the command register is inactive. The device can either read array or autoselect data, or be standby mode. Read The device functions as a read only memory when VPP < VCC + 2 V. The device has two control functions. Both must be satisfied in order to output data. CE# controls power to the device. This pin should be used for specific device selection. OE# controls the device outputs and should be used to gate data to the output pins if a device is selected. Address access time tACC is equal to the delay from stable addresses to valid output data. The chip enable access time tCE is the delay from stable addresses and stable CE# to valid data at the output pins. The output enable access time is the delay from the falling edge of OE# to valid data at the output pins (assuming the addresses have been stable at least tACC–tOE). Standby Mode Output Disable Output from the device is disabled when OE# is at a logic high level. When disabled, output pins are in a high impedance state. Auto Select Flash memories can be programmed in-system or in a standard PROM programmer. The device may be soldered to the circuit board upon receipt of shipment and programmed in-system. Alternatively, the device may initially be programmed in a PROM programmer prior to soldering the device to the board. The Auto select mode allows the reading out of a binary code from the device that will identify its manufacturer and type. This mode is intended for the purpose of automatically matching the device to be programmed with its corresponding programming algor ithm. Thi s mode is functional over the enti re temperature range of the device. Programming In A PROM Programmer The device has two standby modes. The CMOS standby mode (CE# input held at VCC ± 0.5 V), consumes less than 100 µA of current. TTL standby mode (CE# is held at VIH) reduces the current requirements to less than 1mA. When in the standby mode the outputs are in a high impedance state, independent of the OE# input. If the device is deselected during erasure, programming, or program/erase verification, the device will draw active current until the operation is terminated. To activate this mode, the programming equipment must force VID (11.5 V to 13.0 V) on address A9. Two identifier bytes may then be sequenced from the device outputs by toggling address A0 from VIL to VIH. All other address lines must be held at VIL, and VPP must be less than or equal to VCC + 2.0 V while using this Auto select mode. Byte 0 (A0 = V IL) represents the manufacturer code and byte 1 (A0 = VIH) the device identifier code. For the device these two bytes are given in Table 2 below. All identifiers for manufacturer and device codes will exhibit odd parity with the MSB (DQ7) defined as the parity bit. Table 2. Am28F512 Auto Select Code Type A0 Code (HEX) Manufacturer Code VIL 01 Device Code VIH 25 Am28F512 9 ERASE, PROGRAM, AND READ MODE When V PP is equal to 12.0 V ± 5%, the command register is active. All functions are available. That is, the device can program, erase, read array or autoselect data, or be standby mode. Write Operations High voltage must be applied to the VPP pin in order to activate the command register. Data written to the register serves as input to the internal state machine. The output of the state machine determines the operational function of the device. The command register does not occupy an addressable memory location. The register is a latch that stores the command, along with the address and data information needed to execute the command. The register is written by bringing WE# and CE# to VIL, while OE# is at VIH. Addresses are latched on the falling edge of WE#, while data is latched on the rising edge of the WE# pulse. Standard microprocessor write timings are used. The device requires the OE# pin to be V IH for write operations. This condition eliminates the possibility for bus contention during programming operations. In order to write, OE# must be VIH, and CE# and WE# must be V IL. If any pin is not in the correct state a write command will not be executed. Table 3. Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters. Command Definitions The contents of the command register default to 00h (Read Mode) in the absence of high voltage applied to the V PP pin. The device operates as a read only memory. High voltage on the V PP pin enables the command register. Device operations are selected by writing specific data codes into the command register. Table 3 defines these register commands. Read Command Memory contents can be accessed via the read command when V PP is high. To read from the device, write 00h into the command register. Standard microprocessor read cycles access data from the memory. The device will remain in the read mode until the command register contents are altered. The command register defaults to 00h (read mode) upon VPP power-up. The 00h (Read Mode) register default helps ensure that inadvertent alteration of the memory contents does not occur during the V PP power transition. Refer to the AC Read Characteristics and Waveforms for the specific timing parameters. Am28F512 Command Definitions First Bus Cycle Second Bus Cycle Operation (Note 1) Address (Note 2) Data (Note 3) Operation (Note 1) Address (Note 2) Data (Note 3) Read Memory Write X 00H/FFh Read RA RD Read Auto select Write X 80h or 90h Read 00h/01h 01h/25h Erase Set-up/Erase Write Write X 20h Write X 20h Erase-Verify Write EA A0h Read X EVD Program Set-up/ Program Write X 40h Write PA PD Program-Verify Write X C0h Read X PVD Reset Write X FFh Write X FFh Command (Note 4) Notes: 1. Bus operations are defined in Table 1. 2. RA = Address of the memory location to be read. EA = Address of the memory location to be read during erase-verify. PA = Address of the memory location to be programmed. X = Don’t care. Addresses are latched on the falling edge of the WE# pulse. 3. RD = Data read from location RA during read operation. EVD = Data read from location EA during erase-verify. PD = Data to be programmed at location PA. Data latched on the rising edge of WE#. PVD = Data read from location PA during program-verify. PA is latched on the Program command. 4. Refer to the appropriate section for algorithms and timing diagrams. 10 Am28F512 FLASHERASE ERASE SEQUENCE Erase Setup Erase Setup is the first of a two-cycle erase command. It is a command-only operation that stages the device for bulk chip erase. The array contents are not altered with this command. 20h is written to the command register in order to perform the Erase Setup operation. Erase The second two-cycle erase command initiates the bulk erase operation. You must write the Erase command (20h) again to the register. The erase operation begins with the rising edge of the WE# pulse. The erase operation must be terminated by writing a new command (Erase-verify) to the register. This two step sequence of the Setup and Erase commands helps to ensure that memory contents are not accidentally erased. Also, chip erasure can only occur when high voltage is applied to the VPP pin and all control pins are in their proper state. In absence of this high voltage, memory contents cannot be altered. Refer to AC Erase Characteristics and Waveforms for specific timing parameters. Note: The Flash memory device must be fully programmed to 00h data prior to erasure. This equalizes the charge on all memory cells ensuring reliable erasure. Erase-Verify Command The erase operation erases all bytes of the array in parallel. After the erase operation, all bytes must be sequentially verified. The Erase-verify operation is initi- ated by writing A0h to the register. The byte address to be verified must be supplied with the command. Addresses are latched on the falling edge of the WE# pulse or CE# pulse, whichever occurs later. The rising edge of the WE# pulse terminates the erase operation. Margin Verify During the Erase-verify operation, the device applies an i nter nally generated margin vol tage to the addressed byte. Reading FFh from the addressed byte indicates that all bits in the byte are properly erased. Verify Next Address You must write the Erase-verify command with the appropriate address to the register prior to verification of each address. Each new address is latched on the falling edge of WE# or CE# pulse, whichever occurs later. The process continues for each byte in the memory array until a byte does not return FFh data or all the bytes in the array are accessed and verified. If an address is not verified to FFh data, the entire chip is erased again (refer to Erase Setup/Erase). Erase verification then resumes at the address that failed to verify. Erase is complete when all bytes in the array have been verified. The device is now ready to be programmed. At this point, the verification operation is terminated by writing a valid command (e.g. Program Setup) to the command register. Figure 1 and Table 4, the Flasherase electrical erase algorithm, illustrate how commands and bus operations are combined to perform electrical erasure. Refer to AC Erase Characteristics and Waveforms for specific timing parameters. Am28F512 11 Start Yes Data = 00h No Program All Bytes to 00h Apply VPPH Address = 00h PLSCNT = 0 Write Erase Setup Command Write Erase Command Time out 10 ms Write Erase Verify Time out 6 µs Read Data from Device No No PLSCNT = 1000 Yes Apply VPPL Increment PLSCNT Data = FFh Yes Last Address Erase Error No Increment Address Yes Write Reset Command Apply V PPL Erasure Completed Figure 1. 12 Flasherase Electrical Erase Algorithm Am28F512 11559G-6 Flasherase Electrical Erase Algorithm This Flash memory device erases the entire array in parallel. The erase time depends on VPP, temperature, and number of erase/program cycles on the device. In general, reprogramming time increases as the number of erase/program cycles increases. The Flasherase electrical erase algorithm employs an interactive closed loop flow to simultaneously erase all bits in the array. Erasure begins with a read of the memory contents. The device is erased when shipped from the factory. Reading FFh data from the device would immediately be followed by executing the Flashrite programming algorithm with the appropriate data pattern. Should the device be currently programmed, data other than FFh will be returned from address locations. Follow the Flasherase algorithm. Uniform and reliable erasure is ensured by first programming all bits in the device to their charged state (Data = 00h). This is accomplished using the Flashrite Programming Table 4. Bus Operations algorithm. Erasure then continues with an initial erase operation. Erase verification (Data = FFh) begins at address 0000h and continues through the array to the l a s t a dd re s s , o r u n ti l d ata o th er th an FF h i s encountered. If a byte fails to verify, the device is erase d agai n. W i th each e ra se operati on , a n increasing number of bytes verify to the erased state. Typically, devices are erased in less than 100 pulses (one second). Erase efficiency may be improved by storing the address of the last byte that fails to verify in a register. Following the next erase operation, verification may start at the stored address location. A total of 1000 erase pulses are allowed per reprogram cycle, which corresponds to approximately 10 seconds of cumulative erase time. The entire sequence of erase and byte verification is performed with high voltage applied to the V PP pin. Figure 1 illustrates the electrical erase algorithm. Flasherase Electrical Erase Algorithm Command Comments Entire memory must = 00h before erasure (Note 3) Note: Use Flashrite programming algorithm (Figure 3) for programming. Wait for VPP Ramp to VPPH (Note 1) Initialize: Addresses PLSCNT (Pulse count) Standby Erase Setup Data = 20h Erase Data = 20h Write Duration of Erase Operation (tWHWH2) Standby Write Erase-Verify (Note 2) Address = Byte to Verify Data = A0h Stops Erase Operation Standby Write Recovery Time before Read = 6 µs Read Read byte to verify erasure Standby Compare output to FFh Increment pulse count Write Standby Reset Data = FFh, reset the register for read operations Wait for VPP Ramp to VPPL (Note 1) Notes: 1. See AC and DC Characteristics for values of VPP parameters. The V PP power supply can be hard-wired to the device or switchable. When VPP is switched, VPPL may be ground, no connect with a resistor tied to ground, or less than VCC + 2.0 V. 2. Erase Verify is performed only after chip erasure. A final read compare may be performed (optional) after the register is written with the read command. 3. The erase algorithm Must Be Followed to ensure proper and reliable operation of the device. Am28F512 13 A Section B C D E F G Addresses CE# OE# WE# 20h Data Data Out A0h 20h VCC VPP 11559G-7 A B C D E F G Bus Cycle Write Write Time-out Write Time-out Read Standby Command 20h 20h N/A A0h N/A Compare Data N/A Function Erase Setup Erase Erase (10 ms) EraseVerify Transition (6 µs) Erase Verification Proceed per Erase Algorithm Figure 2. AC Waveforms For Erase Operations ANALYSIS OF ERASE TIMING WAVEFORM Note: This analysis does not include the requirement to program the entire array to 00h data prior to erasure. Refer to the Flashrite Programming algorithm. Erase Setup/Erase This analysis illustrates the use of two-cycle erase commands (section A and B). The first erase command (20h) is a Setup command and does not affect the array data (section A). The second erase command (20h) initiates the erase operation (section B) on the rising edge of this WE# pulse. All bytes of the memory array are erased in parallel. No address information is required. The erase pulse occurs in section C. Time-Out A software timing routine (10 ms duration) must be initiated on the rising edge of the WE# pulse of section B. Note: An integrated stop timer prevents any possibility of overerasure by limiting each time-out period of 10 ms. Erase-Verify Upon completion of the erase software timing routine, the microprocessor must write the Erase-verify command (A0h). This command terminates the erase operation on the rising edge of the WE# pulse (section D). The Erase-verify command also stages the device for data verification (section F). After each erase operation each byte must be verified. The byte address to be verified must be supplied with 14 Am28F512 the Erase-verify command (section D). Addresses are latched on the falling edge of the WE# pulse. Another software timing routine (6 µs duration) must be executed to allow for generation of internal voltages for margin checking and read operation (section E). During Erase-verification (section F) each address that returns FFh data is successfully erased. Each address of the array is sequentially verified in this manner by repeating sections D thru F until the entire array is verified or an address fails to verify. Should an address FLASHRITE PROGRAMMING SEQUENCE Program Setup The device is programmed byte by byte. Bytes may be programmed sequentially or at random. Program Setup is the first of a two-cycle program command. It stages the device for byte programming. The Program Setup operation is performed by writing 40h to the command register. Program Only after the program Setup operation is completed will the next WE# pulse initiate the active programming operation. The appropriate address and data for programming must be available on the second WE# pulse. Addresses and data are internally latched on the falling and rising edge of the WE# pulse respectively. The rising edge of WE# also begins the programming operation. You must write the Program-verify command to terminate the programming operation. This two step sequence of the Setup and Program commands helps to ensure that memory contents are not accidentally written. Also, programming can only occur when high voltage is applied to the V PP pin and all control pins are in their proper state. In absence of this high voltage, memory contents cannot be programmed. Refer to AC Characteristics and Waveforms for specific timing parameters. Program Verify Command Following each programming operation, the byte just programmed must be verified. Write C0h into the command register in order to initiate the Program-verify operation. The rising edge of this WE pulse terminates the programming operation. The location fail to verify to FFh data, erase the device again. Repeat sections A thru F. Resume verification (section D) with the failed address. Each data change sequence allows the device to use up to 1,000 erase pulses to completely erase. Typically 100 erase pulses are required. Note: All address locations must be programmed to 00h prior to erase. This equalizes the charge on all memory cells and ensures reliable erasure. Program-verify operation stages the device for verification of the last byte programmed. Addresses were previously latched. No new information is required. Margin Verify During the Program-verify operation, the device applies an internally generated margin voltage to the addressed byte. A normal microprocessor read cycle outputs the data. A successful comparison between the programmed byte and the true data indicates that the byte was successfully programmed. The original programmed data should be stored for comparison. Programming then proceeds to the next desired byte location. Should the byte fail to verify, reprogram (refer to Program Setup/Program). Figure 3 and Table 5 indicate how instructions are combined with the bus operations to perform byte programming. Refer to AC Programming Characteristics and Waveforms for specific timing parameters. Flashrite Programming Algorithm The device Flashrite Programming algorithm employs an interactive closed loop flow to program data byte by byte. Bytes may be programmed sequentially or at random. The Flashrite Programming algorithm uses 10 µs programming pulses. Each operation is followed by a byte verification to determine when the addressed byte has been successfully programmed. The program algorithm allows for up to 25 programming operations per byte per reprogramming cycle. Most bytes verify after the first or second pulse. The entire sequence of programming and byte verification is performed with high voltage applied to the VPP pin. Figure 3 and Table 5 illustrate the programming algorithm. Am28F512 15 Start Apply VPPH PLSCNT = 0 Write Program Setup Command Write Program Command (A/D) Time out 10 µs Write Program Verify Command Time out 6 µs Read Data from Device No Verify Byte No Increment PLSCNT Yes Increment Address No PLSCNT = 25? Yes Last Address Yes Write Reset Command Apply VPPL Apply VPPL Programming Completed Device Failed 11559G-8 Figure 3. 16 Flashrite Programming Algorithm Am28F512 Table 5. Bus Operations Flashrite Programming Algorithm Command Comments Wait for VPP Ramp to VPPH (Note 1) Initialize Pulse counter Standby Program Setup Data = 40h Program Valid Address/Data Write Duration of Programming Operation (tWHWH1) Standby Write Program-Verify (Note 2) Data = C0h Stops Program Operation Standby Write Recovery Time before Read = 6 µs Read Read Byte to Verify Programming Standby Compare Data Output to Data Expected Write Standby Reset Data = FFh, resets the register for read operations. Wait for VPP Ramp to VPPL (Note 1) Notes: 1. See AC and DC Characteristics for values of VPP parameters. The V PP power supply can be hard-wired to the device or switchable. When VPP is switched, VPPL may be ground, no connect with a resistor tied to ground, or less than VCC + 2.0 V. 2. Program Verify is performed only after byte programming. A final read/compare may be performed (optional) after the register is written with the read command. Am28F512 17 B A Section C D E F G Addresses CE# OE# WE# Data In 20h Data Data Out A0h VCC VPP 11559G-9 A B C D E Bus Cycle Write Write Time-out Write Time-out Read Standby Command 40h Program Address, Program Data N/A C0h (Stops Program) N/A Compare Data N/A Program Setup Program Command Latch Address and Data Program (10 µs) Program Verify Transition (6 µs) Program Verification Proceed per Programming Algorithm Function Figure 4. F G AC Waveforms for Programming Operations ANALYSIS OF PROGRAM TIMING WAVEFORMS Program Setup/Program Time-Out Two-cycle write commands are required for program operations (section A and B). The first program command (40h) is a Setup command and does not affect the array data (section A).The second program command latches address and data required for programming on the falling and rising edge of WE# respectively (section B). The rising edge of this WE# pulse (section B) also initiates the programming pulse. The device is programmed on a byte by byte basis either sequentially or randomly. Note: An integrated stop timer prevents any possibility of overprogramming by limiting each time-out period of 10 µs. The program pulse occurs in section C. 18 A software timing routine (10 µs duration) must be initiated on the rising edge of the WE# pulse of section B. Program-Verify Upon completion of the program timing routine, the microprocessor must write the program-verify command (C0h). This command terminates the programming operation on the rising edge of the WE# pulse (section D). The program-verify command also stages the device for data verification (section F). Another software timing routine (6 µs duration) must be executed to allow for Am28F512 generation of internal voltages for margin checking and read operations (section E). Parallel Device Erasure During program-verification (section F) each byte just programmed is read to compare array data with original program data. When successfully verified, the next desired address is programmed. Should a byte fail to verify, reprogram the byte (repeat section A thru F). Each data change sequence allows the device to use up to 25 program pulses per byte. Typically, bytes are verified within one or two pulses. Many applications will use more than one Flash memory device. Total erase time may be minimized by implementing a parallel erase algorithm. Flash memories may erase at different rates. Therefore each device must be verified separately. When a device is completely erased and verified use a masking code to prevent further erasure. The other devices will continue to erase until verified. The masking code applied could be the read command (00h). Algorithm Timing Delays Power-Up/Power-Down Sequence There are four different timing delays associated with the Flasherase and Flashrite algorithms: The device powers-up in the Read only mode. Power supply sequencing is not required. Note that if VCC ≤ 1.0 Volt, the voltage difference between VPP and V CC should not exceed 10.0 Volts. Also, the device has VPP rise time and fall time specification of 500 ns minimum. 1. The first delay is associated with the VPP rise-time when VPP first turns on. The capacitors on the VPP bus cause an RC ramp. After switching on the VPP, the delay required is proportional to the number of devices being erased and the 0.1 mF/device. VPP must reach its final value 100 ns before commands are executed. 2. The second delay time is the erase time pulse width (10 ms). A software timing routine should be run by the local microprocessor to time out the delay. The erase operation must be terminated at the conclusion of the timing routine or prior to executing any system interrupts that may occur during the erase operation. To ensure proper device operation, write the Erase-verify operation after each pulse. 3. A third delay time is required for each programming pulse width (10 ms). The programming algorithm is interactive and verifies each byte after a program pulse. The program operation must be terminated at the conclusion of the timing routine or prior to executing any system interrupts that may occur during the programming operation. 4. A fourth timing delay associated with both the Flasherase and Flashrite algorithms is the write recovery time (6 ms). During this time internal circuitry is changing voltage levels from the erase/ program level to those used for margin verify and read operations. An attempt to read the device during this period will result in possible false data (it may appear the device is not properly erased or programmed). Note: Software timing routines should be written in machine language for each of the delays. Code written in machine language requires knowledge of the appropriate microprocessor clock speed in order to accurately time each delay. Reset Command The Reset command initializes the Flash memory device to the Read mode. In addition, it also provides the user with a safe method to abort any device operation (including program or erase). The Reset command must be written two consecutive times after the setup Program command (40h). This will reset the device to the Read mode. Following any other Flash command write the Reset command once to the device. This will safely abort any previous operation and initialize the device to the Read mode. The Setup Program command (40h) is the only command that requires a two sequence reset cycle. The first Reset command is interpreted as program data. However, FFh data is considered null data during programming operations (memory cells are only programmed from a logical “1” to “0”). The second Reset command safely aborts the programming operation and resets the device to the Read mode. Memory contents are not altered in any case. This detailed information is for your reference. It may prove easier to always issue the Reset command two consecutive times. This eliminates the need to determine if you are in the setup Program state or not. Programming In-System Flash memories can be programmed in-system or in a standard PROM programmer. The device may be soldered to the circuit board upon receipt of shipment and programmed in-system. Alternatively, the device may initially be programmed in a PROM programmer prior to soldering the device to the board. Am28F512 19 Auto Select Command AMD’s Flash memories are designed for use in applications where the local CPU alters memory contents. Accordingly, manufacturer and device codes must be accessible while the device resides in the target system. PROM programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto address lines is not a generally desired system design practice. 20 The device contains an Auto Select operation to supplement traditional PROM programming methodology. The operation is initiated by writing 80h or 90h into the command register. Following this command, a read cycle address 0000h retrieves the manufacturer code of 01h. A read cycle from address 0001h returns the device code. To terminate the operation, it is necessary to write another valid command, such as Reset (FFh), into the register. Am28F512 ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . . –65°C to +150°C Plastic Packages . . . . . . . . . . . . . . . –65°C to +125°C Commercial (C) Devices Ambient Temperature with Power Applied. . . . . . . . . . . . . .–55°C to + 125°C Industrial (I) Devices Ambient Temperature (TA). . . . . . . . . .–40°C to +85°C Voltage with Respect To Ground All pins except A9 and VPP (Note 1) .–2.0 V to +7.0 V Extended (E) Devices VCC (Note 1). . . . . . . . . . . . . . . . . . . .–2.0 V to +7.0 V A9 (Note 2). . . . . . . . . . . . . . . . . . . . –2.0 V to +14.0 V VPP (Note 2). . . . . . . . . . . . . . . . . . . –2.0 V to +14.0 V Output Short Circuit Current (Note 3) . . . . . . 200 mA Notes: 1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, inputs may overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input and I/O pins is VCC + 0.5 V. During voltage transitions, input and I/O pins may overshoot to VCC + 2.0V for periods up to 20ns. Ambient Temperature (TA). . . . . . . . . . . .0°C to +70°C Ambient Temperature (TA). . . . . . . . .–55°C to +125°C VCC Supply Voltages VCC . . . . . . . . . . . . . . . . . . . . . . . . +4.50 V to +5.50 V VPP Voltages Read . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +12.6 V Program, Erase, and Verify . . . . . . +11.4 V to +12.6 V Operating ranges define those limits between which the functionality of the device is guaranteed. 2. Minimum DC input voltage on A9 and VPP pins is -0.5 V. During voltage transitions, A9 and VPP may overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on A9 and VPP is +13.0 V which may overshoot to 14.0 V for periods up to 20 ns. 3. No more than one output shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. Am28F512 21 MAXIMUM OVERSHOOT 20 ns 20 ns +0.8 V –0.5 V –2.0 V 20 ns 11561G-10 Maximum Negative Input Overshoot 20 ns VCC + 2.0 V VCC + 0.5 V 2.0 V 20 ns 20 ns 11561G-11 Maximum Positive Input Overshoot 20 ns 14.0 V 13.5 V VCC + 0.5 V 20 ns 20 ns 11561G-12 Maximum V PP Overshoot 22 Am28F512 DC CHARACTERISTICS over operating range unless otherwise specified TTL/NMOS Compatible Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit ILI Input Leakage Current V CC = VCC Max, VIN = VCC or VSS ±1.0 µA ILO Output Leakage Current V CC = VCC Max, VOUT = VCC or VSS ±1.0 µA ICCS VCC Standby Current VCC = VCC Max, CE# = VIH 0.2 1.0 mA ICC1 VCC Active Read Current VCC = VCC Max, CE# = VIL, OE# = VIH IOUT = 0 mA, at 6 MHz 20 30 mA ICC2 VCC Programming Current CE# = VIL Programming in Progress (Note 4) 20 30 mA ICC3 VCC Erase Current CE# = VIL Erasure in Progress (Note 4) 20 30 mA IPPS VPP Standby Current V PP = VPPL ±1.0 µA IPP1 VPP Read Current IPP2 VPP Programming Current VPP = VPPH Programming in Progress (Note 4) 10 30 mA IPP3 VPP Erase Current VPP = VPPH Erasure in Progress (Note 4) 10 30 mA VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 2.0 VCC + 0.5 V VOL Output Low Voltage I OL = 5.8 mA, VCC = VCC Min 0.45 V VOH1 Output High Voltage I OH = –2.5 mA, VCC = VCC Min 2.4 VID A9 Auto Select Voltage A9 = VID 11.5 IID A9 Auto Select Current A9 = VID Max, VCC = VCC Max VPPL VPP during Read-Only Operations Note: Erase/Program are inhibited when VPP = VPPL VPPH VLKO VPP = VPPH 70 200 µA VPP = VPPL ±1.0 V 13.0 V 50 µA 0.0 VCC +2.0 V VPP during Read/Write Operations 11.4 12.6 V Low VCC Lock-out Voltage 3.2 5 3.7 V Notes: 1. Caution: The Am28F512 must not be removed from (or inserted into) a socket when V CC or VPP is applied. If VCC ð 1.0 Volt, the voltage difference between VPP and VCC should not exceed 10.0 Volts. Also, the Am28F512 has a VPP rise time and fall time specification of 500 ns minimum. 2. ICC1 is tested with OE# = VIH to simulate open outputs. 3. Maximum active power usage is the sum of ICC and IPP. 4. Not 100% tested. Am28F512 23 DC CHARACTERISTICS CMOS Compatible Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit ILI Input Leakage Current VCC = VCC Max, VIN = VCC or VSS ±1.0 µA ILO Output Leakage Current VCC = VCC Max, VOUT = VCC or VSS ±1.0 µA ICCS VCC Standby Current VCC = VCC Max, CE# = VCC + 0.5 V 15 100 µA ICC1 VCC Active Read Current VCC = VCC Max, CE# = VIL, OE# = VIH IOUT = 0 mA, at 6 MHz 20 30 mA ICC2 VCC Programming Current CE# = VIL Programming in Progress (Note 4) 20 30 mA ICC3 VCC Erase Current CE# = VIL Erasure in Progress (Note 4) 20 30 mA IPPS VPP Standby Current VPP = VPPL ±1.0 µA IPP1 VPP Read Current VPP = VPPH 70 200 µA IPP2 VPP Programming Current VPP = VPPH Programming in Progress (Note 4) 10 30 mA IPP3 VPP Erase Current VPP = VPPH Erasure in Progress (Note 4) 10 30 mA VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 0.7 VCC VCC + 0.5 V VOL Output Low Voltage 0.45 V VOH1 Output High Voltage VOH2 IOL = 5.8 mA, VCC = VCC Min IOH = –2.5 mA, VCC = VCC Min 0.85 VCC IOH = –100 µA, V CC = VCC Min VCC –0.4 VID A9 Auto Select Voltage A9 = VID IID A9 Auto Select Current A9 = VID Max, VCC = VCC Max VPPL VPP during Read-Only Operations Note: Erase/Program are inhibited when VPP = VPPL VPPH VLKO V 11.5 13.0 V 50 µA 0.0 VCC + 2.0 V VPP during Read/Write Operations 11.4 12.6 V Low VCC Lock-out Voltage 3.2 5 3.7 V Notes: 1. Caution: The Am28F512 must not be removed from (or inserted into) a socket when VCC or VPP is applied. If VCC ð 1.0 volt, the voltage difference between VPP and VCC should not exceed 10.0 volts. Also, the Am28F512 has a V PP rise time and fall time specification of 500 ns minimum. 2. ICC1 is tested with OE# = VIH to simulate open outputs. 3. Maximum active power usage is the sum of ICC and IPP. 4. Not 100% tested. 24 Am28F512 25 ICC Active in mA 20 15 10 55°C 0°C 25°C 70°C 125°C 5 0 0 1 2 3 4 5 6 Frequency in MHz 7 8 9 10 11 12 11561G-13 Figure 5. Am28F512—Average ICC Active vs. Frequency VCC = 5.5 V, Addressing Pattern = Minmax Data Pattern = Checkerboard TEST CONDITIONS Table 6. Test Specifications 5.0 V Test Condition Output Load 2.7 kΩ Device Under Test Output Load Capacitance, CL (including jig capacitance) CL -70 Input Pulse Levels Note: Diodes are IN3064 or equivalent Unit 1 TTL gate 30 100 ≤10 Input Rise and Fall Times 6.2 kΩ All others pF ns 0.0–3.0 0.45–2.4 V Input timing measurement reference levels 1.5 0.8, 2.0 V Output timing measurement reference levels 1.5 0.8, 2.0 V 11561G-14 Figure 6. Test Setup Am28F512 25 SWITCHING TEST WAVEFORMS 3V 2.4 V 2.0 V 2.0 V Test Points 0.8 V Test Points 1.5 V 1.5 V 0.8 V 0V 0.45 V Input Input Output AC Testing (all speed options except -70): Inputs are driven at 2.4 V for a logic “1” and 0.45 V for a logic “0”. Input pulse rise and fall times are ≤10 ns. Output AC Testing for -70 devices: Inputs are driven at 3.0 V for a logic “1” and 0 V for a logic “0”. Input pulse rise and fall times are ≤10 ns. 11561G-15 SWITCHING CHARACTERISTICS over operating range unless otherwise specified AC Characteristics—Read Only Operation Parameter Symbols Am28F512 JEDEC Standard -70 -90 -120 -150 -200 Unit tAVAV tRC Read Cycle Time (Note 2) Min 70 90 120 150 200 ns tELQV tCE Chip Enable Access Time Max 70 90 120 150 200 ns tAVQV tACC Address Access Time Max 70 90 120 150 200 ns tGLQV tOE Output Enable Access Time Max 35 35 50 55 55 ns tELQX tLZ Chip Enable to Output in Low Z (Note 2) Min 0 0 0 0 0 ns tEHQZ tDF Chip Disable to Output in High Z (Note 1) Max 20 20 30 35 35 ns tGLQX tOLZ Output Enable to Output in Low Z (Note 2) Min 0 0 0 0 0 ns tGHQZ tDF Output Disable to Output in High Z (Note 2) Max 20 20 30 35 35 ns tAXQX tOH Output Hold from first of Address, CE#, or OE# Change (Note 2) Min 0 0 0 0 0 ns Write Recovery Time before Read Min 6 6 6 6 6 µs VCC Setup Time to Valid Read (Note 2) Min 50 50 50 50 50 µs tWHGL tVCS Parameter Description Notes: 1. Guaranteed by design not tested. 2. Not 100% tested. 26 Am28F512 AC Characteristics—Write/Erase/Program Operations Parameter Symbols Am28F512 Speed Options JEDEC Standard -70 -90 -120 -150 -200 Unit tAVAV tWC Write Cycle Time (Note 4) Min 70 90 120 150 200 ns tAVWL tAS Address Setup Time Min 0 0 0 0 0 ns tWLAX tAH Address Hold Time Min 45 45 50 60 75 ns tDVWH tDS Data Setup Time Min 45 45 50 50 50 ns tWHDX tDH Data Hold Time Min 10 10 10 10 10 ns tWHGL tWR Write Recovery Time before Read Min 6 6 6 6 6 µs Read Recovery Time before Write Min 0 0 0 0 0 µs tGHWL Parameter Description tELWL tCS Chip Enable Setup Time Min 0 0 0 0 0 ns tWHEH tCH Chip Enable Hold Time Min 0 0 0 0 0 ns tWLWH tWP Write Pulse Width Min 45 45 50 60 60 ns tWHWL tWPH Write Pulse Width HIGH Min 20 20 20 20 20 ns tWHWH1 Duration of Programming Operation (Note 2) Min 10 10 10 10 10 µs tWHWH2 Duration of Erase Operation (Note 2) Min 9.5 9.5 9.5 9.5 9.5 ms tVPEL VPP Setup Time to Chip Enable LOW (Note 4) Min 100 100 100 100 100 ns tVCS VCC Setup Time to Chip Enable LOW (Note 4) Min 50 50 50 50 50 µs tVPPR VPP Rise Time 90% VPPH (Note 4) Min 500 500 500 500 500 ns tVPPF VPP Fall Time 10% VPPL (Note 4) Min 500 500 500 500 500 ns tLKO VCC < VLKO to Reset (Note 4) Min 100 100 100 100 100 ns Notes: 1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC Characteristics for Read Only operations. 2. Maximum pulse widths not required because the on-chip program/erase stop timer will terminate the pulse widths internally on the device. 3. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of Chip-Enable and Write-Enable. In systems where Chip-Enable defines the Write Pulse Width (within a longer Write-Enable timing waveform) all setup, hold and inactive Write-Enable times should be measured relative to the Chip-Enable waveform. 4. Not 100% tested. Am28F512 27 KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Steady Changing from H to L Changing from L to H Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is High Impedance State (High Z) SWITCHING WAVEFORMS Power-up, Standby Device and Address Selection Outputs Enabled Data Valid Standby, Power-down Addresses Stable Addresses tAVAV (tRC) CE# (E#) tEHQZ (tDF) OE# (G#) tWHGL tGHQZ (tDF) WE# (W#) tGLQV (tOE) tELQV (tCE) tGLQX (tOLZ) tVCS High Z tAXQX (tOH) tELQX (tLZ) Output Valid Data (DQ) High Z tAVQV (tACC) 5.0 V VCC 0V 11561G-16 Figure 7. 28 AC Waveforms for Read Operations Am28F512 SWITCHING WAVEFORMS Power-up, Standby Setup Erase Command Erase Command Erasure Erase-Verify Command Erase Standby, Verification Power-down Addresses tAVAV (tWC) tWLAX (tAH) tAVWL (tAS) tAVAV (tRC) CE# (E)# tELWL (tCS) tEHQZ (tDF) tWHEH (tCH) OE# (G)# tWHWH2 tWHGL tGHQZ (tDF) tGHWL (tOES) tGLQV (tOE) WE# (W)# tWLWH (tWP) tDVWH (tDS) Data (DQ) 5.0 V VCC 0V HIGH Z tWHWL (tWPH) tGLQX (tOLZ) tAXQX (tOH) tWHDX (tDH) DATA IN = 20h DATA IN = 20h DATA IN = A0h VALID DATA OUT tELQX (tLZ) tELQV (tCE ) tVCS tVPEL VPPH VPP VPPL 11561G-17 Figure 8. AC Waveforms for Erase Operations Am28F512 29 SWITCHING WAVEFORMS Power-up, Standby Setup Program Command Program Command Verify Latch Address Programming Command and Data Programming Standby, Verification Power-down Addresses tAVAV (tWC) tAVWL (tAS) CE# (E#) tAVAV (tRC) tWLAX (tAH) tELWL (tCS) tGHQZ (tDF) tWHEH (tCH) OE# (G#) tWHWH1 tWHGL tGHQZ (tDF) tGHWL (tOES) tGLQV (tOE) WE# (W#) tWLWH (tWP) tDVWH (tDS) Data (DQ) 5.0 V VCC 0V tGLQX (tOLZ) tWHWL (t WPH) tWHDX (tDH) HIGH Z DATA IN = 40h DATA IN tAXQX (tOH) DATA IN = C0h VALID DATA OUT tELQX (tLZ) tELQV (tCE ) tVCS tVPEL VPPH VPP VPPL 11561G-18 Figure 9. AC Waveforms for Programmings Operations 30 Am28F512 ERASE AND PROGRAMMING PERFORMANCE Limits Typ (Note 1) Max (Note 2) Unit Chip Erase Time 1 10 sec Excludes 00H programming prior to erasure Chip Programming Time 1 6 sec Excludes system-level overhead Parameter Min Write/Erase Cycles 10,000 Comments Cycles Notes: 1. 25°C, 12 V VPP. 2. Maximum time specified is lower than worst case. Worst case is derived from the Flasherase/Flashrite pulse count (Flasherase = 1000 max and Flashrite = 25 max). Typical worst case for program and erase is significantly less than the actual device limit. LATCHUP CHARACTERISTICS Parameter Min Max Input Voltage with respect to VSS on all pins except I/O pins (Including A9 and VPP) –1.0 V 13.5 V Input Voltage with respect to VSS on all pins I/O pins –1.0 V VCC + 1.0 V –100 mA +100 mA Current Includes all pins except VCC. Test conditions: VCC = 5.0 V, one pin at a time. PIN CAPACITANCE Parameter Symbol Parameter Description Test Conditions Typ Max Unit Input Capacitance VIN = 0 8 10 pF COUT Output Capacitance VOUT = 0 8 12 pF CIN2 VPP Input Capacitance VPP = 0 8 12 pF CIN Note: Sampled, not 100% tested. Test conditions TA = 25°C, f = 1.0 MHz. DATA RETENTION Parameter Test Conditions Min Unit 150°C 10 Years 125°C 20 Years Minimum Pattern Data Retention Time Am28F512 31 PHYSICAL DIMENSIONS PD032—32-Pin Plastic DIP (measured in inches) 1.640 1.670 .600 .625 17 32 .009 .015 .530 .580 Pin 1 I.D. .630 .700 16 .045 .065 0° 10° .005 MIN .140 .225 16-038-S_AG PD 032 EC75 5-28-97 lv SEATING PLANE .090 .110 .120 .160 .016 .022 .015 .060 PL032—32-Pin Plastic Leaded Chip Carrier (measured in inches) .447 .453 .485 .495 .009 .015 .585 .595 .042 .056 .125 .140 Pin 1 I.D. .080 .095 .547 .553 SEATING PLANE .400 REF. .490 .530 .013 .021 .050 REF. .026 .032 TOP VIEW 32 SIDE VIEW Am28F512 16-038FPO-5 PL 032 DA79 6-28-94 ae PHYSICAL DIMENSIONS TS032—32-Pin Standard Thin Small Outline Package (measured in millimeters) 0.95 1.05 Pin 1 I.D. 1 7.90 8.10 0.50 BSC 0.05 0.15 18.30 18.50 19.80 20.20 0.08 0.20 0.10 0.21 1.20 MAX 0° 5° 16-038-TSOP-2 TS 032 DA95 3-25-97 lv 0.50 0.70 Am28F512 33 PHYSICAL DIMENSIONS TSR032—32-Pin Reversed Thin Small Outline Package (measured in millimeters) 0.95 1.05 Pin 1 I.D. 1 0.17 0.27 7.90 8.10 0.50 BSC 0.05 0.15 18.30 18.50 19.80 20.20 0.08 0.20 0.10 0.21 1.20 MAX 0° 5° 0.50 0.70 34 Am28F512 16-038-TSOP-2 TSR032 DA95 8-15-96 lv DATA SHEET REVISION SUMMARY FOR AM28F512 Deleted -75, -95, and -250 speed options. Matched formatting to other current data sheets. Amendment G+1 Removed reference to LCC package in Distinctive Characteristics. Added A15 to PLCC and PDIP connection diagrams. Figure 3, Flashrite Programming Algorithm: Moved end of arrow originating from Increment Address box so that it points to the PLSCNT = 0 box, not the Write Program Verify Command box. This is a correction to the diagram on page 6-189 of the 1998 Flash Memory Data Book. Revision G+2 Programming In A PROM Programmer: Deleted the paragraph “(Refer to the AUTO SELECT paragraph in the ERASE, PROGRAM, and READ MODE section for programming the Flash memory device in-system).” Trademarks Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved. ExpressFlash is a trademark of Advanced Micro Devices, Inc. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Am28F512 35