Infineon ADM6918 18 port 10/100 mbps ethernet switch controller Datasheet

Data Sheet, Rev 1.01, Nov. 2005
ADM6918/X
18 port 10/100 Mbps Ethernet Switch Controller
ADM6918/X
Communications
N e v e r
s t o p
t h i n k i n g .
Edition 2005-11-08
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2005.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
18 port 10/100 Mbps Ethernet Switch Controller
Revision History: 2005-11-08, Rev 1.01
Previous Version:
Page/Date
Subjects (major changes since last revision)
2003-11-25 Rev. 1.0: First release of ADM6918/X
2005-09-09 Changed to the new Infineon format
2005-09-09 Rev. 1.0 changed to Rev. 1.01
2005-11-03 Minor change. Included Green package information
Trademarks
ABM®, ACE®, AOP®, ARCOFI®, ASM®, ASP®, DigiTape®, DuSLIC®, EPIC®, ELIC®, FALC®, GEMINAX®, IDEC®,
INCA®, IOM®, IPAT®-2, ISAC®, ITAC®, IWE®, IWORX®, MUSAC®, MuSLIC®, OCTAT®, OptiPort®, POTSWIRE®,
QUAT®, QuadFALC®, SCOUT®, SICAT®, SICOFI®, SIDEC®, SLICOFI®, SMINT®, SOCRATES®, VINETIC®,
10BaseV®, 10BaseVX® are registered trademarks of Infineon Technologies AG. 10BaseS™, EasyPort™,
VDSLite™ are trademarks of Infineon Technologies AG. Microsoft® is a registered trademark of Microsoft
Corporation, Linux® of Linus Torvalds, Visio® of Visio Corporation, and FrameMaker® of Adobe Systems
Incorporated.
Template: template_A4_3.0.fm / 3 / 2005-01-17
ADM6918/X
Table of Contents
Table of Contents
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1
1.1
1.2
1.3
1.4
1.5
Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Data Lengths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2
2.1
2.2
2.3
Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Diagram-ADM6918/X (SS-SMII Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
11
11
12
3
Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.1
Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.2
Address Learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.3
Address Aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.4
Address Recognition and Packet Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.5
Trunking Port Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.6
Illegal Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.7
Back off Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.8
Buffers and Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.9
Half Duplex Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.10
Full Duplex Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.11
Inter-Packet Gap (IPG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.12
Port VLAN or Tag VLAN Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.13
Priority Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.14
Alert LED Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.15
Broadcast Storm Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.16
Collision LED Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.17
Bandwidth Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.18
Smart Discard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.19
Security Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.20
Smart Counter Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.21
Length 1536 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.22
PHY Management (MDC/MDIO Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.23
Forward Special Packets to the CPU Port (IGMP and Spanning Tree Support) . . . . . . . . . . . . . . .
3.1.24
Special TAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.25
Port 24 and Port 25 Interface (Only SS-SMII Package Support) . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.26
Hardware, EEPROM and SMI Interface for Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.26.1
Hardware Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.26.2
EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.26.3
SMI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
18
18
18
19
19
20
20
20
21
21
21
21
21
22
22
23
23
23
23
23
23
24
24
24
24
26
27
27
29
29
4
4.1
EEPROM Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
EEPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Data Sheet
4
Rev 1.01, 2005-11-08
ADM6918/X
Table of Contents
4.1.1
EEPROM Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5
5.1
5.1.1
Switch Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Switch Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Switch Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6
6.1
6.1.1
6.1.2
6.1.3
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.2.9
6.2.10
6.2.11
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Electrical Characteristics for 3.3 V Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XI/OSCI (Crystal/Oscillator) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EEPROM Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10Base-TX MII Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10Base-TX MII Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100Base-TX MII Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100Base-TX MII Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reduced MII Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SS_SMII Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SS_SMII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Management Interface (SDC/SDIO) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Data Sheet
5
113
113
113
113
113
114
114
114
115
116
116
117
118
119
120
121
122
Rev 1.01, 2005-11-08
ADM6918/X
List of Figures
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Data Sheet
ADM6918/X Block Diagram 10
ADM6918/X Pin Diagram (SS-SMII Interface) 11
Packet Format 25
MII Interface Diagram 26
RMII Interface 27
Hardware, EEPROM and SMI Interface Configuration 27
Read 93c66 via the EEPROM Interface (Index = 2, Data = 16’h1111) 29
Write EEPROM Registers in the ADM6918/X (Index = 2, Data = 16’h2222) 29
Read Switch Register via SMI Interface 30
Write Switch Register via SMI Interface 30
The Search Pointer 94
Address Table Mapping to Output Port MAP 96
Crystal/Oscillator Timing 114
Power on Reset Timing 115
EEPROM Interface Timing 115
10Base-TX MII Output Timing 116
10Base-TX MII Input Timing 117
100Base-TX MII Output Timing 118
100Base-TX MII Input Timing 118
Reduced MII Timing (1 of 2) 119
Reduced MII Timing (2 of 2) 119
SS_SMII Transmit Timing 120
SS_SMII Receive Timing 121
Serial Management Interface (SDC/SDIO) Timing 122
ADM6918/X Packaging 123
6
Rev 1.01, 2005-11-08
ADM6918/X
List of Tables
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
Table 26
Table 27
Table 28
Table 29
Table 30
Table 31
Table 32
Table 33
Table 34
Table 35
Table 36
Table 37
Table 38
Table 39
Table 40
Table 41
Table 42
Table 43
Table 44
Table 45
Table 46
Table 47
Table 48
Table 49
Data Sheet
Abbreviations for Pin Type 12
Abbreviations for Buffer Type 12
I/O Signals 13
Address Recognition and Packet Forwarding 19
Packets Received are Untagged 21
Packets Received are Tagged 21
Port Rising Threshold 22
Port Falling Threshold 23
Discard Ratio 23
Special TAG Fields 25
SS-SMII and RMII Pins 27
Port 24 Duplex Configuration 28
Port 25 Duplex Configuration 28
Pin Type of EECS, EESK, EDI and EDO during Operation 30
EEPROM Format 31
Registers Address Space 36
Registers Overview 36
Register Access Types 40
Registers Clock DomainsRegisters Clock Domains 41
PCR_x Registers 46
Resx Registers 47
FGOPML_x Registers 51
FGOPMH_x Registers 53
Px_VID Registers 56
Switch Register Map 85
Registers Address SpaceRegisters Address Space 86
Registers Overview 86
Register Access Types 86
Registers Clock DomainsRegisters Clock Domains 87
Control Register Description 91
Field Description in the Control Register 91
Status Register Description 92
Field Description in the Status Register 93
Example 94
Control Register Description 95
Field Description in the Control Register 95
Status Register Description 96
Field Description in the Status Register 96
Example 97
Counter Register: Offset 0100H ~ 0167H 109
Electrical Absolute Maximum Ratings 113
Recommended Operating Conditions 113
DC Electrical Characteristics for 3.3 V Operation 113
Crystal/Oscillator Timing 114
Power on Reset Timing 115
EEPROM Interface Timing 115
10Base-TX MII Output Timing 116
10Base-TX MII Input Timing 117
100Base-TX MII Output Timing 118
7
Rev 1.01, 2005-11-08
ADM6918/X
List of Tables
Table 50
Table 51
Table 52
Table 53
Table 54
Data Sheet
100Base-TX MII Input Timing 119
Reduced MII Timing 120
SS_SMII Transmit Timing 120
SS_SMII Receive Timing 121
Serial Management Interface (SDC/SDIO) Timing 122
8
Rev 1.01, 2005-11-08
ADM6918/X
Product Overview
1
Product Overview
1.1
Overview
The ADM6918/X is a high performance/low cost, eighteen-port 10/100 Mbps Ethernet Switch Controller with all
ports supporting 10/100 Mbps full duplex switch function. The ADM6918/X is intended for applications to stand
alone the bridge for the low cost ether-switch market. The ADM6918X is the environmentally friendly “green”
package version. ADM6918/X can be programmed trunking port active. The trunking port can be connected to
server or stacking two switch boxes to enhance the performance.
The ADM6918/X also supports back-pressure in half duplex mode and 802.3x flow control in full duplex mode.
When back-pressure is enabled, and there is no receiving buffer available for the incoming packet, the
ADM6918/X will force a JAM pattern on the receiving port in half duplex mode and transmit the 802.3x packet back
to receiving end in full duplex mode.
An intelligent address recognition algorithm makes ADM6918/X to recognize up to 4096 different MAC addresses
and enables filtering and forwarding at full wire speed.
The ADM6918/X has embedded SRAM for the proprietary buffer management. The SRAM is used to store the
incoming/outgoing packets. These buffers provide elastic storage for transferring data between low-speed and
high-speed segments and buffers are efficiently allocated to improve the efficiency.
1.2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Features
Supports sixteen 10/100M auto-detect Half/Full duplex switch ports with SS-SMII interface and two 10/100M
Half/Full duplex port with RMII/MII interface
Supports up to 4096 MAC addresses table (4-way hashing)
Supports two queue for QOS (1:2 or 1:4 or 1:8 or 1:16)
Supports Port-base, 802.1p and IP TOS priority
Supports store & forward architecture and Performs forwarding and filtering at non-blocking full wire speed
Supports buffer allocation with 256 bytes each
Supports aging function and 802.3x flow control for full duplex and back-pressure function for half duplex
operation in case buffer is full
Supports packet length up to 1536 bytes
Supports Congestion Flow Control
Broadcast storm filter and Alert LED
Port-base VLAN and adjustable VLAN to support up to 32 VLAN group
Serial CPU interface for counter and port status output
CPU can see-through to access PHY
Flexible port trunking on fault tolerance and load balance
Per port 32bits smart counter for Rx/Tx byte/packet count, error count and collision count
Rate-limit control (64K/128K/256K/512K/1M/4M/10M/20M)
Per port auto learning enable/disable and if disable, forward non-learned packet to CPU]
MAC address table accessible (in each entry, reserve one bit for CPU to enable/disable aging out)
Forward special multicast, BPDU, GMRP, GVRP and IGMP packets to CPU port
128 pin QFP package with 3.3 V/1.8V power supply
1.3
Data Sheet
Package Information
9
Rev 1.01, 2005-11-08
ADM6918/X
Product Overview
Product Name
Product Type
Package
Ordering Number
Ethernet Switch Controller
ADM6918/X
P-FQFP-128-1
Q67801H 70A2021)
1) contact Infineon for the updated ordering information
1.4
•
•
•
•
•
Data Lengths
qword: 64-bits
dword: 32-bits
word: 16-bits
byte: 8 bits
nibble: 4 bits
1.5
Block Diagram
˖˿̂˶˾˂
˟˘˗
˜́̇˸̅˹˴˶˸
Embedded Memory
Memory
BIST
Switching Fabric
EEPROM
Control
ˌˆ˖ˉˉ
˜́̇˸̅˹˴˶˸
10/100M
ˠ˜˜˂˥ˠ˜˜
˜́̇˸̅˹˴˶˸
10/100M
10/100M
MAC
MAC
ˁˁˁ
10/100M
10/100M
MAC
MAC
MAC
CLOCK
GENERATOR
Interface Convertor
PHY Control
ˠ˗˖˂
ˠ˗˜ˢ
BIAS
˦˦ˀ˦ˠ˜˜
˜́̇˸̅˹˴˶˸
Figure 1
Data Sheet
ADM6918/X Block Diagram
10
Rev 1.01, 2005-11-08
ADM6918/X
Interface Description
2
Interface Description
2.1
Pin Diagram-ADM6918/X (SS-SMII Interface)
ˉˈ
ˉˉ
GND
VCCIK
GNDIK
M0CRS
M0COL
NC
GND
NC
GND
ALERT
STXD0[0]
EECS
SRXD0[0]
STXD0[1]
SRXD0[1]
STXD0[2]
NC
RESETL
GND
GND
VCC3O
GNDO
SRXD0[2]
SYNC_TX0
STXD0[3]
SYNC_RX0
SRXD0[3]
CLK_TX0
NC
NC
GND
GND
ADM6918
GNDO
VCC3O
GNDIK
VCCIK
STXD0[4]
CLK_RX0
SRXD0[4]
VCCIK
NC
NC
GND
NC
GNDIK
STXD0[5]
SRXD0[5]
STXD0[6]
GND
NC
GND
NC
SRXD0[6]
STXD0[7]
VCC3O
Figure 2
ADM6918/X Pin Diagram (SS-SMII Interface)
2.2
Abbreviations
ˉˇ
ˉˆ
ˉ˅
ˉ˄
ˉ˃
ˈˌ
ˈˋ
ˈˊ
ˈˉ
ˈˈ
ˈˇ
ˈˆ
ˈ˅
ˈ˄
ˈ˃
ˇˌ
ˇˋ
ˇˊ
ˇˉ
ˇˈ
ˇˇ
ˇˆ
ˇ˅
VCCIK
GNDIK
SRXD1[5]
STXD1[6]
SRXD1[6]
ˇ˄
ˇ˃
ˆˌ
ˆˈ
ˆˉ
ˆˊ
ˆˋ
SYNC_RX1
SRXD1[3]
CLK_TX1
VCC3O
GNDO
STXD1[4]
CLK_RX1
SRXD1[4]
STXD1[5]
˅ˉ
˅ˊ
˅ˋ
˅ˌ
ˆ˃
ˆ˄
ˆ˅
ˆˆ
ˆˇ
˅˃
˅˄
˅˅
˅ˆ
˅ˇ
˅ˈ
˄ˌ
GNDPLL
SYNC_TX1
STXD1[3]
MDC
MDIO
TEST2
XI
XO
TEST1
˄ˆ
˄ˇ
˄ˈ
˄ˉ
˄ˊ
˄ˋ
ˌ
˄˃
˄˄
˄˅
ˉ
ˊ
ˋ
˄
˅
ˆ
ˇ
ˈ
CKO25M
SRXD1[1]
STXD1[2]
SRXD1[2]
VCCRG
GNDRG
VREF
CONTROL
VCCPLL
SRXD1[7]
STXD1[7]
GNDO
SRXD0[7]
STXD1[0]
SRXD1[0]
CKO50M
STXD1[1]
˄˅ˇ
˄˅ˈ
˄˅ˉ
˄˅ˊ
˄˅ˋ
ˉˊ
ˉˋ
ˉˌ
ˊ˃
ˊ˄
ˊ˅
ˊˆ
ˊˇ
ˊˈ
˄˅˃
˄˅˄
˄˅˅
˄˅ˆ
M0TXD[3]
M0TXD[2]
M0TXD[1]
M0TXD[0]
M0TXEN
M0TXCLK
M0RXCLK
M0RXDV
˄˄ˉ
˄˄ˊ
˄˄ˋ
˄˄ˌ
ˊˉ
ˊˊ
ˊˋ
ˊˌ
ˋ˃
ˋ˄
ˋ˅
ˋˆ
˄˄˅
˄˄ˆ
˄˄ˇ
˄˄ˈ
VCC3O
GNDO
M0RXD[0]
M0RXD[1]
M0RXD[2]
M0RXD[3]
M1CRS
M1COL
M1TXD[3]
˄˃ˋ
˄˃ˌ
˄˄˃
˄˄˄
M1TXD[2]
M1TXD[1]
M1TXD[0]
VCCIK
GNDIK
M1TXEN
M1TXCLK
M1RXCLK
M1RXDV
M1RXD[0]
M1RXD[1]
M1RXD[2]
M1RXD[3]
EESK
EDI
EDO
˄˃ˇ
˄˃ˈ
˄˃ˉ
˄˃ˊ
ˋˇ
ˋˈ
ˋˉ
ˋˊ
ˋˋ
ˋˌ
ˌ˃
ˌ˄
ˌ˅
ˌˆ
ˌˇ
ˌˈ
ˌˉ
ˌˊ
ˌˋ
ˌˌ
˄˃˃
˄˃˄
˄˃˅
˄˃ˆ
Standard abbreviations for I/O tables:
Data Sheet
11
Rev 1.01, 2005-11-08
ADM6918/X
Interface Description
Table 1
Abbreviations for Pin Type
Abbreviations
Description
I
Standard input-only pin. Digital levels.
O
Output. Digital levels.
I/O
I/O is a bidirectional input/output signal.
AI
Input. Analog levels.
AO
Output. Analog levels.
AI/O
Input or Output. Analog levels.
PWR
Power
GND
Ground
MCL
Must be connected to Low (JEDEC Standard)
MCH
Must be connected to High (JEDEC Standard)
NU
Not Usable (JEDEC Standard)
NC
Not Connected (JEDEC Standard)
Table 2
Abbreviations for Buffer Type
Abbreviations
Description
Z
High impedance
PU1
Pull up, 10 kΩ
PD1
Pull down, 10 kΩ
PD2
Pull down, 20 kΩ
TS
Tristate capability: The corresponding pin has 3 operational states: Low, high and highimpedance.
OD
Open Drain. The corresponding pin has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR. An external pull-up is required to sustain the
inactive state until another agent drives it, and must be provided by the central resource.
OC
Open Collector
PP
Push-Pull. The corresponding pin has 2 operational states: Active-low and active-high
(identical to output with no type attribute).
OD/PP
Open-Drain or Push-Pull. The corresponding pin can be configured either as an output with
the OD attribute or as an output with the PP attribute.
ST
Schmitt-Trigger characteristics
TTL
TTL characteristics
2.3
Pin Description
ADM6918/X pins are categorized into one of the following groups:
•
•
•
•
SS-SMII Networking Interface, 60 pins
MII/RMII Interface, 28 pins
Power/Ground
Miscellaneous pins, 16 pins
Data Sheet
12
Rev 1.01, 2005-11-08
ADM6918/X
Interface Description
Table 3
Pin or Ball
No.
I/O Signals
Name
Pin
Type
Buffer
Type
Function
I
TTL
Port 0 to Port 7 SS-SMII Receive Data Bit
The receive data should be synchronous to the rising edge
of CLK_RX0.
SS-SMII Networking Interface, 60 pins
106
SRXD0_0
108
SRXD0_1
112
SRXD0_2
116
SRXD0_3
120
SRXD0_4
124
SRXD0_5
126
SRXD0_6
2
SRXD0_7
115
SYNC_RX0
I
TTL
Port 0 to Port 7 SS-SMII Synchronous Signal
This signal is synchronous to the rising edge of CLK_RX0.
Active high indicates the byte boundary.
119
CLK_RX0
I
TTL
Reference Receive Clock for Port 0 to Port 7
This signal is 125 MHz input for SS-SMII interface.
104
STXD0_0
O
107
STXD0_1
TTL,
8 mA
109
STXD0_2
Port 0 to Port 7 SS-SMII Transmit Data Bit
The transmit data is synchronous to the rising edge of
CLK_TX0.
114
STXD0_3
118
STXD0_4
123
STXD0_5
125
STXD0_6
127
STXD0_7
113
SYNC_TX0
O
TTL,
8 mA
Port 0 to Port 7 SS-SMII Synchronous Signal
This signal is synchronous to the rising edge of CLK_TX0.
Active high indicates the byte boundary.
117
CLK_TX0
O
TTL,
16 mA
Reference Transmit Clock for Port 0 to Port 7
This signal is 125 MHz output for SS-SMII interface.
4
SRXD1_0
I
TTL
8
SRXD1_1
10
SRXD1_2
Port 8 to Port 15 SS-SMII Receive Data Bit
The receive data should be synchronous to the rising edge
of CLK_RX1.
26
SRXD1_3
32
SRXD1_4
36
SRXD1_5
38
SRXD1_6
40
SRXD1_7
25
SYNC_RX1
I
TTL
Port 8 to Port 15 SS-SMII Synchronous Signal
This signal is synchronous to the rising edge of CLK_RX1.
Active high indicates the byte boundary.
31
CLK_RX1
I
TTL
Reference Receive Clock for Port 8 to Port 15
This signal is 125 MHz input for SS-SMII interface.
Data Sheet
13
Rev 1.01, 2005-11-08
ADM6918/X
Interface Description
Table 3
I/O Signals (cont’d)
Pin or Ball
No.
Name
Pin
Type
Buffer
Type
Function
3
STXD1_0
O
6
STXD1_1
TTL,
8 mA
9
STXD1_2
Port 8 to Port 15 SS-SMII Transmit Data Bit
The transmit data is synchronous to the rising edge of
CLK_TX1.
18
STXD1_3
30
STXD1_4
33
STXD1_5
37
STXD1_6
39
STXD1_7
17
SYNC_TX1
O
TTL,
8 mA
Port 8 to Port 15 SS-SMII Synchronous Signal
This signal is synchronous to the rising edge of CLK_TX1.
Active high indicates the byte boundary.
27
CLK_TX1
O
TTL,
16 mA
Reference Transmit Clock for Port 8 to Port 15
This signal is 125 MHz output for SS-SMII interface.
MII/RMII Interface, 28 pins
68
M0CRS
I
TTL, PD
MII Port0 Carrier Sense
This pin is internal pull-down.
69
M0COL
I
TTL, PD
MII Port0 Collision Input
This pin is internal pull-down.
73
M0TXD_0
I/O
72
M0TXD_1
71
M0TXD_2
70
M0TXD_3
TTL,
MII Port 0 Transmit Data Bit[0:3]
8 mA, PD Synchronous to the rising edge of M0TXCLK.
RMII Port 0 Transmit Data Bit[0:1]
Synchronous to the rising edge of M0RXCLK.
RMIIMODE[1]: Value on M0TXD_3 will be latched at the
rising edge of RESETL to configure port 25 as RMII mode.
RMIIMODE[0]: Value on M0TXD[2] will be latched at the
rising edge of RESETL to configure port 24 as RMII mode.
74
M0TXEN
I/O
TTL,
MII/RMII Port 0 Transmit Enable
8 mA, PD AGDIS. Value on this pin will be latched at the rising edge
of RESETL to set aging disable.
75
M0TXCLK
I
TTL, PD
MII Port 0 Transmit Clock Input
This pin is 25 MHz input for MII interface.
76
M0RXCLK
I
TTL, PD
MII/RMII Port 0 Receive Clock Input
This pin is 25 MHz input for MII interface and 50 MHz
REFCLK input for RMII interface.
77
M0RXDV
I
TTL, PD
MII Port 0 Receive Data Valid
RMII Port 0 Carrier Sense/Receive Data Valid
This pin is internal pull-down.
80
M0RXD_0
I
TTL, PD
81
M0RXD_1
82
M0RXD_2
83
M0RXD_3
MII Port 0 Receive Data Bit[0:3]
RMII Port 0 Receive Data Bit[0:1]
If in RMII mode, M0RXD_3 used for ext_dup_enable and
M0RXD_2 used for ext_dup_full. Internal pull-down. See
Sec3.1.27 for details.
84
M1CRS
I
TTL, PD
MII Port 1 Carrier Sense
This pin is internal pull-down.
Data Sheet
14
Rev 1.01, 2005-11-08
ADM6918/X
Interface Description
Table 3
I/O Signals (cont’d)
Pin or Ball
No.
Name
Pin
Type
Buffer
Type
Function
85
M1COL
I
TTL, PD
MII Port 1 Collision Input
This pin is internal pull-down.
89
M1TXD_0
I/O
88
M1TXD_1
TTL,
8 mA
87
M1TXD_2
86
M1TXD_3
MII Port 1Transmit Data Bit[0:3]
Synchronous to the rising edge of M1TXCLK.
RMII Port 1Transmit Data Bit[0:1]
Synchronous to the rising edge of M1RXCLK.
BPEN. Value on M1TXD[3] will be latched at the rising
edge of RESETL to set Back_pressure enable. Internal
pull-up.
FCEN. Value on M1TXD[2] will be latched at the rising edge
of RESETL to set flow control enable. Internal pull-up.
TNKEN. Value on M1TXD[1] will be latched at the rising
edge of RESETL to set trunking enable. Internal pull-up.
IPGLVING. Value on M1TXD[0] will be latched at the rising
edge of RESETL to set shorter IPG. Internal pull-down.
92
M1TXEN
O
TTL,
MII Port 1 Transmit Enable
8 mA, PU ANEN. Value on this pin will be latched at the rising edge of
RESETL to set auto_negotiation enable. Internal pull-up.
93
M1TXCLK
I
TTL, PD
MII Port1 Transmit Clock Input
This signal is 25 MHz input for MII interface.
94
M1RXCLK
I
TTL, PD
MII1 Receive Clock Input
This signal is 25 MHz input for MII interface and 50 MHz
REFCLK input for RMII interface.
95
M1RXDV
I
TTL, PD
MII/RMII Port 1 Receive Data Valid
This pin is internal pull-down.
96
M1RXD_0
I
TTL PD
97
M1RXD_1
98
M1RXD_2
99
M1RXD_3
MII Port 1 Receive Data Bit[0:3]
RMII Port 1 Receive Data Bit[0:1]
If in RMII mode, M1RXD_3 used for ext_dup_enable and
M1RXD_2 used for ext_dup_full. Internal pull-down. See
Sec3.1.27 for details.
Power/Ground
12
GNDRG
Analog –
GND
Ground for Regulator
11
VCCRG
Analog –
PWR
3.3 V Power Supply for Regulator
16
GNDPLL
Analog –
GND
Ground for PLL
15
VCCPLL
Analog –
PWR
1.8 V Power Supply PLL
35, 50, 67,
91, 122
GNDIK
Digital
GND
–
Ground for Core Logic
34, 49, 66,
90, 121
VCCIK
Digital
PWR
–
1.8 V Power Supply for Core Logic
1, 29, 52, 79, GNDO
111
Digital
GND
–
Ground for I/O PAD
Data Sheet
15
Rev 1.01, 2005-11-08
ADM6918/X
Interface Description
Table 3
I/O Signals (cont’d)
Pin or Ball
No.
Name
Pin
Type
Buffer
Type
Function
28, 51, 78,
110, 128
VCC3O
Digital
PWR
–
3.3 V Power Supply for I/O PAD
Miscellaneous Pins, 16 pins
7
CK25MO
O
TTL,
16 mA
25 MHz Clock Output
This pin will drive out 25 MHz.
5
CK50MO
O
TTL,
16 mA
50 MHz Clock Output
This pin will drive out 50 MHz.
COL_LED_10M
O
TTL,
16 mA
COL_LED_10M
This pin shows collision LED for 10M domain (see
EEPROM Register 1ch, Bit[9]).
22
XI
AI
–
Crystal or OSC 50 MHz Input
This is the clock source of PLL. The PLL will generate
125 MHz for SS-SMII and 50 MHz for RMII and 25 MHz for
MII.
23
XO
AO
–
Crystal 50 MHz Output
59
RESETL
I
TTL, ST
Reset Signal
An active low signal with minimum 100 ms duration is
required.
103
ALERT
O
TTL,
8 mA
Alert LED Display
This pin will show the status of power-on-diagnostic and
broadcast traffic.
COL_LED_100
M
O
TTL,
8 mA
COL_LED_100M
This pin shows collision LED for 100M domain (see
EEPROM Register 1ch, Bit[9]).
21
TEST_2
I
TTL, PD
24
TEST_1
Industrial Test Pins
These pins are internal pull-down.
19
MDC
O
TTL,
16 mA
Management Data Clock
This pin output 2.2 MHz clock to drive PHY and access
corresponding speed and duplex and link status through
MDIO.
20
MDIO
I/O
TTL,
Management Data
8 mA, PU This pin is in-out to PHY. When RESETL is low, this pin will
be tristate. This pin is internal pull-up.
100
EESK
I/O
TTL,
EEPROM Serial Clock
4 mA, PU This pin is clock source for EEPROM. When RESETL is
low, it will be tristate. This pin is internal pull-up.
105
EECS
I/O
TTL,
EEPROM Chip Select
4 mA, PD This pin is chip enable for EEPROM. When RESETL is low,
it will be tristate. This pin is internal pull-down.
101
EDI
I/O
TTL,
EEPROM Serial Data Input
4 mA, PU This pin is output for serial data transfer. When RESETL is
low, it will be tristate. This pin is internal pull-up.
Data Sheet
16
Rev 1.01, 2005-11-08
ADM6918/X
Interface Description
Table 3
I/O Signals (cont’d)
Pin or Ball
No.
Name
Pin
Type
Buffer
Type
Function
102
EDO
I
TTL, PU
EEPROM Serial Data Output
This pin is input for serial data transfer. This pin is internal
pull-up.
14
CONTROL
AO
–
FET Control Signal
The pin is used to control FET for 3.3 V to 1.8 V regulator.
13
VREF
AI
–
Regulator Control Input Signal
64, 62, 60,
55, 56, 47,
48, 45, 43,
41
NC
No Connect
65, 63, 61,
58, 57, 53,
54, 46, 44,
42
GND
Ground
Data Sheet
17
Rev 1.01, 2005-11-08
ADM6918/X
Function Description
3
Function Description
3.1
Introduction
The ADM6918/X uses a “store & forward” switching approach for the following reasons:
1. Store & forward switches allow switching between different speed media (e.g. 10BaseX and 100BaseX). Such
switches require the large elastic buffers, especially bridging between a server on a 100Mbit/s network and
clients on a 10 Mbit/s segment.
2. Store & forward switches improve overall network performance by acting as a “network cache”.
3. Store & forward switches prevent the forwarding of corrupted packets by the frame check sequence (FCS)
before forwarding to the destination port.
3.1.1
Basic Operation
The ADM6918/X receives incoming packets from one of its ports, uses the source address (SA) and VID to update
the address table, and then forwards the packet to the output ports determined by the destination address (DA)
and VID.
If the DA and VID are not found in the address table, the ADM6918/X treats the packet as a broadcast packet and
forwards the packet to the other ports within the same group.
The ADM6918/X automatically learns the port number of attached network devices by examining the SA and VID
of all incoming packets. If the SA and VID are not found in the address table, the device adds it to the table.
3.1.2
Address Learning
The ADM6918/X provides two ways to create the entry in the address table: dynamic learning and manual
learning. A four-way hash algorithm is implemented to allow 4 different addresses to be stored at the same
location. Up to 4k entries can be created and all entries are stored in the internal SSRAM. Two parameters, SA
and VID, are combined to generate the 10-bit hash key to allow that the same addresses with different port number
can exist in the table at the same time.
Dynamic Learning
The ADM6918/X searches for SA and VID of an incoming packet in the address table and acts as follows:
If the SA+VID was not found in the address table (a new address), the ADM6918/X waits until the end of the packet
(non-error packet) and updates the address table. If the SA+VID was found in the address table, then aging value
of each corresponding entry will be reset to 0.
Dynamic learning will be disabled in the following condition:
1.
2.
3.
4.
5.
Security violation happened.
The packet is a PAUSE frame.
The first bit of SA is 1B.
The packet is an error packet (too long, too short or FCS error).
The CPU port leaning function is disabled or enabled but the CPU port instructs the switch not to learn the
packet.
6. The port is in the Disabled or Blocking-not-Listening state in the Spanning Tree Protocol.
Manual Learning
The ADM6918/X implements the manual learning through the CPU’s help. The CPU can create or remove any
entry in the address table. Each entry could be static or pointed to the output port map table. “Static” means the
entry will not be aged forever. It is useful in the security function (forward unknown packets to the CPU port or
discard) or monitor function (forward monitored address to the specific port). Output port map table is also helpful
Data Sheet
18
Rev 1.01, 2005-11-08
ADM6918/X
Function Description
in the IGMP function (if the number of the output port is more than one) or the users want to redirect the special
packets with reserved DA.
3.1.3
Address Aging
The ADM6918/X will periodically (300 ms) remove the non-static address in the address table. This could help to
prevent a station leaves the network and occupies a table space for a long time. Aging function can be disabled
from the hardware pin.
3.1.4
Address Recognition and Packet Forwarding
The ADM6918/X forwards the incoming packets between bridge ports according to the DA and VID as follows:
Table 4
Address Recognition and Packet Forwarding
DA
DA+VID was found in the
address table (entry not
pointed to the output
port map table)
Unicast Address
No Security Violation
Forward packets to the
port determined by the
address table. The packet
may be dropped because
of forwarding group
boundary violation.
DA+VID was found in the DA+VID was not found in
address table (entry
the address table
pointed to the output
port map table)
Forward packets to the
ports determined by the
output port map table
constrained by the
forwarding group.
Forward packets to the
other ports within the same
forwarding group.
Drop or forward to CPU
Drop or forward to CPU
Security Violation
Drop or forward to CPU
Broadcast Address
(All 1’b1)
No Security Violation
Forwarding packets to the Forward packets to the
other ports within the same ports determined by the
forwarding group.
output port map table
constrained by the
forwarding group.
Forward packets to the
other ports within the same
forwarding group.
Security Violation
Drop or forward to CPU
Reserved Address
(01-80-c2-00-00-xx, with
the option to forward
normally)
Drop or forward to CPU
Drop or forward to CPU
No Security Violation
Forwarding packets to the Forward packets to the
other ports within the same ports determined by the
forwarding group.
output port map table
constrained by the
forwarding group.
Forward packets to the
other ports within the same
forwarding group.
Security Violation
Same as the above
Reserved Address
(01-80-c2-00-00-xx, with
the option to forward to
CPU)
Same as the above
Forward the packet to the
CPU port.
Forward the packet to the
CPU port.
Same as the above
Same as the above
No Security Violation
Forward the packet to the
CPU port.
Security Violation
Same as the above
Data Sheet
Same as the above
19
Rev 1.01, 2005-11-08
ADM6918/X
Function Description
Table 4
Address Recognition and Packet Forwarding (cont’d)
DA
DA+VID was found in the
address table (entry not
pointed to the output
port map table)
Reserved Address
(01-80-c2-00-00-xx, with
the option to discard)
No Security Violation
Discard the packet.
Discard the packet.
Discard the packet.
Same as the above
Same as the above
Forward the packet to the
CPU port.
Forward the packet to the
CPU port.
Drop or forward to CPU
Drop or forward to CPU
Forward packets to the
ports determined by the
output port map table
constrained by the
forwarding group.
Forward packets
according the Multicast
Option.
Drop or forward to CPU
Drop or forward to CPU
Forward packets to the
ports determined by the
output port map table
constrained by the
forwarding group.
Forward packets
according the Multicast
Option.
Drop or forward to CPU
Drop or forward to CPU
Security Violation
Same as the above
IGMP Packet
(Port Enable IGMP)
DA+VID was found in the DA+VID was not found in
the address table
address table (entry
pointed to the output
port map table)
No Security Violation
Forward the packet to the
CPU port.
Security Violation
Drop or forward to CPU
IGMP Packet
(Port Disable IGMP)
No Security Violation
Forward packets to the
port determined by the
address table. The packet
may be dropped because
of forwarding group
boundary violation.
Security Violation
Drop or forward to CPU
Others
No Security Violation
Forward packets to the
port determined by the
address table. The packet
may be dropped because
of forwarding group
boundary violation.
Security Violation
Drop or forward to CPU
3.1.5
Trunking Port Forwarding
ADM6918/X supports the trunking forwarding and any port could be assigned to the trunking port. When one or
more of the members link fail, the ADM6918/X will automatically change the transmitting path from the failed link
port to normal link port. Port based load balancing is implemented to distribute the loading.
3.1.6
Illegal Frames
The ADM6918/X will discard all illegal frames such as runt packet (less than 64 bytes), oversize packet (greater
than 1518 or 1522 bytes) or bad CRC.
3.1.7
Back off Algorithm
The ADM6918/X implements the truncated exponential back off algorithm compliant to the 802.3 standard.
ADM6918/X will restart the back off algorithm by choosing 0-9 collision count. After 16 consecutive retransmit
trials, the ADM6918/X resets the collision counter.
Data Sheet
20
Rev 1.01, 2005-11-08
ADM6918/X
Function Description
3.1.8
Buffers and Queues
The ADM6918/X incorporates 18 transmit queues and receive buffer area for the 18 Ethernet ports. The receive
buffers as well as the transmit queues are located within the ADM6918/X along with the switch fabric. The buffers
are divided into 640 blocks of 256 bytes each. The queues of each port are managed according to each port’s
read/write pointer.
Input buffers and output queues are maintained through proprietary patent pending UNIQUE (Universal Queue
management) scheme.
3.1.9
Half Duplex Flow Control
Back-pressure is supported for half-duplex operation.
When the ADM6918/X cannot allocate a receiving buffer for an incoming packet (buffer full), the device will
transmit a jam pattern on the port, thus forcing a collision.
3.1.10
Full Duplex Flow Control
When full duplex port runs out of its receive buffer, a PAUSE command will be issued by ADM6918/X to notice the
packet sender to pause transmission. This frame based flow control is totally compliant to IEEE 802.3x. When flow
control hardware pin is set to high during power on reset and per port PAUSE is enabled, ADM6918/X will output
and accept 802.3x flow control packet.
3.1.11
Inter-Packet Gap (IPG)
IPG is the idle time between any two successive packets from the same port. The value is 9.6us for 10Mbit/s
ETHERNET and 960ns for 100Mbit/s fast Ethernet.
3.1.12
Port VLAN or Tag VLAN Support
Two VLAN settings are supported by the ADM6918/X: the port-based VALN or the tag-based VLAN. For the portbased VLAN the ADM6918/X will use the port number as the index to lookup the forwarding table. For the tagbased VLAN, the ADM6918/X will use the VID to lookup the forwarding table. Each port is assigned a Port VID as
the Default VID if tag-based VLAN is used. The ADM6918/X will check TAG, remove TAG, insert TAG, and recalculate CRC if packet is changed.
Table 5
Packets Received are Untagged
Force no Tag
Bypass
Output Port is Action
Tagged or not
Don’t Care
No
No
Untag as the original
Yes
No
Untag as the original
No
Yes
Add Tag
Yes
Yes
Untag as the original
Table 6
Packets Received are Tagged
Force no Tag
Bypass
Output Port is Action
Tagged or not
No
No
No
The Tag is removed.
Yes
No
No
Tag as the original. The priority in the TAG header is not
checked and VID will not change even if VID is 0 or 1.
Data Sheet
21
Rev 1.01, 2005-11-08
ADM6918/X
Function Description
Table 6
Packets Received are Tagged (cont’d)
Force no Tag
Bypass
Output Port is Action
Tagged or not
No
Yes
No
Tag as the original. The priority in the TAG header is
checked and if the VID is 0 or 1, it may change to PVID (see
EEPROM register 1CH, Bit[3]).
No
No
Yes
Tag as the original. The priority in the TAG header is
checked and if the VID is 0 or 1, it may change to PVID (see
EEPROM register 1ch, Bit[3]).
No
Yes
Yes
Tag as the original. The priority in the TAG header is
checked and if the VID is 0 or 1, it may change to PVID (see
EEPROM register 1ch, Bit[3]).
Yes
Yes
No
Tag as the original. The priority in the TAG header is not
checked. The VID will not change.
Yes
No
Yes
The Tag will be added and packet will be double tagged
output. The VID will not change.
Yes
Yes
Yes
Tag as the original. The priority in the TAG header is not
checked. The VID will not change.
3.1.13
Priority Control
The ADM6918/X provides two priority queues on each output port. Five ways could be used to assign a priority to
a packet.
1.
2.
3.
4.
5.
The priority assigned to each receiving port
The priority field in the 802.1Q Tag Header
The IPv4 TOS field in the IPv4 Header
Priority assigned by the CPU
Management packet (high priority assigned)
3.1.14
Alert LED Display
Two functions are displayed through the Alert LED.
1. Diagnostic Mode after Power on
a) After reset or power up, LED keeps on at least 3 second, and processes internal SSRAM self-test.
b) If test passes, the ADM6918/X turns off LED and goes to the broadcast storm mode.
c) If SSRAM test fails, the ADM6918/X turns off LED, then keeps on.
2. Broadcast Storm Mode after SSRAM Self-test. Packets with DA = ffffffffffffHwill be counted into the storm
counter.
Two thresholds (rising and falling) are used to control the broadcast storm.
a) Time Scale: 50ms is used. The max packet number in 100BaseT is 7490. The max packet number in
10BaseT is 749.
b) Port Rising Threshold, see Table 7.
c) Port Falling Threshold, see Table 8.
Table 7
Port Rising Threshold
Broadcast Storm Threshold
00
01
10
11
All 100TX
Disable
10%
20%
40%
Not All 100TX
Disable
1%
2%
4%
Data Sheet
22
Rev 1.01, 2005-11-08
ADM6918/X
Function Description
Table 8
Port Falling Threshold
Broadcast Storm Threshold
00
01
10
11
All 100TX
Disable
5%
10%
20%
Not All 100TX
Disable
0.5%
1%
2%
3.1.15
Broadcast Storm Filter
If broadcast storming filter is enabled, the broadcast packets (DA = ffff-ffff-ffffH) over the rising threshold within 50
ms will be discarded when the alert LED is turned on.
3.1.16
Collision LED Display
Two collision LEDs are supported. (see EEPROM Register 1CH, Bit[9])
1. 100M Collision LED. If collision happens in one of the ports configured 100M, the 100M Collision LED will flash
in rate of 2 Hz.
2. 10M Collision LED. If collision happens in one of the ports configured 10M, the 10M Collision LED will flash in
rate of 2 Hz.
3.1.17
Bandwidth Control
The ADM6918/X allows the user to limit the bandwidth for each input or output port. 64k, 128K, 256k, 512K, 1M,
4M, 10M and 20M are supported.
3.1.18
Smart Discard
The ADM6918/X supports a smart mechanism to discard packets early according to their priority to prevent the
resource blocked by the low priority. The discard ratio is as follows:
Table 9
Discard Ratio
Discard Mode Utilization
00
01
10
11
00
0%
0%
0%
0%
01
0%
0%
25%
50%
11
0%
25%
50%
75%
3.1.19
Security Support
4 level security schemes are supported by the ADM6918/X. All the security violation address will not be
automatically learned.
The violated packet could be forwarded to the CPU port for management or discarded. When CPU is not present,
ADM6918/X also provides a simple way to lock the first address to prevent illegal address access.
3.1.20
Smart Counter Support
Six counters per port are supported by the ADM6918/X.
1.
2.
3.
4.
5.
6.
Receive Packet Count
Receive Packet Length Count
Transmit Packet Count
Transmit Packet Length Count
The Error Count
The Collision Count
Data Sheet
23
Rev 1.01, 2005-11-08
ADM6918/X
Function Description
3.1.21
Length 1536 Mode
The ADM6918/X provides a function to enable the port to receive packets up to 1536 Byte.
3.1.22
PHY Management (MDC/MDIO Interface)
The ADM6918/X uses the MDC/MDIO interface to set the PHY status. After the reset or power up, the MDC/MDIO
controller will delay about 130 ms to wait for the PHY to ready. The ADM6918/X supports two ways to configure
the PHY setting.
1. PHY master. The switch only reads the PHY status (speed, duplex, link, and pause). This mode is useful when
users want to configure PHY through the CPU help. The ADM6918/X supports an indirect way (a PHY Control
Register) for CPU to access PHYs.
2. PHY slave. The switch uses the EEPROM setting to control the PHY attached (only speed, duplex, link, and
pause are supported). After the port setting changed, the ADM6918/X will use the new setting to program the
PHY again and update the status. 8 commands are provided in this mode to allow the customer to customize
the PHY setting.
Note: The PHY address attached to port 0 is 00008H, the PHY address attached to port 1 is 00009H, …, the PHY
address attached to port 23 is 0001fH, the PHY address attached to port 24 is 00006H and the PHY address
attached to port 25 is 00007H.
3.1.23
Forward Special Packets to the CPU Port (IGMP and Spanning Tree Support)
ADM6918/X will forward the special packets to the CPU port to provide the management function.
1.
2.
3.
4.
5.
6.
7.
8.
DA is 01-80-C2-00-00-00 (BPDU)
DA is 01-80-C2-00-00-02 (Slow Protocol)
DA is 01-80-C2-00-00-03 (802.1x PAE)
DA is 01-80-C2-00-00-04 ~ 01-80-C2-00-00-0f
DA is 01-80-C2-00-00-20 (GMRP)
DA is 01-80-C2-00-00-21 (GVRP)
DA is 01-80-C2-00-00-22 (GVRP)
DA is 01-00-5E-xx-xx-xx and protocol field is 2 for IPV4 (IGMP)
3.1.24
Special TAG
The ADM6918/X has an ability to insert 4Byte special TAG when packets transmitted to the CPU port or to remove
8Byte additional TAG in the packets when packets are received from the CPU port. The configuration is shown in
the CPU Configuration Register. This special function allows the CPU to know the source port which will be used
in the IGMP Snooping, Spanning Tree or the Security function. The CPU also could insert additional 8-byte Tag
to instruct the switch to handle the packets. The packets format is as follows:
Data Sheet
24
Rev 1.01, 2005-11-08
ADM6918/X
Function Description
˧̅˴́̆̀˼̇ʳ˘́˷
ˊʳˢ˖˧˘˧˦
ˣ˥˘˔ˠ˕˟˘
˄ʳˢ˖˧˘˧
˦˙˗
ˉʳˢ˖˧˘˧˦
˗˘˦˧˜ˡ˔˧˜ˢˡʳ˔˗˗˥˘˦˦
ˉʳˢ˖˧˘˧˦
˦ˢ˨˥˖˘ʳ˔˗˗˥˘˦˦
ˇʳˢ˖˧˘˧˦
˦̃˸˶˼˴˿ʳ˧˔˚
˅ʳˢ˖˧˘˧˦
˟˘ˡ˚˧˛˂˧ˬˣ˘
ʳʳʳʳʳʳʳʳʳʳʳʳʳˋʳʳʳʳʳʳʳʳˊʳʳʳʳʳʳʳʳˉʳʳʳʳʳʳʳʳˈʳʳʳʳʳʳʳʳˇʳʳʳʳʳˆʳʳʳʳʳ˅ʳʳʳʳʳ˄
˟˴˵˸˿ʳ
ʳ˥˸̆˸̅̉˸ʳːʳ˃
˦̂̈̅˶˸ʳˣ̂̅̇ˮˇˍ˃˰
˄̆̇ʳ˕̌̇˸
˅́˷ʳ˕̌̇˸
˧˔˚ˮ˄ˈˍˋ˰
ˆ̅˷ʳ˕̌̇˸
˧˔˚ˮˊˍ˃˰
ˇ̇˻ʳ˕̌̇˸
˟˸˴̅́ʳ˦˸˿˸˶̇
ˠ˔˖ʳ˖˟˜˘ˡ˧ʳ˗˔˧˔
ˇˉˀˀ˄ˈ˃˃ʳ
ˢ˖˧˘˧˦
˟˸˴̅́ʳ˩˴˿˼˷
ˣ˔˗
ˤ̈˸̈˸ʳ˦˸˿˸˶̇
˙˥˔ˠ˘ʳ˖˛˘˖˞ʳ˦˘ˤ˨˘ˡ˖˘
ˇʳˢ˖˧˘˧˦
ˤ̈˸̈˸ʳ˩˴˿˼˷
ˢ̈̇̃̈̇ʳˣ̂̅̇ʳˠ˴̃ʳ˩˴˿˼˷
˥˸˶˸˼̉˸ʳ˘́˷
ʳʳʳʳʳʳʳʳʳʳʳʳʳˋʳʳʳʳʳʳʳʳˊʳʳʳʳʳʳʳʳˉʳʳʳʳʳʳʳʳˈʳʳʳʳʳʳʳʳˇʳʳʳʳʳˆʳʳʳʳʳ˅ʳʳʳʳʳ˄
ˊʳˢ˖˧˘˧˦
ˣ˥˘˔ˠ˕˟˘
˄ʳˢ˖˧˘˧
˦˙˗
ˉʳˢ˖˧˘˧˦
˗˘˦˧˜ˡ˔˧˜ˢˡʳ˔˗˗˥˘˦˦
ˉʳˢ˖˧˘˧˦
˦ˢ˨˥˖˘ʳ˔˗˗˥˘˦˦
ˋʳˢ˖˧˘˧˦
˦̃˸˶˼˴˿ʳ˧˔˚
˅ʳˢ˖˧˘˧˦
˟˘ˡ˚˧˛˂˧ˬˣ˘
ʳ˟˴˵˸˿ʳ
˄̆̇ʳ˕̌̇˸
ʳʳʳʳʳʳʳʳʳʳʳʳˢ̈̇̃̈̇ʳˣ̂̅̇ʳˠ˴̃ˮ˅ˉˍ˅˃˰
˅́˷ʳ˕̌̇˸
ʳʳˋʳʳʳʳʳʳˊʳʳʳʳʳʳʳˉʳʳʳʳʳʳˈʳʳʳʳʳʳˇʳʳʳʳʳʳˆʳʳʳʳʳʳ˅ʳʳʳʳʳʳʳ˄ʳʳʳ
ʳʳˢ̈̇̃̈̇ʳˣ̂̅̇ʳˠ˴̃ˮ˄ˌˍ˄˅˰
ʳʳˢ̈̇̃̈̇ʳˣ̂̅̇ʳˠ˴̃ˮ˄˄ˍˇ˰
ˢ̈̇̃̈̇ʳˣ̂̅̇ʳˠ˴̃ˮˆˍ˃˰
ʳʳʳʳ
ˆ̅˷ʳ˕̌̇˸
ˇ̇˻ʳʳ˕̌̇˸
ˈ̇˻ʳ˕̌̇˸
˥˸̆˸̅̉˸˷
ˉ̇˻ʳ˕̌̇˸
˥˸̆˸̅̉˸˷
ˊ̇˻ʳ˕̌̇˸
˥˸̆˸̅̉˸˷
ˋ̇˻ʳ˕̌̇˸
ˠ˔˖ʳ˖˟˜˘ˡ˧ʳ˗˔˧˔
ˇˉˀˀ˄ˈ˃˃ʳ
ˢ˖˧˘˧˦
ˣ˔˗
ˇʳˢ˖˧˘˧˦
˙˥˔ˠ˘ʳ˖˛˘˖˞ʳ˦˘ˤ˨˘ˡ˖˘
Figure 3
Packet Format
Table 10
Special TAG Fields
Configuration
Description
Label
The field is used for CPU to decide if the special TAG is valid. If the switch finds 8b’0
the Label doesn’t equal to the value assigned by the EEPROM, it must receive
as the normal mode. This case exists when user wants the switch to insert 4 byte
special tag even for Pause packets.
Output Port Map
Valid
1B
0B
Data Sheet
Default
, The switch is instructed to override the switch operation. It will forward the 1’b0
packets following the Output Port Map field.
, The switch will treat the packet as the normal mode.
25
Rev 1.01, 2005-11-08
ADM6918/X
Function Description
Table 10
Special TAG Fields (cont’d)
Configuration
Description
Default
Output Port
Map[26:0]
Bit[26] = 1, the CPU wants to forward packets to more than 2 ports.
Bit[26] = 0, the CPU wants to forward packets to only one port.
Bit[x], x = 0 ~ 25, the CPU wants to forward packets to Port x.
Example:
1. The CPU wants to forward packet to P1 and P2 then the Output Port Map is
as follows:
Bit 26, 25~24, 23~16, 15~8, 7~0
Map 1, 00, 0000_0000, 0000_0000, 0000_0110
2. The CPU wants to forward packets to P5 only.
Bit 26, 25~24, 23~16, 15~8, 7~0
Map 0, 00, 0000_0000, 0000_0000, 0010_0000
27’h0
TAG[25:0]
This value is the same as the TAG header if the CPU port is configured to a TAG 16’h0
port.
Source Port[4:0]
This field indicates the source port the packet comes from.
Queue Valid
1B
5’h0
0B
, The switch is instructed to override the switch operation. It will forward the 1’b0
packets using the Queue Select Field.
, The switch will treat the packets as the normal mode.
Queue Select
1B
0B
, Mapped for High Queue
, Mapped for Low Queue
Learn Valid
1B
0B
, The switch is instructed to override the switch operation. The CPU port will 1’b0
use the Learn Field to decide how to learn the packet.
, The switch will treat the packets as the normal mode. That is, the CPU port
will learn or disable learning according the Disable CPU Port Learning
Function configured in the CPU Control Register.
1B
0B
, Learn the packet
, Don’t learn the packet
Learn Select
3.1.25
1’b0
1’b0
Port 24 and Port 25 Interface (Only SS-SMII Package Support)
Three interfaces in port 24 and port 25 are supported by the ADM6918/X: (1) MII Interface (2) RMII Interface.
ˠ ˃˧ ˫ ˖˟ ˞
ˣ ̂ ̅̇ʳ˅ ˇ
ʻˠ ˜˜ʼ
Figure 4
Data Sheet
˧ ˫ ˲˖˟ ˞
ˠ ˄˧ ˫ ˖˟ ˞
˧˫ ˲˖ ˟˞
ˠ ˃˧˫ ˘ ˡ
˧ ˫ ˲˘ˡ
ˠ ˄˧˫ ˘ ˡ
˧˫ ˲˘ ˡ
ˠ ˃˧ ˫ ˗ ˃
˧ ˫ ˗ ˮ˃ ˰
ˠ ˄˧ ˫ ˗ ˃
˧ ˫ ˗ ˮ˃ ˰
ˠ ˃˧ ˫ ˗ ˄
˧ ˫ ˗ ˮ˄ ˰
ˠ ˄˧ ˫ ˗ ˄
˧ ˫ ˗ ˮ˄ ˰
ˠ ˃˧ ˫ ˗ ˅
˧ ˫ ˗ ˮ˅ ˰
ˠ ˄˧ ˫ ˗ ˅
˧ ˫ ˗ ˮ˅ ˰
ˠ ˃˧ ˫ ˗ ˆ
˧ ˫ ˗ ˮˆ ˰
ˠ ˄˧ ˫ ˗ ˆ
˧ ˫ ˗ ˮˆ ˰
ˠ ˃˥ ˫ ˖˟ ˞
˥ ˫ ˲˖ ˟˞
ˠ ˃˥ ˫ ˗ ˩
˥ ˫ ˲˗ ˩
ˠ ˃˥ ˫ ˗ ˃
ˠ ˃˥ ˫ ˗ ˄
ˣ ̂ ̅̇ʳ˅ ˈ
ʻˠ ˜˜ʼ
ˣ˛ ˬ ʳ
ˠ ˄˥ ˫ ˖˟ ˞
˥ ˫ ˲˖˟ ˞
ˠ ˄˥˫ ˗ ˩
˥ ˫ ˲˗ ˩
˥ ˫ ˗ ˮ˃ ˰
ˠ ˄˥ ˫ ˗ ˃
˥ ˫ ˗ ˮ˃ ˰
˥ ˫ ˗ ˮ˄ ˰
ˠ ˄˥ ˫ ˗ ˄
˥ ˫ ˗ ˮ˄ ˰
ˠ ˃˥ ˫ ˗ ˅
˥ ˫ ˗ ˮ˅ ˰
ˠ ˄˥ ˫ ˗ ˅
˥ ˫ ˗ ˮ˅ ˰
ˠ ˃˥ ˫ ˗ ˆ
˥ ˫ ˗ ˮˆ ˰
ˠ ˄˥ ˫ ˗ ˆ
˥ ˫ ˗ ˮˆ ˰
ˠ ˃˖ ˥˦
˖˥˦
ˠ ˄˖ ˥˦
˖˥˦
ˠ ˃˖ˢ ˟
˖ˢ˟
ˠ ˄˖ˢ ˟
˖ˢ˟
ˣ˛ ˬ ʳ
MII Interface Diagram
26
Rev 1.01, 2005-11-08
ADM6918/X
Function Description
ˈ˃ˠ ˛ ˭
ˠ ˃˥˫ ˖ ˟˞
ˣ ̂ ̅̇ʳ˅ ˇ
ʻ˥ ˠ ˜˜ʼ
ˈ˃ˠ ˛ ˭
˖˟˞˥˘˙
ˠ ˃˧˫ ˘ˡ
˧ ˫ ˲˘ ˡ
ˠ ˃˧˫ ˗ ˃
˧ ˫ ˗ ˮ˃ ˰
ˠ ˃˧˫ ˗ ˄
˧ ˫ ˗ ˮ˄ ˰
ˠ ˄˥ ˫ ˖ ˟˞
ˣ ̂ ̅̇ʳ˅ ˈ
ʻ˥ ˠ ˜˜ʼ
ˣ˛ ˬʳ
˖˟˞˥˘˙
ˠ ˄˧ ˫ ˘ˡ
˧ ˫ ˲˘ ˡ
ˠ ˄˧ ˫ ˗ ˃
˧ ˫ ˗ ˮ˃ ˰
ˠ ˄˧ ˫ ˗ ˄
˧ ˫ ˗ ˮ˄ ˰
ˠ ˃˥ ˫ ˗ ˩
˖ ˥ ˦˲˗ ˩
ˠ ˄˥˫ ˗ ˩
˖ ˥ ˦˲˗ ˩
ˠ ˃˥ ˫ ˗ ˃
˥ ˫ ˗ ˮ˃ ˰
ˠ ˄˥ ˫ ˗ ˃
˥ ˫ ˗ ˮ˃ ˰
ˠ ˃˥ ˫ ˗ ˄
˥ ˫ ˗ ˮ˄ ˰
ˠ ˄˥ ˫ ˗ ˄
˥ ˫ ˗ ˮ˄ ˰
Figure 5
RMII Interface
3.1.26
Hardware, EEPROM and SMI Interface for Configuration
ˣ˛ ˬ ʳ
Three ways are supported to configure the setting in the ADM6918/X: (1) Hardware Setting (2) EERPROM
Interface (3) SMI Interface. Users could use EEPROM and SMI interfaces combined with the CPU port to provide
proprietary functions. Four pins are needed when using these two interfaces. See the following figure as a
description.
˔˗ˠˉˌ˄ˋ
˘˘˖˦
˘˘˦˞
˘˗˜
˘˗ˢ
˘˘ˣ˥ˢˠʻˌˆ˶ˉˉʼ
˖ˣ˨
Figure 6
Hardware, EEPROM and SMI Interface Configuration
3.1.26.1
Hardware Setting
The ADM6918/X provides some hardware pins where values reside on during power on or reset will be strapped
for the default setting.
Table 11
SS-SMII and RMII Pins
SS-SMII Pin
Name
RMII Pin
Name
Description
M1TXD0
M1TXD0
IPG Average 92 bit time. Internally Pulled Down.
0B
, Disable IPG Average 92
1B
, Enable IPG Average 92
M1TXD1
M1TXD1
Trunk En. Internally Pulled Up.
0B
, Trunking Disable. The ADM6918/X has no trunking function even if
EEPROM sets.
1B
, Trunking Enable. Use EEPROM to configure the trunk member.
Data Sheet
27
Rev 1.01, 2005-11-08
ADM6918/X
Function Description
Table 11
SS-SMII and RMII Pins (cont’d)
SS-SMII Pin
Name
RMII Pin
Name
Description
M1TXD2
M1TXD2
Pause. Internally Pulled Up.
0B
, The switch doesn’t allow the Pause function even if EEPROM set. The
only way to start the Pause function is through the CPU help.
1B
, The switch allows the Pause function. This function can be disabled by
the EEPROM.
M1TXD3
M1TXD3
Back-Pressure. Internally Pulled Up.
0B
, The switch doesn’t allow the Back-Pressure function even if EEPROM
set.
1B
, The switch allows the Back-Pressure function. This function can be
disabled by the EEPROM.
M1TXEN
M1TXEN
Auto-Neg En. Internally Pulled Up.
0B
, The switch doesn’t allow Auto-Negotiation function even if EEPROM set.
The only way to start the Auto-Negotiation function is through the CPU
help.
1B
, The switch allows the Auto-Negotiation function. This function can be
disabled by the EEPROM.
M0TXEN
M0TXEN
Aging Dis. Internally Pulled Down.
0B
, The switch will age the entry in the address table.
1B
, The switch will not age the entry in the address table.
M0TXD0
Don’t Support Port 24 Interface Configuration
Don’t Support M0TXD0, M0TXD2, Interface
0B
, 0, Port 24 is configured to MII in SS-SMII package (internal value).
xB
, 1, Port 24 is configured to RMII in SS-SMII package.
M0TXD2
M0TXD1
M0TXD3
Don’t Support Port 25 Interface Configuration
Don’t Support M0TXD1, M0TXD3, Interface
configured to MII in SS-SMII package (internal value).
xB
, 1, Port 25 is configured to RMII is SS-SMII package
When port 24 or port 25 is configured to RMII mode in SS-SMII package, we can use the hardware pins to
configure duplex status of these two ports.
Table 12
Port 24 Duplex Configuration
M0RXD3
M0RXD2
Description
0
0
Duplex status is determined as port 0 ~ port 23.
0
1
Duplex status is determined as port 0 ~ port 23.
1
0
Full Duplex is determined.
1
1
Half Duplex is determined.
Table 13
Port 25 Duplex Configuration
M1RXD3
M1RXD2
Description
0
0
Duplex status is determined as port 0 ~ port 23.
0
1
Duplex status is determined as port 0 ~ port 23.
1
0
Full Duplex is determined.
1
1
Half Duplex is determined.
Data Sheet
28
Rev 1.01, 2005-11-08
ADM6918/X
Function Description
3.1.26.2
EEPROM Interface
The EEPROM Interface is provided so the users could easily configure the setting without CPU's help. Because
the EEPROM Interface is the same as the 93c66, it also allows the CPU to write the EEPROM register and renew
the 93c66 at the same time. After the power up or reset (default value from the hardware pins fetched in this stage),
the ADM6918/X will automatically detect the presence of the EEPROM by reading the address 0 in the 96c66. If
the value = 16'h4154, it will read all the data in the 93c66. If not, the ADM6918/X will stop loading the 93c66. The
user also could pull down the EDO to force the ADM6918/X not to load the 93c66. The 93c66 loading time is
around 30ms. Then CPU should give the high-z value in the EECS, EESK and EDI pins in this period if we really
want to use CPU to read or write the registers in the ADM6918/X.
The EEPROM Interface needs only one Write command to complete a writing operation. If updating the 93c66 at
the same time is necessary, three commands Write Enable, Write, and Write Disable are needed to complete this
job (See 93c66 Spec. for a reference). Users should note that the EERPOM interface only allows the CPU to write
the EEPROM register in the ADM6918/X and doesn't support the READ command. If CPU gives the Read
Command, ADM6918/X will not respond and 93c66 will respond with the value. Users should also note that one
additional EESK cycle is needed between any continuous commands (Read or Write)
˘˘˖˦ʻ˖ˣ˨ʼ
˘˘˦˞ʻ˖ˣ˨ʼ
ˢ́˸ʳ̀̂̅˸ʳ˘˘˦˞ʳ˼̆ʳ́˸˸˷˸˷
˄
˘˗˜ʳʻ˖ˣ˨ʼ
˄
˦̇˴̅̇
˃
˔ˊ
˔ˉ
ˢ̃˶̂˷˸
˔ˈ
˔ˇ
˔ˆ
˔˅
˔˄
˔˃
˘˘ˣ˥ˢˠʳ˔˷̅˸̆̆ʳʻ˜́˷˸̋ʼ
˘˗ˢʳʻˌˆ˶ˇˉʼ
˃
˗˄ˈ
˗˄ˇ
˗˄ˆ
˗˄˅
˗˄˄
˗˄˃
˗ˌ
˗ˋ
˗̈̀̀̌
˗ˊ
˗ˉ
˗ˈ
˗ˇ
˗ˆ
˗˅
˗˄
˗˄
˗˃
˗˃
˗˴̇˴ʳ
˘˘ˣ˥ˢˠʳ˥˸˴˷ʳˢ̃˸̅˴̇˼̂́
Figure 7
Read 93c66 via the EEPROM Interface (Index = 2, Data = 16’h1111)
˘˘˖˦ʻ˖ˣ˨ʼ
˘˘˦˞ʻ˖ˣ˨ʼ
˘˗˜ʳʻ˖ˣ˨ʼ
ˢ́˸ʳ̀̂̅˸ʳ˘˘˦˞ʳ˼̆ʳ́˸˸˷˸˷
˄
˦̇˴̅̇
˃
˃
ˢ̃˶̂˷˸
˔ˊ
˔ˉ
˔ˈ
˔ˇ
˔ˆ
˔˅
˔˄
˔˃
˗˄ˈ
˗˄ˇ
˗˄ˆ
˗˄˅
˗˄˄
˗˄˃
˘˘ˣ˥ˢˠʳ˔˷̅˸̆̆ʳʻ˜́˷˸̋ʼ
˗ˌ
˗ˋ
˗ˊ
˗ˉ
˗ˈ
˗ˇ
˗ˆ
˗˅
˗˴̇˴
˘˘ˣ˥ˢˠʳ˪̅˼̇˸ʳˢ̃˸̅˴̇˼̂́
Figure 8
Write EEPROM Registers in the ADM6918/X (Index = 2, Data = 16’h2222)
3.1.26.3
SMI Interface
The SMI consists of two pins, management data clock (EESK) and management data input/output (EDI). The
ADM6918/X is designed to support an EESK frequency up to 25 MHz. The EDI pin is bi-directional and may be
shared with other devices. EECS pin may be needed (pulled to low) if EEPROM interface is also used.
The EDI pin requires a 1.5 kΩ pull-up which, during idle and turnaround periods, will pull EDI to a logic one state.
ADM6918/X requires a single initialization sequence of 32 bits of preamble following power-up/hardware reset.
The first 32 bits are preamble consisting of 32 contiguous logic one bits on EDI and 32 corresponding cycles on
EESK. Following preamble is the start-of-frame field indicated by a <01> pattern. The next field signals the
operation code (OP): <10> indicates read from management register operation, and <01> indicates write to
Data Sheet
29
Rev 1.01, 2005-11-08
ADM6918/X
Function Description
management register operation. The next field is management register address. It is 10 bits wide and the most
significant bit is transferred first.
During Read operation, a 2-bit turn around (TA) time spacing between the register address field and data field is
provided for the EDI to avoid contention. Following the turnaround time, a 32-bit data stream is read from or written
into the management registers of the ADM6918/X.
(A) Preamble Suppression
The SMI of ADM6918/X supports a preamble suppression mode. The ADM6918/X requires a single initialization
sequence of 32 bits of preamble following power-up/hardware reset. This requirement is generally met by pullingup the resistor of EDI While the ADM6918/X will respond to management accesses without preamble, a minimum
of one idle bit between management transactions is required.
When ADM6918/X detects that there is address match, then it will enable Read/Write capability for external
access. When address is mismatched, then ADM6918/X will tristate the EDI pin.
(B) Read Switch Register via SMI Interface (Offset Hex = 10’h2, Data = 32’h2600_0000)
ˢ́˸ʳ̀̂̅˸ʳ˘˘˦˞ʳ˼̆ʳ́˸˸˷˸˷
EESK
EDI(CPU)
~
~
EDI(AD3110)
z
0
Preamble
1
1
0
0
0
0
Opcode
(Read)
Start
0
0
0
0
0
1
0
z
0
0
0
1
0
0
TA
Register Address (10'h2 in this example)
1
1
0
0
0
0
0
0
z
Register Data (32'h26000000 in this Example)
SMI Read Operation
Figure 9
Read Switch Register via SMI Interface
(C) Write Switch Register via SMI Interface (Offset Hex = 10’h180, Data = 32’h1300_0000)
ˢ́˸ʳ̀̂̅˸ʳ˘˘˦˞ʳ˼̆ʳ́˸˸˷˸˷
EESK
EDI (CPU)
z
Preamble
0
1
Start
0
1
Opcode
(Write)
0
1
1
0
0
0
0
0
0
0
1
Register Address (10'h180 in this example)
0
0
0
0
1
TA
0
0
1
1
0
0
0
~
~
0
0
0
z
Register Data (32'h13000000 in this Example)
SMI Write Operation
Figure 10
Write Switch Register via SMI Interface
(D) The Pin Type of EECS, EESK, EDI and EDO during the Operation
Table 14
Pin Type of EECS, EESK, EDI and EDO during Operation
Pin Name
Reset Operation
Load EEPROM
Write Operation
Read Operation
EECS
Input
Output
Input
Input
EESK
Input
Output
Input
Input
EDI
Input
Output
Input
Input / Output
EDO
Input
Input
Input
Input
Data Sheet
30
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
4
EEPROM Register Format
The EEPROM can be auto-detected by ADM6918/X through the signature register. The ADM6918/X supports C66
EEPROM. After the EEPROM is loaded, the output pins of ADM6918/X are tristate and released to CPU. The
release time is about 30ms after end of RESET. Whenever CPU modifies the setting of C66, the new value will be
written to ADM6918/X at the same time. If CPU changes the port setting (Duplex/Speed/AEN), the ADM6918/X
will restart the auto-negotiation automatically.
Table 15
EEPROM Format
Offset Hex
0200H
0201H
0202H
0203H
0204H
0205H
Index
Bit 15 - 8
Bit 7 - 0
Type
Default
Low
0H
Signature
ro
4154H
High
1H
Global Configuration
rw
3800H
Low
2H
Port 0 Configuration
rw
80FFH
High
3H
Port 1 Configuration
rw
80FFH
Low
4H
Port 2 Configuration
rw
80FFH
High
5H
Port 3 Configuration
rw
80FFH
0206H
0207H
Low
6H
Port 4 Configuration
rw
80FFH
High
7H
Port 5 Configuration
rw
80FFH
0208H
0209H
Low
8H
Port 6 Configuration
rw
80FFH
High
9H
Port 7 Configuration
rw
80FFH
Low
AH
Port 8 Configuration
rw
80FFH
High
BH
Port 9 Configuration
rw
80FFH
Low
CH
Port10 Configuration
rw
80FFH
High
DH
Port 11 Configuration
rw
80FFH
020AH
020BH
020CH
020DH
020E
020f
Low
EH
Port 12 Configuration
rw
80FFH
High
FH
Port 13 Configuration
rw
80FFH
0210H
0211H
Low
10H
Port 14 Configuration
rw
80FFH
High
11H
Port 15 Configuration
rw
80FFH
Low
12H
Reserved
rw
80FFH
High
13H
Reserved
rw
80FFH
Low
14H
Reserved
rw
80FFH
High
15H
Reserved
rw
80FFH
0212H
0213H
0214H
0215H
0216H
0217H
Low
16H
Reserved
rw
80FFH
High
17H
Reserved
rw
80FFH
0218H
0219H
Low
18H
Reserved
rw
80FFH
High
19H
Reserved
rw
80FFH
Low
1AH
Port 16 Configuration
rw
80FFH
High
1BH
Port 17 Configuration
rw
80FFH
Low
1CH
Miscellaneous Configuration
rw
820H
High
1DH
TOS Priority Map
VLAN Priority Map
rw
0H
021AH
021BH
021CH
021DH
021EH
021FH
Low
1EH
Forwarding Group 0 Outbound Port Map Low
rw
FFFFH
High
1FH
Forwarding Group 0 Outbound Port Map High
rw
3FFH
0220H
0221H
Low
20H
Forwarding Group 1 Outbound Port Map Low
rw
FFFFH
High
21H
Forwarding Group 1 Outbound Port Map High
rw
3FF
Data Sheet
31
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
Table 15
EEPROM Format (cont’d)
Offset Hex
0222H
0223H
Index
Bit 15 - 8
Bit 7 - 0
Type
Default
Low
22H
Forwarding Group 2 Outbound Port Map Low
rw
FFFFH
High
23H
Forwarding Group 2 Outbound Port Map High
rw
3FFH
0224H
0225H
Low
24H
Forwarding Group 3 Outbound Port Map Low
rw
FFFFH
High
25H
Forwarding Group 3 Outbound Port Map High
rw
3FFH
0226H
0227H
Low
26H
Forwarding Group 4 Outbound Port Map Low
rw
FFFFH
High
27H
Forwarding Group 4 Outbound Port Map High
rw
3FFH
Low
28H
Forwarding Group 5 Outbound Port Map Low
rw
FFFFH
High
29H
Forwarding Group 5 Outbound Port Map High
rw
3FFH
Low
2AH
Forwarding Group 6 Outbound Port Map Low
rw
FFFFH
High
2BH
Forwarding Group 6 Outbound Port Map High
rw
3FFH
0228H
0229H
022AH
022BH
022CH
022DH
Low
2CH
Forwarding Group 7 Outbound Port Map Low
rw
FFFFH
High
2DH
Forwarding Group 7 Outbound Port Map High
rw
3FFH
022EH
022FH
Low
2EH
Forwarding Group 8 Outbound Port Map Low
rw
FFFFH
High
2FH
Forwarding Group 8 Outbound Port Map High
rw
3FFH
Low
30H
Forwarding Group 9 Outbound Port Map Low
rw
FFFFH
High
31H
Forwarding Group 9 Outbound Port Map High
rw
3FFH
Low
32H
Forwarding Group 10 Outbound Port Map Low
rw
FFFFH
High
33H
Forwarding Group 10 Outbound Port Map High
rw
3FFH
0230H
0231H
0232H
0233H
0234H
0235H
Low
34H
Forwarding Group 11 Outbound Port Map Low
rw
FFFFH
High
35H
Forwarding Group 11 Outbound Port Map High
rw
3FFH
0236H
0237H
Low
36H
Forwarding Group 12 Outbound Port Map Low
rw
FFFFH
High
37H
Forwarding Group 12 Outbound Port Map High
rw
3FFH
Low
38H
Forwarding Group 13 Outbound Port Map Low
rw
FFFFH
High
39H
Forwarding Group 13 Outbound Port Map High
rw
3FFH
Low
3AH
Forwarding Group 14 Outbound Port Map Low
rw
FFFFH
High
3BH
Forwarding Group 14 Outbound Port Map High
rw
3FFH
0238H
0239H
023AH
023BH
023CH
023DH
Low
3CH
Forwarding Group 15 Outbound Port Map Low
rw
FFFFH
High
3DH
Forwarding Group 15 Outbound Port Map High
rw
3FFH
023EH
023FH
Low
3EH
Forwarding Group 16 Outbound Port Map Low
rw
FFFFH
High
3FH
Forwarding Group 16 Outbound Port Map High
rw
3FFH
Low
40H
Forwarding Group 17 Outbound Port Map Low
rw
FFFFH
High
41H
Forwarding Group 17 Outbound Port Map High
rw
3FFH
Low
42H
Forwarding Group 18 Outbound Port Map Low
rw
FFFFH
High
43H
Forwarding Group 18 Outbound Port Map High
rw
3FFH
0240H
0241H
0242H
0243H
0244H
0245H
Low
44H
Forwarding Group 19 Outbound Port Map Low
rw
FFFFH
High
45H
Forwarding Group 19 Outbound Port Map High
rw
3FFH
0246H
0247H
Low
46H
Forwarding Group 20 Outbound Port Map Low
rw
FFFFH
High
47H
Forwarding Group 20 Outbound Port Map High
rw
3FFH
Low
48H
Forwarding Group 21 Outbound Port Map Low
rw
FFFFH
High
49H
Forwarding Group 21 Outbound Port Map High
rw
3FFH
0248H
0249H
Data Sheet
32
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
Table 15
EEPROM Format (cont’d)
Offset Hex
024AH
024BH
Index
Bit 15 - 8
Bit 7 - 0
Type
Default
Low
4AH
Forwarding Group 22 Outbound Port Map Low
rw
FFFFH
High
4BH
Forwarding Group 22 Outbound Port Map High
rw
3FFH
024CH
024DH
Low
4CH
Forwarding Group 23 Outbound Port Map Low
rw
FFFFH
High
4DH
Forwarding Group 23 Outbound Port Map High
rw
3FFH
024EH
024FH
Low
4EH
Forwarding Group 24 Outbound Port Map Low
rw
FFFFH
High
4FH
Forwarding Group 24 Outbound Port Map High
rw
3FFH
0250H
Low
50H
Forwarding Group 25 Outbound Port Map Low
rw
FFFFH
0251H
High
51H
Forwarding Group 25 Outbound Port Map High
rw
3FFH
0252H
0253H
Low
52H
Forwarding Group 26 Outbound Port Map Low
rw
FFFFH
High
53H
Forwarding Group 26 Outbound Port Map High
rw
3FFH
0254H
0255H
Low
54H
Forwarding Group 27 Outbound Port Map Low
rw
FFFFH
High
55H
Forwarding Group 27 Outbound Port Map High
rw
3FFH
0256H
0257H
Low
56H
Forwarding Group 28 Outbound Port Map Low
rw
FFFFH
High
57H
Forwarding Group 28 Outbound Port Map High
rw
3FFH
Low
58H
Forwarding Group 29 Outbound Port Map Low
rw
FFFFH
High
59H
Forwarding Group 29 Outbound Port Map High
rw
3FFH
Low
5AH
Forwarding Group 30 Outbound Port Map Low
rw
FFFFH
High
5BH
Forwarding Group 30 Outbound Port Map High
rw
3FFH
0258H
0259H
025AH
025BH
025CH
025DH
Low
5CH
Forwarding Group 31 Outbound Port Map Low
rw
FFFFH
High
5DH
Forwarding Group 31 Outbound Port Map High
rw
3FFH
025EH
025FH
Low
5EH
rw
1H
High
5FH
P1 VID
rw
1H
Low
60H
P2 VID
rw
1H
High
61H
P3 VID
rw
1H
Low
62H
P4 VID
rw
1H
High
63H
P5 VID
rw
1H
0260H
0261H
0262H
0263H
PVID shift
P0 VID
0264H
0265H
Low
64H
P6 VID
rw
1H
High
65H
P7 VID
rw
1H
0266H
0267H
Low
66H
P8 VID
rw
1H
High
67H
P9 VID
rw
1H
Low
68H
P10 VID
rw
1H
High
69H
P11 VID
rw
1H
Low
6AH
P12 VID
rw
1H
High
6BH
P13 VID
rw
1H
0268H
0269H
026AH
026BH
026CH
026DH
Low
6CH
P14 VID
rw
1H
High
6DH
P15 VID
rw
1H
026EH
026FH
Low
6EH
Reserved
rw
1H
High
6FH
Reserved
rw
1H
Low
70H
Reserved
rw
1H
High
71H
Reserved
rw
1H
0270H
0271H
Data Sheet
33
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
Table 15
EEPROM Format (cont’d)
Offset Hex
0272H
0273H
Index
Bit 15 - 8
Bit 7 - 0
Type
Default
Low
72H
Reserved
rw
1H
High
73H
Reserved
rw
1H
0274H
0275H
Low
74H
Reserved
rw
1H
High
75H
Reserved
rw
1H
0276H
0277H
Low
76H
P16 VID
rw
1H
High
77H
P17 VID
rw
1H
Low
78H
P0, P1, P2, P3 Bandwidth Control Register
rw
0H
High
79H
P4, P5, P6, P7 Bandwidth Control Register
rw
0H
Low
7AH
P8, P9, P10, P11 Bandwidth Control Register
rw
0H
High
7BH
P12, P13, P14, P15 Bandwidth Control Register
rw
0H
0278H
0279H
027AH
027BH
027CH
027DH
Low
7CH
Reserved
rw
0H
High
7DH
Reserved
rw
0H
027EH
027FH
Low
7EH
P24, P25 Bandwidth Control Register
rw
0H
High
7FH
Bandwidth Control Enable Register Low
rw
0H
Low
80H
Bandwidth Control Enable Register High
rw
0H
High
81H
Reserved
rw
0H
Low
82H
Reserved
rw
0H
High
83H
Reserved
rw
100H
0280H
0281H
0282H
0283H
0284H
0285H
Low
84H
Reserved
rw
0H
High
85H
Reserved
rw
0H
0286H
0287H
Low
86H
Reserved
rw
0H
High
87H
Reserved
rw
0H
Low
88H
Reserved
rw
0H
High
89H
Reserved
rw
0H
Low
8AH
Reserved
rw
FF00H
HIGH
8BH
Customized PHY Control Group 0
rw
0H
0288H
0289H
028AH
028BH
028CH
028DH
Low
8CH
Customized PHY Control Group 1
rw
0H
HIGH
8DH
Customized PHY Control Group 2
rw
0H
028EH
028FH
Low
8EH
Customized PHY Control Group 3
rw
0H
HIGH
8FH
Group 0 PHY Customized DATA 0
rw
0H
Low
90H
Group 0 PHY Customized DATA 1
rw
0H
HIGH
91H
Group 1 PHY Customized DATA 0
rw
0H
Low
92H
Group 1 PHY Customized DATA 1
rw
0H
HIGH
93H
Group 2 PHY Customized DATA 0
rw
0H
0290H
0291H
0292H
0293H
0294H
0295H
Low
94H
Group 2 PHY Customized DATA 1
rw
0H
HIGH
95H
Group 3 PHY Customized DATA 0
rw
0H
0296H
0297H
Low
96H
Group 3 PHY Customized DATA 1
rw
0H
HIGH
97H
PHY Customized Enable Register
rw
0H
Low
98H
PPPOE Control Register 0
rw
0H
HIGH
99H
PPPOE Control Register 1
rw
0H
0298H
0299H
Data Sheet
34
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
Table 15
EEPROM Format (cont’d)
Offset Hex
029AH
029BH
Index
Bit 15 - 8
Bit 7 - 0
Type
Default
Low
9AH
PHY Control Register 0
rw
0H
HIGH
9BH
PHY Control Register 1
rw
0H
029CH
029DH
Low
9CH
Disable MDIO Active Register 0
rw
0H
HIGH
9DH
Disable MDIO Active Register 1
rw
0H
029EH
029FH
Low
9EH
Disable Port Register 0
rw
0H
HIGH
9FH
Disable Port Register 1
rw
0H
Low
A0H
IGMP Enable Register 0
rw
0H
HIGH
A1H
IGMP Enable Register 1
rw
0H
Low
A2H
CPU Control Register
rw
001FH
HIGH
A3H
MAC Forward Mode Register 0
rw
4H
02A0H
02A1H
02A2H
02A3H
02A4H
02A5H
Low
A4H
MAC Forward Mode Register 1
rw
3H
HIGH
A5H
MAC Forward Mode Register 2
rw
0H
02A6H
02A7H
Low
A6H
Trunking Enable Register 0
rw
0H
HIGH
A7H
Trunking Enable Register 1
rw
0H
Data Sheet
35
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
4.1
EEPROM Registers
Table 16
Registers Address Space
Module
Base Address
End Address
EEPROM
0200H
02A7H
Table 17
Note
Registers Overview
Register Short Name
Register Long Name
Offset Address
Page Number
SIG
Signature
0200H
41
GCR
Global Configuration Register
0201H
41
PCR_0
Port 0 Configuration Register
0202H
43
PCR_1
Port 1 Configuration
0203H
46
PCR_2
Port 2 Configuration
0204H
46
PCR_3
Port 3 Configuration
0205H
46
PCR_4
Port 4 Configuration
0206H
46
PCR_5
Port 5 Configuration
0207H
46
PCR_6
Port 6 Configuration
0208H
46
PCR_7
Port 7 Configuration
0209H
46
PCR_8
Port 8 Configuration
020AH
46
PCR_9
Port 9 Configuration
020BH
46
PCR_10
Port 10 Configuration
020CH
46
PCR_11
Port 11 Configuration
020DH
46
PCR_12
Port 12 Configuration
020EH
46
PCR_13
Port 13 Configuration
020FH
46
PCR_14
Port 14 Configuration
0210H
46
PCR_15
Port 15 Configuration
0211H
46
RES1
Reserved Register 1
0212H
46
RES2
Reserved Register 2
0213H
47
RES3
Reserved Register 3
0214H
47
RES4
Reserved Register 4
0215H
47
RES5
Reserved Register 5
0216H
47
RES6
Reserved Register 6
0217H
47
RES7
Reserved Register 7
0218H
47
RES8
Reserved Register 8
0219H
47
PCR_16
Port 16 Configuration
021AH
46
PCR_17
Port 17 Configuration
021BH
46
MC
Miscellaneous Configuration
021CH
48
VLAN
VLAN(TOS) Priority Map
021DH
48
FGOPML_0
Forwarding Group 0 Outbound Port Map Low
021EH
50
FGOPMH_0
Forwarding Group 0 Outbound Port Map High
021FH
52
FGOPML_1
Forwarding Group 1 Outbound Port Map Low
0220H
51
FGOPMH_1
Forwarding Group 1 Outbound Port Map High
0221H
53
Data Sheet
36
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
Table 17
Registers Overview (cont’d)
Register Short Name
Register Long Name
Offset Address
Page Number
FGOPML_2
Forwarding Group 2 Outbound Port Map Low
0222H
51
FGOPMH_2
Forwarding Group 2 Outbound Port Map High
0223H
53
FGOPML_3
Forwarding Group 3 Outbound Port Map Low
0224H
51
FGOPMH_3
Forwarding Group 3 Outbound Port Map High
0225H
53
FGOPML_4
Forwarding Group 4 Outbound Port Map Low
0226H
51
FGOPMH_4
Forwarding Group 4 Outbound Port Map High
0227H
53
FGOPML_5
Forwarding Group 5 Outbound Port Map Low
0228H
51
FGOPMH_5
Forwarding Group 5 Outbound Port Map High
0229H
53
FGOPML_6
Forwarding Group 6 Outbound Port Map Low
022AH
51
FGOPMH_6
Forwarding Group 6 Outbound Port Map High
022BH
53
FGOPML_7
Forwarding Group 7 Outbound Port Map Low
022CH
51
FGOPMH_7
Forwarding Group 7 Outbound Port Map High
022DH
53
FGOPML_8
Forwarding Group 8 Outbound Port Map Low
022EH
51
FGOPMH_8
Forwarding Group 8 Outbound Port Map High
022FH
53
FGOPML_9
Forwarding Group 9 Outbound Port Map Low
0230H
51
FGOPMH_9
Forwarding Group 9 Outbound Port Map High
0231H
53
FGOPML_10
Forwarding Group 10 Outbound Port Map Low
0232H
51
FGOPMH_10
Forwarding Group 10 Outbound Port Map High
0233H
53
FGOPML_11
Forwarding Group 11 Outbound Port Map Low
0234H
51
FGOPMH_11
Forwarding Group 11 Outbound Port Map High
0235H
53
FGOPML_12
Forwarding Group 12 Outbound Port Map Low
0236H
51
FGOPMH_12
Forwarding Group 12 Outbound Port Map High
0237H
53
FGOPML_13
Forwarding Group 13 Outbound Port Map Low
0238H
51
FGOPMH_13
Forwarding Group 13 Outbound Port Map High
0239H
53
FGOPML_14
Forwarding Group 14 Outbound Port Map Low
023AH
51
FGOPMH_14
Forwarding Group 14 Outbound Port Map High
023BH
53
FGOPML_15
Forwarding Group 15 Outbound Port Map Low
023CH
51
FGOPMH_15
Forwarding Group 15 Outbound Port Map High
023DH
53
FGOPML_16
Forwarding Group 16 Outbound Port Map Low
023EH
51
FGOPMH_16
Forwarding Group 16 Outbound Port Map High
023FH
53
FGOPML_17
Forwarding Group 17 Outbound Port Map Low
0240H
51
FGOPMH_17
Forwarding Group 17 Outbound Port Map High
0241H
53
FGOPML_18
Forwarding Group 18 Outbound Port Map Low
0242H
52
FGOPMH_18
Forwarding Group 18 Outbound Port Map High
0243H
53
FGOPML_19
Forwarding Group 19 Outbound Port Map Low
0244H
52
FGOPMH_19
Forwarding Group 19 Outbound Port Map High
0245H
53
FGOPML_20
Forwarding Group 20 Outbound Port Map Low
0246H
52
FGOPMH_20
Forwarding Group 20 Outbound Port Map High
0247H
53
FGOPML_21
Forwarding Group 21 Outbound Port Map Low
0248H
52
FGOPMH_21
Forwarding Group 21 Outbound Port Map High
0249H
53
FGOPML_22
Forwarding Group 22 Outbound Port Map Low
024AH
52
Data Sheet
37
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
Table 17
Registers Overview (cont’d)
Register Short Name
Register Long Name
Offset Address
Page Number
FGOPMH_22
Forwarding Group 22 Outbound Port Map High
024BH
53
FGOPML_23
Forwarding Group 23 Outbound Port Map Low
024CH
52
FGOPMH_23
Forwarding Group 23 Outbound Port Map High
024DH
54
FGOPML_24
Forwarding Group 24 Outbound Port Map Low
024EH
52
FGOPMH_24
Forwarding Group 24 Outbound Port Map High
024FH
54
FGOPML_25
Forwarding Group 25 Outbound Port Map Low
0250H
52
FGOPMH_25
Forwarding Group 25 Outbound Port Map High
0251H
54
FGOPML_26
Forwarding Group 26 Outbound Port Map Low
0252H
52
FGOPMH_26
Forwarding Group 26 Outbound Port Map High
0253H
54
FGOPML_27
Forwarding Group 27 Outbound Port Map Low
0254H
52
FGOPMH_27
Forwarding Group 27 Outbound Port Map High
0255H
54
FGOPML_28
Forwarding Group 28 Outbound Port Map Low
0256H
52
FGOPMH_28
Forwarding Group 28 Outbound Port Map High
0257H
54
FGOPML_29
Forwarding Group 29 Outbound Port Map Low
0258H
52
FGOPMH_29
Forwarding Group 29 Outbound Port Map High
0259H
54
FGOPML_30
Forwarding Group 30 Outbound Port Map Low
025AH
52
FGOPMH_30
Forwarding Group 30 Outbound Port Map High
025BH
54
FGOPML_31
Forwarding Group 31 Outbound Port Map Low
025CH
52
FGOPMH_31
Forwarding Group 31 Outbound Port Map High
025DH
54
P0VIDS
P0 VID and PVID Shift
025EH
54
P1_VID
P1 VID Configuration
025FH
55
P2_VID
P2 VID Configuration
0260H
56
P3_VID
P3 VID Configuration
0261H
56
P4_VID
P4 VID Configuration
0262H
56
P5_VID
P5 VID Configuration
0263H
56
P6_VID
P6 VID Configuration
0264H
56
P7_VID
P7 VID Configuration
0265H
56
P8_VID
P8 VID Configuration
0266H
56
P9_VID
P9 VID Configuration
0267H
56
P10_VID
P10 VID Configuration
0268H
56
P11_VID
P11 VID Configuration
0269H
56
P12_VID
P12 VID Configuration
026AH
56
P13_VID
P13 VID Configuration
026BH
56
P14_VID
P14 VID Configuration
026CH
56
P15_VID
P15 VID Configuration
026DH
56
RES9
Reserved Register 9
026EH
47
RES10
Reserved Register 10
026FH
47
RES11
Reserved Register 11
0270H
47
RES12
Reserved Register 12
0271H
47
RES13
Reserved Register 13
0272H
47
RES14
Reserved Register 14
0273H
47
Data Sheet
38
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
Table 17
Registers Overview (cont’d)
Register Short Name
Register Long Name
Offset Address
Page Number
RES15
Reserved Register 15
0274H
47
RES16
Reserved Register 16
0275H
47
P24_VID
P24 VID Configuration
0276H
56
P25_VID
P25 VID Configuration
0277H
56
P0_3_BCR
P0, P1, P2, P3 Bandwidth Control Register
0278H
56
P4_7_BCR
P4, P5, P6, P7 Bandwidth Control Register
0279H
57
P8_11_BCR
P8, P9, P10, P11 Bandwidth Control Register
027AH
59
P12_15_BCR
P12, P13, P14, P15 Bandwidth Control Register
027BH
60
RES17
Reserved Register 17
027CH
47
RES18
Reserved Register 18
027DH
47
P24_25_BCR
P24, P25 Bandwidth Control Register
027EH
61
BCERL
Bandwidth Control Enable Register Low
027FH
62
BCERH
Bandwidth Control Enable Register High
0280H
63
RES19
Reserved Register 19
0281H
47
RES20
Reserved Register 20
0282H
47
RES21
Reserved Register 21
0283H
47
RES22
Reserved Register 22
0284H
47
RES23
Reserved Register 23
0285H
47
RES24
Reserved Register 24
0286H
47
RES25
Reserved Register 25
0287H
47
RES26
Reserved Register 26
0288H
47
RES27
Reserved Register 27
0289H
47
RES28
Reserved Register 28
028AH
47
CPHYCG0
Customized PHY Control Group 0
028BH
63
CPHYCG1
Customized PHY Control Group 1
028CH
65
CPHYCG2
Customized PHY Control Group 2
028DH
66
CPHYCG3
Customized PHY Control Group 3
028EH
66
G0PHYCD0
Group 0 PHY Customized DATA 0
028FH
67
G0PHYCD1
Group 0 PHY Customized DATA 1
0290H
67
G1PHYCD0
Group 1 PHY Customized DATA 0
0291H
68
G1PHYCD1
Group 1 PHY Customized DATA 1
0292H
68
G2PHYCD0
Group 2 PHY Customized DATA 0
0293H
68
G2PHYCD1
Group 2 PHY Customized DATA 1
0294H
69
G3PHYCD0
Group 3 PHY Customized DATA 0
0295H
69
G3PHYCD1
Group 3 PHY Customized DATA 1
0296H
69
PHYCE
PHY Customized Enable Register
0297H
70
PPPOEC0
PPPOE Control Register 0
0298H
71
PPPOEC1
PPPOE Control Register 1
0299H
72
PHYCR0
PHY Control Register 0
029AH
72
PHYCR1
PHY Control Register 1
029BH
73
DMDIOAR0
Disable MDIO Active Register 0
029CH
74
Data Sheet
39
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
Table 17
Registers Overview (cont’d)
Register Short Name
Register Long Name
Offset Address
Page Number
DMDIOAR1
Disable MDIO Active Register 1
029DH
75
PDR0
Port Disable Register 0
029EH
75
PDR1
Port Disable Register 1
029FH
76
IGMPSCR0
IGMP Snooping Control Register 0
02A0H
76
IGMPSCR1
IGMP Snooping Control Register 1
02A1H
77
CPUCR
CPU Control Register
02A2H
78
SMACFCR0
Special MAC Forward Control Register 0
02A3H
80
SMACFCR1
Special MAC Forward Control Register 1
02A4H
81
SMACFCR2
Special MAC Forward Control Register 2
02A5H
82
TER0
Trunking Enable Register 0
02A6H
83
TER1
Trunking Enable Register 1
02A7H
84
The register is addressed wordwise.
Table 18
Register Access Types
Mode
Symbol Description HW
Description SW
read/write
rw
Register is used as input for the HW
Register is read and writable by SW
read
r
Register is written by HW (register
Value written by software is ignored by
between input and output -> one cycle hardware; that is, software may write any
delay)
value to this field without affecting hardware
behavior (= Target for development.)
Read only
ro
Register is set by HW (register between SW can only read this register
input and output -> one cycle delay)
Read virtual
rv
Physically, there is no new register, the SW can only read this register
input of the signal is connected directly
to the address multiplexer.
Latch high,
self clearing
lhsc
Latch high signal at high level, clear on SW can read the register
read
Latch low,
self clearing
llsc
Latch high signal at low-level, clear on SW can read the register
read
Latch high,
mask clearing
lhmk
Latch high signal at high level, register SW can read the register, with write mask
cleared with written mask
the register can be cleared (1 clears)
Latch low,
mask clearing
llmk
Latch high signal at low-level, register
cleared on read
SW can read the register, with write mask
the register can be cleared (1 clears)
Interrupt high,
self clearing
ihsc
Differentiate the input signal (low>high) register cleared on read
SW can read the register
Interrupt low,
self clearing
ilsc
Differentiate the input signal (high>low) register cleared on read
SW can read the register
Interrupt high,
mask clearing
ihmk
Differentiate the input signal (highSW can read the register, with write mask
>low) register cleared with written mask the register can be cleared
Interrupt low,
mask clearing
ilmk
Differentiate the input signal (low>high) register cleared with written
mask
Data Sheet
40
SW can read the register, with write mask
the register can be cleared
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
Table 18
Register Access Types (cont’d)
Mode
Symbol Description HW
Description SW
Interrupt enable ien
register
Enables the interrupt source for
interrupt generation
SW can read and write this register
latch_on_reset
lor
rw register, value is latched after first
clock cycle after reset
Register is read and writable by SW
Read/write
self clearing
rwsc
Register is used as input for the hw, the Writing to the register generates a strobe
register will be cleared due to a HW
signal for the HW (1 pdi clock cycle)
mechanism.
Register is read and writable by SW.
Table 19
Registers Clock DomainsRegisters Clock Domains
Clock Short Name
4.1.1
Description
EEPROM Register Descriptions
Signature
SIG
Signature
Offset
0200H
Reset Value
4154H
6,*
UR
Field
Bits
Type
Description
SIG
15:0
ro
Signature
The value must be at 4154H. ADM6918/X uses this value to check if the
EEPROM is attached. If the value in the EEPROM doesn’t equal to
4154H, the ADM6918/X will not load the EEPROM even if the EEPROM
is attached.
Global Configuration Register
GCR
Global Configuration Register
Data Sheet
Offset
0201H
41
Reset Value
3800H
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
5HV
)0&(
/(% )170 %0
%
UZ
UZ
UZ
UZ
9*0 &9*
UZ
UZ
'0
345
%6)(
%
%67
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
FMCEB
14
rw
Fast Management Clock Enable Bit
0B
, The switch will use 2.5 M clock to configure the phys.
1B
, The switch will use 10 M clock to configure the phys.
LEB
13
rw
Length 1536 Enable Bit
0B
, The switch can receive packets of less then 1518 bytes.
1B
, The switch can receive packets of less than 1536 bytes.
FNTM
12
rw
Force No Tag Mode
0B
, The switch is not configured to Force No Tag Mode.
1B
, The switch is configured to Force No Tag Mode. In this mode, the
ADM6918/X will not recognize the VLAN TAG even if they contain
a Tag Header.
BM
11
rw
Bypass Mode
0B
, The switch is not configured to Bypass Mode.
1B
, The switch is configured to Bypass Mode. The packets will not be
modified when they are transmitted.
VGM
10
rw
VLAN Group Mode
1B
, The switch is configured to Tagged Based VLAN
0B
, The switch is configured to Port Based VLAN.
CVG
9
rw
Check VLAN Group
0B
, The ADM6918/X will disable the Check VLAN Group function.
1B
, The ADM6918/X will check if the packets and the receiving port
are at the same Forwarding Group. That is, the output port map for
the receiving packet must contain the receiving port. If they belong
to different Forwarding Group, the receiving packets will be
discarded.
Note: Example: Port 3 receives a packet and finds Forwarding
Group contains P0, P1, and P2 (doesn’t contain P3). This
packet will be dropped.
DM
8:5
rw
Discard Mode
This function enables the switch to discard packets according to their
priorities if the receiving port disables the flow control function. Users
could use this to prevent packets with the low priority to block those with
high priority.
Bit[8:7] = High Queue Discard Mode (see Sec. 3.1.18)
Bit[6:5] = Low Queue Discard Mode
Data Sheet
42
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
Field
Bits
Type
Description
PQR
4:3
rw
Priority Queue Ratio
The ADM6918/X supports two priorities on each output port using
weighted round robin scheme. The ratio between the low and high queue
is as follows:
Bit[4:3] Ratio
00B , 1:2
01B , 1:4
10B , 1:8
11B , 1:16
BSFEB
2
rw
Broadcast Storm Filtering Enable Bit
0B
, The ADM6918/X disables the broadcast storm filtering function.
1B
, The ADM6918/X enables the broadcast storm filtering function.
BST
1:0
rw
Broadcast Storm Threshold
Port 0 Configuration Register
PCR_0
Port 0 Configuration Register
Offset
0202H
Reset Value
80FFH
%3(%
)60
330
(33
793
6)(
73
'$
6$
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
$1(0 )&$) ) + )' +'
&5
' '$$5 '$$5 $$5 $$5
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
BPEB
15
rw
Back Pressure Enable Bit
0B
, The MAC controller doesn’t support back-pressure function in half
duplex.
1B
, The MAC controller supports back-pressure function in half
duplex.
Data Sheet
43
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
Field
Bits
Type
Description
FSM
14:13
rw
Four Security Mode
00B , The switch will forward packets with “unknown source addresses”
to the CPU port and not learn it if the receiving port is configured to
enable security function. The “unknown source address” means
that we can’t find an equal address existed in the learning table and
its corresponding port number equals to the receiving port. This
function needs CUP’s help because we need to create a “static
address” to the learning table from the CPU. “Static” means this
address will always exist in the leaning table and can only be
removed through the CPU. When the address is configured to
“Static”, we can prevent this address from overlapping when it is
received from a port without the security function enabled.
01B , The switch will discard packets with “unknown source addresses”
and not learn it if the receiving port is configured to enable security
function. Only packets with source addresses existed in the
learning table will be forwarded.
10B , The first received packets will be locked at the receiving port if the
receiving port is configured to enable security function. Only the
packets with the source address same as the locked one will be
forwarded and learned.
11B , The first received packets will be locked as above. The difference
is that the receiving port will not receive and learn packets any more
after the link goes down even it links up again (it may happen if the
station moves to the other port).
PPM
12
rw
Port-base Priority Mapping
0B
, Mapped for the Low Queue.
1B
, Mapped for the High Queue.
EPP
11
rw
Enable Port-base Priority
0B
, The switch will use the IPv4 or Tag priority fields for the queue
mapping (See Bit [10]). If the packets contain no priority field, then
the switch will use the Port-Priority for the default priority.
1B
, The switch will always use the Port-Priority for the queue mapping
even if the receiving packets contain IPv4 or Tag information.
TVP
10
rw
TOS over VLAN Priority
0B
, When the receiving packets contain the IPv4 and Tag Priority at
the same time, the switch will use Tag priority field for the queue
mapping.
1B
, When the receiving packets contain the IPv4 and Tag Priority at
the same time, the switch will use IPv4 priority field for the queue
mapping.
SFE
9
rw
Security Function Enable
0B
, The switch disables the security function.
1B
, The switch enables the security function. Four security modes
could be selected through Bit[14:13].
Data Sheet
44
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
Field
Bits
Type
Description
TP
8
rw
Tagged Port
0B
, The transmitted port is configured to an untagged port. The
transmitted packets from an untagged port will not contain a Tag
Header except the transmitted packets are management packet or
the Bypass Mode is enabled.
1B
, The transmitted port is configured to a tagged port. The
transmitted packets from a tagged port will always contain a Tag
Header except the transmitted packets are management packet or
the Bypass Mode is enabled.
DA
7
rw
Duplex Ability
This bit will be used as Bit 8 (Duplex Select) in the Basic Mode Control
Register if bypass management function is not enabled, and be used as
Duplex Desired if bypass management function is enabled.
0B
, Half Duplex Enabled.
1B
, Full Duplex Enabled.
SA
6
rw
Speed Ability
This bit will be used as Bit 13 (Speed Select) in the Basic Mode Control
Register if bypass management function is not enabled, and be used as
Speed Desired if bypass management function is enabled.
0B
, 10 Mbit/s Enabled.
1B
, 100 Mbit/s Enabled.
ANEMCR
5
rw
Auto Negotiation Enable in Basic Mode Control Register
0B
, Auto-Negotiation is Disabled.
1B
, Auto-Negotiation is Enabled.
FCAFD
4
rw
802.3x Flow Control Ability in Full Duplex
0B
, (1). Mac controller doesn’t support Pause Frames when the port is
configured to bypass management function from MDC/MDIO.
(2). If the port is not configured to bypass management function
form MDC/MDIO, then it will be used as the Pause bit in AutoNegotiation Advertisement Register and the Pause function will not
be advertised. If Auto-Negotiation function is disabled, then this bit
is used and Pause is not supported.
(3). If the port is not configured to bypass management function
from MDC/MDIO and no PHY is attached to this port, the MAC
controller will not support Pause Frames in the full duplex.
1B
, (1). MAC controller supports Pause Frames when the port is
configured to bypass management function from MDC/MDIO.
(2). If the port is not configured to bypass management function
form MDC/MDIO, then it will be used as the Pause bit in AutoNegotiation Advertisement Register and the Pause function will be
advertised. If Auto-Negotiation function is disabled, then this bit is
used and Pause is supported.
(3). If the port is not configured to bypass management function
from MDC/MDIO and no PHY is attached to this port, the MAC
controller will support Pause Frames in the full duplex.
100FDAAR
3
rw
100Base-TX Full Duplex Ability in Auto-Negotiation Advertisement
Register
0B
, 100Base-Tx Full Duplex is not advertised.
1B
, 100Base-TX Full Duplex is advertised.
Data Sheet
45
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
Field
Bits
Type
Description
100HDAAR
2
rw
100Base-TX Half Duplex Ability in Auto-Negotiation Advertisement
Register
0B
, 100Base-TX Half Duplex is not advertised.
1B
, 100Base-TX Half Duplex is advertised.
10FDAAR
1
rw
10Base-T Full Duplex Ability in Auto-Negotiation Advertisement
Register
0B
, 10Base-T Full Duplex is not advertised.
1B
, 10Base-T Full Duplex is advertised.
10HDAAR
0
rw
10Base-T Half Duplex Ability in Auto-Negotiation Advertisement
Register
0B
, 10Base-T Half Duplex is not advertised.
1B
, 10Base-T Half Duplex is advertised.
All PCR_x registers have the same structure and characteristics, see PCR_0.
The offset addresses of the other PCR_x registers are listed in Table 20.
Table 20
PCR_x Registers
Register Short Name
Register Long Name
Offset Address
PCR_1
Port 1 Configuration
0203H
PCR_2
Port 2 Configuration
0204H
PCR_3
Port 3 Configuration
0205H
PCR_4
Port 4 Configuration
0206H
PCR_5
Port 5 Configuration
0207H
PCR_6
Port 6 Configuration
0208H
PCR_7
Port 7 Configuration
0209H
PCR_8
Port 8 Configuration
020AH
PCR_9
Port 9 Configuration
020BH
PCR_10
Port 10 Configuration
020CH
PCR_11
Port 11 Configuration
020DH
PCR_12
Port 12 Configuration
020EH
PCR_13
Port 13 Configuration
020FH
PCR_14
Port 14 Configuration
0210H
PCR_15
Port 15 Configuration
0211H
PCR_16
Port 16 Configuration
021AH
PCR_17
Port 17 Configuration
021BH
Page Number
Reserved Register 1
RES1
Reserved Register 1
Data Sheet
Offset
0212H
46
Reset Value
Table 15
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
5HV
UZ
Field
Bits
Type
Description
Res
15:0
rw
Reserved
For the future use and don’t modify the values.
Default: See Chapter 4
All RESx registers have the same structure and characteristics, see RES1. The offset addresses of the other RESx
registers are listed in Table 21.
Table 21
Resx Registers
Register Short Name
Register Long Name
Offset Address
RES2
Reserved Register 2
0213H
RES3
Reserved Register 3
0214H
RES4
Reserved Register 4
0215H
RES5
Reserved Register 5
0216H
RES6
Reserved Register 6
0217H
RES7
Reserved Register 7
0218H
RES8
Reserved Register 8
0219H
RES9
Reserved Register 9
026EH
RES10
Reserved Register 10
026FH
RES11
Reserved Register 11
0270H
RES12
Reserved Register 12
0271H
RES13
Reserved Register 13
0272H
RES14
Reserved Register 14
0273H
RES15
Reserved Register 15
0274H
RES16
Reserved Register 16
0275H
RES17
Reserved Register 17
027CH
RES18
Reserved Register 18
027DH
RES19
Reserved Register 19
0281H
RES20
Reserved Register 20
0282H
RES21
Reserved Register 21
0283H
RES22
Reserved Register 22
0284H
RES23
Reserved Register 23
0285H
RES24
Reserved Register 24
0286H
RES25
Reserved Register 25
0287H
RES26
Reserved Register 26
0288H
RES27
Reserved Register 27
0289H
RES28
Reserved Register 28
028AH
Data Sheet
47
Page Number
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
Miscellaneous Configuration
MC
Miscellaneous Configuration
5HV
Offset
021CH
Reset Value
0820H
5HV
&/('
(
5HV
(5,'
5HV
UZ
UZ
UZ
UZ
UZ
5&' '%)
UZ
UZ
Field
Bits
Type
Description
Res
13:10
rw
Reserved
CLEDE
9
rw
Collision LED Enable
0B
, The switch will not provide two collision LEDs for 10M and 100M
domain individually
1B
, The switch will provide two collision LEDs for 10M and 100M
domain individually and flash in rate of 2 Hz.
Res
8:4
rw
Reserved
ERID
3
rw
Enable Replace VLAN ID
0B
, The switch will use the original VID received from the Tag Header.
1B
, The switch will replace the VID with the PVID associated with the
receiving port when the received packets are priority tagged or its
VID in the Tag Header equals to 1.
Res
2
rw
Reserved
RCD
1
rw
Recommend 16th Collision Drop
0B
, The Mac controller will retransmit packets even when the collision
count is larger than 16.
1B
, The Mac controller will drop packets when the collision count is
larger than 16.
DBF
0
rw
Disable CSMA/CD Back-off Function
0B
, The Mac controller supports random back off function.
1B
, The MAC controller will disable random back off function.
VLAN(TOS) Priority Map
VLAN
VLAN(TOS) Priority Map
Offset
021DH
034 034 034 034 034 034 034 034
UZ
UZ
Data Sheet
UZ
UZ
UZ
UZ
UZ
Reset Value
0000H
0347 0347 0347 0347 0347 0347 0347 0347
UZ
UZ
48
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
Field
Bits
Type
Description
MPQ7
15
rw
Mapped Priority Queue of TOS 7
0B
, Mapped for Low Queue
1B
, Mapped for High Queue
MPQ6
14
rw
Mapped Priority Queue of TOS 6
0B
, Mapped for Low Queue
1B
, Mapped for High Queue
MPQ5
13
rw
Mapped Priority Queue of TOS 5
0B
, Mapped for Low Queue
1B
, Mapped for High Queue
MPQ4
12
rw
Mapped Priority Queue of TOS 4
0B
, Mapped for Low Queue
1B
, Mapped for High Queue
MPQ3
11
rw
Mapped Priority Queue of TOS 3
0B
, Mapped for Low Queue
1B
, Mapped for High Queue
MPQ2
10
rw
Mapped Priority Queue of TOS 2
0B
, Mapped for Low Queue
1B
, Mapped for High Queue
MPQ1
9
rw
Mapped Priority Queue of TOS 1
0B
, Mapped for Low Queue
1B
, Mapped for High Queue
MPQ0
8
rw
Mapped Priority Queue of TOS 0
0B
, Mapped for Low Queue
1B
, Mapped for High Queue
MPQT7
7
rw
Mapped Priority Queue of Tag Value 7
0B
, Mapped for Low Queue
1B
, Mapped for High Queue
MPQT6
6
rw
Mapped Priority Queue of Tag Value 6
0B
, Mapped for Low Queue
1B
, Mapped for High Queue
MPQT5
5
rw
Mapped Priority Queue of Tag Value 5
0B
, Mapped for Low Queue
1B
, Mapped for High Queue
MPQT4
4
rw
Mapped Priority Queue of Tag Value 4
0B
, Mapped for Low Queue
1B
, Mapped for High Queue
MPQT3
3
rw
Mapped Priority Queue of Tag Value 3
0B
, Mapped for Low Queue
1B
, Mapped for High Queue
MPQT2
2
rw
Mapped priority Queue of Tag Value 2
0B
, Mapped for Low Queue
1B
, Mapped for High Queue
MPQT1
1
rw
Mapped Priority Queue of Tag Value 1
0B
, Mapped for Low Queue
1B
, Mapped for High Queue
Data Sheet
49
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
Field
Bits
Type
Description
MPQT0
0
rw
Mapped Priority Queue of Tag Value 0
0B
, Mapped for Low Queue
1B
, Mapped for High Queue
Forwarding Group 0 Outbound Port Map Low
FGOPML_0
Forwarding Group 0 Outbound Port Map Low
Offset
021EH
Reset Value
FFFFH
)*B )*B )*B )*B )*B )*B
)*B )*B )*B )*B )*B )*B )*B )*B )*B )*B
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
FG_15
15
rw
Forwarding Group Port 15
0B
, Port 15 is not in the Forwarding Group
1B
, Port 15 is in the Forwarding Group
FG_14
14
rw
Forwarding Group Port 14
0B
, Port 14 is not in the Forwarding Group
1B
, Port 14 is in the Forwarding Group
FG_13
13
rw
Forwarding Group Port 13
0B
, Port 13 is not in the Forwarding Group
1B
, Port 13 is in the Forwarding Group
FG_12
12
rw
Forwarding Group Port 12
0B
, Port 12 is not in the Forwarding Group
1B
, Port 12 is in the Forwarding Group
FG_11
11
rw
Forwarding Group Port 11
0B
, Port 11 is not in the Forwarding Group
1B
, Port 11 is in the Forwarding Group
FG_10
10
rw
Forwarding Group Port 10
0B
, Port 10 is not in the Forwarding Group
1B
, Port 10 is in the Forwarding Group
FG_9
9
rw
Forwarding Group Port 9
0B
, Port 9 is not in the Forwarding Group
1B
, Port 9 is in the Forwarding Group
FG_8
8
rw
Forwarding Group Port 8
0B
, Port 8 is not in the Forwarding Group
1B
, Port 8 is in the Forwarding Group
FG_7
7
rw
Forwarding Group Port 7
0B
, Port 7 is not in the Forwarding Group
1B
, Port 7 is in the Forwarding Group
Data Sheet
50
UZ
UZ
UZ
UZ
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
Field
Bits
Type
Description
FG_6
6
rw
Forwarding Group Port 6
0B
, Port 6 is not in the Forwarding Group
1B
, Port 6 is in the Forwarding Group
FG_5
5
rw
Forwarding Group Port 5
0B
, Port 5 is not in the Forwarding Group
1B
, Port 5 is in the Forwarding Group
FG_4
4
rw
Forwarding Group Port 4
0B
, Port 4 is not in the Forwarding Group
1B
, Port 4 is in the Forwarding Group
FG_3
3
rw
Forwarding Group Port 3
0B
, Port 3 is not in the Forwarding Group
1B
, Port 3 is in the Forwarding Group
FG_2
2
rw
Forwarding Group Port 2
0B
, Port 2 is not in the Forwarding Group
1B
, Port 2 is in the Forwarding Group
FG_1
1
rw
Forwarding Group Port 1
0B
, Port 1 is not in the Forwarding Group
1B
, Port 1 is in the Forwarding Group
FG_0
0
rw
Forwarding Group Port 0
0B
, Port 0 is not in the Forwarding Group
1B
, Port 0 is in the Forwarding Group
All FGOPML_x registers have the same structure and characteristics, see FGOPML_0. The offset addresses of
the other FGOPML_x registers are listed in Table 22.
Table 22
FGOPML_x Registers
Register Short Name
Register Long Name
Offset Address
FGOPML_1
Forwarding Group 1 Outbound Port Map Low
0220H
FGOPML_2
Forwarding Group 2 Outbound Port Map Low
0222H
FGOPML_3
Forwarding Group 3 Outbound Port Map Low
0224H
FGOPML_4
Forwarding Group 4 Outbound Port Map Low
0226H
FGOPML_5
Forwarding Group 5 Outbound Port Map Low
0228H
FGOPML_6
Forwarding Group 6 Outbound Port Map Low
022AH
FGOPML_7
Forwarding Group 7 Outbound Port Map Low
022CH
FGOPML_8
Forwarding Group 8 Outbound Port Map Low
022EH
FGOPML_9
Forwarding Group 9 Outbound Port Map Low
0230H
FGOPML_10
Forwarding Group 10 Outbound Port Map Low
0232H
FGOPML_11
Forwarding Group 11 Outbound Port Map Low
0234H
FGOPML_12
Forwarding Group 12 Outbound Port Map Low
0236H
FGOPML_13
Forwarding Group 13 Outbound Port Map Low
0238H
FGOPML_14
Forwarding Group 14 Outbound Port Map Low
023AH
FGOPML_15
Forwarding Group 15 Outbound Port Map Low
023CH
FGOPML_16
Forwarding Group 16 Outbound Port Map Low
023EH
FGOPML_17
Forwarding Group 17 Outbound Port Map Low
0240H
Data Sheet
51
Page Number
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
Table 22
FGOPML_x Registers (cont’d)
Register Short Name
Register Long Name
Offset Address
FGOPML_18
Forwarding Group 18 Outbound Port Map Low
0242H
FGOPML_19
Forwarding Group 19 Outbound Port Map Low
0244H
FGOPML_20
Forwarding Group 20 Outbound Port Map Low
0246H
FGOPML_21
Forwarding Group 21 Outbound Port Map Low
0248H
FGOPML_22
Forwarding Group 22 Outbound Port Map Low
024AH
FGOPML_23
Forwarding Group 23 Outbound Port Map Low
024CH
FGOPML_24
Forwarding Group 24 Outbound Port Map Low
024EH
FGOPML_25
Forwarding Group 25 Outbound Port Map Low
0250H
FGOPML_26
Forwarding Group 26 Outbound Port Map Low
0252H
FGOPML_27
Forwarding Group 27 Outbound Port Map Low
0254H
FGOPML_28
Forwarding Group 28 Outbound Port Map Low
0256H
FGOPML_29
Forwarding Group 29 Outbound Port Map Low
0258H
FGOPML_30
Forwarding Group 30 Outbound Port Map Low
025AH
FGOPML_31
Forwarding Group 31 Outbound Port Map Low
025CH
Page Number
Forwarding Group 0 Outbound Port Map High
FGOPMH_0
Forwarding Group 0 Outbound Port Map High
Offset
021FH
Reset Value
03FFH
)*B )*B )*B )*B )*B )*B )*B )*B )*B )*B
5HV
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
FG_25
9
rw
Forwarding Group Port 25
0B
, Port 25 is not in the Forwarding Group
1B
, Port 25 is in the Forwarding Group
FG_24
8
rw
Forwarding Group Port 24
0B
, Port 24 is not in the Forwarding Group
1B
, Port 24 is in the Forwarding Group
FG_23
7
rw
Forwarding Group Port 23
0B
, Port 23 is not in the Forwarding Group
1B
, Port 23 is in the Forwarding Group
FG_22
6
rw
Forwarding Group Port 22
0B
, Port 22 is not in the Forwarding Group
1B
, Port 22 is in the Forwarding Group
FG_21
5
rw
Forwarding Group Port 21
0B
, Port 21 is not in the Forwarding Group
1B
, Port 21 is in the Forwarding Group
Data Sheet
52
UZ
UZ
UZ
UZ
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
Field
Bits
Type
Description
FG_20
4
rw
Forwarding Group Port 20
0B
, Port 20 is not in the Forwarding Group
1B
, Port 20 is in the Forwarding Group
FG_19
3
rw
Forwarding Group Port 19
0B
, Port 19 is not in the Forwarding Group
1B
, Port 19 is in the Forwarding Group
FG_18
2
rw
Forwarding Group Port 18
0B
, Port 18 is not in the Forwarding Group
1B
, Port 18 is in the Forwarding Group
FG_17
1
rw
Forwarding Group Port 17
0B
, Port 17 is not in the Forwarding Group
1B
, Port 17 is in the Forwarding Group
FG_16
0
rw
Forwarding Group Port 16
0B
, Port 16 is not in the Forwarding Group
1B
, Port 16 is in the Forwarding Group
All FGOPMH_x registers have the same structure and characteristics, see FGOPMH_0. The offset addresses of
the other FGOPMH_x registers are listed in Table 23.
Table 23
FGOPMH_x Registers
Register Short Name
Register Long Name
Offset Address
FGOPMH_1
Forwarding Group 1 Outbound Port Map High
0221H
FGOPMH_2
Forwarding Group 2 Outbound Port Map High
0223H
FGOPMH_3
Forwarding Group 3 Outbound Port Map High
0225H
FGOPMH_4
Forwarding Group 4 Outbound Port Map High
0227H
FGOPMH_5
Forwarding Group 5 Outbound Port Map High
0229H
FGOPMH_6
Forwarding Group 6 Outbound Port Map High
022BH
FGOPMH_7
Forwarding Group 7 Outbound Port Map High
022DH
FGOPMH_8
Forwarding Group 8 Outbound Port Map High
022FH
FGOPMH_9
Forwarding Group 9 Outbound Port Map High
0231H
FGOPMH_10
Forwarding Group 10 Outbound Port Map High
0233H
FGOPMH_11
Forwarding Group 11 Outbound Port Map High
0235H
FGOPMH_12
Forwarding Group 12 Outbound Port Map High
0237H
FGOPMH_13
Forwarding Group 13 Outbound Port Map High
0239H
FGOPMH_14
Forwarding Group 14 Outbound Port Map High
023BH
FGOPMH_15
Forwarding Group 15 Outbound Port Map High
023DH
FGOPMH_16
Forwarding Group 16 Outbound Port Map High
023FH
FGOPMH_17
Forwarding Group 17 Outbound Port Map High
0241H
FGOPMH_18
Forwarding Group 18 Outbound Port Map High
0243H
FGOPMH_19
Forwarding Group 19 Outbound Port Map High
0245H
FGOPMH_20
Forwarding Group 20 Outbound Port Map High
0247H
FGOPMH_21
Forwarding Group 21 Outbound Port Map High
0249H
FGOPMH_22
Forwarding Group 22 Outbound Port Map High
024BH
Data Sheet
53
Page Number
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
Table 23
FGOPMH_x Registers (cont’d)
Register Short Name
Register Long Name
Offset Address
FGOPMH_23
Forwarding Group 23 Outbound Port Map High
024DH
FGOPMH_24
Forwarding Group 24 Outbound Port Map High
024FH
FGOPMH_25
Forwarding Group 25 Outbound Port Map High
0251H
FGOPMH_26
Forwarding Group 26 Outbound Port Map High
0253H
FGOPMH_27
Forwarding Group 27 Outbound Port Map High
0255H
FGOPMH_28
Forwarding Group 28 Outbound Port Map High
0257H
FGOPMH_29
Forwarding Group 29 Outbound Port Map High
0259H
FGOPMH_30
Forwarding Group 30 Outbound Port Map High
025BH
FGOPMH_31
Forwarding Group 31 Outbound Port Map High
025DH
Page Number
P0 VID and PVID Shift
P0VIDS
P0 VID and PVID Shift
9,'6
Offset
025EH
5HV
39,'
UZ
Data Sheet
Reset Value
0001H
UZ
54
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
Field
Bits
Type
Description
VIDS
15:13
rw
VID Shift
This function maps 4096 VLAN into 32 Forwarding Groups
1. In Tagged Based VLAN, the ADM6918/X will use 5 bits from VID as the
Index to map into forwarding groups. 32 forwarding groups are defined in
the ADM6918/X. We use F0, F1, … F31 to call each forwarding group.
This looking scheme is different from the Port Based VLAN because Port
Based VLAN uses port number as the Index to map into the forwarding
groups and then F26 ~ F31 will not be used. The VID is defined as
follows:
• The port’s Default VID is used if the frame is not 802.3ac Tagged (No
Tag Header in the frame).
• The port’s Default VID is used if the frame is 802.3ac Tagged (Tag
Header in the frame) and the frame’s VID is 0000H or 0001H and the
Enable Replace VLAN ID function is enabled.
• The VID in the Tag Header is used if the frame is 802.3 Tagged and
the frame’s VID is not 0000H or 0001H.
• The VID in the Tag Header is used if the frame is 802.3 Tagged and
the frame’s VID is 0000H or 0001H and Enable Replace VLAN ID
function is not enabled.
2. The relation between VID Shift, VID and the forwarding group is as
follows:
Bit[15:13] Forwarding Group
000B , VID[4:0]
001B , VID[5:1]
010B , VID[6:2]
011B , VID[7:3]
100B , VID[8:4]
101B , VID[9:5]
110B , VID[10:6]
111B , VID[11:7]
P0VID
11:0
rw
Port 0 VID
The port’s Default VID is used if the frame is untagged or if the frame’s
VID is 0000H or 0001H and Enable Replace VLAN ID function (also see
Miscellaneous Configuration Register) is enabled.
P1 VID Configuration
P1_VID
P1 VID Configuration
Offset
025FH
5HV
Reset Value
0001H
3'9,'
UZ
Data Sheet
55
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
Field
Bits
Type
Description
PDVID
11:0
rw
The Port’s Default VID
All Px_VID registers have the same structure and characteristics, see P1_VID. The offset addresses of the other
Px_VID registers are listed in Table 24.
Table 24
Px_VID Registers
Register Short Name
Register Long Name
Offset Address
P2_VID
P2 VID Configuration
0260H
P3_VID
P3 VID Configuration
0261H
P4_VID
P4 VID Configuration
0262H
P5_VID
P5 VID Configuration
0263H
P6_VID
P6 VID Configuration
0264H
P7_VID
P7 VID Configuration
0265H
P8_VID
P8 VID Configuration
0266H
P9_VID
P9 VID Configuration
0267H
P10_VID
P10 VID Configuration
0268H
P11_VID
P11 VID Configuration
0269H
P12_VID
P12 VID Configuration
026AH
P13_VID
P13 VID Configuration
026BH
P14_VID
P14 VID Configuration
026CH
P15_VID
P15 VID Configuration
026DH
P24_VID
P24 VID Configuration
0276H
P25_VID
P25 VID Configuration
0277H
Page Number
P0, P1, P2, P3 Bandwidth Control Register
P0_3_BCR
P0, P1, P2, P3 Bandwidth Control Register
Offset
0278H
Reset Value
0000H
353
/&
307&
353
/&
307&
353
/&
307&
353
/&
307&
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
P3RPLC
15
rw
Port 3 Receive Packet Length Counted on the Source Port
0B
, The switch will add length to the P3 counter, default
Data Sheet
56
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
Field
Bits
Type
Description
P3MTC
14:12
rw
Port 3 Meter Threshold Control
000B , 64k, default
001B , 128k
010B , 256k
011B , 512k
100B , 1M
101B , 4M
110B , 10M
111B , 20M
P2RPLC
11
rw
Port 2 Receive Packet Length Counted on the Source Port
0B
, The switch will add length to the P2 counter, default
P2MTC
10:8
rw
Port 2 Meter Threshold Control
000B , 64k, default
001B , 128k
010B , 256k
011B , 512k
100B , 1M
101B , 4M
110B , 10M
111B , 20M
P1RPLC
7
rw
Port 1 Receive Packet Length Counted on the Source Port
0B
, The switch will add length to the P1 counter, default
P1MTC
6:4
rw
Port 1 Meter Threshold Control
000B , 64k, default
001B , 128k
010B , 256k
011B , 512k
100B , 1M
101B , 4M
110B , 10M
111B , 20M
P0RPLC
3
rw
Port 0 Receive Packet Length Counted on the Source Port
0B
, The switch will add length to the P0 counter, default
P0MTC
2:0
rw
Port 0 Meter Threshold Control
000B , 64k, default
001B , 128k
010B , 256k
011B , 512k
100B , 1M
101B , 4M
110B , 10M
111B , 20M
P4, P5, P6, P7 Bandwidth Control Register
P4_7_BCR
P4, P5, P6, P7 Bandwidth Control Register
Data Sheet
Offset
0279H
57
Reset Value
0000H
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
353
/&
307&
353
/&
307&
353
/&
307&
353
/&
307&
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
P7RPLC
15
rw
Port 7 Receive Packet Length Counted on the Source Port
0B
, The switch will add length to the P7 counter, default
P7MTC
14:12
rw
Port 7 Meter Threshold Control
000B , 64k, default
001B , 128k
010B , 256k
011B , 512k
100B , 1M
101B , 4M
110B , 10M
111B , 20M
P6RPLC
11
rw
Port 6 Receive Packet Length Counted on the Source Port
0B
, The switch will add length to the P6 counter, default
P6MTC
10:8
rw
Port 6 Meter Threshold Control
000B , 64k, default
001B , 128k
010B , 256k
011B , 512k
100B , 1M
101B , 4M
110B , 10M
111B , 20M
P5RPLC
7
rw
Port 5 Receive Packet Length Counted on the Source Port
0B
, The switch will add length to the P5 counter, default
P5MTC
6:4
rw
Port 5 Meter Threshold Control
000B , 64k, default
001B , 128k
010B , 256k
011B , 512k
100B , 1M
101B , 4M
110B , 10M
111B , 20M
P4RPLC
3
rw
Port 4 Receive Packet Length Counted on the Source Port
0B
, The switch will add length to the P4 counter, default
Data Sheet
58
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
Field
Bits
Type
Description
P4MTC
2:0
rw
Port 4 Meter Threshold Control
000B , 64k, default
001B , 128k
010B , 256k
011B , 512k
100B , 1M
101B , 4M
110B , 10M
111B , 20M
P8, P9, P10, P11 Bandwidth Control Register
P8_11_BCR
P8, P9, P10, P11 Bandwidth Control Register
Offset
027AH
Reset Value
0000H
35
3/&
307&
35
3/&
307&
353
/&
307&
353
/&
307&
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
P11RPLC
15
rw
Port 11 Receive Packet Length Counted on the Source Port
0B
, The switch will add length to the P11 counter, default
P11MTC
14:12
rw
Port 11 Meter Threshold Control
000B , 64k, default
001B , 128k
010B , 256k
011B , 512k
100B , 1M
101B , 4M
110B , 10M
111B , 20M
P10RPLC
11
rw
Port 10 Receive Packet Length Counted on the Source Port
0B
, The switch will add length to the P10 counter, default
P10MTC
10:8
rw
Port 10 Meter Threshold Control
000B , 64k, default
001B , 128k
010B , 256k
011B , 512k
100B , 1M
101B , 4M
110B , 10M
111B , 20M
P9RPLC
7
rw
Port 9 Receive Packet Length Counted on the Source Port
0B
, The switch will add length to the P9 counter, default
Data Sheet
59
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
Field
Bits
Type
Description
P9MTC
6:4
rw
Port 9 Meter Threshold Control
000B , 64k, default
001B , 128k
010B , 256k
011B , 512k
100B , 1M
101B , 4M
110B , 10M
111B , 20M
P8RPLC
3
rw
Port 8 Receive Packet Length Counted on the Source Port
0B
, The switch will add length to the P8 counter, default
P8MTC
2:0
rw
Port 8 Meter Threshold Control
000B , 64k, default
001B , 128k
010B , 256k
011B , 512k
100B , 1M
101B , 4M
110B , 10M
111B , 20M
P12, P13, P14, P15 Bandwidth Control Register
P12_15_BCR
P12, P13, P14, P15 Bandwidth Control
Register
Offset
027BH
Reset Value
0000H
35
3/&
307&
35
3/&
307&
35
3/&
307&
35
3/&
307&
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
P15RPLC
15
rw
Port 15 Receive Packet Length Counted on the Source Port
0B
, The switch will add length to the P15 counter, default
P15MTC
14:12
rw
Port 15 Meter Threshold Control
000B , 64k, default
001B , 128k
010B , 256k
011B , 512k
100B , 1M
101B , 4M
110B , 10M
111B , 20M
Data Sheet
60
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
Field
Bits
Type
Description
P14RPLC
11
rw
Port 14 Receive Packet Length Counted on the Source Port
0B
, The switch will add length to the P14 counter, default
P14MTC
10:8
rw
Port 14 Meter Threshold Control
000B , 64k, default
001B , 128k
010B , 256k
011B , 512k
100B , 1M
101B , 4M
110B , 10M
111B , 20M
P13RPLC
7
rw
Port 13 Receive Packet Length Counted on the Source Port
0B
, The switch will add length to the P13 counter, default
P13MTC
6:4
rw
Port 13 Meter Threshold Control
000B , 64k, default
001B , 128k
010B , 256k
011B , 512k
100B , 1M
101B , 4M
110B , 10M
111B , 20M
P12RPLC
3
rw
Port 12 Receive Packet Length Counted on the Source Port
0B
, The switch will add length to the P12 counter, default
P12MTC
2:0
rw
Port 12 Meter Threshold Control
000B , 64k, default
001B , 128k
010B , 256k
011B , 512k
100B , 1M
101B , 4M
110B , 10M
111B , 20M
P24, P25 Bandwidth Control Register
P24_25_BCR
P24, P25 Bandwidth Control Register
5HV
Data Sheet
Offset
027EH
Reset Value
0000H
35
3/&
307&
35
3/&
307&
UZ
UZ
UZ
UZ
61
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
Field
Bits
Type
Description
P17RPLC
7
rw
Port 25 Receive Packet Length Counted on the Source Port
0B
, The switch will add length to the P25 counter, default
P17MTC
6:4
rw
Port 25 Meter Threshold Control
000B , 64k, default
001B , 128k
010B , 256k
011B , 512k
100B , 1M
101B , 4M
110B , 10M
111B , 20M
P16RPLC
3
rw
Port 24 Receive Packet Length Counted on the Source Port
0B
, The switch will add length to the P24 counter, default
P16MTC
2:0
rw
Port 24 Meter Threshold Control
000B , 64k, default
001B , 128k
010B , 256k
011B , 512k
100B , 1M
101B , 4M
110B , 10M
111B , 20M
Bandwidth Control Enable Register Low
BCERL
Bandwidth Control Enable Register Low
Offset
027FH
Reset Value
0000H
%&(3 %&(3 %&(3 %&(3 %&(3 %&(3 %&(3 %&(3 %&(3 %&(3 %&(3 %&(3 %&(3 %&(3 %&(3 %&(3
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
BCEP15
15
rw
Bandwidth Control Enable for Port 15
BCEP14
14
rw
Bandwidth Control Enable for Port 14
BCEP13
13
rw
Bandwidth Control Enable for Port 13
BCEP12
12
rw
Bandwidth Control Enable for Port 12
BCEP11
11
rw
Bandwidth Control Enable for Port 11
BCEP10
10
rw
Bandwidth Control Enable for Port 10
BCEP9
9
rw
Bandwidth Control Enable for Port 9
BCEP8
8
rw
Bandwidth Control Enable for Port 8
Data Sheet
62
UZ
UZ
UZ
UZ
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
Field
Bits
Type
Description
BCEP7
7
rw
Bandwidth Control Enable for Port 7
BCEP6
6
rw
Bandwidth Control Enable for Port 6
BCEP5
5
rw
Bandwidth Control Enable for Port 5
BCEP4
4
rw
Bandwidth Control Enable for Port 4
BCEP3
3
rw
Bandwidth Control Enable for Port 3
BCEP2
2
rw
Bandwidth Control Enable for Port 2
BCEP1
1
rw
Bandwidth Control Enable for Port 1
BCEP0
0
rw
Bandwidth Control Enable for Port 0
0B
, Port 0 disables the bandwidth control.
1B
, Port 0 enables the bandwidth control.
Bandwidth Control Enable Register High
BCERH
Bandwidth Control Enable Register High
Offset
0280H
Reset Value
0000H
%&(3 %&(3
5HV
UZ
5HV
UZ
UZ
Field
Bits
Type
Description
BCEP25
9
rw
Bandwidth Control Enable for Port 25
BCEP24
8
rw
Bandwidth Control Enable for Port 24
Res
7:0
rw
Reserved
Customized PHY Control Group 0
CPHYCG0
Customized PHY Control Group 0
Offset
028BH
Reset Value
0000H
3+<$&
5$&
3+<$&
5$&
UZ
UZ
UZ
UZ
Data Sheet
63
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
Field
Bits
Type
Description
PHYAC1
15:13
rw
PHY Address of the Command 1
If Bit[2:0] in PHY Customized Enable Register = 010B or 011B.
000B , The switch will write command 1 into Port 0 (PHY Address =
32’h8).
001B , The switch will write command 1 into Port 1 (PHY Address =
32’h9).
010B , The switch will write command 1 into Port 2 (PHY Address =
32’ha).
011B , The switch will write command 1 into Port 3 (PHY Address =
32’hb).
100B , The switch will write command 1 into Port 4 (PHY Address =
32’hc).
101B , The switch will write command 1 into Port 5 (PHY Address =
32’hd).
110B , The switch will write command 1 into Port 6 (PHY Address =
32’he).
111B , The switch will write command 1 into Port 7 (PHY Address =
32’hf).
RAC1
12:8
rw
Register Address of the Command 1
PHYAC0
7:5
rw
PHY Address of the Command 0
If Bit[2:0] in PHY Customized Enable Register = 001B or 011B.
000B , The switch will write command 0 into Port 0 (PHY Address =
32’h8).
001B , The switch will write command 0 into Port 1 (PHY Address =
32’h9).
010B , The switch will write command 0 into Port 2 (PHY Address =
32’ha).
011B , The switch will write command 0 into Port 3 (PHY Address =
32’hb).
100B , The switch will write command 0 into Port 4 (PHY Address =
32’hc).
101B , The switch will write command 0 into Port 5 (PHY Address =
32’hd).
110B , The switch will write command 0 into Port 6 (PHY Address =
32’he).
111B , The switch will write command 0 into Port 7 (PHY Address =
32’hf).
RAC0
4:0
rw
Register Address of the Command 0
Note: The ADM6918/X supports eight additional commands for the customer to configure the PHY attached. Four
groups are defined and each group shares two commands. Group 0 contains P0, P1, P2, P3, P4, P5, P6
and P7. Group 1 contains P8, P9, P10, P11, P12, P13, P14 and P15. Group 2 contains P16, P17, P18, P19,
P20, P21, P22 and P23. Group 3 contains P24 and P25. 3 bits enable register is associated with each group.
Each command is associated with a PHY address, a register address, and data for writing.
Data Sheet
64
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
Customized PHY Control Group 1
CPHYCG1
Customized PHY Control Group 1
Offset
028CH
Reset Value
0000H
3+<$&
5$&
3+<$&
5$&
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
PHYAC3
15:13
rw
PHY Address of the Command 3
Bit[5:3] in PHY Customized Enable Register = 010B or 011B.
000B , The switch will write command 3 into Port 8 (PHY Address =
32’h10).
001B , The switch will write command 3 into Port 9 (PHY Address =
32’h11).
010B , The switch will write command 3 into Port 10 (PHY Address =
32’h12).
011B , The switch will write command 3 into Port 11 (PHY Address =
32’h13).
100B , The switch will write command 3 into Port 12 (PHY Address =
32’h14).
101B , The switch will write command 3 into Port 13 (PHY Address =
32’h15).
110B , The switch will write command 3 into Port 14 (PHY Address =
32’h16).
111B , The switch will write command 3 into Port 15 (PHY Address =
32’h17).
RAC3
12:8
rw
Register Address of the Command 3
Data Sheet
65
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
Field
Bits
Type
Description
PHYAC2
7:5
rw
PHY Address of the Command 2
Bit[5:3] in PHY Customized Enable Register = 001B or 011B.
000B , The switch will write command 2 into Port 8 (PHY Address =
32’h10).
001B , The switch will write command 2 into Port 9 (PHY Address =
32’h11).
010B , The switch will write command 2 into Port 10 (PHY Address =
32’h12).
011B , The switch will write command 2 into Port 11 (PHY Address =
32’h13).
100B , The switch will write command 2 into Port 12 (PHY Address =
32’h14).
101B , The switch will write command 2 into Port 13 (PHY Address =
32’h15).
110B , The switch will write command 2 into Port 14 (PHY Address =
32’h16).
111B , The switch will write command 2 into Port 15 (PHY Address =
32’h17).
RAC2
4:0
rw
Register Address of the Command 2
Customized PHY Control Group 2
CPHYCG2
Customized PHY Control Group 2
Offset
028DH
Reset Value
0000H
5HV
UZ
Field
Bits
Type
Description
Res
15:0
rw
Reserved
Default 0000H
Customized PHY Control Group 3
CPHYCG3
Customized PHY Control Group 3
5HV
Data Sheet
Offset
028EH
3+<$
&
5$&
UZ
UZ
Reset Value
0000H
5HV
66
3+<$
&
5$&
UZ
UZ
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
Field
Bits
Type
Description
PHYAC7
13
rw
PHY Address of the Command 7
Bit[11:9] in PHY Customized Enable Register = 010B or 011B.
0B
, The switch will write command 7 into Port 24 (PHY Address =
32’h6).
1B
, The switch will write command 7 into Port 25 (PHY Address =
32’h7).
RAC7
12:8
rw
Register Address of the Command 7
PHYAC6
5
rw
PHY Address of the Command 6
Bit[11:9] in PHY Customized Enable Register = 001B or 011B.
0B
, The switch will write command 6 into Port 24 (PHY Address =
32’h6).
1B
, The switch will write command 6 into Port 25 (PHY Address =
32’h7).
RAC6
4:0
rw
Register Address of the Command 6
Group 0 PHY Customized DATA 0
G0PHYCD0
Group 0 PHY Customized DATA 0
Offset
028FH
Reset Value
0000H
'&
UZ
Field
Bits
Type
Description
DC0
15:0
rw
Data for Command 0
Group 0 PHY Customized DATA 1
G0PHYCD1
Group 0 PHY Customized DATA 1
Offset
0290H
Reset Value
0000H
'&
UZ
Field
Bits
Type
Description
DC1
15:0
rw
Data for Command 1
Data Sheet
67
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
Group 1 PHY Customized DATA 0
G1PHYCD0
Group 1 PHY Customized DATA 0
Offset
0291H
Reset Value
0000H
'&
UZ
Field
Bits
Type
Description
DC2
15:0
rw
Data for Command 2
Group 1 PHY Customized DATA 1
G1PHYCD1
Group 1 PHY Customized DATA 1
Offset
0292H
Reset Value
0000H
'&
UZ
Field
Bits
Type
Description
DC3
15:0
rw
Data for Command 3
Group 2 PHY Customized DATA 0
G2PHYCD0
Group 2 PHY Customized DATA 0
Offset
0293H
Reset Value
0000H
'&
UZ
Field
Bits
Type
Description
DC4
15:0
rw
Data for Command 4
Data Sheet
68
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
Group 2 PHY Customized DATA 1
G2PHYCD1
Group 2 PHY Customized DATA 1
Offset
0294H
Reset Value
0000H
'&
UZ
Field
Bits
Type
Description
DC5
15:0
rw
Data for Command 5
Group 3 PHY Customized DATA 0
G3PHYCD0
Group 3 PHY Customized DATA 0
Offset
0295H
Reset Value
0000H
'&
UZ
Field
Bits
Type
Description
DC6
15:0
rw
Data for Command 6
Group 3 PHY Customized DATA 1
G3PHYCD1
Group 3 PHY Customized DATA 1
Offset
0296H
Reset Value
0000H
'&
UZ
Field
Bits
Type
Description
DC7
15:0
rw
Data for Command 7
Data Sheet
69
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
PHY Customized Enable Register
PHYCE
PHY Customized Enable Register
5HV
Offset
0297H
Reset Value
0000H
&(*
&(*
&(*
&(*
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
CEG3
11:9
rw
PHY Customized Enable For Group 3
000B , Disable writing additional commands into any PHYs in Group 3.
001B , Write command 6 into related port specified by the Customized
PHY Control Group 3.
010B , Write command 7 into related port specified by the Customized
PHY Control Group 3.
100B , Disable writing additional commands into any PHYs in Group 3.
101B , Write command 6 into all PHYs in Group 3.
110B , Write command 7 into all PHYs in Group 3.
111B , Write command 6 and command 7 into all PHYs in Group 3.
CEG2
8:6
rw
PHY Customized Enable For Group 2
000B , Disable writing additional commands into any PHYs in Group 2.
001B , Write command 4 into related port specified by the Customized
PHY Control Group 2.
010B , Write command 5 into related port specified by the Customized
PHY Control Group 2.
100B , Disable writing additional commands into any PHYs in Group 2.
101B , Write command 4 into all PHYs in Group 2.
110B , Write command 5 into all PHYs in Group 2.
111B , Write command 5 and command 5 into all PHYs in Group 2.
CEG1
5:3
rw
PHY Customized Enable For Group 1
000B , Disable writing additional commands into any PHYs in Group 1.
001B , Write command 2 into related port specified by the Customized
PHY Control Group 1.
010B , Write command 3 into related port specified by the Customized
PHY Control Group 1.
100B , Disable writing additional commands into any PHYs in Group 1.
101B , Write command 2 into all PHYs in Group 1.
110B , Write command 3 into all PHYs in Group 1.
111B , Write command 2 and command 3 into all PHYs in Group 1.
Data Sheet
70
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
Field
Bits
Type
Description
CEG0
2:0
rw
PHY Customized Enable For Group 0
000B , Disable writing additional commands into any PHYs in Group 0.
001B , Write command 0 into related port specified by the Customized
PHY Control Group 0.
010B , Write command 1 into related port specified by the Customized
PHY Control Group 0.
100B , Disable writing additional commands into any PHYs in Group 0.
101B , Write command 0 into all PHYs in Group 0.
110B , Write command 1 into all PHYs in Group 0.
111B , Write command 0 and command 1 into all PHYs in Group 0.
PPPOE Control Register 0
PPPOEC0
PPPOE Control Register 0
Offset
0298H
Reset Value
0000H
(3 (3 (3 (3 (3 (3 (37 (37 (37 (37 (37 (37 (37 (37 (37 (37
73
73
73
73
73
73
3
3
3
3
3
3
3
3
3
3
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
EP15TP
15
rw
Enable Port 15 to Transmit PPPoE Packet Only
EP14TP
14
rw
Enable Port 14 to Transmit PPPoE Packet Only
EP13TP
13
rw
Enable Port 13 to Transmit PPPoE Packet Only
EP12TP
12
rw
Enable Port 12 to Transmit PPPoE Packet Only
EP11TP
11
rw
Enable Port 11 to Transmit PPPoE Packet Only
EP10TP
10
rw
Enable Port 10 to Transmit PPPoE Packet Only
EP9TP
9
rw
Enable Port 9 to Transmit PPPoE Packet Only
EP8TP
8
rw
Enable Port 8 to Transmit PPPoE Packet Only
EP7TP
7
rw
Enable Port 7 to Transmit PPPoE Packet Only
EP6TP
6
rw
Enable Port 6 to Transmit PPPoE Packet Only
EP5TP
5
rw
Enable Port 5 to Transmit PPPoE Packet Only
EP4TP
4
rw
Enable Port 4 to Transmit PPPoE Packet Only
EP3TP
3
rw
Enable Port 3 to Transmit PPPoE Packet Only
EP2TP
2
rw
Enable Port 2 to Transmit PPPoE Packet Only
EP1TP
1
rw
Enable Port 1 to Transmit PPPoE Packet Only
EP0TP
0
rw
Enable Port 0 to Transmit PPPoE Packet Only
The ADM6918/X will recognize packets with length-type = 8863H or
8864H as the PPPOE packets.
0B
, The port 0 is not configured to transmit PPPOE packets only.
1B
, The port 0 is configured to transmit PPPOE packets only.
Data Sheet
71
UZ
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
PPPOE Control Register 1
PPPOEC1
PPPOE Control Register 1
Offset
0299H
5HV
(03&
UZ
Reset Value
0000H
(3 (3
73
73
UZ
5HV
UZ
UZ
Field
Bits
Type
Description
EMPC
10
rw
Enable Management Packet Cross PPPOE PORT Function
0B
, Management packets could not be transmitted by the PPPOE
port.
1B
, Management packets could be transmitted by any port even if it is
configured to PPPOE port.
EP25TP
9
rw
Enable Port 25 to Transmit PPPoE Packet Only
EP24TP
8
rw
Enable Port 24 to Transmit PPPoE Packet Only
Res
7:0
rw
Reserved
PHY Control Register 0
PHYCR0
PHY Control Register 0
Offset
029AH
Reset Value
0000H
3+< 3+< 3+< 3+< 3+< 3+<
3+< 3+< 3+< 3+< 3+< 3+< 3+< 3+< 3+< 3+<
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
PHY15
15
rw
PHY Port 15
0B
, PHY acts as the slave.
1B
, PHY attached to port 15 acts as the master.
PHY14
14
rw
PHY Port 14
0B
, PHY acts as the slave.
1B
, PHY attached to port 14 acts as the master.
PHY13
13
rw
PHY Port 13
0B
, PHY acts as the slave.
1B
, PHY attached to port 13 acts as the master.
Data Sheet
72
UZ
UZ
UZ
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
Field
Bits
Type
Description
PHY12
12
rw
PHY Port 12
0B
, PHY acts as the slave.
1B
, PHY attached to port 12 acts as the master.
PHY11
11
rw
PHY Port 11
0B
, PHY acts as the slave.
1B
, PHY attached to port 11 acts as the master.
PHY10
10
rw
PHY Port 10
0B
, PHY acts as the slave.
1B
, PHY attached to port 10 acts as the master.
PHY9
9
rw
PHY Port 9
0B
, PHY acts as the slave.
1B
, PHY attached to port 9 acts as the master.
PHY8
8
rw
PHY Port 8
0B
, PHY acts as the slave.
1B
, PHY attached to port 8 acts as the master.
PHY7
7
rw
PHY Port 7
0B
, PHY acts as the slave.
1B
, PHY attached to port 7 acts as the master.
PHY6
6
rw
PHY Port 6
0B
, PHY acts as the slave.
1B
, PHY attached to port 6 acts as the master.
PHY5
5
rw
PHY Port 5
0B
, PHY acts as the slave.
1B
, PHY attached to port 5 acts as the master.
PHY4
4
rw
PHY Port 4
0B
, PHY acts as the slave.
1B
, PHY attached to port 4 acts as the master.
PHY3
3
rw
PHY Port 3
0B
, PHY acts as the slave.
1B
, PHY attached to port 3 acts as the master.
PHY2
2
rw
PHY Port 2
0B
, PHY acts as the slave.
1B
, PHY attached to port 2 acts as the master.
PHY1
1
rw
PHY Port 1
0B
, PHY acts as the slave.
1B
, PHY attached to port 1 acts as the master.
PHY0
0
rw
PHY Port 0
0B
, PHY acts as the slave. The switch will use the setting in the
eeprom register to manage PHY attached.
1B
, PHY attached to port 0 acts as the master. That is the switch will
not configure the PHY attached and it will only poll the PHY to know
the state that PHY operates.
PHY Control Register 1
Data Sheet
73
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
PHYCR1
PHY Control Register 1
Offset
029BH
Reset Value
0000H
3+< 3+<
5HV
UZ
5HV
UZ
UZ
Field
Bits
Type
Description
PHY25
9
rw
PHY Port 25
0B
, PHY acts as the slave.
1B
, PHY attached to port 25 acts as the master.
PHY24
8
rw
PHY Port 24
0B
, PHY acts as the slave.
1B
, PHY attached to port 24 acts as the master.
Res
7:0
rw
Reserved
Disable MDIO Active Register 0
DMDIOAR0
Disable MDIO Active Register 0
Offset
029CH
Reset Value
0000H
3% 3% 3% 3% 3% 3% 3%0 3%0 3%0 3%0 3%0 3%0 3%0 3%0 3%0 3%0
0)( 0)( 0)( 0)( 0)( 0)( )(
)(
)(
)(
)(
)(
)(
)(
)(
)(
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
P15BMFE
15
rw
Port 15 Bypass MDIO Function Enable
P14BMFE
14
rw
Port 14 Bypass MDIO Function Enable
P13BMFE
13
rw
Port 13 Bypass MDIO Function Enable
P12BMFE
12
rw
Port 12 Bypass MDIO Function Enable
P11BMFE
11
rw
Port 11 Bypass MDIO Function Enable
P10BMFE
10
rw
Port 10 Bypass MDIO Function Enable
P9BMFE
9
rw
Port 9 Bypass MDIO Function Enable
P8BMFE
8
rw
Port 8 Bypass MDIO Function Enable
P7BMFE
7
rw
Port 7 Bypass MDIO Function Enable
P6BMFE
6
rw
Port 6 Bypass MDIO Function Enable
P5BMFE
5
rw
Port 5 Bypass MDIO Function Enable
P4BMFE
4
rw
Port 4 Bypass MDIO Function Enable
P3BMFE
3
rw
Port 3 Bypass MDIO Function Enable
Data Sheet
74
UZ
UZ
UZ
UZ
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
Field
Bits
Type
Description
P2BMFE
2
rw
Port 2 Bypass MDIO Function Enable
P1BMFE
1
rw
Port 1 Bypass MDIO Function Enable
P0BMFE
0
rw
Port 0 Bypass MDIO Function Enable
0B
, Bypass MDIO Disable. The status is dominated by the MDC/MDIO
function except the linkup status, which may be disabled, by the
port disable function or the spanning protocol.
1B
, Bypass MDIO Enable. The effect by the function is as follows:
Link Status: Port 0 is forced to link up unless the port is disabled or
the spanning tree is in disabled state.
Speed Status: Port 0 is configured to Bit [6] in the Port Configuration
Register.
Duplex Status: Port 0 is configured to Bit [7] in the Port
Configuration Register.
Pause Status: Port 0 is configured to Bit [4] in the Port Configuration
Register.
Back Pressure Status: Port 0 is configured to Bit[15] in the Port
Configuration Register.
Disable MDIO Active Register 1
DMDIOAR1
Disable MDIO Active Register 1
Offset
029DH
Reset Value
0000H
3% 3%
0)( 0)(
5HV
UZ
5HV
UZ
UZ
Field
Bits
Type
Description
P25BMFE
9
rw
Port 25 Bypass MDIO Function Enable
P24BMFE
8
rw
Port 24 Bypass MDIO Function Enable
Res
7:0
rw
Reserved
Port Disable Register 0
PDR0
Port Disable Register 0
Offset
029EH
Reset Value
0000H
3' 3' 3' 3' 3' 3' 3'5 3'5 3'5 3'5 3'5 3'5 3'5 3'5 3'5 3'5
57
57
57
57
57
57
7
7
7
7
7
7
7
7
7
7
UZ
UZ
Data Sheet
UZ
UZ
UZ
UZ
UZ
UZ
UZ
75
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
Field
Bits
Type
Description
P15DRT
15
rw
Port 15 Disable Receive and Transmit
P14DRT
14
rw
Port 14 Disable Receive and Transmit
P13DRT
13
rw
Port 13 Disable Receive and Transmit
P12DRT
12
rw
Port 12 Disable Receive and Transmit
P11DRT
11
rw
Port 11 Disable Receive and Transmit
P10DRT
10
rw
Port 10 Disable Receive and Transmit
P9DRT
9
rw
Port 9 Disable Receive and Transmit
P8DRT
8
rw
Port 8 Disable Receive and Transmit
P7DRT
7
rw
Port 7 Disable Receive and Transmit
P6DRT
6
rw
Port 6 Disable Receive and Transmit
P5DRT
5
rw
Port 5 Disable Receive and Transmit
P4DRT
4
rw
Port 4 Disable Receive and Transmit
P3DRT
3
rw
Port 3 Disable Receive and Transmit
P2DRT
2
rw
Port 2 Disable Receive and Transmit
P1DRT
1
rw
Port 1 Disable Receive and Transmit
P0DRT
0
rw
Port 0 Disable Receive and Transmit
0B
, The port acts as the normal mode.
1B
, The port will not receive or transmit packets. Learning is disabled
in the disabled port.
Port Disable Register 1
PDR1
Port Disable Register 1
Offset
029FH
Reset Value
0000H
3' 3'
57
57
5HV
UZ
UZ
5HV
UZ
Field
Bits
Type
Description
P25DRT
9
rw
Port 25 Disable Receive and Transmit
P24DRT
8
rw
Port 24 Disable Receive and Transmit
Res
7:0
rw
Reserved
IGMP Snooping Control Register 0
IGMPSCR0
IGMP Snooping Control Register 0
Data Sheet
Offset
02A0H
76
Reset Value
0000H
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
3( 3( 3( 3( 3( 3( 3(, 3(, 3(, 3(, 3(, 3(, 3(, 3(, 3(, 3(,
,6)
,6)
,6)
,6)
,6)
,6)
6)
6)
6)
6)
6)
6)
6)
6)
6)
6)
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
P15EISF
15
rw
Port 15 Enable IGMP Snooping Function
P14EISF
14
rw
Port 14 Enable IGMP Snooping Function
P13EISF
13
rw
Port 13 Enable IGMP Snooping Function
P12EISF
12
rw
Port 12 Enable IGMP Snooping Function
P11EISF
11
rw
Port 11 Enable IGMP Snooping Function
P10EISF
10
rw
Port 10 Enable IGMP Snooping Function
P9EISF
9
rw
Port 9 Enable IGMP Snooping Function
P8EISF
8
rw
Port 8 Enable IGMP Snooping Function
P7EISF
7
rw
Port 7 Enable IGMP Snooping Function
P6EISF
6
rw
Port 6 Enable IGMP Snooping Function
P5EISF
5
rw
Port 5 Enable IGMP Snooping Function
P4EISF
4
rw
Port 4 Enable IGMP Snooping Function
P3EISF
3
rw
Port 3 Enable IGMP Snooping Function
P2EISF
2
rw
Port 2 Enable IGMP Snooping Function
P1EISF
1
rw
Port 1 Enable IGMP Snooping Function
P0EISF
0
rw
Port 0 Enable IGMP Snooping Function
The packets with the header (DA = 01005exxxxxx, Length_Type = 0800,
IP version = 4, and Protocol type = 2) will be recognized as the IGMP
packets, and the switch will forward it to the CPU port.
0B
, The port 0 is not configured to enable IGMP Snooping Function.
And the IGMP packets will be handled as the normal multicast
packets.
1B
, The port 0 is configured to enable IGMP Snooping Function.
IGMP Snooping Control Register 1
IGMPSCR1
IGMP Snooping Control Register 1
5HV
0&5
UZ
Data Sheet
Offset
02A1H
3( 3(
,6)
,6)
UZ
UZ
Reset Value
0000H
5HV
UZ
77
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
Field
Bits
Type
Description
MCR
11:10
rw
Multicast Control Register
Packets with the following conditions will follow the Multicast Control
Register to handle packets.
Conditions:
Destination address is not found in the address table.
AND Destination address is a multicast address.
AND Destination address is not all 1’b1.
AND Destination address is not a reserved address(0180c2000~~).
OR IGMP packets received by the port which disables the IGMP function.
Multicast Control, Action
00B , Forward to all ports within the same forwarding group except the
self port.
01B , Send to the CPU port.
10B , Discard.
11B , Reserved.
P25EISF
9
rw
Port 25 Enable IGMP Snooping Function
P24EISF
8
rw
Port 24 Enable IGMP Snooping Function
Res
7:0
rw
Reserved
CPU Control Register
CPUCR
CPU Control Register
5HV
Offset
02A2H
Reset Value
001FH
'&38
3/
/*
5HV
(,
(7
(5
&3831
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
DCPUPL
13
rw
Disable CPU Port Learning Function
0B
, The packets received from the CPU port will be learned.
1B
, The packets received from the CPU port will not be learned.
Data Sheet
78
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
Field
Bits
Type
Description
LG
12:11
rw
Learning Group
ADM6918/X has an ability to learn packets according their forwarding
groups. The ADM6918/X could be divided into 32 learning groups. We
use L0, L1, … and L31 to call each learning group.
0xB , Normal mode, learning with SA only.
10B , MAC Clone mode, learning with SA and VID[0]. When packets are
received and could be learned, they are learned divided into two
Groups. Even forwarding groups are learned into L0 and odd
forwarding groups are learned into L1.
11B , Learning with SA and VID[4:0]. When packets are received and
could be learned, they are learned according to their forwarding
group. That is packets belonging to F0 is learned into L0, packets
belonging to F1 is learned into L1, … and packets belonging to F31
is leaned into L31.
Res
10:8
rw
Reserved
EI
7
rw
Enable Insert
Enable insert 4-byte special tag when Pause happens and Bit[6] is
enabled.
0B
, ADM6918/X will add 4-byte special TAG when pause happens.
1B
, ADM6918/X will add 4-byte special TAG when pause happens.
ET
6
rw
Enable Transmit
Enable transmit 4-byte special tag to the CPU port to support IGMP
snooping, spanning tree or the security function.
0B
, ADM6918/X will transmit packets as the normal mode.
1B
, ADM6918/X will insert addition 4-byte special TAG when it has
packets to be transmitted to the CPU port.
ER
5
rw
Enable Receive
Enable receive 8-byte special tag from the CPU port to support IGMP
snooping, spanning tree or the security function.
0B
, CPU will transmit packets as the normal state.
1B
, CPU will transmit packets with additional 8-byte special TAG and
the ADM6918/X will remove this special TAG, use information
contained to forward packets and recalculate CRC value when this
packet is re-transmitted.
Data Sheet
79
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
Field
Bits
Type
Description
CPUPN
4:0
rw
CPU Port Number
The ADM6918/X allows any port to be configured to be the CPU port. The
default CPU port is port 31. That is CPU port is not present.
00000B , CPU port is configured to port 0.
00001B , CPU port is configured to port 1.
00010B , CPU port is configured to port 2.
00011B , CPU port is configured to port 3.
00100B , CPU port is configured to port 4.
00101B , CPU port is configured to port 5.
00110B , CPU port is configured to port 6.
00111B , CPU port is configured to port 7.
01000B , CPU port is configured to port 8.
01001B , CPU port is configured to port 9.
01010B , CPU port is configured to port 10.
01011B , CPU port is configured to port 11.
01100B , CPU port is configured to port 12.
01101B , CPU port is configured to port 13.
01110B , CPU port is configured to port 14.
01111B , CPU port is configured to port 15.
10000B , CPU port is configured to port 16.
10001B , CPU port is configured to port 17.
10010B , CPU port is configured to port 18.
10011B , CPU port is configured to port 19.
10100B , CPU port is configured to port 20.
10101B , CPU port is configured to port 21.
10110B , CPU port is configured to port 22.
10111B , CPU port is configured to port 23.
11000B , CPU port is configured to port 24.
11001B , CPU port is configured to port 25.
Special MAC Forward Control Register 0
SMACFCR0
Special MAC Forward Control Register 0
Offset
02A3H
Reset Value
0004H
)B
)B
)B
)B
)B
)B
)B
)B
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
F15_14
15:14
rw
Forwarding 15_14
The forwarding option for destination address = 0180c2000023
~0180c20000ff
Data Sheet
80
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
Field
Bits
Type
Description
F13_12
13:12
rw
Forwarding 13_12
The forwarding option for destination address = 0180c2000020
~0180c2000022 (GMRP, GVRP, GARP)
F11_10
11:10
rw
Forwarding 11_10
The forwarding option for destination address = 0180c2000010
~0180c200001f
F9_8
9:8
rw
Forwarding 9_8
The forwarding option for destination address = 0180c2000004
~0180c200000f
F7_6
7:6
rw
Forwarding 7_6
The forwarding option for destination address = 0180c2000003 (802.1x
PAE address)
F5_4
5:4
rw
Forwarding 5_4
The forwarding option for destination address = 48’h0180c2000002
(Slow Protocol)
F3_2
3:2
rw
Forwarding 3_2
The forwarding option for destination address = 0180c2000001
(Reserved for Pause address), MAC control field = 8808, OP Code !=
0001
F1_0
1:0
rw
Forwarding 1_0
The forwarding option for destination address = 48’h0180c2000000
(BPDU)
Notes
1. The options are defined here: 00B = The switch will forward the packets as the normal mode. That is for
reserved addresses existed in the learning table (because reserved address is multicast address, it could only
be created through the CPU help if it really exists in the learning table). We will use “output port field” as the
index to lookup the multicast table. At last, the looked output port map (may be modified by the forwarding
process) is used as the output ports to forward packets. For reserved addresses, which don’t exist in the
learning table, it will be broadcast to the forwarding group except the receiving port.01B = The switch will
discard the packets.10B = The switch will forward the packets to the CPU port. If the packet is received from
the CPU port, the packet will be forwarded as the normal mode.11B = The switch will forward the packet to
CPU port. If this packet is received from CPU Port, this packet will be discard.
2. The forwarding options stated above will be of no effect for the CPU port when users enable the “Special Tag
Function” and its output vector field is valid.
Special MAC Forward Control Register 1
SMACFCR1
Special MAC Forward Control Register 1
Data Sheet
Offset
02A4H
81
Reset Value
0003H
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
)B
)B
)B
)B
)B
)B
5HV
)B
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
F15_14
15:14
rw
Forwarding 15_14
The forwarding option for destination address = 0180c2000023
~0180c20000ff
F13_12
13:12
rw
Forwarding 13_12
The forwarding option for destination address = 0180c2000020
~0180c2000022 (GMRP, GVRP, GARP)
F11_10
11:10
rw
Forwarding 11_10
The forwarding option for destination address = 0180c2000010
~0180c200001f
F9_8
9:8
rw
Forwarding 9_8
The forwarding option for destination address = 0180c2000004
~0180c200000f
F7_6
7:6
rw
Forwarding 7_6
The forwarding option for destination address = 0180c2000003 (802.1x
PAE address)
F5_4
5:4
rw
Forwarding 5_4
The forwarding option for destination address = 48’h0180c2000002
(Slow Protocol)
Res
3:2
rw
Reserved
F1_0
1:0
rw
Forwarding 1_0
The forwarding option for destination address = 48’h0180c2000000
(BPDU)
Note: The ADM6918/X will divide packets into management or unmanagement packets. Management packets will
not be dropped even if the buffer is full for no flow control environment. Only management packets will be
forwarded or received in Blocking-N-Listening or the Learning state.
The options are defined here:00B = The packets will not be classified as the management packets and it will
be treated as the normal packet.01B = The packets will be classified as the management packets and it will
be transmitted no modified.10B = The packets will be classified as the management packets and it will be
transmitted without tag.11B = The packets will be classified as the management packets and it will be
transmitted with tag or without tag as the system configuration.
Special MAC Forward Control Register 2
SMACFCR2
Special MAC Forward Control Register 2
Data Sheet
Offset
02A5H
82
Reset Value
0000H
Rev 1.01, 2005-11-08
ADM6918/X
EEPROM Register Format
5HV
)
)
)
)
)
)
5HV
)
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
F7
7
rw
Forwarding 7
The forwarding option for destination address = 0180c2000023
~0180c20000ff
F6
6
rw
Forwarding 6
The forwarding option for destination address = 0180c2000020
~0180c2000022 (GMRP, GVRP, GARP)
F5
5
rw
Forwarding 5
The forwarding option for destination address = 0180c2000010
~0180c200001f
F4
4
rw
Forwarding 4
The forwarding option for destination address = 0180c2000004
~0180c200000f
F3
3
rw
Forwarding 3
The forwarding option for destination address = 0180c2000003 (802.1x
PAE address)
F2
2
rw
Forwarding 2
The forwarding option for destination address = 48’h0180c2000002
(Slow Protocol)
Res
1
rw
Reserved
F0
0
rw
Forwarding 0
The forwarding option for destination address = 48’h0180c2000000
(BPDU)
Note: The options are defined here:1B = The packets will cross forwarding group.0B = The packets will not cross
the forwarding packet.
Trunking Enable Register 0
TER0
Trunking Enable Register 0
Offset
02A6H
Reset Value
0000H
37 37 37 37 37 37
37( 37( 37( 37( 37( 37( 37( 37( 37( 37(
(
(
(
(
(
(
UZ
UZ
Data Sheet
UZ
UZ
UZ
UZ
UZ
UZ
UZ
83
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Rev 1.01, 2005-11-08
ADM6918/X
Switch Register Map
Field
Bits
Type
Description
P15TE
15
rw
Port 15 Trunking Enable
P14TE
14
rw
Port 14 Trunking Enable
P13TE
13
rw
Port 13 Trunking Enable
P12TE
12
rw
Port 12 Trunking Enable
P11TE
11
rw
Port 11 Trunking Enable
P10TE
10
rw
Port 10 Trunking Enable
P9TE
9
rw
Port 9 Trunking Enable
P8TE
8
rw
Port 8 Trunking Enable
P7TE
7
rw
Port 7 Trunking Enable
P6TE
6
rw
Port 6 Trunking Enable
P5TE
5
rw
Port 5 Trunking Enable
P4TE
4
rw
Port 4 Trunking Enable
P3TE
3
rw
Port 3 Trunking Enable
P2TE
2
rw
Port 2 Trunking Enable
P1TE
1
rw
Port 1 Trunking Enable
P0TE
0
rw
Port 0 Trunking Enable
The ADM6918/X supports one trunking port. Any port could be assigned
to the trunking port. The trunking function is of the effect only the trunking
hardware setting = 1.
0B
, Port 0 is not assigned to a member of the trunking port.
1B
, Port 0 is assigned to a member of the trunking port.
Trunking Enable Register 1
TER1
Trunking Enable Register 1
Offset
02A7H
37 37
(
(
5HV
UZ
UZ
Bits
Type
Description
P25TE
9
rw
Port 25 Trunking Enable
P24TE
8
rw
Port 24 Trunking Enable
Res
7:0
rw
Reserved
Data Sheet
5HV
UZ
Field
5
Reset Value
0000H
Switch Register Map
84
Rev 1.01, 2005-11-08
ADM6918/X
Switch Register Map
Table 25
Switch Register Map
Offset Hex
Bit 31 ~ 0
Type
0H
Version ID
ro
1H
Link Status
ro
2H
Speed Status
ro
3H
Duplex Status
ro
4H
Flow Control Status
ro
5H
Address Table Control Register 0
rw
6H
Address Table Control Register 1
rw
7H
Address Table Control Register 2
rw
8H
Address Table Status Register 0
ro
9H
Address Table Status Register 1
ro
AH
Address Table Status Register 2
ro
BH
PHY Control/Status Register
rw
CH
Reserved
ro
DH
Hardware Status
ro
EH
RxPKT Overflow
roc
FH
RxLEN Overflow
roc
10H
TxPKT Overflow
roc
11H
TxLEN Overflow
roc
12H
RxERR Overflow
roc
13H
RxCOL Overflow
roc
14H
Renew Counter Register
rw
15H
Read Counter Control Register
rw
16H
Read Counter Status Register
ro
17H
Reload MDIO Register
rw
18H
P0 ~ P15 Spanning Tree Port State
rw
19H
P16 ~ P25 Spanning Tree Port State
rw
1AH
Source Port Register
ro
1BH
Transmit Port Register
rw
1CH
Buffer Status Register 0
roc
1DH
Buffer Status Register 1
roc
1EH
Buffer Status Register 2
roc
1FH
Buffer Status Register 3
roc
1xxH
Counter Register
rw
2xxH
EEPROM Register
rw
Data Sheet
85
Rev 1.01, 2005-11-08
ADM6918/X
Switch Register Map
5.1
Switch Registers
Table 26
Registers Address SpaceRegisters Address Space
Module
Base Address
End Address
Switch
00H
1BH
Table 27
Note
Registers Overview
Register Short Name
Register Long Name
Offset Address
Page Number
VID
Version ID
00H
87
LS
Link Status
01H
88
SS
Speed Status
02H
89
DS
Duplex Status
03H
89
FCS
Flow Control Status
04H
90
PHYCR
PHY Control Register
0BH
97
HS
Hardware Status
0DH
98
RPCO
Receive Packet Count Overflow
0EH
99
RPLCO
Receive Packet Length Count Overflow
0FH
99
TPCO
Transmit Packet Count Overflow
10H
100
TPLCO
Transmit Packet Length Count Overflow
11H
101
ECO
Error Count Overflow
12H
102
CCO
Collision Count Overflow
13H
103
RCR
Renew Counter Register
14H
103
RCCR
Read Counter Control Register
15H
105
RCSR
Read Counter Status Register
16H
105
RMDIOR
Reload MDIO Register
17H
106
STPS0
Spanning Tree Port State 0
18H
107
STPS1
Spanning Tree Port State 1
19H
108
SCPR
Source Port Register
1AH
108
TRPR
Transmit Port Register
1BH
109
The register is addressed wordwise.
Table 28
Register Access Types
Mode
Symbol Description HW
Description SW
read/write
rw
Register is used as input for the HW
Register is read and writable by SW
read
r
Register is written by HW (register
Value written by software is ignored by
between input and output -> one cycle hardware; that is, software may write any
delay)
value to this field without affecting hardware
behavior (= Target for development.)
Read only
ro
Register is set by HW (register between SW can only read this register
input and output -> one cycle delay)
Data Sheet
86
Rev 1.01, 2005-11-08
ADM6918/X
Switch Register Map
Table 28
Register Access Types (cont’d)
Mode
Symbol Description HW
Read virtual
rv
Physically, there is no new register, the SW can only read this register
input of the signal is connected directly
to the address multiplexer.
Latch high,
self clearing
lhsc
Latch high signal at high level, clear on SW can read the register
read
Latch low,
self clearing
llsc
Latch high signal at low-level, clear on SW can read the register
read
Latch high,
mask clearing
lhmk
Latch high signal at high level, register SW can read the register, with write mask
cleared with written mask
the register can be cleared (1 clears)
Latch low,
mask clearing
llmk
Latch high signal at low-level, register
cleared on read
SW can read the register, with write mask
the register can be cleared (1 clears)
Interrupt high,
self clearing
ihsc
Differentiate the input signal (low>high) register cleared on read
SW can read the register
Interrupt low,
self clearing
ilsc
Differentiate the input signal (high>low) register cleared on read
SW can read the register
Interrupt high,
mask clearing
ihmk
Differentiate the input signal (highSW can read the register, with write mask
>low) register cleared with written mask the register can be cleared
Interrupt low,
mask clearing
ilmk
Differentiate the input signal (low>high) register cleared with written
mask
SW can read the register, with write mask
the register can be cleared
Interrupt enable ien
register
Enables the interrupt source for
interrupt generation
SW can read and write this register
latch_on_reset
lor
rw register, value is latched after first
clock cycle after reset
Register is read and writable by SW
Read/write
self clearing
rwsc
Register is used as input for the hw, the Writing to the register generates a strobe
register will be cleared due to a HW
signal for the HW (1 pdi clock cycle)
mechanism.
Register is read and writable by SW.
Table 29
Registers Clock DomainsRegisters Clock Domains
Clock Short Name
5.1.1
Description SW
Description
Switch Register Descriptions
Version ID
VID
Version ID
Offset
00H
Data Sheet
87
Reset Value
0003 1100H
Rev 1.01, 2005-11-08
ADM6918/X
Switch Register Map
5HV
Field
Bits
Type
Description
PC
19:4
ro
Project Code
VC
3:0
ro
Version Code
3&
9&
UR
UR
Link Status
LS
Link Status
Offset
01H
Reset Value
0000 0000H
5HV
3 3
5HV
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
/6 /6 /6 /6 /6 /6 /6 /6 /6 /6
UR UR
UR
UR UR UR UR UR UR UR UR UR UR UR UR UR UR UR UR
Field
Bits
Type
Description
P25LS
25
ro
Port 25 Link Status
P24LS
24
ro
Port 24 Link Status
Res
23:16
ro
Reserved
P15LS
15
ro
Port 15 Link Status
P14LS
14
ro
Port 14 Link Status
P13LS
13
ro
Port 13 Link Status
P12LS
12
ro
Port 12 Link Status
P11LS
11
ro
Port 11 Link Status
P10LS
10
ro
Port 10 Link Status
P9LS
9
ro
Port 9 Link Status
P8LS
8
ro
Port 8 Link Status
P7LS
7
ro
Port 7 Link Status
P6LS
6
ro
Port 6 Link Status
P5LS
5
ro
Port 5 Link Status
P4LS
4
ro
Port 4 Link Status
P3LS
3
ro
Port 3 Link Status
P2LS
2
ro
Port 2 Link Status
P1LS
1
ro
Port 1 Link Status
P0LS
0
ro
Port 0 Link Status
0B
, Port 0 links down.
1B
, Port 0 links up.
Data Sheet
88
Rev 1.01, 2005-11-08
ADM6918/X
Switch Register Map
Speed Status
SS
Speed Status
Offset
02H
Reset Value
03FF FFFFH
5HV
3 3
5HV
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
66 66 66 66 66 66 66 66 66 66
UR UR
UR
UR UR UR UR UR UR UR UR UR UR UR UR UR UR UR UR
Field
Bits
Type
Description
P25SS
25
ro
Port 25 Speed Status
P24SS
24
ro
Port 24 Speed Status
Res
23:16
ro
Reserved
P15SS
15
ro
Port 15 Speed Status
P14SS
14
ro
Port 14 Speed Status
P13SS
13
ro
Port 13 Speed Status
P12SS
12
ro
Port 12 Speed Status
P11SS
11
ro
Port 11 Speed Status
P10SS
10
ro
Port 10 Speed Status
P9SS
9
ro
Port 9 Speed Status
P8SS
8
ro
Port 8 Speed Status
P7SS
7
ro
Port 7 Speed Status
P6SS
6
ro
Port 6 Speed Status
P5SS
5
ro
Port 5 Speed Status
P4SS
4
ro
Port 4 Speed Status
P3SS
3
ro
Port 3 Speed Status
P2SS
2
ro
Port 2 Speed Status
P1SS
1
ro
Port 1 Speed Status
P0SS
0
ro
Port 0 Speed Status
0B
, Port 0 operates in 10M.
1B
, Port 0 operates in 100M.
Duplex Status
DS
Duplex Status
Data Sheet
Offset
03H
89
Reset Value
03FF FFFFH
Rev 1.01, 2005-11-08
ADM6918/X
Switch Register Map
5HV
3 3
5HV
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
'6 '6 '6 '6 '6 '6 '6 '6 '6 '6
UR UR
UR
UR UR UR UR UR UR UR UR UR UR UR UR UR UR UR UR
Field
Bits
Type
Description
P25DS
25
ro
Port 25 Duplex Status
P24DS
24
ro
Port 24 Duplex Status
Res
23:16
ro
Reserved
P15DS
15
ro
Port 15 Duplex Status
P14DS
14
ro
Port 14 Duplex Status
P13DS
13
ro
Port 13 Duplex Status
P12DS
12
ro
Port 12 Duplex Status
P11DS
11
ro
Port 11 Duplex Status
P10DS
10
ro
Port 10 Duplex Status
P9DS
9
ro
Port 9 Duplex Status
P8DS
8
ro
Port 8 Duplex Status
P7DS
7
ro
Port 7 Duplex Status
P6DS
6
ro
Port 6 Duplex Status
P5DS
5
ro
Port 5 Duplex Status
P4DS
4
ro
Port 4 Duplex Status
P3DS
3
ro
Port 3 Duplex Status
P2DS
2
ro
Port 2 Duplex Status
P1DS
1
ro
Port 1 Duplex Status
P0DS
0
ro
Port 0 Duplex Status
0B
, Port 0 operates in half duplex.
1B
, Port 0 operates in full duplex.
Flow Control Status
FCS
Flow Control Status
Offset
04H
Reset Value
03FF FFFFH
5HV
3 3
5HV
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
) ) ) ) ) ) ) ) ) )
UR UR
UR
UR UR UR UR UR UR UR UR UR UR UR UR UR UR UR UR
Field
Bits
Type
Description
P25FCS
25
ro
Port 25 Flow Control Status
P24FCS
24
ro
Port 24 Flow Control Status
Data Sheet
90
Rev 1.01, 2005-11-08
ADM6918/X
Switch Register Map
Field
Bits
Type
Description
Res
23:16
ro
Reserved
P15FCS
15
ro
Port 15 Flow Control Status
P14FCS
14
ro
Port 14 Flow Control Status
P13FCS
13
ro
Port 13 Flow Control Status
P12FCS
12
ro
Port 12 Flow Control Status
P11FCS
11
ro
Port 11 Flow Control Status
P10FCS
10
ro
Port 10 Flow Control Status
P9FCS
9
ro
Port 9 Flow Control Status
P8FCS
8
ro
Port 8 Flow Control Status
P7FCS
7
ro
Port 7 Flow Control Status
P6FCS
6
ro
Port 6 Flow Control Status
P5FCS
5
ro
Port 5 Flow Control Status
P4FCS
4
ro
Port 4 Flow Control Status
P3FCS
3
ro
Port 3 Flow Control Status
P2FCS
2
ro
Port 2 Flow Control Status
P1FCS
1
ro
Port 1 Flow Control Status
P0FCS
0
ro
Port 0 Flow Control Status
0B
, Port 0 disables flow control function.
1B
, Port 0 enables Pause function in full duplex or Back Pressure
function in half duplex.
Address Table Control and Status Registers
Address Table Control Register 0 (Offset: 5H)
Address Table Control Register 1 (Offset: 6H)
Address Table Control Register 2 (Offset:7H)
Address Table Status Register 0 (Offset: 8H)
Address Table Status Register 1 (Offset: 9H)
Address Table Status Register 2 (Offset: AH)
The ADM6918/X provides custom commands to access the address table as well as the multicast output port map
table. Six registers are used and they mean differently when different tables are accessed.
1. The Control and Status Register Description for the Address Table
Table 30
Control Register Description
Command Field
Entry State
Control_2[2:0]
Control_1[31:30] Control_1[29:26] Control_1[25:21] Control_1[20:16] {Control_1[15:0],
Control_0[31:0]}
Table 31
Control Field
Output Port/
Multicast Index
Forwarding
Group
MAC Address
Field Description in the Control Register
Field
Description
MAC Address[47:0]
This field is 48-bit layer-2 address. The address could be the unicast address or the
multicast address.
Forwarding Group[4:0]
This field describes the Learning Group the address belongs to.
Data Sheet
91
Rev 1.01, 2005-11-08
ADM6918/X
Switch Register Map
Table 31
Field Description in the Control Register (cont’d)
Field
Description
Output Port[4:0]/Multicast
Index[4:0]
This field has two means. One is described as the output port and the other is
described as the multicast index.
Entry State[0]
The Static Bit. When this bit is set to a one, then the address entry will not be aged
forever. This bit could be changed only through the CUP’s help.
Entry State[1]
This bit is used to distinguish the output port/ multicast index field.
When a match (the same MAC address and the same forwarding group in the
address table) is found, the value in the output port field is returned as the output
port, and may be modified by the forwarding group before the packet is transferred
to the output queue.
When a match (the same MAC address and the same forwarding group in the
address table) is found, the multicast output port map entry addressed by the
multicast index is returned as the output port map, and may be modified by the
forwarding group before the packet is transferred to the output queue.
Command Field[2:0]/
Control Field[3:0]
The command and control fields are combined to provide different operations.
Before the operation is initiated, users should confirm if the search engine is
available. See the busy bit in the status register.
Command Field
Control Field
Operation
000
0111
Create a new address
000
1111
Overwrite an existed address
001
1111
Erase an existed address
010
0000
Search an empty address
010
1001
Search by the port in the Output Port field
010
1010
Search by the forwarding group specified in
the Forwarding Group field
010
1100
Search by the address specified in the MAC
Address field
010
1110
Search by the address and forwarding group
010
1101
Search by the address and output port
010
1011
Search by the forwarding group and the
output port
010
1111
Search by the address, the forwarding group
and the output port
011
0100
Initial to location by the address field
011
0000
Initial to the first address
Table 32
Status Register Description
Busy
Command Bad State
Result
Status_2[3] Status_2
[2:0]
Data Sheet
Status_1
[29]
Entry
State
Occupy
Output Port/
Forwarding MAC Address
Multicast Index Group
Status_1
[28:27]
Status_1
[26]
Status_1
[25:21]
92
Status_1
[20:16]
{Status_1
[15:0],
Status_0
[31:0]}
Rev 1.01, 2005-11-08
ADM6918/X
Switch Register Map
Table 33
Field Description in the Status Register
Field
Description
MAC Address[47:0]
After the search operation is successful, the switch will return the MAC address
in this field. If the search fails, this field doesn’t mean anything.
Forwarding Group[4:0]
After the search operation is successful, the switch will return the Forwarding
Group in this. If the search fails, this field doesn’t mean anything.
Output Port[4:0]/ Multicast
Index[4:0]
After the search operation is successful, the switch will return output port /
multicast index in this field. The users could use the entry_state[1] returned to
distinguish if the entry should point to the multicast output port map table.
Occupy
After the search is successful, the switch will return the value indicating if the
entry existed.
0B
, The searched entry doesn’t exist.
1B
, The searched entry exists.
Entry State[0]
After the search is successful, the switch will return the value in this field
indicating if value is static.
0B
, The searched entry is not static and will be aged.
1B
, The searched entry is static.
Entry State[1]
After the search is successful, the switch will return the value in this field
indicating if the entry points to the multicast output port map table.
0B
, The entry doesn’t point to the multicast output port map table.
1B
, The entry points to the multicast output port map table.
Bad State
After the search is successful, the switch will return the value indicating if the
entry is bad.
0B
, The entry is not bad and will be used for data storage.
1B
, The entry is bad and isn’t used for data storage.
Command Result[2:0]
This field indicates the access result.
000B , Command OK.
001B , All Entry Used. This result happens only for the create operation.
ADM6918/X uses the 4-way address lookup engine so it allows 4 different
addresses stored at each hash location. If these 4 entries are all static,
then CPU will not successfully create 5th different address hashed to the
same location and 001 will be returned. The only way to create 5th
different address is to remove one of early addresses.
010B , Entry Not Found.
011B , Try Next Entry.
101B , Command Error.
Busy
This bit indicates if the table engine for access is available.
0B
, The engine is available.
1B
, The engine is busy and it will not access the command from the CPU.
2. Rules to Access the Address Table
1. Check the Busy Bit in the status register to see if the access engine is available. If the engine is busy, wait until
the engine is free. If the engine is available, go to the following step.
2. Write the MAC address[31:0] into the control register 0.
3. Write the MAC address[47:32], Forwarding Group, Output Port/Multicast Index, Control Field and the Entry
State into the control register 1.
4. Write the Command into the control register 2 to define the operation.
5. Wait for the engine to complete (Check the Busy Bit).
Data Sheet
93
Rev 1.01, 2005-11-08
ADM6918/X
Switch Register Map
6. Read the desired result returned in the status register.
Note: Before the “Search command”, the CPU should execute the “Initial command” to initial the search pointer.
The search engine could search the aim from the top to the bottom. The search engine has an ability to
automatically move the pointer to the associated location (The result will be returned). Because more than
one entry may match the searching condition (by port, by address, etc.) at the same time, the CPU should
continue to restart the search engine until the Command Result = Entry Not is found to confirm that no other
matching entries exist.
˜́˼̇˼˴˿ʳ̇̂ʳ˹˼̅̆̇ʳ˴˷˷̅˸̆̆
ʻˣ̂˼́̇˸̅ʳ˽̈̀ ̃̆ʳ̇̂ʳˠ ˔˖ʳ˃ʼ
˔˷˷̅˸̆̆ʳ˴˹̇˸̅ʳ˻˴̆˻˸˷
˃
ˠ ˔˖˃
ˠ ˔˖˄
ˠ ˔˖˅
ˠ ˔˖ˆ
˄
ˠ ˔˖ˇ
ˠ ˔˖ˈ
ˠ ˔˖ˉ
ˠ ˔˖ˊ
˅
ˠ ˔˖ˋ
ˠ ˔˖ˌ
ˠ ˔˖˄˃
ˠ ˔˖˄˄
˜́˼̇˼˴˿ʳ̇̂ʳˠ ˔˖ˋʿʳˠ ˔˖ˌʿʳˠ ˔˖˄˃ʿʳˠ ˔˖˄˄
ʻˣ̂˼́̇˸̅ʳ˽̈̀ ̃̆ʳ̇̂ʳˠ ˔˖ˋʼ
˄˃˅˄
˄˃˅˅
˄˃˅ˆ
Figure 11
ˠ ˔˖
ˇ˃ˋˇ
ˠ ˔˖
ˇ˃ˋˋ
ˠ ˔˖
ˇ˃ˌ˅
ˠ ˔˖
ˇ˃ˋˈ
ˠ ˔˖
ˇ˃ˋˌ
ˠ ˔˖
ˇ˃ˌˆ
ˠ ˔˖
ˇ˃ˋˉ
ˠ ˔˖
ˇ˃ˌ˃
ˠ ˔˖
ˇ˃ˌˇ
ˠ ˔˖
ˇ˃ˋˊ
ˠ ˔˖
ˇ˃ˌ˄
ˠ ˔˖
ˇ˃ˌˈ
The Search Pointer
3. Example
Table 34
Example
Example
Step
The user needs ADM6918/X
to forward the specified
unicast packet
(DA = 0012_3456_789AH and
Forwarding Group = 2) to port
3 forever.
Step 1: Check the Busy bit. If Busy = 0B, go to the step 2. If Busy = 1B, wait.
Step 2: Write 3456_789AH into control register 0.
Step 3: Write 5C62_0012H into the control register 1.
Step 4: Write 0000_0000H into the control register 2 to start the “Create” operation.
Step 5: Read the status register 2 to check the busy bit. If Busy = 0B, check the
Command Result to see if the create operation is successful. If Busy = 1B, wait for
completion.
Data Sheet
94
Rev 1.01, 2005-11-08
ADM6918/X
Switch Register Map
Table 34
Example (cont’d)
Example
Step
The user needs the
ADM6918/X to forward the
specified multicast packet
(DA = 0123_4567_89ABH
and Forwarding Group = 3) to
port 5 only. This address
could be aged.
Step 1: Check the Busy bit. If Busy = 0B, go to the step 2. If Busy = 1B, wait.
Step 2: Write 4567_89ABH into control register 0.
Step 3: Write 1CA3_0123H into the control register 1.
Step 4: Write 0000_0000H into the control register 2 to start the “Create” operation.
Step 5: Read the status register 2 to check the busy bit. If Busy = 0B, check the
Command Result to see if the create operation is successful. If Busy = 1B, wait for
completion.
The user wants to know how Step 1: Check the Busy bit. If Busy = 0B, go to the step 2. If Busy = 1B, wait.
many stations attached to
Step 2: Write 0000_0000H into control register 1.
port 4.
Step 3: Write 0000_0003H into control register 2 to start the “Initial to the first
address” operation.
Step 4: Read the status register 2 to check the busy bit. If Busy = 0B, check the
Command Result to see if the initial operation is successful. If Busy = 1B, wait for
completion.
Step 5: Write 2480_0000H into control register 1.
Step 6: Write 0000_0002H into control register 2 to start the “Search by port”
operation.
Step 7: Read the status register 2 to check the busy bit. If Busy = 0B, check the
Command Result to see if the search operation is successful (the Mac address
attached to port 4 could be derived from the MAC address in the status register).
If Busy = 1B, wait for completion.
Step 8: If Command Result = “Command OK”, it means some other MAC
addresses attached to port 4 may exist. We should restart the “Search by port”
command again to let the search engine to look another addresses.
Step 9: If the Command Result = “Entry Not Found”, it means no other addresses
attached to port 4 exist.
Control and Status Register for the Multicast Output Port Map Table
1. The Control and Status Register Descriptions
Table 35
Control Register Description
Command Field
Multicast Index
Output Port Map
Control_2[2:0]
Control_0[30:26]
Control_0[25:0]
Table 36
Field Description in the Control Register
Field
Description
Output Port Map
This field describes the output ports associated with the multicast index.Bit [0] is for port 0,
Bit[1] is for port 1, … and Bit[25] for port 25.
Multicast Index
refer to Figure 12.
Command Field
100B , Create an entry in the output port map table (indexed by the Multicast Index).
101B , Search an entry in the output port map table (indexed by the Multicast Index).
Data Sheet
95
Rev 1.01, 2005-11-08
ADM6918/X
Switch Register Map
ˠ̈˿̇˼˶˴̆̇ʳˢ̈̇̃̈̇ʳˣ̂̅̇ʳˠ˴̃ʳ˧˴˵˿˸
ˠ̈˿̇˼˶˴̆̇ʳ
˜́˷˸̋
˅ˈ ˅ˇ
̑ʳ̑
˅ ˄
˃
˃
˔˷˷̅˸̆̆ʳ˧˴˵˿˸
˄
˘́̇̅̌ʳ˦̇˴̇˸ˮ˄˰ʳːʳ˃
ˢ̈̇̃̈̇ʳˣ̂̅̇
˨́˼˶˴̆̇ʳ˔˷˷̅
˘́̇̅̌ʳ˦̇˴̇˸ˮ˄˰ʳːʳ˃
ˢ̈̇̃̈̇ʳˣ̂̅̇
˨́˼˶˴̆̇ʳ˔˷˷̅
˘́̇̅̌ʳ˦̇˴̇˸ˮ˄˰ʳːʳ˄
ˠ̈˿̇˼˶˴̆̇ʳ˜́˷˸̋ʳːʳ˅
ˠ̈˿̇˼˶˴̆̇ʳ˔˷˷̅
˘́̇̅̌ʳ˦̇˴̇˸ˮ˄˰ʳːʳ˃
ˢ̈̇̃̈̇ʳˣ̂̅̇
˨́˼˶˴̆̇ʳ˔˷˷̅
˘́̇̅̌ʳ˦̇˴̇˸ˮ˄˰ʳːʳ˃
ˢ̈̇̃̈̇ʳˣ̂̅̇
˨́˼˶˴̆̇ʳ˔˷˷̅
˘́̇̅̌ʳ˦̇˴̇˸ˮ˄˰ʳːʳ˃
ˢ̈̇̃̈̇ʳˣ̂̅̇
˨́˼˶˴̆̇ʳ˔˷˷̅
˅
ˢ̈̇̃̈̇ʳˣ̂̅̇ʳˠ˴̃
ˆ˃
ˆ˄
Figure 12
Address Table Mapping to Output Port MAP
Table 37
Status Register Description
Busy
Command Result
Output Port Map
Status_2[3]
Status_2[2:0]
Status_0[25:0]
Table 38
Field Description in the Status Register
Field
Description
Output Port Map
The content associated with the multicast index will be here after searching.
Command Result
000B = Command OK
Busy
This bit indicates if the output port map engine is available.
0B
, The engine is available.
1B
, The engine is busy and it will not access the command from the CPU.
2. Rules to Access the Multicast Output Port Map Table
1. Check the Busy Bit to see if the access engine is available. If the engine is busy, wait until the engine is free.
If the engine is available, go to the following step.
2. Write output port map and the multicast index into the control register 0.
3. Write the command into the control register 2.
4. Read the Busy Bit. If Busy = 1B, wait. If Busy = 0B, the operation completes.
3. Example
Data Sheet
96
Rev 1.01, 2005-11-08
ADM6918/X
Switch Register Map
Table 39
Example
Example
Step
The user needs the ADM6918/X to forward
the specified multicast packet (DA =
0123_4567_89ABH and Forwarding Group =
3) to port 1, port2 and port 25. This address
could be aged. We assume the CPU wants
to write output port map into index 1.
Step 1: Check the Busy bit. If Busy = 0B, go to the step 2. If Busy =
1B, wait.
Step 2: Write 0060_0006H into control register 0.
Step 3: Write 0000_0004H into control register 2 start the “Write”
command.
Step 4: Check the Busy bit. If Busy = 1B, wait. If Busy = 1B, go to
the next step.
Step 5: Write 4567_89ABH into control register 0.
Step 6: Write 9c23_0123H into the control register 1.
Step 7: Write 0000_0000H into the control register 2 to start the
“Create” operation.
Step 8: Read the status register 2 to check the busy bit. If Busy =
0B, check the Command Result to see if the create operation is
successful. If Busy = 1B, wait for completion.
PHY Control Register
PHYCR
PHY Control Register
Offset
0BH
Reset Value
0000 0000H
5HV
$%
% &2
31
5$
')
UZ UZ
UZ
UZ
UZ
Field
Bits
Type
Description
ABB
27
rw
Access (Busy) Bit
CO
26
rw
Command Option
0B
, Write
1B
, Read
PN
25:21
rw
Port Number
RA
20:16
rw
Register Address
DF
15:0
rw
Data Field
This field indicates the data for reading or writing.
Notes
1. This register allows the user to control the PHY attached through the CUP’s help.
2. Rule for Read Operation:
Step 1: Poll the Busy bit (Bit[27]) to check if the PHY control module is busy.
Step 2: Write the port number (Bit[25:21]), register address (Bit[20:16]), command (Bit[26]) and Access
Data Sheet
97
Rev 1.01, 2005-11-08
ADM6918/X
Switch Register Map
bit(Bit[27]) to start the read operation.
Step 3: Poll the Busy bit (Bit[27]). If Busy = 1B, wait. If Busy = 0B, data is returned in the data field.
3. Rule for Write Operation:
Step 1: Poll the Busy bit (Bit[27]) to check if the PHY control module is busy.
Step 2: Write the port number (Bit[25:21]), register address (Bit[20:16]), command (Bit[26]), data field
(Bit[15:0]) and Access bit(Bit[27]) to start the write operation.
Step 3: Poll the Busy bit (Bit[27]). If Busy = 1B, wait. If Busy = 0B, writing operation completes.
4. Example: The user wants to read the Basic Control Register in Port 1.
Step 1: Read Bit[27] to check if PHY module is in progress.
Step 2: If Bit[27] = 0B, write Bit[27] = 1B, Bit[26] = 1B, Bit[25:21] = 5’h1 and Bit[20:16] = 5’h0.
Step 3: Poll the Busy bit. If Bit[27] = 0B, data is returned in the data field. If Bit[27] = 1B, wait.
Hardware Status
The Reset Value is done by hardware setting.
HS
Hardware Status
Offset
0DH
Reset Value
Hardware SettingH
%5 3B
,3 )& %3 $1
0 20 7( * ( ( ( $'
5HV
UR
UR
UR UR UR UR UR UR
Field
Bits
Type
Description
BRMII
8
ro
Bond RMII (SS-SMII or Pure RMII Mode)
0B
, The switch is in SS-SMII package.
1B
, The switch is in RMII package.
P24_25OM
7:6
ro
Port 24 or Port 25 Operate in RMII or MII Mode
00B , Port 24 and Port 25 are both configured to MII mode.
01B , Port 24 is configured to RMII; Port 25 is configured to MII.
10B , Port 24 is configured to MII; Port 25 is configured to RMII.
11B , Port 24 and Port 25 are both configured to RMII.
TE
5
ro
Trunking Enable From Hardware
0B
, Trunking Disable.
1B
, Trunking Enable.
IPG92TE
4
ro
IPG 92 Bit Time Enable From Hardware Pin
0B
, IPG 92 Disable.
1B
, IPG 92 Enable.
FCE
3
ro
Flow Control Enable For Full Duplex From Hardware Pin
0B
, Flow Control Disable.
1B
, Flow Control Enable.
BPE
2
ro
Back Pressure Enable From Hardware Pin
0B
, Back Pressure Disable.
1B
, Back Pressure Enable.
ANE
1
ro
Auto-Negotiation Enable From Hardware Pin
0B
, Auto-Negotiation Disable.
1B
, Auto-Negotiation Enable.
Data Sheet
98
Rev 1.01, 2005-11-08
ADM6918/X
Switch Register Map
Field
Bits
Type
Description
AD
0
ro
Aging Disable From Hardware Pin
0B
, Aging Enable.
1B
, Aging Disable.
Receive Packet Count Overflow
RPCO
Receive Packet Count Overflow
Offset
0EH
Reset Value
0000 0000H
5HV
3 3
5HV
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
&2 &2 &2 &2 &2 &2 &2 &2 &2 &2
URF URF
UR
URF URF
URFURF
URF URF URF URF URF URF URF URF URF URF URF URF URF
Field
Bits
Type
Description
P25CO
25
roc
Port 25 Receive Packet Count Overflow
P24CO
24
roc
Port 24 Receive Packet Count Overflow
Res
23:16
ro
Reserved
P15CO
15
roc
Port 15 Receive Packet Count Overflow
P14CO
14
roc
Port 14 Receive Packet Count Overflow
P13CO
13
roc
Port 13 Receive Packet Count Overflow
P12CO
12
roc
Port 12 Receive Packet Count Overflow
P11CO
11
roc
Port 11 Receive Packet Count Overflow
P10CO
10
roc
Port 10 Receive Packet Count Overflow
P9CO
9
roc
Port 9 Receive Packet Count Overflow
P8CO
8
roc
Port 8 Receive Packet Count Overflow
P7CO
7
roc
Port 7 Receive Packet Count Overflow
P6CO
6
roc
Port 6 Receive Packet Count Overflow
P5CO
5
roc
Port 5 Receive Packet Count Overflow
P4CO
4
roc
Port 4 Receive Packet Count Overflow
P3CO
3
roc
Port 3 Receive Packet Count Overflow
P2CO
2
roc
Port 2 Receive Packet Count Overflow
P1CO
1
roc
Port 1 Receive Packet Count Overflow
P0CO
0
roc
Port 0 Receive Packet Count Overflow
1B
, Receive packet count in port 0 overflows and it will be cleared after
read from CPU.
Receive Packet Length Count Overflow
Data Sheet
99
Rev 1.01, 2005-11-08
ADM6918/X
Switch Register Map
RPLCO
Receive Packet Length Count Overflow
Offset
0FH
Reset Value
0000 0000H
5HV
3 3
5HV
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
/ / / / / / / / / /
URF URF
UR
URF URF URF URF URF URF URF URF URF URF URF URF URF URF URF URF
Field
Bits
Type
Description
P25LCO
25
roc
Port 25 Receive Packet Length Count Overflow
P24LCO
24
roc
Port 24 Receive Packet Length Count Overflow
Res
23:16
ro
Reserved
P15LCO
15
roc
Port 15 Receive Packet Length Count Overflow
P14LCO
14
roc
Port 14 Receive Packet Length Count Overflow
P13LCO
13
roc
Port 13 Receive Packet Length Count Overflow
P12LCO
12
roc
Port 12 Receive Packet Length Count Overflow
P11LCO
11
roc
Port 11 Receive Packet Length Count Overflow
P10LCO
10
roc
Port 10 Receive Packet Length Count Overflow
P9LCO
9
roc
Port 9 Receive Packet Length Count Overflow
P8LCO
8
roc
Port 8 Receive Packet Length Count Overflow
P7LCO
7
roc
Port 7 Receive Packet Length Count Overflow
P6LCO
6
roc
Port 6 Receive Packet Length Count Overflow
P5LCO
5
roc
Port 5 Receive Packet Length Count Overflow
P4LCO
4
roc
Port 4 Receive Packet Length Count Overflow
P3LCO
3
roc
Port 3 Receive Packet Length Count Overflow
P2LCO
2
roc
Port 2 Receive Packet Length Count Overflow
P1LCO
1
roc
Port 1 Receive Packet Length Count Overflow
P0LCO
0
roc
Port 0 Receive Packet Length Count Overflow
1B
, Receive packet length count in port 0 overflows and it will be
cleared after read from CPU.
Transmit Packet Count Overflow
TPCO
Transmit Packet Count Overflow
Offset
10H
Reset Value
0000 0000H
5HV
Data Sheet
7 7
5HV
7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7
&2 &2 &2 &2 &2 &2 &2 &2 &2 &2
URF URF
UR
URF URF URF URF URF URF URF URF URF URF URF URF URF URF URF URF
100
Rev 1.01, 2005-11-08
ADM6918/X
Switch Register Map
Field
Bits
Type
Description
T25CO
25
roc
Port 25 Transmit Packet Count Overflow
T24CO
24
roc
Port 24 Transmit Packet Count Overflow
Res
23:16
ro
Reserved
T15CO
15
roc
Port 15 Transmit Packet Count Overflow
T14CO
14
roc
Port 14 Transmit Packet Count Overflow
T13CO
13
roc
Port 13 Transmit Packet Count Overflow
T12CO
12
roc
Port 12 Transmit Packet Count Overflow
T11CO
11
roc
Port 11 Transmit Packet Count Overflow
T10CO
10
roc
Port 10 Transmit Packet Count Overflow
T9CO
9
roc
Port 9 Transmit Packet Count Overflow
T8CO
8
roc
Port 8 Transmit Packet Count Overflow
T7CO
7
roc
Port 7 Transmit Packet Count Overflow
T6CO
6
roc
Port 6 Transmit Packet Count Overflow
T5CO
5
roc
Port 5 Transmit Packet Count Overflow
T4CO
4
roc
Port 4 Transmit Packet Count Overflow
T3CO
3
roc
Port 3 Transmit Packet Count Overflow
T2CO
2
roc
Port 2 Transmit Packet Count Overflow
T1CO
1
roc
Port 1 Transmit Packet Count Overflow
T0CO
0
roc
Port 0 Transmit Packet Count Overflow
1B
, Transmit packet count in port 0 overflows and it will be cleared
after read from CPU.
Transmit Packet Length Count Overflow
TPLCO
Transmit Packet Length Count Overflow
Offset
11H
Reset Value
0000 0000H
5HV
7 7
5HV
7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7
/ / / / / / / / / /
URF URF
UR
URF URF URF URF URF URF URF URF URF URF URF URF URF URF URF URF
Field
Bits
Type
Description
T25LCO
25
roc
Port 25 Transmit Packet Length Count Overflow
T24LCO
24
roc
Port 24 Transmit Packet Length Count Overflow
Res
23:16
ro
Reserved
T15LCO
15
roc
Port 15 Transmit Packet Length Count Overflow
T14LCO
14
roc
Port 14 Transmit Packet Length Count Overflow
T13LCO
13
roc
Port 13 Transmit Packet Length Count Overflow
T12LCO
12
roc
Port 12 Transmit Packet Length Count Overflow
Data Sheet
101
Rev 1.01, 2005-11-08
ADM6918/X
Switch Register Map
Field
Bits
Type
Description
T11LCO
11
roc
Port 11 Transmit Packet Length Count Overflow
T10LCO
10
roc
Port 10 Transmit Packet Length Count Overflow
T9LCO
9
roc
Port 9 Transmit Packet Length Count Overflow
T8LCO
8
roc
Port 8 Transmit Packet Length Count Overflow
T7LCO
7
roc
Port 7 Transmit Packet Length Count Overflow
T6LCO
6
roc
Port 6 Transmit Packet Length Count Overflow
T5LCO
5
roc
Port 5 Transmit Packet Length Count Overflow
T4LCO
4
roc
Port 4 Transmit Packet Length Count Overflow
T3LCO
3
roc
Port 3 Transmit Packet Length Count Overflow
T2LCO
2
roc
Port 2 Transmit Packet Length Count Overflow
T1LCO
1
roc
Port 1 Transmit Packet Length Count Overflow
T0LCO
0
roc
Port 0 Transmit Packet Length Count Overflow
1B
, Transmit packet length count in port 0 overflows and it will be
cleared after read from CPU.
Error Count Overflow
ECO
Error Count Overflow
Offset
12H
Reset Value
0000 0000H
5HV
3 3
5HV
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
( ( ( ( ( ( ( ( ( (
URF URF
UR
URF URF URF URF URF URF URF URF URF URF URF URF URF URF URF URF
Field
Bits
Type
Description
P25ECO
25
roc
Port 25 Error Count Overflow
P24ECO
24
roc
Port 24 Error Count Overflow
Res
23:16
ro
Reserved
P15ECO
15
roc
Port 15 Error Count Overflow
P14ECO
14
roc
Port 14 Error Count Overflow
P13ECO
13
roc
Port 13 Error Count Overflow
P12ECO
12
roc
Port 12 Error Count Overflow
P11ECO
11
roc
Port 11 Error Count Overflow
P10ECO
10
roc
Port 10 Error Count Overflow
P9ECO
9
roc
Port 9 Error Count Overflow
P8ECO
8
roc
Port 8 Error Count Overflow
P7ECO
7
roc
Port 7 Error Count Overflow
P6ECO
6
roc
Port 6 Error Count Overflow
P5ECO
5
roc
Port 5 Error Count Overflow
P4ECO
4
roc
Port 4 Error Count Overflow
Data Sheet
102
Rev 1.01, 2005-11-08
ADM6918/X
Switch Register Map
Field
Bits
Type
Description
P3ECO
3
roc
Port 3 Error Count Overflow
P2ECO
2
roc
Port 2 Error Count Overflow
P1ECO
1
roc
Port 1 Error Count Overflow
P0ECO
0
roc
Port 0 Error Count Overflow
1B
, Error count in port 0 overflows and it will be cleared after read from
CPU.
Collision Count Overflow
CCO
Collision Count Overflow
Offset
13H
Reset Value
0000 0000H
5HV
3 3
5HV
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
& & & & & & & & & &
URF URF
UR
URF URF URF URF URF URF URF URF URF URF URF URF URF URF URF URF
Field
Bits
Type
Description
P25CCO
25
roc
Port 25 Collision Count Overflow
P24CCO
24
roc
Port 24 Collision Count Overflow
Res
23:16
ro
Reserved
P15CCO
15
roc
Port 15 Collision Count Overflow
P14CCO
14
roc
Port 14 Collision Count Overflow
P13CCO
13
roc
Port 13 Collision Count Overflow
P12CCO
12
roc
Port 12 Collision Count Overflow
P11CCO
11
roc
Port 11 Collision Count Overflow
P10CCO
10
roc
Port 10 Collision Count Overflow
P9CCO
9
roc
Port 9 Collision Count Overflow
P8CCO
8
roc
Port 8 Collision Count Overflow
P7CCO
7
roc
Port 7 Collision Count Overflow
P6CCO
6
roc
Port 6 Collision Count Overflow
P5CCO
5
roc
Port 5 Collision Count Overflow
P4CCO
4
roc
Port 4 Collision Count Overflow
P3CCO
3
roc
Port 3 Collision Count Overflow
P2CCO
2
roc
Port 2 Collision Count Overflow
P1CCO
1
roc
Port 1 Collision Count Overflow
P0CCO
0
roc
Port 0 Collision Count Overflow
1B
, Collision Count in port 0 overflows and it will be cleared after read
from CPU.
Renew Counter Register
Data Sheet
103
Rev 1.01, 2005-11-08
ADM6918/X
Switch Register Map
RCR
Renew Counter Register
Offset
14H
Reset Value
0000 0000H
5HV
$% & &
% 5HV
& & & & & &
& & & & & & & & & &
UZ UZ UZ
UR
UZ UZ UZ UZ UZ UZ UZ UZ UZ UZ UZ UZ UZ UZ UZ UZ
Field
Bits
Type
Description
ABB
26
rw
Access (Busy) Bit
C25
25
rw
Counter Port 25
1B
, Clear Port 25 Corresponding Counters
C24
24
rw
Counter Port 24
1B
, Clear Port 24 Corresponding Counters
Res
23:16
ro
Reserved
C15
15
rw
Counter Port 15
1B
, Clear Port 15 Corresponding Counters
C14
14
rw
Counter Port 14
1B
, Clear Port 14 Corresponding Counters
C13
13
rw
Counter Port 13
1B
, Clear Port 13 Corresponding Counters
C12
12
rw
Counter Port 12
1B
, Clear Port 12 Corresponding Counters
C11
11
rw
Counter Port 11
1B
, Clear Port 11 Corresponding Counters
C10
10
rw
Counter Port 10
1B
, Clear Port 10 Corresponding Counters
C9
9
rw
Counter Port 9
1B
, Clear Port 9 Corresponding Counters
C8
8
rw
Counter Port 8
1B
, Clear Port 8 Corresponding Counters
C7
7
rw
Counter Port 7
1B
, Clear Port 7 Corresponding Counters
C6
6
rw
Counter Port 6
1B
, Clear Port 6 Corresponding Counters
C5
5
rw
Counter Port 5
1B
, Clear Port 5 Corresponding Counters
C4
4
rw
Counter Port 4
1B
, Clear Port 4 Corresponding Counters
C3
3
rw
Counter Port 3
1B
, Clear Port 3 Corresponding Counters
C2
2
rw
Counter Port 2
1B
, Clear Port 2 Corresponding Counters
Data Sheet
104
Rev 1.01, 2005-11-08
ADM6918/X
Switch Register Map
Field
Bits
Type
Description
C1
1
rw
Counter Port 1
1B
, Clear Port 1 Corresponding Counters
C0
0
rw
Counter Port 0
1B
, Clear Port 0 Corresponding Counters
Notes
1. This register allows the user to reset all counters for the corresponding port. If the renew counter module is
busy all other modules about counters are not accessible.
2. Rule:
Step 1: Poll the busy bit to check if the renew counter module is busy.
Step 2: If the renew counter module is available, write the port (Bit[25:0]) the user wants to reset and the busy
bit(Bit[26]) to 1.
Step 3: Poll the busy bit to check if the renew counter module completes the job.
3. Example:
Users want to reset P0, P1, P2, P3 corresponding counters.
Step 1: Read Bit[26] to check if reset is in progress.
Step 2: If Bit[26] = 0, write Bit[26] = 1B, Bit[25:0] = 00_0000_0000_0000_0000_0000_1111B into the register.
Step 3: Poll the busy bit to check if reset completes.
Read Counter Control Register
RCCR
Read Counter Control Register
Offset
15H
Reset Value
0000_0000H
5HV
Field
Bits
Type
Description
ABB
8
rw
Access (Busy) Bit
CI
7:0
rw
Counter Index
$%
%
&,
UZ
UZ
Read Counter Status Register
RCSR
Read Counter Status Register
Data Sheet
Offset
16H
105
Reset Value
0000 0000H
Rev 1.01, 2005-11-08
ADM6918/X
Switch Register Map
&,
UR
Field
Bits
Type
Description
CI
31:0
ro
Counter Index
The corresponding counter index by the Bit[7:0] is returned here.
Notes
1. The Read Counter Control Register and the Read Counter Status Register provide users to read counter if he
wants to use fast management clock (fast than 5 MHz).
2. Rules:
Step 1: Read the Busy bit to check if the read counter module is busy
Step 2: If the module is free, write the counter index and access bit into the control register
Step 3: Poll the Busy bit. If Busy = 1B, wait. If Busy = 0B read the status register
3. Example: Users want to read Port 1 Receive Packet Count
Step 1: Read Bit[8] to check if the read counter module is busy
Step 3: Then Port 1 Receive Packet Count will be loaded into the Counter Status Register (Offset: 16H)
Step 2: If Bit[8] = 0, then write bit[8] = 1B, Bit[7:0] = 8’b1 into the register
Step 4: Read Counter Status Register (Offset: 16H) and the content read is the Port 1 Receive Packet Count
Reload MDIO Register
RMDIOR
Reload MDIO Register
Offset
17H
Reset Value
0000 0000H
5HV
3 3
5HV
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
0 0 0 0 0 0 0 0 0 0
UZ UZ
UR
UZ UZ UZ UZ UZ UZ UZ UZ UZ UZ UZ UZ UZ UZ UZ UZ
Field
Bits
Type
Description
P25MDIO
25
rw
Port 25 MDIO Register Reload
P24MDIO
24
rw
Port 24 MDIO Register Reload
Res
23:16
ro
Reserved
P15MDIO
15
rw
Port 15 MDIO Register Reload
P14MDIO
14
rw
Port 14 MDIO Register Reload
P13MDIO
13
rw
Port 13 MDIO Register Reload
P12MDIO
12
rw
Port 12 MDIO Register Reload
P11MDIO
11
rw
Port 11 MDIO Register Reload
Data Sheet
106
Rev 1.01, 2005-11-08
ADM6918/X
Switch Register Map
Field
Bits
Type
Description
P10MDIO
10
rw
Port 10 MDIO Register Reload
P9MDIO
9
rw
Port 9 MDIO Register Reload
P8MDIO
8
rw
Port 8 MDIO Register Reload
P7MDIO
7
rw
Port 7 MDIO Register Reload
P6MDIO
6
rw
Port 6 MDIO Register Reload
P5MDIO
5
rw
Port 5 MDIO Register Reload
P4MDIO
4
rw
Port 4 MDIO Register Reload
P3MDIO
3
rw
Port 3 MDIO Register Reload
P2MDIO
2
rw
Port 2 MDIO Register Reload
P1MDIO
1
rw
Port 1 MDIO Register Reload
P0MDIO
0
rw
Port 0 MDIO Register Reload
1B
, Status of Port 0 PHY attached will be reloaded and updated to the
switch. After PHY is reloaded, Bit[0] will be cleared.
Spanning Tree Port State 0
STPS0
Spanning Tree Port State 0
Offset
18H
Reset Value
0000 0000H
36 36 36 36 36 36 367 367 367 367 367 367 367 367 367 367
736 736 736 736 736 736 36
36
36
36
36
36
36
36
36
36
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
UZ
Field
Bits
Type
Description
P15STPS
31:30
rw
Port 15 Spanning Tree Port Status
P14STPS
29:28
rw
Port 14 Spanning Tree Port Status
P13STPS
27:26
rw
Port 13 Spanning Tree Port Status
P12STPS
25:24
rw
Port 12 Spanning Tree Port Status
P11STPS
23:22
rw
Port 11 Spanning Tree Port Status
P10STPS
21:20
rw
Port 10 Spanning Tree Port Status
P9STPS
19:18
rw
Port 9 Spanning Tree Port Status
P8STPS
17:16
rw
Port 8 Spanning Tree Port Status
P7STPS
15:14
rw
Port 7 Spanning Tree Port Status
P6STPS
13:12
rw
Port 6 Spanning Tree Port Status
P5STPS
11:10
rw
Port 5 Spanning Tree Port Status
P4STPS
9:8
rw
Port 4 Spanning Tree Port Status
P3STPS
7:6
rw
Port 3 Spanning Tree Port Status
P2STPS
5:4
rw
Port 2 Spanning Tree Port Status
P1STPS
3:2
rw
Port 1 Spanning Tree Port Status
P0STPS
1:0
rw
Port 0 Spanning Tree Port Status
Data Sheet
107
UZ
UZ
UZ
UZ
UZ
Rev 1.01, 2005-11-08
ADM6918/X
Switch Register Map
Note: The ADM6918/X supports 4 port status to support Spanning Tree
Protocol.
00B = Forwarding State. The port acts as the normal
mode.
01B = Disabled State. The port entity will not transmit
and receive any packets. Learning is disabled in this
state.
10B = Learning State. The port entity will only transmit and receive management packets. All other packets
are discarded. Learning is enabled for all good frames.
11B = Blocking-not-Listening. Only the management packets defined by the ADM6918/X will be received and
transmitted.
All other packets are discarded by the port entity. Learning is disabled in this state.
Spanning Tree Port State 1
STPS1
Spanning Tree Port State 1
Offset
19H
Reset Value
0000 0000H
36 36
736 736
5HV
UZ
UZ
5HV
UR
Field
Bits
Type
Description
P25STPS
19:18
rw
Port 25 Spanning Tree Port Status
P24STPS
17:16
rw
Port 24 Spanning Tree Port Status
Res
15:0
ro
Reserved
Source Port Register
SCPR
Source Port Register
Offset
1AH
Reset Value
0000_0000H
5HV
6&3
UR
Field
Bits
Type
Description
SCP
4:0
ro
The Source Port
The CPU can read this register to get the source port when he receives
a packet.
Data Sheet
108
Rev 1.01, 2005-11-08
ADM6918/X
Switch Register Map
Note: The value will be correct after the SA is transmitted.
Transmit Port Register
TRPR
Transmit Port Register
Offset
1BH
Reset Value
0000 0000H
5HV
%, %,
7 7
%,7B
UZ UZ
UZ
Field
Bits
Type
Description
BIT27
27
rw
Bit 27
0B
, The command is not valid.
1B
, The command is valid.
BIT26
26
rw
Bit 26
The destination ports is more than 1
BIT25_0
25:0
rw
Bit 25_0
The destination ports the CPU wants to forward.
Note: The value should be written before CPU transmits a packet.
Counter Register
Offset 0100H ~ 019BH
Table 40
Counter Register: Offset 0100H ~ 0167H
Offset Hex Index Description
Offset Hex Index Description
The Receive Count
0100
0
Port 0 Receive Packet Count
011A
1A
Port 0 Receive Packet Length
Count
0101
1
Port 1 Receive Packet Count
011B
1B
Port 1 Receive Packet Length
Count
0102
2
Port 2 Receive Packet Count
011C
1C
Port 2 Receive Packet Length
Count
0103
3
Port 3 Receive Packet Count
011D
1D
Port 3 Receive Packet Length
Count
0104
4
Port 4 Receive Packet Count
011E
1E
Port 4 Receive Packet Length
Count
0105
5
Port 5 Receive Packet Count
011F
1F
Port 5 Receive Packet Length
Count
Data Sheet
109
Rev 1.01, 2005-11-08
ADM6918/X
Switch Register Map
Table 40
Counter Register: Offset 0100H ~ 0167H (cont’d)
Offset Hex Index Description
Offset Hex Index Description
0106
6
Port 6 Receive Packet Count
0120
20
Port 6 Receive Packet Length
Count
0107
7
Port 7 Receive Packet Count
0121
21
Port 7 Receive Packet Length
Count
0108
8
Port 8 Receive Packet Count
0122
22
Port 8 Receive Packet Length
Count
0109
9
Port 9 Receive Packet Count
0123
23
Port 9 Receive Packet Length
Count
010A
A
Port 10 Receive Packet Count
0124
24
Port 10 Receive Packet Length
Count
010B
B
Port 11 Receive Packet Count
0125
25
Port 11 Receive Packet Length
Count
010C
C
Port 12 Receive Packet Count
0126
26
Port 12 Receive Packet Length
Count
010D
D
Port 13 Receive Packet Count
0127
27
Port 13 Receive Packet Length
Count
010E
E
Port 14 Receive Packet Count
0128
28
Port 14 Receive Packet Length
Count
010F
F
Port 15 Receive Packet Count
0129
29
Port 15 Receive Packet Length
Count
0110
10
Port 16 Receive Packet Count
012A
2A
Port 16 Receive Packet Length
Count
0111
11
Port 17 Receive Packet Count
012B
2B
Port 17 Receive Packet Length
Count
0112
12
Port 18 Receive Packet Count
012C
2C
Port 18 Receive Packet Length
Count
0113
13
Port 19 Receive Packet Count
012D
2D
Port 19 Receive Packet Length
Count
0114
14
Port 20 Receive Packet Count
012E
2E
Port 20 Receive Packet Length
Count
0115
15
Port 21 Receive Packet Count
012F
2F
Port 21 Receive Packet Length
Count
0116
16
Port 22 Receive Packet Count
0130
30
Port 22 Receive Packet Length
Count
0117
17
Port 23 Receive Packet Count
0131
31
Port 23 Receive Packet Length
Count
0118
18
Port 24 Receive Packet Count
0132
32
Port 24 Receive Packet Length
Count
0119
19
Port 25 Receive Packet Count
0133
33
Port 25 Receive Packet Length
Count
Port 0 Transmit Packet Count
014E
4E
Port 0 Transmit Packet Length
Count
The Transmit Count
0134
Data Sheet
34
110
Rev 1.01, 2005-11-08
ADM6918/X
Switch Register Map
Table 40
Counter Register: Offset 0100H ~ 0167H (cont’d)
Offset Hex Index Description
Offset Hex Index Description
0135
35
Port 1 Transmit Packet Count
014F
4F
Port 1 Transmit Packet Length
Count
0136
36
Port 2 Transmit Packet Count
0150
50
Port 2 Transmit Packet Length
Count
0137
37
Port 3 Transmit Packet Count
0151
51
Port 3 Transmit Packet Length
Count
0138
38
Port 4 Transmit Packet Count
0152
52
Port 4 Transmit Packet Length
Count
0139
39
Port 5 Transmit Packet Count
0153
53
Port 5 Transmit Packet Length
Count
013A
3A
Port 6 Transmit Packet Count
0154
54
Port 6 Transmit Packet Length
Count
013B
3B
Port 7 Transmit Packet Count
0155
55
Port 7 Transmit Packet Length
Count
013C
3C
Port 8 Transmit Packet Count
0156
56
Port 8 Transmit Packet Length
Count
013D
3D
Port 9 Transmit Packet Count
0157
57
Port 9 Transmit Packet Length
Count
013E
3E
Port 10 Transmit Packet Count
0158
58
Port 10 Transmit Packet Length
Count
013F
3F
Port 11 Transmit Packet Count
0159
59
Port 11 Transmit Packet Length
Count
0140
40
Port 12 Transmit Packet Count
015A
5A
Port 12 Transmit Packet Length
Count
0141
41
Port 13 Transmit Packet Count
015B
5B
Port 13 Transmit Packet Length
Count
0142
42
Port 14 Transmit Packet Count
015C
5C
Port 14 Transmit Packet Length
Count
0143
43
Port 15 Transmit Packet Count
015D
5D
Port 15 Transmit Packet Length
Count
0144
44
Port 16 Transmit Packet Count
015E
5E
Port 16 Transmit Packet Length
Count
0145
45
Port 17 Transmit Packet Count
015F
5F
Port 17 Transmit Packet Length
Count
0146
46
Port 18 Transmit Packet Count
0160
60
Port 18 Transmit Packet Length
Count
0147
47
Port 19 Transmit Packet Count
0161
61
Port 19 Transmit Packet Length
Count
0148
48
Port 20 Transmit Packet Count
0162
62
Port 20 Transmit Packet Length
Count
0149
49
Port 21 Transmit Packet Count
0163
63
Port 21 Transmit Packet Length
Count
014A
4A
Port 22 Transmit Packet Count
0164
64
Port 22 Transmit Packet Length
Count
Data Sheet
111
Rev 1.01, 2005-11-08
ADM6918/X
Switch Register Map
Table 40
Counter Register: Offset 0100H ~ 0167H (cont’d)
Offset Hex Index Description
Offset Hex Index Description
014B
4B
Port 23 Transmit Packet Count
0165
65
Port 23 Transmit Packet Length
Count
014C
4C
Port 24 Transmit Packet Count
0166
66
Port 24 Transmit Packet Length
Count
014D
4D
Port 25 Transmit Packet Count
0167
67
Port 25 Transmit Packet Length
Count
Error and Collision Count
0168
68
Port 0 Receive Error Count
0182
82
Port 0 Collision Count
0169
69
Port 1 Receive Error Count
0183
83
Port 1 Collision Count
016A
6A
Port 2 Receive Error Count
0184
84
Port 2 Collision Count
016B
6B
Port 3 Receive Error Count
0185
85
Port 3 Collision Count
016C
6C
Port 4 Receive Error Count
0186
86
Port 4 Collision Count
016D
6D
Port 5 Receive Error Count
0187
87
Port 5 Collision Count
016E
6E
Port 6 Receive Error Count
0188
88
Port 6 Collision Count
016F
6F
Port 7 Receive Error Count
0189
89
Port 7 Collision Count
0170
70
Port 8 Receive Error Count
018A
8A
Port 8 Collision Count
0171
71
Port 9 Receive Error Count
018B
8B
Port 9 Collision Count
0172
72
Port 10 Receive Error Count
018C
8C
Port 10 Collision Count
0173
73
Port 11 Receive Error Count
018D
8D
Port 11 Collision Count
0174
74
Port 12 Receive Error Count
018E
8E
Port 12 Collision Count
0175
75
Port 13 Receive Error Count
018F
8F
Port 13 Collision Count
0176
76
Port 14 Receive Error Count
0190
90
Port 14 Collision Count
0177
77
Port 15 Receive Error Count
0191
91
Port 15 Collision Count
0178
78
Port 16 Receive Error Count
0192
92
Port 16 Collision Count
0179
79
Port 17 Receive Error Count
0193
93
Port 17 Collision Count
017A
7A
Port 18 Receive Error Count
0194
93
Port 18 Collision Count
017B
7B
Port 19 Receive Error Count
0195
95
Port 19 Collision Count
017C
7C
Port 20 Receive Error Count
0196
96
Port 20 Collision Count
017D
7D
Port 21 Receive Error Count
0197
97
Port 21 Collision Count
017E
7E
Port 22 Receive Error Count
0198
98
Port 22 Collision Count
017F
7F
Port 23 Receive Error Count
0199
99
Port 23 Collision Count
0180
80
Port 24 Receive Error Count
019A
9A
Port 24 Collision Count
0181
81
Port 25 Receive Error Count
019B
9B
Port 25 Collision Count
Data Sheet
112
Rev 1.01, 2005-11-08
ADM6918/X
Electrical Specifications
6
Electrical Specifications
6.1
DC Characteristics
6.1.1
Absolute Maximum Ratings
Table 41
Electrical Absolute Maximum Ratings
Parameter
Symbol
3.3 V Power Supply
VCCO
VCCIK
VIN
1.8 V Power Supply
Input Voltage
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
3.0
–
3.6
V
–
1.71
–
1.89
V
–
-0.3
–
VCC 33 +
V
–
V
–
0.3
Output Voltage
Vout
-0.3
–
VCC 33 +
Storage Temperature
TSTG
PD
ESD
-55
–
155
°C
–
–
–
1.0
W
–
–
–
3000
V
–
Unit
Note / Test Condition
0.3
Power Dissipation
ESD Rating
6.1.2
Recommended Operating Conditions
Table 42
Recommended Operating Conditions
Parameter
Symbol
Power Supply
Input Voltage
Junction Operating
Temperature
6.1.3
VCC
VIN
Tj
Values
Min.
Typ.
Max.
3.135
3.3
3.465
V
–
0
–
VCC
V
–
0
25
115
°C
–
Unit
Note / Test Condition
DC Electrical Characteristics for 3.3 V Operation
Under Vcc= 3.0 V~3.6V, Tj= 0°C~115°C
Table 43
DC Electrical Characteristics for 3.3 V Operation
Parameter
Symbol
VIL
Input High Voltage
VIH
Output Low Voltage
VOL
Output High Voltage
VOH
Input Pull-up/down Resistance RI
Input Low Voltage
Data Sheet
Values
Min.
Typ.
Max.
–
–
0.8
V
TTL
2.0
–
–
V
TTL
–
–
0.4
V
TTL
2.3
–
–
V
TTL
–
50
–
KΩ
VIL = 0 V or VIH = VCC
113
Rev 1.01, 2005-11-08
ADM6918/X
Electrical Specifications
6.2
AC Characteristics
6.2.1
XI/OSCI (Crystal/Oscillator) Timing
t XI PE
t XI H
V
V
t XI L
IH XI
IL XI
t XI RIS
Figure 13
Crystal/Oscillator Timing
Table 44
Crystal/Oscillator Timing
Parameter
t XI FAL
Symbol
Values
Min.
Typ.
Max.
Unit
Note / Test Condition
XI/OSCI Clock Period
t_XI_PER
20.0 50ppm
20.0
20.0 +
50ppm
ns
–
XI/OSCI Clock High
t_XI_HI
t_XI_LO
t_XI_RISE
8
10.0
–
ns
–
8
10.0
–
ns
–
–
–
2
ns
–
t_XI_FALL
–
–
2
ns
–
XI/OSCI Clock Low
XI/OSCI Clock Rise Time, VIL
(max) to VIH (min)
XI/OSCI Clock Fall Time, VIH
(min) to VIL (max)
6.2.2
Data Sheet
Power On Reset
114
Rev 1.01, 2005-11-08
ADM6918/X
Electrical Specifications
0us
50ms
100ms
150ms
tRST
RST*
tCONF
All Configuration Pins
Figure 14
Power on Reset Timing
Table 45
Power on Reset Timing
Parameter
Symbol
tRST
tCONF
RST Low Period
Start of Configuration Pins
6.2.3
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
150
–
–
ms
–
100
–
–
ns
–
EEPROM Interface Timing
0us
6.4us
12.8us
19.2us
EECS
tESKL
tESKH
tESK
EESK
tEWDD
EEDO
tERDS
tERDH
EEDI
Figure 15
EEPROM Interface Timing
Table 46
EEPROM Interface Timing
Parameter
EESK Period
EESK Low Period
EESK High Period
EEDI to EESK Rising Setup
Time
Data Sheet
Symbol
tESK
tESKL
tESKH
tERDS
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
–
3.2
–
µs
–
–
1.6
–
µs
–
–
1.6
–
µs
–
10
–
–
ns
–
115
Rev 1.01, 2005-11-08
ADM6918/X
Electrical Specifications
Table 46
EEPROM Interface Timing (cont’d)
Parameter
Symbol
EEDI to EESK Rising Hold
Time
Values
tERDH
EESK Falling to EEDO Output tEWDD
Delay Time
6.2.4
Unit
Note / Test Condition
Min.
Typ.
Max.
10
–
–
ns
–
–
–
20
ns
–
10Base-TX MII Output Timing
0ns
500ns
1000ns
1500ns
2000ns
2500ns
tCK
tCKL
tCKH
MII_TXCLK
tTXOD
MII_TXEN
MII_TXD
Figure 16
10Base-TX MII Output Timing
Table 47
10Base-TX MII Output Timing
Parameter
Symbol
MII_TXCLK Period
MII_TXCLK Low Period
MII_TXCLK High Period
MII_TXD, MII_TXEN to
MII_TXCLK Rising Output
Delay
6.2.5
Data Sheet
tCK
tCKL
tCKH
tTXOD
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
–
400
–
ns
–
160
–
240
ns
–
160
–
240
ns
–
10
–
20
ns
–
10Base-TX MII Input Timing
116
Rev 1.01, 2005-11-08
ADM6918/X
Electrical Specifications
0ns
1000ns
2000ns
tCK
tCKL
tCKH
MII_RXCLK
tRXS
MII_RXDV
tRXH
MII_RXD
MII_CRS
Figure 17
10Base-TX MII Input Timing
Table 48
10Base-TX MII Input Timing
Parameter
Symbol
MII_RXCLK Period
MII_RXCLK Low Period
MII_RXCLK High Period
MII_CRS, MII_RXDV and
MII_RXD to MII_RXCLK rising
setup
tCK
tCKL
tCKH
tRXS
MII_CRS, MII_RXDV and
tRXH
MII_RXD to MII_RXCLK rising
hold
6.2.6
Data Sheet
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
–
400
–
ns
–
160
–
240
ns
–
160
–
240
ns
–
10
–
–
ns
–
10
–
–
ns
–
100Base-TX MII Output Timing
117
Rev 1.01, 2005-11-08
ADM6918/X
Electrical Specifications
0ns
50ns
100ns
150ns
200ns
250ns
tCK
tCKL
tCKH
MII_TXCLK
tTXOD
MII_TXEN
MII_TXD
Figure 18
100Base-TX MII Output Timing
Table 49
100Base-TX MII Output Timing
Parameter
Symbol
MII_TXCLK Period
MII_TXCLK Low Period
MII_TXCLK High Period
MII_TXD, MII_TXEN to
MII_TXCLK Rising Out put
Delay
6.2.7
tCK
tCKL
tCKH
tTXOD
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
–
40
–
ns
–
16
–
24
ns
–
16
–
24
ns
–
10
–
20
ns
–
100Base-TX MII Input Timing
0ns
100ns
200ns
tCK
tCKL
tCKH
MII_RXCLK
tRXS
MII_RXDV
tRXH
MII_RXD
MII_CRS
Figure 19
Data Sheet
100Base-TX MII Input Timing
118
Rev 1.01, 2005-11-08
ADM6918/X
Electrical Specifications
Table 50
100Base-TX MII Input Timing
Parameter
Symbol
MII_RXCLK Period
MII_RXCLK Low Period
MII_RXCLK High Period
MII_CRS, MII_RXDV and
MII_RXD to MII_RXCLK rising
setup
Values
tCK
tCKL
tCKH
tRXS
MII_CRS, MII_RXDV and
tRXH
MII_RXD to MII_RXCLK rising
hold
6.2.8
Unit
Note / Test Condition
Min.
Typ.
Max.
–
40
–
ns
–
16
–
24
ns
–
16
–
24
ns
–
10
–
–
ns
–
10
–
–
ns
–
Reduced MII Timing
0ns
50ns
100ns
tCKL
tCK
tCKH
REFCLK
RMII_TXEN
tTXH
tTXS
TXD[1:0]
Figure 20
Reduced MII Timing (1 of 2)
0ns
50ns
100ns
tCK
tCKL
tCKH
REFCLK
RMII_CRSDV
tRXH
tRXS
RXD[1:0]
Figure 21
Data Sheet
Reduced MII Timing (2 of 2)
119
Rev 1.01, 2005-11-08
ADM6918/X
Electrical Specifications
Table 51
Reduced MII Timing
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
tCK
tCKL
tCKH
tTXS
–
20
–
ns
–
–
10
–
ns
–
–
10
–
ns
–
4
–
–
ns
–
TXEN, TXD to REFCLK rising
hold time
tTXH
2
–
–
ns
–
CSRDV, RXD to REFCLK
rising setup time
tRXS
4
–
–
ns
–
CRSDV, RXD to REFCLK
rising hold time
tRXH
2
–
–
ns
–
RMII_REFCLK Period
RMII_REFCLK Low Period
RMII_REFCLK High Period
TXEN, TXD to REFCLK rising
setup time
6.2.9
SS_SMII Transmit Timing
0ns
20ns
40ns
tCKL
tCK
tCKH
CLK_TX
SYNC_TX
tTRN
tOD
STXD[7:0]
Figure 22
SS_SMII Transmit Timing
Table 52
SS_SMII Transmit Timing
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
tCK
tCKL
–
8
–
ns
–
–
4
–
ns
–
R SS_SMII Output Clock High tCKH
Period
–
4
–
ns
–
Txdata/TxSync output delay to tOD
CLK_TX
2
–
5
ns
–
Txdata/RxSync Rise/Fall Time tTRN
–
1
–
ns
–
SS_SMII Output Clock Period
SS_SMII Output Clock Low
Period
Data Sheet
120
Rev 1.01, 2005-11-08
ADM6918/X
Electrical Specifications
6.2.10
SS_SMII Receive Timing
0ns
20ns
40ns
tCKL
tCK
tCKH
CLK_RX
SYNC_RX
tDH
tDS
SRXD[7:0]
Figure 23
SS_SMII Receive Timing
Table 53
SS_SMII Receive Timing
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
–
8
–
ns
–
SS_SMII CLK_RX Low Period tCKL
–
4
–
ns
–
SS_SMII CLK_RX High Period tCKH
–
4
–
ns
–
SS_SMII CLK_RX Clock
Period
tCK
Rxdata/RxSync setup to
CLK_RX rising edge
tDS
1.5
–
–
ns
–
Rxdata/RxSync hold from
CLK_RX rising edge
tDH
1
–
–
ns
–
Data Sheet
121
Rev 1.01, 2005-11-08
ADM6918/X
Electrical Specifications
6.2.11
Serial Management Interface (SDC/SDIO) Timing
SDC/SDIO timing is same as MDC/MDIO except Data Length is 32 bits.
0ns
1ms
2ms
tCKL
tCK
tCKH
SDC
tOD
SDIO (output)
tDH
tDS
SDIO (input)
Figure 24
Serial Management Interface (SDC/SDIO) Timing
Table 54
Serial Management Interface (SDC/SDIO) Timing
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
–
400
–
ns
–
SS_SMII CLK_RX Low Period tCKL
–
200
–
ns
–
SS_SMII CLK_RX High Period tCKH
–
200
–
ns
–
–
–
20
ns
–
10
–
–
ns
–
10
–
–
ns
–
SS_SMII CLK_RX Clock
Period
S DC to S DIO Output Delay
S DIO Input to S DC Setup
Time
tCK
tOD
tDS
S DIO Input to S DC Hold Time tDH
Data Sheet
122
Rev 1.01, 2005-11-08
ADM6918/X
Packaging
7
Packaging
17.2 +/- 0.2 mm
14.0 +/- 0.1 mm
18.5 mm
23.2 +/- 0.2 mm
20.0 +/- 0.1 mm
12.5 mm
3.4 mm
MAX
0.5 mm
Figure 25
Data Sheet
ADM6918/X Packaging
123
Rev 1.01, 2005-11-08
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