ON MC3403DG Single supply quad operational amplifier Datasheet

MC3403, MC3303
Single Supply Quad
Operational Amplifiers
The MC3403 is a low cost, quad operational amplifier with true
differential inputs. The device has electrical characteristics similar to
the popular MC1741C. However, the MC3403 has several distinct
advantages over standard operational amplifier types in single supply
applications. The quad amplifier can operate at supply voltages as low
as 3.0 V or as high as 36 V with quiescent currents about one third of
those associated with the MC1741C (on a per amplifier basis). The
common mode input range includes the negative supply, thereby
eliminating the necessity for external biasing components in many
applications. The output voltage range also includes the negative
power supply voltage.
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MARKING
DIAGRAMS
14
14
1
Features
•
•
•
•
•
•
•
•
•
•
•
•
SOIC−14
D SUFFIX
CASE 751A
MC3x03DG
AWLYWW
1
Short Circuit Protected Outputs
Class AB Output Stage for Minimal Crossover Distortion
True Differential Input Stage
Single Supply Operation: 3.0 V to 36 V
Split Supply Operation: ±1.5 V to ±18 V
Low Input Bias Currents: 500 nA Max
Four Amplifiers Per Package
Internally Compensated
Similar Performance to Popular MC1741C
Industry Standard Pin−outs
ESD Diodes Added for Increased Ruggedness
Pb−Free Packages are Available
14
PDIP−14
P SUFFIX
CASE 646
14
MC3x03P
AWLYYWWG
1
x
= 3 or 4
A
= Assembly Location
WL = Wafer Lot
YY, Y = Year
WW = Work Week
G
= Pb−Free Package
1
PIN CONNECTIONS
Single Supply
3.0 V to 36 V
VCC
Split Supplies
Out 1 1
VCC
1
1
1.5 V to 18 V
2
Inputs 1
3
2
2
3
3
4
4
VEE, GND
VCC
1.5 V to 18 V
−
+
1
3
−
13
+
12
4
5
Inputs 2
VEE
14 Out 4
6
Inputs 4
11
+
2
−
4 +
−
Out 2 7
VEE/GND
10
Inputs 3
9
8
Out 3
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
October, 2006 − Rev. 10
1
Publication Order Number:
MC3403/D
MC3403, MC3303
ORDERING INFORMATION
Device
Shipping †
Package
MC3303D
SOIC−14
MC3303DG
SOIC−14
(Pb−Free)
MC3303DR2
SOIC−14
MC3303DR2G
SOIC−14
(Pb−Free)
MC3303P
PDIP−14
MC3303PG
PDIP−14
(Pb−Free)
MC3403D
SOIC−14
MC3403DG
SOIC−14
(Pb−Free)
MC3403DR2
SOIC−14
MC3403DR2G
SOIC−14
(Pb−Free)
MC3403P
PDIP−14
MC3403PG
PDIP−14
(Pb−Free)
55 Units / Rail
2500 Tape & Reel
25 Units / Rail
55 Units / Rail
2500 Tape & Reel
25 Units / Rail
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MAXIMUM RATINGS
Rating
Symbol
Value
VCC
VCC, VEE
36
±18
Input Differential Voltage Range (Note 1)
VIDR
±36
Vdc
Input Common Mode Voltage Range (Notes 1 and 2)
VICR
±18
Vdc
Storage Temperature Range
Tstg
−55 to +125
°C
Power Supply Voltages
Single Supply
Split Supplies
Operating Ambient Temperature Range
MC3303
MC3403
Junction Temperature
TA
TJ
−40 to +85
0 to +70
150
Unit
Vdc
°C
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Split power supplies.
2. For supply voltages less than ±18 V, the absolute maximum input voltage is equal to the supply voltage.
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2
MC3403, MC3303
ELECTRICAL CHARACTERISTICS
(VCC = +15 V, VEE = −15 V for MC3403; VCC = +14 V, VEE = GND for MC3303 TA = 25°C, unless otherwise noted.)
MC3403
MC3303
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
Input Offset Voltage
TA = Thigh to Tlow (Note 3)
VIO
−
−
2.0
−
10
12
−
−
2.0
−
8.0
10
mV
Input Offset Current
TA = Thigh to Tlow
IIO
−
−
30
−
50
200
−
−
30
−
75
250
nA
20
15
200
−
−
−
20
15
200
−
−
−
Characteristic
Large Signal Open Loop Voltage Gain
VO = ±10 V, RL = 2.0 k
TA = Thigh to Tlow
AVOL
V/mV
Input Bias Current
TA = Thigh to Tlow
IIB
−
−
−200
−
−500
−800
−
−
−200
−
−500
−1000
nA
Output Impedance f = 20 Hz
zo
−
75
−
−
75
−
Input Impedance f = 20 Hz
zi
0.3
1.0
−
0.3
1.0
−
M
Output Voltage Range
RL = 10 k
RL = 2.0 k
RL = 2.0 k, TA = Thigh to Tlow
VO
±12
±10
±10
±13.5
±13
−
−
−
−
12
10
10
12.5
12
−
−
−
−
V
Input Common Mode Voltage Range
VICR
+13 V
−VEE
+13 V
−VEE
−
+12 V
−VEE
+12.5 V
−VEE
−
V
Common Mode Rejection RS ≤ 10 k
CMR
70
90
−
70
90
−
dB
Power Supply Current (VO = 0) RL = ∞
ICC, IEE
−
2.8
7.0
−
2.8
7.0
mA
ISC
±10
±20
±45
±10
±30
±45
mA
Positive Power Supply Rejection Ratio
PSRR+
−
30
150
−
30
150
V/V
Negative Power Supply Rejection Ratio
PSRR−
−
30
150
−
30
150
V/V
Average Temperature Coefficient of Input
Offset Current
TA = Thigh to Tlow
IIO/T
−
50
−
−
50
−
pA/°C
Average Temperature Coefficient of Input
Offset Voltage
TA = Thigh to Tlow
VIO/T
−
10
−
−
10
−
V/°C
Power Bandwidth
AV = 1, RL = 10 k VO = 20 V(p−p), THD = 5%
BWp
−
9.0
−
−
9.0
−
kHz
Small−Signal Bandwidth
AV = 1, RL = 10 k VO = 50 mV
BW
−
1.0
−
−
1.0
−
MHz
Slew Rate AV = 1, Vi = −10 V to +10 V
SR
−
0.6
−
−
0.6
−
V/s
Rise Time AV = 1, RL = 10 k VO = 50 mV
tTLH
−
0.35
−
−
0.35
−
s
Fall Time AV = 1, RL = 10 k VO = 50 mV
tTLH
−
0.35
−
−
0.35
−
s
Overshoot AV = 1, RL = 10 k VO = 50 mV
os
−
20
−
−
20
−
%
Phase Margin AV = 1, RL = 2.0 k, VO = 200 pF
m
−
60
−
−
60
−
°
−
−
1.0
−
−
1.0
−
%
Individual Output Short−Circuit Current (Note 4)
Crossover Distortion
(Vin = 30 mVpp,Vout= 2.0 Vpp, f = 10 kHz)
3. MC3303: Tlow = −40°C, Thigh = +85°C, MC3403: Tlow = 0°C, Thigh = +70°C
4. Not to exceed maximum package power dissipation.
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3
MC3403, MC3303
ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, VEE = GND, TA = 25°C, unless otherwise noted.)
MC3403
MC3303
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
Input Offset Voltage
VIO
−
2.0
10
−
−
10
mV
Input Offset Current
IIO
−
30
50
−
−
75
nA
Input Bias Current
IIB
−
−200
−500
−
−
−500
nA
Large Signal Open Loop Voltage Gain
RL = 2.0 k
AVOL
10
200
−
10
200
−
V/mV
Power Supply Rejection Ratio
PSRR
−
−
150
−
−
150
V/V
3.3
VCC−2.0
3.5
VCC−1.7
−
−
3.3
VCC−2.0
3.5
VCC−1.7
−
−
Characteristic
Output Voltage Range (Note 5)
RL = 10 k, VCC = 5.0 V
RL = 10 k, 5.0 ≤ VCC ≤ 30 V
VOR
Power Supply Current
ICC
−
2.5
7.0
−
2.5
7.0
mA
Channel Separation
f = 1.0 kHz to 20 kHz
(Input Referenced)
CS
−
−120
−
−
−120
−
dB
5. Output will swing to ground with a 10 k pull down resistor.
Output
Q19
VCC
Q18
Q27
Q20
Q17
Q23
Q16
40 k
5.0 pF
Q29
31k
Q28
Q1
+
Q22
Q24
Q2
Q6
Q5
Q3
Q4
Q13
37 k
Q25
Q21
Q15
2.0 k
Q9
Inputs
−
Bias Circuitry
Common to Four
Amplifiers
Q12
Q10
Q7
60 k
Q11
25
Q30
2.4 k
Q8
VEE (GND)
Figure 1. Representative Schematic Diagram
(1/4 of Circuit Shown)
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4
Vpp
MC3403, MC3303
CIRCUIT DESCRIPTION
5.0 V/DIV
stage performs not only the first stage gain function but also
performs the level shifting and Transconductance reduction
functions. By reducing the Transconductance, a smaller
compensation capacitor (only 5.0 pF) can be employed, thus
saving chip area. The Transconductance reduction is
accomplished by splitting the collectors of Q24 and Q22.
Another feature of this input stage is that the input common
mode range can include the negative supply or ground, in
single supply operation, without saturating either the input
devices or the differential to single−ended converter. The
second stage consists of a standard current source load
amplifier stage.
The output stage is unique because it allows the output to
swing to ground in single supply operation and yet does not
exhibit any crossover distortion in split supply operation.
This is possible because Class AB operation is utilized.
Each amplifier is biased from an internal voltage regulator
which has a low temperature coefficient, thus giving each
amplifier good temperature characteristics as well as
excellent power supply rejection.
20 s/DIV
Figure 2. Inverter Pulse Response
The MC3403/3303 is made using four internally
compensated, two−stage operational amplifiers. The first
stage of each consists of differential input device Q24 and
Q22 with input buffer transistors Q25 and Q21 and the
differential to single ended converter Q3 and Q4. The first
120
50 mV/DIV
0.5 V/DIV
A VOL , LARGE SIGNAL
OPEN LOOP VOLTAGE GAIN (dB)
AV = 100
80
60
40
20
0
−20
*Note Class A B output stage produces distortion less sinewave.
VCC = 15 V
VEE = −15 V
TA = 25°C
100
1.0
10
50 s/DIV
Figure 3. Sine Wave Response
VO, OUTPUT VOLTAGE RANGE (V pp)
VO, OUTPUT VOLTAGE (Vpp )
+15 V
−
20
VO
+
−15 V
10 k
15
10
5.0
TA = 25°C
0
−5.0
1.0 k
100 k
1.0 M
Figure 4. Open Loop Frequency Response
30
25
100
1.0 k
10 k
f, FREQUENCY (Hz)
10 k
100 k
f, FREQUENCY (Hz)
20
10
0
1.0 M
TA = 25°C
30
0
Figure 5. Power Bandwidth
2.0
4.0
6.0 8.0 10
12
14
16
18
VCC AND (VEE), POWER SUPPLY VOLTAGES (V)
20
Figure 6. Output Swing versus Supply Voltage
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5
MC3403, MC3303
I IB, INPUT BIAS CURRENT (nA)
I IB , INPUT BIAS CURRENT (nA)
VCC = 15 V
VEE = −15 V
TA = 25°C
300
200
100
−75 −55
−35
−15
5.0
25
45
65
85
170
160
150
105 125
0
2.0
4.0
6.0
8.0
10
12
14
16
18
T, TEMPERATURE (°C)
VCC AND (VEE), POWER SUPPLY VOLTAGES (V)
Figure 7. Input Bias Current
versus Temperature
Figure 8. Input Bias Current
versus Supply Voltage
VCC
50 k
1N914
VCC
10 k
R2
−
5.0 k
1/2
MC3403
+
1N914
VCC
10 k
VO
Vref
−
1/2
MC3403
+
10 k
R1
fo =
1
Vref = VCC
2
R1
VO = R1 +R2
R
VO =
R
1
V
2 CC
Figure 9. Voltage Reference
+
e1
1/2
1
R
C
e2
Hysteresis
R2
VOH
Vref
−
1/2
MC3403
+
− 1/2
MC3403
+
For: fo = 1.0 kHz
R = 16 k
C = 0.01 F
C
R
a R1
b R1
C
1
2RC
Figure 10. Wien Bridge Oscillator
MC3403
−
R1
VO
R1
1/2
MC3403
+
Vin
eo
−
VO
VO
VOL
VinL
R1
VinL=
(VOL −Vref) +Vref
R1 +R2
1
R
C
VinH=
R1
(VOH −Vref) +Vref
R1 +R2
Vh=
R1
(VOH −VOL)
R1 +R2
R
eo = C (1 +a +b) (e2 −e1)
Figure 11. High Impedance Differential
Amplifier
Figure 12. Comparator with Hysteresis
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6
VinH
Vref
20
MC3403, MC3303
R
R
C1
Vin
100 k
C
R2
−
fo =
R1 = QR
C
1/2
−
MC3403
+
100 k
1/2
1/2
MC3403
+
Vref
R1
R2
Bandpass
Output
= 1.0 kHz
= 10
=1
=1
Where:
−
1
V
2 CC
R = 160 k
C = 0.001 F
R1 = 1.6 M
R2 = 1.6 M
R3 = 1.6 M
C1
Notch Output
MC3403
+
TBP = center frequency gain
TN = passband notch gain
Vref =
Vref
R3
1/2
For: fo
Q
TBP
TN
R2 = R1
TBP
R3 = TNR2
C1 = 10 C
−
MC3403
+
Vref
1
2RC
Vref
Figure 13. Bi−Quad Filter
VCC
C
R1
Vin
Vref =
1/2
R2
Triangle Wave
Output
Vref
300 k
Given:
R3
1/2
+
MC3403
−
75 k
R1
100 k
Vref
C
1/2
MC3403
−
Square Wave
Output
R1 +RC
4 CRf R1
if R3 =
CO = 10 C
Vref =
1
V
2 CC
fo = center frequency
A(fo) = gain at center frequency
Choose value fo, C
Then:
R3 =
Q
fo C
R1 =
R3
2 A(fo)
R2 =
R1 R5
4Q2 R1 −R5
Oo fo
For less than 10% error from operational amplifier
< 0.1
BW
where fo and BW are expressed in Hz.
If source impedance varies, filter may be preceded with
voltage follower buffer to stabilize filter parameters.
Rf
f=
VO
MC3403
+
R2
Vref
CO
−
1
V
2 CC
+
C
R3
R2 R1
R2 +R1
Figure 14. Function Generator
Figure 15. Multiple Feedback Bandpass Filter
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7
MC3403, MC3303
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−A−
14
8
−B−
P 7 PL
0.25 (0.010)
M
7
1
G
−T−
D 14 PL
0.25 (0.010)
T B
S
A
DIM
A
B
C
D
F
G
J
K
M
P
R
J
M
K
M
F
R X 45 _
C
SEATING
PLANE
B
M
S
SOLDERING FOOTPRINT*
7X
7.04
14X
1.52
1
14X
0.58
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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8
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0_
7_
0.228 0.244
0.010 0.019
MC3403, MC3303
PACKAGE DIMENSIONS
PDIP−14
CASE 646−06
ISSUE P
14
8
1
7
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
A
F
L
N
C
−T−
SEATING
PLANE
H
G
D 14 PL
J
K
0.13 (0.005)
M
DIM
A
B
C
D
F
G
H
J
K
L
M
N
INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.290
0.310
−−−
10 _
0.015
0.039
MILLIMETERS
MIN
MAX
18.16
19.56
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.37
7.87
−−−
10 _
0.38
1.01
M
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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MC3403/D
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