ICST ICS91719YGLF-T Low emi, spread modulating, clock generator Datasheet

ICS91719
Integrated
Circuit
Systems, Inc.
Low EMI, Spread Modulating, Clock Generator
Features:
•
ICS91719 is a Spread Spectrum Clock targeted for
Mobile PC and LCD panel applications. Generates an
EMI optimized clock signal (EMI peak reduction of 714 dB on 3rd-19th harmonics) through use of Spread
Spectrum techniques.
•
ICS91719 focuses on the lower input frequency
range of 14.318 to 80.00 MHz with a spread
modulation of 20kHz to 40kHz.
Pin Configuration
GND
X1 _CLKIN
X2
GNDA
VDDA
VDD
GND
Specifications:
•
Supply Voltages: VDD = 3.3V ±0.3V
•
Frequency range: 14.318 MHz ≤ Fin ≥ 80 MHz
•
Cyc to Cyc jitter: <150ps
•
Output duty cycle 40/60% (worst case)
•
Guarantees +85°C operational condition.
•
16-pin TSSOP package 4.4mm body (173mils), 0.65
mm pitch
•
14.318 MHz crystal input or reference clock input
•
27MHz, 48MHz and 66MHz reference clock input
Input Select Functionality
FS_IN1 FS_IN0 MHZ
0
0
1
1
0
1
0
1
14.318 in 27.00 out
14.318 in/out
27.00 in/out
48.00 in/out
66.66 in/out
* * CLKOUT/FS_IN0
PD#
REF_STOP
SD A
SDAT
SCLK
FS_IN0:1
0506D—08/16/04
VDDREF
VDDREF_SEL_2.5V/3.3V# ^
REF_OUT/VDDREF_SEL_1.8V * *
**REF_Stop
^PD#
SCLK
SDATA
^SPREAD_ENABLE/FS_IN1
16-pin TSSOP
** Internal pull-down
^ Internal pull-up
Default Spread %
-0.8% downspread
-0.8% downspread
-0.8% downspread
-0.8% downspread
REF Voltage Select Functionality
REFOUT
SPREAD#
16
15
14
13
12
11
10
9
Notes:
Block Diagram
CLKIN
1
2
3
4
5
6
7
8
PLL1
Spread
Spectrum
Spectr
um
Control
Logic
Config.
Reg.
CLKOUT
CLK
OUT
Pin14
Pin15
REF Voltage
0
0
1
1
0
1
0
1
N/A
1.8V
2.5V
3.3V
ICS91719
Pin Descriptions
PIN #
PIN NAME
1
2
3
4
5
6
7
10
11
12
13
GND
X1 _CLKIN
X2
GNDA
VDDA
VDD
GND
CLKOUT
FS_IN0
^SPREAD_ENABLE
FS_IN1
SDATA
SCLK
^PD#
**REF_Stop
14
REF_OUT/VDDREF_SEL_1.8V * *
15
16
VDDREF_SEL_2.5V/3.3V# ^
VDDREF
8
9
PIN TYPE
PWR
IN
OUT
PWR
PWR
PWR
PWR
OUT
IN
IN
IN
IN
IN
IN
IN/OUT
PWR
PWR
DESCRIPTION
Ground pin for 3V outputs
Crystal input or CLOCKIN input
Crystal output
Analog ground
Analog power supply for 3V
Power supply for 3V
Ground pin for 3V outputs
Modulated clock output
Latched input for input frequency select
Spread enable pin
Latched input for input frequency select
Data pin for I2C circuitry 5V tolerant
Clock pin for I2C circuitry 5V tolerant
Power down
Stop control for REF_CLOCK output STOP:1, RUNNING:0
REF_CLOCK output
REF_CLOCK power supply voltage select
Power supply for REF_CLOCK
^internal pull-up
**internal pull-down
0506D—08/16/04
2
ICS91719
Table 1: Frequency Configuration Table
(See I2C Byte 0)
FS4 FS3 FS2 FS1 FS0 Sprd Type Sprd %
14in/27out
14in/14ou
t
27in/27ou
t
48in/48ou
t
66in/66ou
t
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
DOWN
1
0
1 SPREAD
(-)
0
1
Center
0
1 Spread (+/-)
0
1
0
DOWN
1
0
SPREAD
1
(-)
0
1
0
1
0
1 CENTER
0 SPREAD
1
(+/-)
0
1
0
DOWN
1
0
1 SPREAD
(-)
0
1
Center
0
1 Spread (+/-)
0.60
0.80
1.00
1.25
1.50
2.00
0.50
1.00
0.60
0.80
1.00
1.25
1.50
1.75
2.00
2.50
3.00
0.30
0.40
0.50
0.70
1.00
1.20
1.50
0.60
0.80
1.00
1.25
1.50
2.00
0.50
1.00
0506D—08/16/04
3
ICS91719
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
How to Read:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller
Controller
ICS clock
Controller
ICS clock
Controller
ICS clock
Controller
(host) sends a start bit.
(host) sends the write address D2 (H)
will acknowledge
(host) sends a dummy command code
will acknowledge
(host) sends a dummy byte count
will acknowledge
(host) starts sending first byte (Byte 0)
through byte 6
ICS clock will acknowledge each byte one at a
time.
Controller (host) sends a Stop bit
•
How to Write:
Controller (Host)
Start Bit
Address
D2(H)
Controller (host) will send start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 7
Controller (host) will need to acknowledge each
byte
Controller (host) will send a stop bit
How to Read:
Controller (Host)
Start Bit
Address
D3(H)
ICS (Slave/Receiver)
ICS (Slave/Receiver)
ACK
Byte Count
ACK
Dummy Command Code
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Stop Bit
Byte 0
Dummy Byte Count
Byte 0
Byte 1
Byte 2
Byte 1
Byte 3
Byte 2
Byte 4
Byte 3
Byte 5
Byte 4
Byte 6
Byte 5
Byte 7
Byte 6
Byte 7
ACK
Stop Bit
Notes:
1.
2.
3.
4.
5.
6.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller.
The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any
complete byte has been transferred. The Command code and Byte count shown above must be sent, but the
data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
0506D—08/16/04
4
ICS91719
BYTE
0
Affected Pin
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
-
TYPE
Byte 0:
Control Function
FS0
FS1
FS2
FS3
Spread/FS0
Spread/FS1
Spread/FS2
Spread/FS3
Bit 3
Bit 2
Bit 1
FS4
PD# Tri_Sate
Spread Enable
Bit 0
HW/SW Control
FS4
PD# Tri_Sate
Spread Enable
Spread Spectrum Control
FS 3:4 Hard/Software
Select
Bit Control
0
1
PWD
RW
RW
RW
R
R/R
W
RW
RW
1
0
0
0
Hi-Z
OFF
LOW
ON
0
1
1
RW
HW
SW
0
BYTE
1
Pin #
Bit 7
Bit 6
-
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Affected Pin
Name
TYPE
Byte 1:
Control Function
Reserved
SLEW
Reserved
Slew Rate REF-OUT
FS-IN_1 Readback
FS-IN_0 Readback
SLEW
CLK_OUT_Enable
REF_OUT_Enable
Reserved
FS-IN_1 Readback
FS-IN_0 Readback
Slew Rate CLK-OUT
CLK_OUT_Enable
REF_OUT_Enable
Reserved
Bit Control
0
1
R
RW Nominal Fast
Not
RW Freerun Freerun
RW Nominal Fast
RW Nominal Fast
RW Disable Enable
RW Disable Enable
R
-
PWD
1
1
1
1
1
1
1
1
BYTE
2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Affected Pin
Pin #
Name
x
x
x
x
x
x
x
x
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Control Function
TYPE
Byte 2:
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RW
RW
RW
RW
RW
RW
RW
0506D—08/16/04
5
Bit Control
0
1
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
PWD
1
1
1
1
1
1
1
1
ICS91719
BYTE
3
Pin #
Affected Pin
Name
Control Function
Bit 7
Bit 6
X
RESERVED
RESERVED
RESERVED
RESERVED
Bit 5
X
RESERVED
RESERVED
Bit 4
X
RESERVED
RESERVED
Bit 3
Bit 2
Bit 1
Bit 0
x
X
X
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
X
X
TYPE
Byte 3:
Bit Control
0
1
RW Disable Enable
RW Disable Enable
Not
RW Freerun Freerun
Not
RW Freerun Freerun
Not
RW Freerun Freerun
RW Disable Enable
RW Disable Enable
RW Disable Enable
PWD
1
1
1
1
1
1
1
1
BYTE
4
Pin #
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
X
Affected Pin
Name
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Control Function
TYPE
Byte 4:
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RW
RW
RW
RW
RW
RW
RW
RW
Bit Control
0
1
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
PWD
1
1
1
1
1
1
1
1
BYTE
5
Pin #
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
X
Affected Pin
Name
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Control Function
TYPE
Byte 5:
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RW
RW
RW
RW
0506D—08/16/04
6
Bit Control
0
1
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
PWD
1
1
1
1
1
1
1
1
ICS91719
BYTE
6
Pin #
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
X
X
Affected Pin
Name
Revision ID Bit 3
Revision ID Bit 2
Revision ID Bit 1
Revision ID Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
Control Function
TYPE
Byte 6:
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
R
R
R
R
R
R
R
R
0506D—08/16/04
7
Bit Control
0
1
-
-
PWD
1
1
1
1
1
1
1
1
ICS91719
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage on any pin with respect to GND . . .
Storage Temperature . . . . . . . . . . . . . . . . . . . .
Operating Temperature . . . . . . . . . . . . . . . . . .
Ambient Operating Temperature under Bias .
Power Dissipation . . . . . . . . . . . . . . . . . . . . . .
3.3 V
-0.5 to +7.0 V
–55°C to +125°C
0°C to +85°C
-55 to +125 °C
0.5 W
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
T A = 0 - 85°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
SYMBOL
V IH
V IL
I IH
I IL1
Powerdown Current
Input Frequency
Input Crystal Frequency
Input Clock Frequency
Pin Inductance
Input Capacitance1
I DD3.3PD
Fi
F CY I
F CLK I
Lpin
C IN
C OUT
C INX
Transition time 1
Settling time1
Clk Stabilization 1
Ttrans
Ts
T STAB
t PZH,t PZL
Delay 1
1
CONDITIONS
V IN = V DD
V IN = 0 V; Inputs with no pull-up resistors
MIN
2
V SS - 0.3
-5
-5
V DD = 3.3 V
Logic Inputs
Output pin capacitance
X1 & X2 pins
To 1st crossing of target frequency
From 1st crossing to 1% target frequency
From V DD = 3.3 V to 1% target frequency
Output enable delay (all outputs)
Guaranteed by design, not 100% tested in production.
0506D—08/16/04
8
27
TYP
3
5
14.318
14.318 Typ + 10%
80
7
5
6
36
45
1
1
MAX
V DD + 0.3
0.8
5
3
3
3
10
UNITS
V
V
mA
mA
mA
MHz
MHz
MHz
nH
pF
pF
pF
ms
ms
ms
ns
ICS91719
Electrical Characteristics - CPU
TA = 0 - 85°C; VDD = 3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
Output High Voltage
VOH3
IOH = -1 mA
Output Low Voltage
VOL3
IOL = 1 mA
Rise Time
tr3
VOL = 0.41V, VOH = 0.86V
Fall Time
tf3
VOH = 0.86V VOL = 0.41V
measurement from differential waveform dt3
Duty Cycle
0.35V to +035V
VT = 50%
tjcyc-cyc1
Jitter, Cycle to cycle
1
2
MIN
2.4
TYP
MAX
UNITS
V
0.5
0.5
0.7
0.8
0.4
1
1
ns
ns
45
51
55
%
76
150
ps
MIN
TYP
MAX
20
2.4
48
60
1.25
1.3
0.4
-23
27
2
2
UNITS
MHz
Ω
V
V
mA
mA
ns
ns
53
170
55
300
%
ps
Guaranteed by design, not 100% tested in production.
IOWT can be varied and is selectable thru the MULTSEL pin.
Electrical Characteristics - REF
TA = 0 - 85°C; VDD = 3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
Output Frequency
FO1
Output Impedance
RDSP11
VO = VDD*(0.5)
1
IOH = -1 mA
Output High Voltage
VOH
1
IOL = 1 mA
Output Low Voltage
VOL
V OH@MIN = 1.0 V, V OH@MAX = 3.135 V
Output High Current
IOH1
1
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V
Output Low Current
IOL
1
VOL = 0.4 V, VOH = 2.4 V
Rise Time
tr1
1
VOH = 2.4 V, VOL = 0.4 V
Fall Time
tf1
Duty Cycle
Jitter
1
dt11
tjcyc-cyc1
VT = 1.5 V
VT = 1.5 V
-29
29
1
1
45
Guaranteed by design, not 100% tested in production.
0506D—08/16/04
9
ICS91719
c
N
L
E1
INDEX
AREA
E
1 2
α
D
A
A2
4.40 mm. Body, 0.65 mm. Pitch TSSOP
(173 mil)
(25.6 mil)
In Millimeters
In Inches
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
MAX
MIN
MAX
A
-1.20
-.047
A1
0.05
0.15
.002
.006
A2
0.80
1.05
.032
.041
b
0.19
0.30
.007
.012
c
0.09
0.20
.0035
.008
D
SEE VARIATIONS
SEE VARIATIONS
E
6.40 BASIC
0.252 BASIC
E1
4.30
4.50
.169
.177
e
0.65 BASIC
0.0256 BASIC
L
0.45
0.75
.018
.030
N
SEE VARIATIONS
SEE VARIATIONS
a
0°
8°
0°
8°
aaa
-0.10
-.004
A1
VARIATIONS
-Ce
N
SEATING
PLANE
b
aaa C
16
D mm.
MIN
4.90
D (inch)
MAX
5.10
Reference Doc.: JEDEC Publication 95, MO-153
10-0035
4.40mm Body, .65mm pitch
Ordering Information
ICS91719yGLF-T
Example:
ICS XXXX y G LF- T
Designation for tape and reel packaging
Lead Free (Optional)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0506D—08/16/04
10
MIN
.193
MAX
.201
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