Intersil CD40175BMS Cmos quad â dâ type flip-flop Datasheet

CD40175BMS
CMOS Quad ‘D’ Type Flip-Flop
December 1992
Features
Pinout
• High Voltage Type (20V Rating)
CD40175BMS
TOP VIEW
• Output Compatible with Two HTL Loads, Two Low Power
TTL Loads, or One Low Power Schottky TTL Load
16 VDD
CLEAR 1
• Functional Equivalent to TTL74175
Q1 2
15 Q4
• 100% Tested for Quiescent Current at 20V
Q1 3
14 Q4
• 5V, 10V and 15V Parametric Ratings
D1 4
13 D4
• Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC
D2 5
12 D3
Q2 6
11 Q3
Q2 7
10 Q3
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
9 CLOCK
VSS 8
VDD = PIN 16
VSS = PIN 8
• Standardized Symmetrical Output Characteristics
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Functional Diagram
Applications
D1
• Shift Registers
2
4
F/F1
3
Q1
Q1
• Buffer/Storage Registers
• Pattern Generators
D2
7
5
F/F2
6
Description
CD40175BMS consists of four identical D-type flip-flops.
Each flip-flop has an independent DATA D input and complementary Q and Q outputs. The CLOCK and CLEAR inputs
are common to all flip-flops. Data are transferred to the Q
outputs on the positive going transition of the clock pulse. All
four flip-flops are simultaneously reset by a low level on the
CLEAR input.
These devices can function as shift register elements or as
T-type flip-flops for toggle and counter applications.
D3
10
12
F/F3
D4
15
13
F/F4
CLOCK
CLEAR
11
14
Q2
Q2
Q3
Q3
Q4
Q4
9
1
VSS = 8
VDD = 16
The CD40175BMS is supplied in these 16-lead outline
packages:
Braze Seal DIP
Ceramic Flatpack
H4T
H6W
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1392
File Number
3360
Specifications CD40175BMS
Absolute Maximum Ratings
Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
Thermal Resistance
θja
θjc
Ceramic DIP and FRIT Package . . . . . 80oC/W
20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70oC/W
20oC/W
Maximum Package Power Dissipation (PD) at +125oC
For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS (NOTE 1)
VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
Input Leakage Current
IIL
VIN = VDD or GND
VDD = 20
VDD = 18V
Input Leakage Current
IIH
VIN = VDD or GND
VDD = 20
VDD = 18V
Output Voltage
Output Voltage
VOL15
VOH15
VDD = 15V, No Load
VDD = 15V, No Load (Note 3)
LIMITS
GROUP A
SUBGROUPS
TEMPERATURE
MIN
MAX
UNITS
1
+25oC
-
2
µA
2
+125oC
-
200
µA
3
-55oC
-
2
µA
1
+25oC
-100
-
nA
2
+125oC
-1000
-
nA
3
-55oC
-100
-
nA
1
+25oC
-
100
nA
2
+125oC
-
1000
nA
3
-55oC
-
100
nA
1, 2, 3
+25oC,
+125oC,
-55oC
-
50
mV
1, 2, 3
+25oC,
+125oC,
-55oC
14.95
-
V
Output Current (Sink)
IOL5
VDD = 5V, VOUT = 0.4V
1
+25oC
0.53
-
mA
Output Current (Sink)
IOL10
VDD = 10V, VOUT = 0.5V
1
+25oC
1.4
-
mA
1
+25oC
3.5
-
mA
1
+25oC
-
-0.53
mA
Output Current (Sink)
Output Current (Source)
IOL15
IOH5A
VDD = 15V, VOUT = 1.5V
VDD = 5V, VOUT = 4.6V
Output Current (Source)
IOH5B
VDD = 5V, VOUT = 2.5V
1
+25oC
-
-1.8
mA
Output Current (Source)
IOH10
VDD = 10V, VOUT = 9.5V
1
+25oC
-
-1.4
mA
1
+25oC
-
-3.5
mA
1
+25oC
-2.8
-0.7
V
VSS = 0V, IDD = 10µA
1
+25oC
0.7
2.8
V
VDD = 2.8V, VIN = VDD or GND
7
+25oC
VDD = 20V, VIN = VDD or GND
7
+25oC
VDD = 18V, VIN = VDD or GND
8A
+125oC
VDD = 3V, VIN = VDD or GND
8B
-55oC
Output Current (Source)
N Threshold Voltage
P Threshold Voltage
Functional
IOH15
VNTH
VPTH
F
VDD = 15V, VOUT = 13.5V
VDD = 10V, ISS = -10µA
VOH > VOL <
VDD/2 VDD/2
V
Input Voltage Low
(Note 2)
VIL
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
+25oC, +125oC, -55oC
-
1.5
V
Input Voltage High
(Note 2)
VIH
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
+25oC, +125oC, -55oC
3.5
-
V
Input Voltage Low
(Note 2)
VIL
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25oC, +125oC, -55oC
-
4
V
Input Voltage High
(Note 2)
VIH
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25oC, +125oC, -55oC
11
-
V
NOTES: 1. All voltages referenced to device GND, 100% testing being
implemented.
2. Go/No Go test with limits applied to inputs.
7-1393
3. For accuracy, voltage is measured differentially to VDD. Limit
is 0.050V max.
Specifications CD40175BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Propagation Delay
Clock to Q Output
Propagation Delay
Clear to Q Output
Transition Time
Maximum Clock Input
Frequency
SYMBOL
TPHL1
TPLH1
TPHL2
CONDITIONS (NOTES 1, 2)
GROUP A
SUBGROUPS TEMPERATURE
VDD = 5V, VIN = VDD or GND
9
10, 11
VDD = 5V, VIN = VDD or GND
9
10, 11
TTHL
TTLH
VDD = 5V, VIN = VDD or GND
9
10, 11
FCL
VDD = 5V, VIN = VDD or GND
9
10, 11
+25oC
+125oC,
-55oC
+25oC
+125oC,
-55oC
+25oC
+125oC,
-55oC
+25oC
+125oC,
-55oC
LIMITS
MIN
MAX
UNITS
-
400
ns
-
540
ns
-
500
ns
-
675
ns
-
200
ns
-
270
ns
2
-
MHz
1.48
-
MHz
MIN
MAX
UNITS
-
1
µA
-
30
µA
-
2
µA
-
60
µA
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
NOTES
VDD = 5V, VIN = VDD or GND
1, 2
TEMPERATURE
-55oC,
+25oC
+125oC
VDD = 10V, VIN = VDD or GND
1, 2
-55oC,
+25oC
+125oC
VDD = 15V, VIN = VDD or GND
Output Voltage
VOL
VDD = 5V, No Load
1, 2
1, 2
-
2
µA
+125oC
-
120
µA
+25oC, +125oC,
-
50
mV
-55oC,
+25oC
-55oC
Output Voltage
VOL
VDD = 10V, No Load
1, 2
+25oC, +125oC,
-55oC
-
50
mV
Output Voltage
VOH
VDD = 5V, No Load
1, 2
+25oC, +125oC,
-55oC
4.95
-
V
Output Voltage
VOH
VDD = 10V, No Load
1, 2
+25oC, +125oC,
-55oC
9.95
-
V
Output Current (Sink)
IOL5
VDD = 5V, VOUT = 0.4V
1, 2
+125oC
0.36
-
mA
-55oC
0.64
-
mA
+125oC
0.9
-
mA
-55oC
1.6
-
mA
+125oC
2.4
-
mA
-55oC
4.2
-
mA
+125oC
-
-0.36
mA
-55oC
-
-0.64
mA
+125oC
-
-1.15
mA
-55oC
-
-2.0
mA
+125oC
-
-0.9
mA
-55oC
-
-1.6
mA
Output Current (Sink)
Output Current (Sink)
Output Current (Source)
Output Current (Source)
Output Current (Source)
IOL10
IOL15
IOH5A
IOH5B
IOH10
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
VDD = 5V, VOUT = 4.6V
1, 2
1, 2
1, 2
VDD = 5V, VOUT = 2.5V
1, 2
VDD = 10V, VOUT = 9.5V
7-1394
1, 2
Specifications CD40175BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
Output Current (Source)
Input Voltage Low
SYMBOL
IOH15
VIL
CONDITIONS
VDD =15V, VOUT = 13.5V
VDD = 10V, VOH > 9V, VOL < 1V
NOTES
TEMPERATURE
MIN
MAX
UNITS
1, 2
+125oC
-
-2.4
mA
-55oC
-
-4.2
mA
+25oC, +125oC,
-
3
V
1, 2
-55oC
Input Voltage High
VIH
Propagation Delay
Clock to Q Output
TPHL1
TPLH1
Propagation Delay
Clear to Q Output
Transition Time
Minimum Data Setup
Time
TPHL2
VDD = 10V, VOH > 9V, VOL < 1V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
TTHL
TTLH
TS
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
Minimum Data Hold Time
TH
VDD = 5V
VDD = 10V
VDD = 15V
Minimum Clear Pulse
Width
TW
VDD = 5V
VDD = 10V
VDD = 15V
Maximum Clock Rise or
Fall Time
TRCL
TFCL
VDD = 5V
VDD = 10V
VDD = 15V
Minimum Clear Removal
Time (Clear to be High
before Positive Transition
of Clock)
Minimum Clock Pulse
Width
TREM
VDD = 5V
VDD = 10V
VDD = 15V
TW
VDD = 5V
VDD = 10V
VDD = 15V
Input Capacitance
CIN
Any Input
1, 2
+25oC, +125oC,
-55oC
7
-
V
1, 2, 3
+25oC
-
160
ns
o
1, 2, 3
+25 C
-
120
ns
1, 2, 3
+25oC
-
200
ns
1, 2, 3
+25oC
-
150
ns
o
1, 2, 3
+25 C
-
100
ns
1, 2, 3
+25oC
-
80
ns
1, 2, 3
+25oC
-
120
ns
1, 2, 3
+25oC
-
50
ns
1, 2, 3
+25oC
-
40
ns
1, 2, 3
+25oC
-
80
ns
1, 2, 3
+25oC
-
40
ns
1, 2, 3
+25oC
-
30
ns
1, 2, 3
+25oC
-
200
ns
1, 2, 3
+25oC
-
80
ns
1, 2, 3
+25oC
-
60
ns
1, 2, 3, 4
+25oC
15
-
µs
1, 2, 3, 4
+25oC
15
-
µs
1, 2, 3, 4
+25oC
15
-
µs
1, 2, 3
+25oC
-
250
ns
1, 2, 3
+25oC
-
100
ns
1, 2, 3
+25oC
-
80
ns
1, 2, 3
+25oC
-
250
ns
1, 2, 3
+25oC
-
100
ns
1, 2, 3
+25oC
-
75
ns
1, 2
+25oC
-
7.5
pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation
delay of the output of the driving stage for the estimated capacitive load.
7-1395
Specifications CD40175BMS
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
UNITS
IDD
VDD = 20V, VIN = VDD or GND
1, 4
+25oC
-
7.5
µA
1, 4
+25oC
-2.8
-0.2
V
VDD = 10V, ISS = -10µA
1, 4
+25oC
-
±1
V
VSS = 0V, IDD = 10µA
1, 4
+25oC
0.2
2.8
V
1, 4
+25oC
-
±1
V
1
+25oC
VOH >
VDD/2
VOL <
VDD/2
V
1, 2, 3, 4
+25oC
-
1.35 x
+25oC
Limit
ns
Supply Current
N Threshold Voltage
VNTH
N Threshold Voltage
Delta
∆VTN
P Threshold Voltage
VTP
P Threshold Voltage
Delta
∆VTP
Functional
F
VDD = 10V, ISS = -10µA
VSS = 0V, IDD = 10µA
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
Propagation Delay Time
TPHL
TPLH
VDD = 5V
3. See Table 2 for +25oC limit.
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC
PARAMETER
SYMBOL
DELTA LIMIT
Supply Current - MSI-1
IDD
± 0.2µA
Output Current (Sink)
IOL5
± 20% x Pre-Test Reading
IOH5A
± 20% x Pre-Test Reading
Output Current (Source)
TABLE 6. APPLICABLE SUBGROUPS
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Initial Test (Pre Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
100% 5004
1, 7, 9, Deltas
CONFORMANCE GROUP
PDA (Note 1)
Interim Test 3 (Post Burn-In)
100% 5004
1, 7, 9
100% 5004
1, 7, 9, Deltas
100% 5004
2, 3, 8A, 8B, 10, 11
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Sample 5005
1, 2, 3, 8A, 8B, 9
PDA (Note 1)
Final Test
Group A
Group B
Group D
READ AND RECORD
IDD, IOL5, IOH5A, RONDEL10
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
CONFORMANCE GROUPS
Group E Subgroup 2
TEST
READ AND RECORD
MIL-STD-883
METHOD
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
1, 9
Table 4
7-1396
Specifications CD40175BMS
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
Static Burn-In 1
(Note 1)
2, 3, 6, 7, 10, 11,
14, 15
1, 4, 5, 8, 9, 12, 13
16
Static Burn-In 2
(Note 1)
2, 3, 6, 7, 10, 11,
14, 15
8
1, 4, 5, 9, 12,
13, 16
Dynamic BurnIn (Note 1)
-
8
1, 16
2, 3, 6, 7, 10, 11,
14, 15
8
1, 4, 5, 9, 12,
13, 16
Irradiation
(Note 2)
9V ± -0.5V
50kHz
25kHz
2, 3, 6, 7, 10, 11,
14, 15
9
4, 5, 12, 13
NOTES:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V
Logic Diagram
CL
CL
p
n
p
n
VDD
D
*
CL
CL
Q
CL
CL
p
n
CLR
p
n
CL
*
VSS
Q
CL
1
*
CL
CLK
*
CL
ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION
NETWORK
9
FIGURE 1. 1 OF 4 FLIP-FLOPS
TRUTH TABLE FOR 1 OF 4 FLIP-FLOPS (Positive Logic)
INPUTS
CLOCK
X
OUTPUTS
DATA
CLEAR
Q
Q
0
1
0
1
1
1
1
0
X
1
Q
Q
X
0
0
1
1 = High level
X = Don’t care
0 = Low level
7-1397
CD40175BMS
400
AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) = +25oC
300
SUPPLY VOLTAGE (VDD) = 5V
250
200
150
10V
100
15V
50
0
0
10
20 30
40
70 80
50 60
LOAD CAPACITANCE (CL) (pF)
80
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
25
20
10V
10
5V
0
5
10
15
FIGURE 4. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
-5
-15
-20
-25
-15V
40
60
80
100
LOAD CAPACITANCE (CL) (pF)
AMBIENT TEMPERATURE (TA) = +25oC
15.0
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
12.5
10.0
10V
7.5
5.0
2.5
5V
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
0
-10
-10V
20
FIGURE 5. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
-30
FIGURE 6. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
AMBIENT TEMPERATURE (TA) = +25oC
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
AMBIENT TEMPERATURE (TA) = +25oC
0
15V
50
0
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
10V
FIGURE 3. TYPICAL TRANSITION TIME AS A FUNCTION OF
LOAD CAPACITANCE
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
5
100
0
0
AMBIENT TEMPERATURE (TA) = +25oC
15
SUPPLY VOLTAGE (VDD) = 5V
150
100
FIGURE 2. TYPICAL PROPAGATION DELAY TIME (CLOCK TO
OUTPUT) AS A FUNCTION OF LOAD CAPACITANCE
30
200
0
0
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
-5
-10V
-15V
-10
-15
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
350
TRANSITION TIME (tTHL, tTLH) (ns)
PROPAGATION DELAY TIME (tPHL, tPLH) (ns)
Electrical Performance Characteristics
FIGURE 7. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
7-1398
CD40175BMS
POWER DISSIPATION PER FLIP-FLOP (PD) (µW)
Electrical Performance Characteristics
105
8
6
4
(Continued)
AMBIENT TEMPERATURE (TA) = +25oC
2
SUPPLY VOLTAGE (VDD) = 15V
104 8
6
4
5V
2
3
10 8
10V
6
4
2
102
8
6
4
CL = 50pF
CL = 15pF
2
10
2
1
4
68
2
4
68
2
4
68
2
10
102
103
CLOCK INPUT FREQUENCY (fCL) (kHz)
4
68
104
FIGURE 8. TYPICAL DYNAMIC POWER DISSIPATION AS A FUNCTION OF CLOCK FREQUENCY
Chip Dimensions and Pad Layout
Dimensions in parenthesis are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10-3 inch).
METALLIZATION:
PASSIVATION:
Thickness: 11kÅ − 14kÅ,
AL.
10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
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