AMD AM188

Am186 ER and Am188 ER
TM
TM
High-Performance, 80C186- and 80C188-Compatible,
16-Bit Embedded Microcontrollers with RAM
DISTINCTIVE CHARACTERISTICS
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E86TM
family 80C186- and 80C188-compatible
microcontrollers with enhanced bus interface
— Lower system cost with high performance
— 3.3-V ± 0.3-V operation with 5-V tolerant I/O
Memory integration
— 32 Kbyte of internal SRAM
— Internal SRAM provides same performance as
zero-wait-state external memory
High performance
— 25-, 33-, 40- and 50-MHz operating frequencies
— Supports zero-wait-state operation at 50 MHz
with 55-ns external memory
— 1-Mbyte memory address space
— 64-Kbyte I/O space
Enhanced features provide faster access to
memory and various clock input modes
— Nonmultiplexed address bus provides glueless
interface to external RAM and ROM
— Phase-locked loop (PLL) enables processor to
operate at up to four times clock input frequency
Enhanced integrated peripherals
— Thirty-two programmable I/O (PIO) pins
— Asynchronous serial port allows full-duplex, 7-bit
or 8-bit data transfers
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GENERAL DESCRIPTION
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The Am186TMER and Am188TMER microcontrollers are
par t of the AMD E86™ family of embedded
microcontrollers and microprocessors based on the
x86 architecture. The Am186ER and Am188ER
microcontrollers are the ideal upgrade for designs
requiring 80C186/80C188 microcontroller
c o m p a t i b i l i t y, i n c r e a s e d p e r f o r m a n c e, s e r i a l
communications, a direct bus interface, and integrated
memory.
The Am186ER and Am188ER microcontrollers
integrate memory and the functions of the CPU,
nonmultiplexed address bus, timers, chip selects,
interrupt controller, DMA controller, PSRAM controller,
w a t c h d o g t i m e r, a s y n c h r o n o u s s e r i a l p o r t ,
synchronous serial interface, and programmable I/O
© Copyright 2000 Advanced Micro Devices, Inc. All rights reserved.
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— DMA to and from asynchronous serial port
— Synchronous serial interface allows half-duplex,
bidirectional data transfer to and from ASICs
— Reset configuration register
— Additional external interrupts
— Hardware watchdog timer can generate NMI or
system reset
— Pseudo static RAM (PSRAM) controller includes
auto refresh capability
Familiar 80C186 peripherals with enhanced
functionality
— Two independent DMA channels
— Programmable interrupt controller with six
external interrupts
— Three programmable 16-bit timers
— Programmable memory and peripheral
chip-select logic
— Programmable wait state generator
— Power-save clock mode
Software-compatible with the 80C186 and
80C188 microcontrollers
Widely available native development tools,
applications, and system software
Available in the following packages:
— 100-pin, thin quad flat pack (TQFP)
— 100-pin, plastic quad flat pack (PQFP)
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(PIO) pins on one chip. Compared to the 80C186/
8 0 C 1 8 8 m i c r o c o n t r o l l e r s, t h e A m 1 8 6 E R a n d
Am188ER microcontrollers enable designers to reduce
the size, power consumption, and cost of embedded
systems, while increasing functionality and
performance.
The Am186ER and Am188ER microcontrollers have
been designed to meet the most common
requirements of embedded products developed for the
communications, office automation, mass storage, and
general embedded markets. Specific applications
include feature phones, cellular phones, PBXs,
multiplexers, modems, disk drives, hand-held terminals
and desktop ter minals, fax machines, printers,
photocopiers, and industrial controls.
Publication# 20732 Rev: D Amendment/0
Issue Date: June 2000
Am186™ER MICROCONTROLLER BLOCK DIAGRAM
INT2/INTA0
INT3/INTA1/IRQ
CLKOUTA
INT1/SELECT
INT4
TMROUT0
INT0
CLKOUTB
TMRIN0
NMI
X2
X1
GND
Interrupt
Control Unit
Watchdog
Timer (WDT)
Control
Registers
Execution
Unit
Control
Registers
TMRIN1
Timer Control
Unit
0
1 (WDT)
Max Count B
Registers
Max Count A
Registers
16-Bit Count
Registers
Control
Registers
RES
Control
Registers
ARDY
SRDY
Refresh
Control
Unit
A
PSRAM
Control
Unit
S2
S1/IMDIS
S0/SREN
DT/R
DEN
HOLD
HLDA
S6/
CLKSEL1
UZI/
CLKSEL2
DRQ0
DRQ1
DMA
Unit
2
0
1
20-Bit Source
Pointers
20-Bit Destination
Pointers
16-Bit Count
Registers
Control
Registers
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F
Control
Registers
VCC
Clock and
Power
Management
Unit
TMROUT1
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32 Kbyte
SRAM
(16K x 16)
Bus
Interface
Unit
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A19–A0
Control
Registers
WLB
AD15–AD0
WR
BHE/ADEN
PIO31–
PIO0*
Control
Registers
Asynchronous
Serial Port
TXD
RXD
Control
Registers
Chip-Select
Unit
Synchronous Serial
Interface
RD
WHB
PIO
Unit
SCLK
PCS6/A2
LCS/ONCE0
SDATA
SDEN0 SDEN1
PCS5/A1
MCS3/RFSH
MCS2–MCS0
PCS3–PCS0
UCS/ONCE1
ALE
Note:
* All PIO signals are shared with other physical pins. See the pin descriptions beginning on page 30 and Table 3 on page 36 for
information on shared functions.
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Am186TMER and Am188TMER Microcontrollers Data Sheet
Am188™ER MICROCONTROLLER BLOCK DIAGRAM
INT2/INTA0
INT3/INTA1/IRQ
CLKOUTA
INT1/SELECT
INT4
TMROUT0
INT0
CLKOUTB
TMRIN0
NMI
X2
X1
Clock and
Power
Management
Interrupt
Control Unit
Watchdog
Timer (WDT)
Control
Registers
Control
Registers
GND
DRQ1
DMA
Unit
Timer Control
Unit
0
1 (WDT)
2
Max Count B
Registers
Max Count A
Registers
16-Bit Count
Registers
Control
Registers
RES
Control
Registers
ARDY
SRDY
Refresh
Control
Unit
A
PSRAM
Control
Unit
S2
S1/IMDIS
S0/SREN
DT/R
DEN
HOLD
HLDA
S6/
CLKSEL1
UZI/
CLKSEL2
DRQ0
0
1
20-Bit Source
Pointers
20-Bit Destination
Pointers
16-Bit Count
Registers
Control
Registers
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Control
Registers
VCC
Execution
Unit
TMROUT1
TMRIN1
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32 Kbyte
SRAM
(32K x 8)
Bus
Interface
Unit
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WB
WR
RFSH2/ADEN
ALE
Asynchronous
Serial Port
Chip-Select
Unit
TXD
RXD
Control
Registers
Synchronous Serial
Interface
SCLK
PCS6/A2
LCS/ONCE0
AD7–AD0
PIO31–
PIO0*
Control
Registers
RD
A19–A0
AO15–AO8
Control
Registers
PIO
Unit
SDATA
SDEN0 SDEN1
PCS5/A1
MCS3/RFSH
MCS2–MCS0
PCS3–PCS0
UCS/ONCE1
Notes:
* All PIO signals are shared with other physical pins. See the pin descriptions beginning on page 30 and Table 3 on page 36 for
information on shared functions.
Am186TMER and Am188TMER Microcontrollers Data Sheet
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ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order numbers (valid combinations) are
formed by a combination of the elements below.
Am186ER
–50
V
C
\W
LEAD FORMING
\W=Trimmed and Formed
TEMPERATURE RANGE
C = ER Commercial (TC =0°C to +100°C)
I = ER Industrial (TA =–40°C to +85°C)
where: TC = case temperature
where: TA = ambient temperature
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PACKAGE TYPE
V=100-Pin Thin Quad Flat Pack (TQFP)
K=100-Pin Plastic Quad Flat Pack (PQFP)
SPEED OPTION
–25 = 25 MHz
–33 = 33 MHz
–40 = 40 MHz
–50 = 50 MHz
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DEVICE NUMBER/DESCRIPTION
Am186ER = High-Performance, 80C186-Compatible,
16-Bit Embedded Microcontroller with RAM
Am188ER = High-Performance, 80C188-Compatible,
16-Bit Embedded Microcontroller with RAM
Valid Combinations
Am186ER–25
Am186ER–33
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Am186ER–40
Am186ER–50
Am188ER–25
Am188ER–33
Am188ER–40
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VC\W or
KC\W
Valid Combinations
Valid combinations list configurations planned to be
supported in volume for this device. Consult the
local AMD sales office to confirm availability of
specific valid combinations and to check on newly
released combinations.
VC\W or
KC\W
Am188ER–50
Am186ER–25
Am186ER–33
Am186ER–40
KI\W or
VI\W
Am186ER–50
Am188ER–25
Am188ER–33
Am188ER–40
KI\W or
VI\W
Am188ER–50
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Am186TMER and Am188TMER Microcontrollers Data Sheet
TABLE OF CONTENTS
Distinctive Characteristics ............................................................................................................ 1
General Description ..................................................................................................................... 1
Am186™ER Microcontroller Block Diagram ................................................................................ 2
Am188™ER Microcontroller Block Diagram ................................................................................ 3
Ordering Information .................................................................................................................... 4
List of Figures .............................................................................................................................. 9
List of Tables ............................................................................................................................... 9
Revision History ......................................................................................................................... 10
E86™ Family of Embedded Microprocessors and Microcontrollers .......................................... 12
Related Documents ....................................................................................................... 13
Demonstration Board Products ...................................................................................... 13
Third-Party Development Support Products ............................................................................13
Customer Service .......................................................................................................... 13
Key Features and Benefits ........................................................................................................ 14
Application Considerations ............................................................................................ 14
Comparison of the Am186™ER and 80C186 Microcontrollers ................................................. 15
TQFP Connection Diagram and Pinouts—Am186™ER Microcontroller ................................... 16
TQFP Pin Assignments—Am186™ER Microcontroller (Sorted by Pin Number) ...................... 17
TQFP Pin Assignments—Am186™ER Microcontroller (Sorted by Pin Name) .......................... 18
TQFP Connection Diagram and Pinouts—Am188™ER Microcontroller ................................... 19
TQFP Pin Assignments—Am188™ER Microcontroller (Sorted by Pin Number) ...................... 20
TQFP Pin Assignments—Am188™ER Microcontroller (Sorted by Pin Name) ......................... 21
PQFP Connection Diagram and Pinouts—Am186™ER Microcontroller ................................... 22
PQFP Pin Assignments—Am186™ER Microcontroller (Sorted by Pin Number) ...................... 23
PQFP Pin Assignments—Am186™ER Microcontroller (Sorted by Pin Name) ......................... 24
PQFP Connection Diagram and Pinouts—Am188™ER Microcontroller ................................... 25
PQFP Pin Assignments—Am188™ER Microcontroller (Sorted by Pin Number) ...................... 26
PQFP Pin Assignments—Am188™ER Microcontroller (Sorted by Pin Name) ......................... 27
Logic Symbol—Am186™ER Microcontroller ............................................................................. 28
Logic Symbol—Am188™ER Microcontroller ............................................................................. 29
Pin Descriptions ......................................................................................................................... 30
Pins Used by Emulators ................................................................................................. 30
A19–A0 (A19/PIO9, A18/PIO8, A17/PIO7) .................................................................... 30
AD7–AD0 ....................................................................................................................... 30
AD15–AD8 (Am186™ER Microcontroller) ..................................................................... 30
AO15–AO8 (Am188™ER Microcontroller) ..................................................................... 30
ALE ................................................................................................................................ 31
ARDY ............................................................................................................................. 31
BHE/ADEN (Am186™ER Microcontroller Only) ............................................................ 31
CLKOUTA ...................................................................................................................... 31
CLKOUTB ...................................................................................................................... 31
DEN/PIO5 ...................................................................................................................... 31
DRQ1–DRQ0 (DRQ1/PIO13, DRQ0/PIO12) ................................................................. 32
DT/R/PIO4 ..................................................................................................................... 32
GND ............................................................................................................................... 32
HLDA ............................................................................................................................. 32
HOLD ............................................................................................................................. 32
INT0 ............................................................................................................................... 32
INT1/SELECT ................................................................................................................ 32
INT2/INTA0/PIO31 ......................................................................................................... 33
INT3/INTA1/IRQ ............................................................................................................. 33
INT4/PIO30 .................................................................................................................... 33
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Am186TMER and Am188TMER Microcontrollers Data Sheet
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LCS/ONCE0 ................................................................................................................... 33
MCS3/RFSH/PIO25 ....................................................................................................... 33
MCS2–MCS0 (MCS2/PIO24, MCS1/PIO15, MCS0/PIO14) .......................................... 34
NMI ................................................................................................................................ 34
PCS3–PCS0 (PCS3/PIO19, PCS2/PIO18, PCS1/PIO17, PCS0/PIO16) ...................... 34
PCS5/A1/PIO3 ............................................................................................................... 34
PCS6/A2/PIO2 ............................................................................................................... 34
PIO31–PIO0 (Shared) .................................................................................................... 35
RD .................................................................................................................................. 35
RES ................................................................................................................................ 35
RFSH2/ADEN (Am188™ER Microcontroller Only) ........................................................ 35
RXD/PIO28 .................................................................................................................... 35
S2 ................................................................................................................................... 35
S1/IMDIS ........................................................................................................................ 37
S0/SREN ........................................................................................................................ 37
S6/CLKSEL1/PIO29 ....................................................................................................... 37
SCLK/PIO20 .................................................................................................................. 37
SDATA/PIO21 ................................................................................................................ 37
SDEN1/PIO23, SDEN0/PIO22 ....................................................................................... 37
SRDY/PIO6 .................................................................................................................... 38
TMRIN0/PIO11 .............................................................................................................. 38
TMRIN1/PIO0 ................................................................................................................ 38
TMROUT0/PIO10 .......................................................................................................... 38
TMROUT1/PIO1 ............................................................................................................ 38
TXD/PIO27 ..................................................................................................................... 38
UCS/ONCE1 .................................................................................................................. 38
UZI/CLKSEL2/PIO26 ..................................................................................................... 38
VCC ................................................................................................................................ 39
WHB (Am186™ER Microcontroller Only) ...................................................................... 39
WLB (Am186™ER Microcontroller Only) ........................................................................ 39
WB (Am188™ER Microcontroller Only) ......................................................................... 39
WR ................................................................................................................................. 39
X1 ................................................................................................................................... 39
X2 ................................................................................................................................... 39
Functional Description ............................................................................................................... 40
Memory Organization ..................................................................................................... 40
I/O Space ....................................................................................................................... 40
Bus Operation ............................................................................................................................ 41
Bus Interface Unit ...................................................................................................................... 41
Nonmultiplexed Address Bus ......................................................................................... 41
Byte Write Enables ........................................................................................................ 41
Output Enable ................................................................................................................ 41
Pseudo Static RAM (PSRAM) Support .......................................................................... 44
Peripheral Control Block (PCB) ................................................................................................. 44
Reading and Writing the PCB ........................................................................................ 44
Clock and Power Management .................................................................................................. 44
Phase-Locked Loop (PLL) ............................................................................................. 44
Crystal-Driven Clock Source .......................................................................................... 45
External Source Clock ................................................................................................... 45
System Clocks ............................................................................................................... 48
Power-Save Operation ................................................................................................... 48
Initialization and Processor Reset .................................................................................. 48
Reset Configuration Register ......................................................................................... 48
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Am186TMER and Am188TMER Microcontrollers Data Sheet
Chip-Select Unit ......................................................................................................................... 49
Chip-Select Timing ......................................................................................................... 49
Ready and Wait-State Programming ............................................................................. 49
Memory Maps ................................................................................................................ 50
Chip-Select Overlap ....................................................................................................... 51
Upper Memory Chip Select ............................................................................................ 51
Low Memory Chip Select ............................................................................................... 51
Midrange Memory Chip Selects ..................................................................................... 51
Peripheral Chip Selects ................................................................................................. 52
Internal Memory ......................................................................................................................... 52
Interaction with External RAM ........................................................................................ 52
Emulator and Debug Modes .......................................................................................... 52
Refresh Control Unit .................................................................................................................. 53
Interrupt Control Unit ................................................................................................................. 53
Programming the Interrupt Control Unit ......................................................................... 53
Timer Control Unit ...................................................................................................................... 53
Watchdog Timer ........................................................................................................................ 54
Direct Memory Access ............................................................................................................... 54
DMA Operation .............................................................................................................. 55
Asynchronous Serial Port/DMA Transfers ..................................................................... 55
DMA Channel Control Registers .................................................................................... 55
DMA Priority ................................................................................................................... 55
Asynchronous Serial Port .......................................................................................................... 56
DMA Transfers through the Serial Port .......................................................................... 56
Synchronous Serial Interface ..................................................................................................... 56
Four-Pin Interface .......................................................................................................... 57
Programmable I/O (PIO) Pins .................................................................................................... 57
Low-Voltage Operation .............................................................................................................. 59
Low-Voltage Standard ................................................................................................... 59
Power Savings ............................................................................................................... 59
Input/Output Circuitry ..................................................................................................... 59
Absolute Maximum Ratings ....................................................................................................... 60
Operating Ranges ...................................................................................................................... 60
DC Characteristics Over Commercial and Industrial Operating Ranges ................................... 60
Thermal Characteristics ............................................................................................................. 61
TQFP Package .............................................................................................................. 61
Typical Ambient Temperatures ...................................................................................... 62
Commercial and Industrial Switching Characteristics and Waveforms ...................................... 67
Key to Switching Waveforms ......................................................................................... 67
Alphabetical Key to Switching Parameter Symbols ....................................................... 68
Numerical Key to Switching Parameter Symbols .......................................................... 69
Switching Characteristics over Commercial and Industrial Operating Ranges,
Read Cycle (25 MHz and 33 MHz) ................................................................................ 70
Switching Characteristics over Commercial and Industrial Operating Ranges,
Read Cycle (40 MHz and 50 MHz) ................................................................................ 71
Read Cycle Waveforms ................................................................................................. 72
Switching Characteristics over Commercial and Industrial Operating Ranges,
Write Cycle (25 MHz and 33 MHz) ................................................................................ 73
Switching Characteristics over Commercial and Industrial Operating Ranges,
Write Cycle (40 MHz and 50 MHz) ................................................................................ 74
Write Cycle Waveforms ................................................................................................. 75
Switching Characteristics over Commercial and Industrial Operating Ranges,
Internal RAM Show Read Cycle (25 MHz and 33 MHz) ................................................ 76
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Am186TMER and Am188TMER Microcontrollers Data Sheet
7
Switching Characteristics over Commercial and Industrial Operating Ranges,
Internal RAM Show Read Cycle (40 MHz and 50 MHz) ................................................ 76
Internal RAM Show Read Cycle Waveform ................................................................... 77
Switching Characteristics over Commercial and Industrial Operating Ranges,
PSRAM Read Cycle (25 MHz and 33 MHz) .................................................................. 78
Switching Characteristics over Commercial and Industrial Operating Ranges,
PSRAM Read Cycle (40 MHz and 50 MHz) .................................................................. 79
PSRAM Read Cycle Waveforms ................................................................................... 80
Switching Characteristics over Commercial and Industrial Operating Ranges,
PSRAM Write Cycle (25 MHz and 33 MHz) ................................................................... 81
Switching Characteristics over Commercial and Industrial Operating Ranges,
PSRAM Write Cycle (40 MHz and 50 MHz) ................................................................... 82
PSRAM Write Cycle Waveforms .................................................................................... 83
Switching Characteristics over Commercial and Industrial Operating Ranges,
PSRAM Refresh Cycle (25 MHz and 33 MHz) .............................................................. 84
Switching Characteristics over Commercial and Industrial Operating Ranges,
PSRAM Refresh Cycle (40 MHz and 50 MHz) .............................................................. 85
PSRAM Refresh Cycle Waveforms ............................................................................... 86
Switching Characteristics over Commercial and Industrial Operating Ranges,
Interrupt Acknowledge Cycle (25 MHz and 33 MHz) ..................................................... 87
Switching Characteristics over Commercial Operating Ranges,
Interrupt Acknowledge Cycle (40 MHz and 50 MHz) ..................................................... 88
Interrupt Acknowledge Cycle Waveforms ...................................................................... 89
Switching Characteristics over Commercial and Industrial Operating Ranges,
Software Halt Cycle (25 MHz and 33 MHz) ................................................................... 90
Switching Characteristics over Commercial and Industrial Operating Ranges,
Software Halt Cycle (40 MHz and 50 MHz) ................................................................... 90
Software Halt Cycle Waveforms .................................................................................... 91
Switching Characteristics over Commercial and Industrial Operating Ranges,
Clock (25 MHz) .............................................................................................................. 92
Switching Characteristics over Commercial and Industrial Operating Ranges,
Clock (33 MHz) .............................................................................................................. 93
Switching Characteristics over Commercial and Industrial Operating Ranges,
Clock (40 MHz and 50 MHz) .......................................................................................... 94
Clock Waveforms—Active Mode ................................................................................... 95
Clock Waveforms—Power-Save Mode .......................................................................... 95
Switching Characteristics over Commercial and Industrial Operating Ranges,
Ready and Peripheral Timing (25 MHz and 33 MHz) .................................................... 96
Switching Characteristics over Commercial and Industrial Operating Ranges,
Ready and Peripheral Timing (40 MHz and 50 MHz) .................................................... 96
Synchronous Ready Waveforms ................................................................................... 97
Asynchronous Ready Waveforms .................................................................................. 97
Peripheral Waveforms ................................................................................................... 98
Switching Characteristics over Commercial and Industrial Operating Ranges,
Reset and Bus Hold (25 MHz and 33 MHz) ................................................................... 99
Switching Characteristics over Commercial and Industrial Operating Ranges,
Reset and Bus Hold (40 MHz and 50 MHz) ................................................................... 99
Reset Waveforms ........................................................................................................ 100
Signals Related to Reset Waveforms .......................................................................... 100
Bus Hold Waveforms—Entering .................................................................................. 101
Bus Hold Waveforms—Leaving ................................................................................... 101
Switching Characteristics over Commercial and Industrial Operating Ranges,
Synchronous Serial Interface (SSI) (25 MHz and 33 MHz) ......................................... 102
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Am186TMER and Am188TMER Microcontrollers Data Sheet
Switching Characteristics over Commercial and Industrial Operating Ranges,
Synchronous Serial Interface (SSI) (40 MHz and 50 MHz) ......................................... 102
Synchronous Serial Interface (SSI) Waveforms .......................................................... 103
TQFP Physical Dimensions ..................................................................................................... 104
PQFP Physical Dimensions ..................................................................................................... 105
Index ................................................................................................................................... Index-1
LIST OF FIGURES
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Am186ER 50-MHz Example System Design ......................................................... 15
Typical 80C186 System Design ............................................................................. 15
Two-Component Address Example ....................................................................... 40
Am186™ER Microcontroller Address Bus—Normal Operation ............................. 42
Am186™ER Microcontroller—Address Bus Disable in Effect ............................... 42
Am188™ER Microcontroller Address Bus—Normal Operation ............................. 43
Am188™ER Microcontroller—Address Bus Disable in Effect ............................... 43
Am186™ER and Am188™ER Microcontrollers Oscillator Configurations ............ 45
Peripheral Control Block Register Map .................................................................. 46
Clock Organization ................................................................................................ 48
ARDY and SRDY Synchronization Logic Diagram ................................................ 49
Example Memory Maps ......................................................................................... 50
DMA Unit Block Diagram ....................................................................................... 56
Synchronous Serial Interface Multiple Write .......................................................... 58
Synchronous Serial Interface Multiple Read .......................................................... 58
Thermal Resistance (°C/Watt) ............................................................................... 61
Thermal Characteristics Equations ........................................................................ 61
Typical Ambient Temperatures for PQFP with Two-Layer Board .......................... 63
Typical Ambient Temperatures for TQFP with Two-Layer Board .......................... 64
Typical Ambient Temperatures for PQFP with Four-Layer to Six-Layer Board ..... 65
Typical Ambient Temperatures for TQFP with Four-Layer to Six-Layer Board ..... 66
LIST OF TABLES
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
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Related AMD Products—E86™ Family Devices ................................................... 12
Data Byte Encoding ............................................................................................... 31
Numeric PIO Pin Assignments .............................................................................. 36
Alphabetic PIO Pin Assignments ........................................................................... 36
Bus Cycle Encoding ............................................................................................... 37
Clocking Modes ..................................................................................................... 39
Segment Register Selection Rules ........................................................................ 40
Maximum and Minimum Clock Frequencies .......................................................... 44
Am186ER Microcontroller Maximum DMA Transfer Rates .................................. 55
Thermal Characteristics (°C/Watt) ......................................................................... 61
Typical Power Consumption Calculation ............................................................... 62
Junction Temperature Calculation ......................................................................... 62
Typical Ambient Temperatures for PQFP with Two-Layer Board .......................... 63
Typical Ambient Temperatures for TQFP with Two-Layer Board .......................... 64
Typical Ambient Temperatures for PQFP with Four-Layer to Six-Layer Board ..... 65
Typical Ambient Temperatures for TQFP with Four-Layer to Six-Layer Board ..... 66
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Am186TMER and Am188TMER Microcontrollers Data Sheet
9
REVISION HISTORY
Date
Rev Description
Feb. 2000
D
Replaced block diagrams on page 2 and page 3 with updated diagrams showing that the internal data
bus interfaces via the BIU and not RAM.
Feb. 2000
D
Added new industrial parts for “Ordering Information” on page 4.
Feb. 2000
D
Updated product listings and customer service matter on page 12 and page 13.
Feb. 2000
D
Replaced Figure 8 on page 45 (microcontroller oscillator configurations) with updated figure.
Feb. 2000
D
Updated several references to watchdog timer on page 54 to reflect that the WDT is inactive after
reset, not active).
Feb. 2000
D
Provided a value for the TBD in the table entitled, “DC Characteristics Over Commercial and Industrial
Operating Ranges” on page 60.
Feb. 2000
D
Updated table title and "Min" values for No. 66 in the switching characteristics table, “Read Cycle (40
MHz and 50 MHz)” on page 71.
Feb. 2000
D
Updated table title and "Max" values for No. 87 in the switching characteristics table, “Write Cycle (40
MHz and 50 MHz)” on page 74.
Feb. 2000
D
Updated table title and "Min" value for No. 9 (50 MHz) in the switching characteristics table, “Internal
RAM Show Read Cycle (40 MHz and 50 MHz)” on page 76.
Feb. 2000
D
Updated table title and "Min" values for No. 66 in the switching characteristics table, “PSRAM Read
Cycle (40 MHz and 50 MHz)” on page 79.
Feb. 2000
D
Updated table title and "Max" value for No. 68 (40 MHz) in the switching characteristics table,
“PSRAM Write Cycle (40 MHz and 50 MHz)” on page 82.
Feb. 2000
D
Updated table title in the switching characteristics table, “PSRAM Refresh Cycle (40 MHz and 50
MHz)” on page 85.
Feb. 2000
D
Updated table title in the switching characteristics table, “Software Halt Cycle (40 MHz and 50 MHz)”
on page 90.
Feb. 2000
D
Updated "Min" and "Max" values in the switching characteristics table, “Clock (33 MHz)” on page 93.
Feb. 2000
D
Updated table title in the switching characteristics table, “Clock (40 MHz and 50 MHz)” on page 94.
Feb. 2000
D
Updated table title in the switching characteristics table, “Ready and Peripheral Timing (40 MHz and
50 MHz)” on page 96.
Feb. 2000
D
Updated table title in the switching characteristics table, “Reset and Bus Hold (40 MHz and 50 MHz)”
on page 99.
Feb. 2000
D
Updated table title in the switching characteristics table, “Synchronous Serial Interface (SSI) (40 MHz
and 50 MHz)” on page 102.
Feb. 2000
D
In the table "Switching Characteristics over Commercial and Industrial Operating Ranges Read Cycle
(40 MHz and 50 MHz)", row 9, column "50 MHz" - "Min", the "0" is deleted.
Feb. 2000
D
In the table "Switching Characteristics over Commercial and Industrial Operating Ranges Read Cycle
(40 MHz and 50 MHz)", row 66, column "40 MHz" - "Min", the value is changed.
Feb. 2000
D
In the table "Switching Characteristics over Commercial and Industrial Operating Ranges Read Cycle
(40 MHz and 50 MHz)", row 66, column "50 MHz" - "Min", the value is changed.
Feb. 2000
D
In the table "Switching Characteristics over Commercial and Industrial Operating Ranges PSRAM
Write Cycle (40 MHz and 50 MHz)", row 68, column "40 MHz" - "Max", the value is changed.
May 2000
D
Under “Key Features and Benefits” on page 14, in the third bullet "Enhanced functionality," the
feature, "a PSRAM controller" was added.
May 2000
D
Under “HOLD” on page 32, the sentence, "A HOLD request is second only to DRAM or PSRAM
refresh requests in priority of activity requests received by the processor." is changed.
D
10
R
A
T
F
Am186TMER and Am188TMER Microcontrollers Data Sheet
Date
Rev Description
May 2000
D
Under “SRDY/PIO6” on page 38, the following sentence was added: "When SRDY is configured as
P106, the internal SRDY signal is driven Low."
May 2000
D
In Table 8, “Maximum and Minimum Clock Frequencies,” on page 44, the values are changed in the
cell of row "Divide by 2" and column "X1/X2 Min" and in the cell of row "Divide by 2" and column
"CLKOUTA Min".
May 2000
D
In “Switching Characteristics over Commercial and Industrial Operating Ranges” on page 93, Max
value in the number "36" row was changed to "33."
May 2000
D
In “Switching Characteristics over Commercial and Industrial Operating Ranges” on page 94, the
value in "40 MHz Max" for row number 36 was changed to "33."
May 2000
D
In “Synchronous Ready Waveforms” on page 97, the diagram was changed.
May 2000
D
In “Asynchronous Ready Waveforms” on page 97, the diagram was changed.
May 2000
D
In "BHE/ADEN", on page 31, the second paragraph under ADEN was changed.
May 2000
D
In "UZI/CLKSEL2/PIO26", on page 38, the paragraph description of UZI was changed.
May 2000
D
In “Read Cycle Waveforms” on page 72, the UZI line in the diagram was changed.
May 2000
D
In “Write Cycle Waveforms” on page 75, the UZI line in the diagram was changed.
May 2000
D
Added the diagram, Table 11, “ARDY and SRDY Synchronization Logic Diagram,” on page 49.
May 2000
D
Added an index.
D
R
A
T
F
Am186TMER and Am188TMER Microcontrollers Data Sheet
11
E86™ FAMILY OF EMBEDDED MICROPROCESSORS AND MICROCONTROLLERS
AMD-K6™-2E
Microprocessor
Am5x86®
Microprocessor
Am486®DX
Microprocessor
ÉlanSC400
Microcontroller
Am386®SX/DX
Microprocessors
Élan™SC310
Microcontroller
ÉlanSC520
Microcontroller
ÉlanSC410
Microcontroller
ÉlanSC300
Microcontroller
Am186CC
Communications
Controller
Am186CH HDLC
Microcontroller
Am186™CU USB
Microcontroller
Am186EM and
Am188™EM
Microcontrollers
80C186 and 80C188
Microcontrollers
Am186EMLV &
Am188EMLV
Microcontrollers
Am186ES and
Am188ES
Microcontrollers
Am186ER and
Am188ER
Microcontrollers
Am186ESLV &
Am188ESLV
Microcontrollers
Am186ED
Microcontroller
Am186EDLV
Microcontroller
T
F
— Microprocessors
— 16- and 32-bit microcontrollers
80L186 and 80L188
Microcontrollers
— 16-bit microcontrollers
E86™ Family of Embedded Microprocessors and Microcontrollers
Table 1.
Device1
80C186/80C188
80L186/80L188
Am186™EM/Am188™EM
Am186EMLV/Am188EMLV
Am186ES/Am188ES
Am186ESLV/Am188ESLV
Am186ED
Am186EDLV
Description
16-bit microcontroller
Low-voltage, 16-bit microcontroller
High-performance, 16-bit embedded microcontroller
High-performance, 16-bit embedded microcontroller
High-performance, 16-bit embedded microcontroller
High-performance, 16-bit embedded microcontroller
High-performance, 80C186- and 80C188-compatible, 16-bit embedded microcontroller with 8- or
16-bit external data bus
High-performance, 80C186- and 80C188-compatible, low-voltage, 16-bit embedded
microcontroller with 8- or 16-bit external data bus
High-performance, low-voltage, 16-bit embedded microcontroller with 32 Kbyte of internal SRAM
High-performance, 16-bit embedded communications controller
High-performance, 16-bit embedded HDLC microcontroller
High-performance, 16-bit embedded USB microcontroller
High-performance, highly integrated, low-voltage, 32-bit embedded microcontroller
High-performance, single-chip, 32-bit embedded PC/AT-compatible microcontroller
High-performance, single-chip, low-power, PC/AT-compatible microcontroller
High-performance, single-chip, PC/AT-compatible microcontroller
High-performance, single-chip, 32-bit embedded microcontroller
High-performance, 32-bit embedded microprocessor with 16-bit external data bus
High-performance, 32-bit embedded microprocessor with 32-bit external data bus
High-performance, 32-bit embedded microprocessor with 32-bit external data bus
High-performance, 32-bit embedded microprocessor with 32-bit external data bus
High-performance, 32-bit embedded microprocessor with 64-bit external data bus
and 3DNow!™ technology
D
Am186ER/Am188ER
Am186CC
Am186CH
Am186CU
ÉlanSC300
ÉlanSC310
ÉlanSC400
ÉlanSC410
ÉlanSC520
Am386®SX
Am386®DX
Am486®DX
Am5x86®
AMD-K6™-2E
A
Related AMD Products—E86™ Family Devices
R
Notes:
1. 186 = 16-bit microcontroller and 80C186-compatible (except where noted otherwise); 188 = 16-bit microcontroller with 8-bit
external data bus and 80C188-compatible (except where noted otherwise); LV = low voltage
12
Am186TMER and Am188TMER Microcontrollers Data Sheet
Related Documents
The following documents provide additional information regarding the Am186ER and Am188ER microcontrollers.
n Am186ER and Am188ER Microcontrollers User’s
Manual, order #21684
n FusionE86SM Catalog, order #19255
n Making the Most of the Am186™ER or Am188™ER
Microcontroller Application Note, order #21046
n Using the 3.3-V Am186™ER or Am188™ER Microcontroller in a 5-V System Application Note,
order #21045
n Comparing the Am186™EM and Am186ER Microcontrollers Technical Bulletin (Available only at
www.amd.com/products/epd/techdocs.)
n The Advantages of Integrated RAM Technical Bulletin (Available only at www.amd.com/products/
epd/techdocs.)
A full description of the Am186ER and Am188ER microcontrollers’ registers and instructions is included in
the Am186ER and Am188ER Microcontrollers User’s
Manual listed above.
To order literature, contact the nearest AMD sales office or call the literature center at one of the numbers
listed on the back cover of this manual. In addition, all
these documents are available in PDF form on the
AMD web site. To access the AMD home page, go to
www.amd.com. Then follow the Embedded Processor
link for information about E86 microcontrollers.
R
Demonstration Board Products
The SD186ER demonstration board product is a standalone, low-cost evaluation platform for the Am186ER
microcontroller.
D
The SD186ER board demonstrates the basic processor functionality and features of the Am186ER microcontroller and the simplicity of its system design. The
SD186ER demonstration board is designed with the
Am186/Am188 expansion interface that provides access to the Am186ER microcontroller signals. The
104-pin expansion interface facilitates prototyping by
enabling the demonstration board to be used as the
minimal system core of a design. Contact your local
AMD sales office for more information on demonstration board availability and pricing.
Third-Party Development Support Products
The FusionE86 Program of Partnerships for Application Solutions provides the customer with an array of
products designed to meet critical time-to-market
needs. Products and solutions available from the AMD
FusionE86 partners include protocol stacks, emulators,
hardware and software debuggers, board-level products, and software development tools, among others.
In addition, mature development tools and applications
for the x86 platform are widely available in the general
marketplace.
Customer Service
The AMD customer service network includes U.S. offices, international offices, and a customer training center. Expert technical assistance is available from the
AMD worldwide staff of field application engineers and
factory support staff to answer E86 and Comm86 family hardware and software development questions.
Hotline and World Wide Web Support
For answers to technical questions, AMD provides
e-mail support as well as a toll-free number for direct
access to our corporate applications hotline.
Note: The support telephone numbers listed below
are subject to change. For current telephone numbers,
refer to www.amd.com/support/literature.
T
F
The AMD World Wide Web home page provides the
latest product information, including technical information and data on upcoming product releases. In addition, EPD CodeKit software on the Web site provides
tested source code example applications.
Corporate Applications Hotline
A
(800) 222-9323
44-(0) 1276-803-299
Toll-free for U.S. and Canada
U.K. and Europe hotline
Additional contact information is listed on the back of
this datasheet. For technical support questions on all
E86 and Comm86 products, send e-mail to [email protected]
World Wide Web Home Page
To access the AMD home page go to: www.amd.com.
Then follow the Embedded Processors link for information about E86 family and Comm86™ products.
Questions, requests, and input concerning AMD’s
WWW pages can be sent via e-mail to [email protected]
Documentation and Literature
Free information such as data books, user’s manuals,
data sheets, application notes, the <Italics>E86™
Family Products and Development Tools CD, order
#21058, and other literature is available with a simple
phone call. Internationally, contact your local AMD
sales office for product literature. Additional contact
information is listed on the back of this data sheet.
Literature Ordering
(800) 222-9323
Toll-free for U.S. and Canada
Am186TMER and Am188TMER Microcontrollers Data Sheet
13
KEY FEATURES AND BENEFITS
The Am186ER and Am188ER microcontrollers are
higher-performance, highly integrated versions of the
80C186/80C188 microprocessors, offering a migration
path that was previously unavailable. New peripherals,
on-chip system interface logic, and 32 Kbyte of internal
memory on the Am186ER microcontroller reduce the
cost of existing 80C186/80C188 designs. Upgrading to
the Am186ER microcontroller is an attractive solution
for several reasons:
n Integrated SRAM—32 Kbyte of internal SRAM ensures a low-cost supply of memory and a smaller
form factor for system designs. The internal memory provides the same performance as external
zero-wait-state SRAM devices.
n 3.3-V operation with 5-V-tolerant I/O—3.3-V operation provides much lower power consumption
when compared to existing 5-V designs. Plus, the
Am186ER and Am188ER controllers accommodate
current 5-V designs with 5-V-tolerant I/O drivers.
n x86 software compatibility—80C186/80C188compatible and upward-compatible with the other
members of the AMD E86 family.
n Enhanced performance—The Am186ER and
Am188ER microcontrollers increase the performance of 80C186/80C188 systems, and the nonmultiplexed address bus offers faster, unbuffered
access to commodity-speed, external memory.
functionality—Enhanced
on-chip
n Enhanced
peripherals include an asynchronous serial port, up
to 32 PIOs, a hardware watchdog timer, an
additional interrupt pin, a synchronous serial
interface, a PSRAM controller, a 16-bit reset
configuration register, and enhanced chip-select
functionality.
D
R
Application Considerations
The integration enhancements of the Am186ER microcontroller provide a high-performance, low-systemcost solution for 16-bit embedded microcontroller designs. Both multiplexed and nonmultiplexed address
buses are available on the Am186ER and Am188ER
microcontrollers. The nonmultiplexed address bus
eliminates system-support logic ordinarily needed to
interface with external memory devices, while the multiplexed address/data bus maintains the value of previously engineered, customer-specific peripherals and
circuits within the upgraded design. Figure 1 on page
15 illustrates an example system design that uses the
integrated peripheral set to achieve high performance
with reduced system cost.
system form factor, decreased system power, stable
RAM supply, and lower system cost compared with
buying external SRAM. The integrated RAM also ensures that an entire embedded system will not require
requalification based on the short life cycles of external
SRAM. Additionally, for those systems using more
RAM than required because of the granularity of external RAM, the Am186ER microcontroller provides a
closer system match.
Clock Generation
The integrated clock generation circuitr y of the
Am186ER and Am188ER microcontrollers enables the
processors to operate at up to four times the crystal frequency. The design in Figure 1 achieves 50-MHz CPU
operation while using a 12.5-MHz crystal. The clocking
frequency function is controlled by an internal PLL. The
following modes are available (see Figure 10 on page
48):
T
F
n Divide by Two—The frequency of the fundamental
clock is half the frequency of the crystal with the PLL
disabled.
n Times One—The frequency of the fundamental
clock will be the same as the external crystal with
the PLL enabled.
n Times Four—The frequency of the fundamental
clock is four times the frequency of the crystal with
the PLL enabled.
A
The default mode is Times Four.
Memory Interface
The integrated memor y controller logic of the
Am186ER and Am188ER microcontrollers provides a
direct address bus to memory devices. Using an external address latch controlled by the address latch enable (ALE) signal is no longer necessary. Individual
byte-write-enable signals on the Am186ER and
Am188ER microcontrollers eliminate the need for external high/low byte-write-enable circuitry. The maximum bank size programmable for the memory chipselect signals is increased to facilitate the use of highdensity memory devices.
The improved memory timing specifications for the
Am186ER and Am188ER microcontrollers facilitate the
use of external memory devices with 55-ns access
times at 50-MHz CPU operation. As a result, overall
system cost is significantly reduced as system designers are able to use commonly available memory technology.
Internal Memory
The 32-Kbyte internal RAM fulfills the memory requirements for many embedded systems. These systems
can take advantage of the increased reliability, smaller
14
Am186TMER and Am188TMER Microcontrollers Data Sheet
Direct Memory Interface Example
Figure 1 illustrates the direct interface to memory of the
Am186ER microcontroller. The A19–A0 bus connects
to the memory address inputs, the AD bus connects to
the data inputs and outputs, and the chip selects connect to the memory chip-select inputs.
Am186ER
Microcontroller
A19–A0
X1
Figure 1 also shows an implementation of an RS-232
console or modem communications port. The RS-232to-CMOS voltage-level converter is required for the
electrical interface with the external device.
Serial Port
X1
R
WR
ALE
RD
OE
UCS
CS
INT4–INT0
DMA 0–1
TXD
CLKOUTA
50 MHz
RXD
T
F
Figure 1. Am186™ER 50-MHz Example
System Design
PAL
A
Am29F400
Flash
WE
SRAM
WE
WE
Address
Address
Data
Data
RD
OE
OE
UCS
CS
CS
AD15–AD0
D
RS-232
Level
Converter
LATCH
BHE
A0
Address
Data
Timer 0–2
Figure 1 shows an example system using a 50-MHz
Am186ER microcontroller. Figure 2 shows a comparable system implementation with an 80C186 microcontroller. Because of its superior integration, the
Am186ER system does not require the support devices
required on the 80C186 example system. In addition,
the Am186ER microcontroller provides significantly
better performance with its 50-MHz clock rate.
X2
AD15–AD0
WE
32 Kbyte
SRAM
COMPARISON OF THE Am186™ER AND
80C186 MICROCONTROLLERS
40-MHz
Crystal
WR
X2
12.5-MHz
Crystal
Am29F400
Flash
LCS
PCS0
Timer 0–2
LATCH
PIOs
Serial
Port
RS-232
Level
Converter
INT3
INT2–INT0
DMA 0–1
CLKOUT
Figure 2.
20 MHz
Typical 80C186 System Design
Am186TMER and Am188TMER Microcontrollers Data Sheet
15
2
3
AD9
AD2
4
5
AD10
AD3
6
7
AD11
AD4
8
9
AD12
AD5
GND
10
11
RES
GND
MCS3/ RFSH
MCS2
VCC
PCS 0
PCS 1
GND
PCS 2
PCS 3
VCC
PCS 5/A1
PCS 6/A2
LCS / ONCE 0
UCS / ONCE1
INT0
INT1/ SELECT
INT2/INTA 0
INT3/INTA 1/IRQ
94
93
92
91
90
89
88
87
86
85
83
82
81
80
79
78
77
76
14
15
16
17
40
41
42
43
44
45
46
47
48
49
50
CLKOUTB
GND
A19
A18
VCC
A17
A16
A15
A14
A13
A12
SCLK
BHE/ADEN
WR
RD
ALE
ARDY
26
27
D
R
38
39
24
25
VCC
CLKOUTA
SDEN1
SDEN0
36
37
22
23
34
35
RXD
SDATA
A
S0/SREN
GND
X1
X2
UZI/CLKSEL2
TXD
20
21
S1/IMDIS
S6/CLKSEL1
18
19
84
TMROUT1
TMRIN1
Am186ER Microcontroller
Notes:
Pin 1 is marked for orientation.
16
Am186TMER and Am188TMER Microcontrollers Data Sheet
INT4
MCS1
MCS0
71
70
DEN
DT/R
NMI
69
68
SRDY
HOLD
67
66
HLDA
65
64
WHB
GND
63
62
A0
A1
61
60
VCC
A2
59
58
A3
A4
57
56
A5
A6
55
54
A7
A8
53
52
A9
A10
51
A11
T
F
32
33
AD15
12
13
S2
VCC
AD14
AD7
73
72
30
31
AD6
75
74
28
29
AD13
96
95
DRQ0
1
AD8
AD1
DRQ1
TMRIN0
TMROUT0
100
AD0
99
98
97
TQFP CONNECTION DIAGRAM AND PINOUTS—Am186™ER MICROCONTROLLER
Top Side View—100-Pin Thin Quad Flat Pack (TQFP)
WLB
TQFP PIN ASSIGNMENTS—Am186™ER MICROCONTROLLER
(Sorted by Pin Number)
Pin No. Name
Pin No. Name
Pin No. Name
Pin No. Name
1
AD0
26
SCLK/PIO20
51
A11
76
INT3/INTA1/IRQ
2
AD8
27
BHE/ADEN
52
A10
77
INT2/INTA0
3
AD1
28
WR
53
A9
78
INT1/SELECT
4
AD9
29
RD
54
A8
79
INT0
5
AD2
30
ALE
55
A7
80
UCS/ONCE1
6
AD10
31
ARDY
56
A6
81
LCS/ONCE0
7
AD3
32
S2
57
A5
82
PCS6/A2/PIO2
8
AD11
33
S1/IMDIS
58
A4
83
PCS5/A1/PIO3
9
AD4
34
S0/SREN
59
A3
84
VCC
10
AD12
35
GND
60
A2
11
AD5
36
X1
61
VCC
12
GND
37
X2
62
A1
13
AD13
38
VCC
63
A0
14
AD6
39
CLKOUTA
64
GND
15
VCC
40
CLKOUTB
65
WHB
16
AD14
41
GND
66
WLB
17
AD7
42
A19/PIO9
67
HLDA
18
AD15
43
A18/PIO8
68
HOLD
19
S6/CKLSEL1/PIO29
44
VCC
69
20
UZI/CLKSEL2/PIO26
21
TXD
22
RXD
23
SDATA/PIO21
24
SDEN1/PIO23
25
SDEN0/PIO22
D
R
T
F
85
PCS3/PIO19
86
PCS2/PIO18
87
GND
88
PCS1/PIO17
89
PCS0/PIO16
90
VCC
91
MCS2
92
MCS3/RFSH
93
GND
SRDY/PIO6
94
RES
70
NMI
95
TMRIN1/PIO0
71
DT/R/PIO4
96
TMROUT1/PIO1
72
DEN/PIO5
97
TMROUT0/PIO10
A
45
A17/PIO7
46
A16
47
A15
48
A14
73
MCS0/PIO14
98
TMRIN0/PIO11
49
A13
74
MCS1/PIO15
99
DRQ1/PIO13
50
A12
75
INT4
100
DRQ0/PIO12
Am186TMER and Am188TMER Microcontrollers Data Sheet
17
TQFP PIN ASSIGNMENTS—Am186™ER MICROCONTROLLER
(Sorted by Pin Name)
Pin Name
No.
Pin Name
No.
Pin Name
No.
Pin Name
No.
A0
63
AD5
11
GND
93
S2
32
A1
62
AD6
14
HLDA
67
S6/CLKSEL1/PIO29
19
A2
60
AD7
17
HOLD
68
SCLK/PIO20
26
A3
59
AD8
2
INT0
79
SDATA/PIO21
23
A4
58
AD9
4
INT1/SELECT
78
SDEN0/PIO22
25
A5
57
AD10
6
INT2/INTA0
77
SDEN1/PIO23
24
A6
56
AD11
8
INT3/INTA1/IRQ
76
SRDY/PIO6
69
A7
55
AD12
10
INT4
75
TMRIN0/PIO11
98
A8
54
AD13
13
LCS/ONCE0
81
TMRIN1/PIO0
95
A9
53
AD14
16
MCS0/PIO14
A10
52
AD15
18
MCS1/PIO15
A11
51
ALE
30
MCS2
A12
50
ARDY
31
MCS3/RFSH
A13
49
BHE/ADEN
27
NMI
A14
48
CLKOUTA
39
PCS0/PIO16
A15
47
CLKOUTB
40
PCS1/PIO17
A16
46
DEN/PIO5
72
PCS2/PIO18
A17/PIO7
45
DRQ0/PIO12
100
PCS3/PIO19
A18/PIO8
43
DRQ1/PIO13
99
PCS5/A1/PIO3
A19/PIO9
42
DT/R/PIO4
71
AD0
1
GND
AD1
3
GND
AD2
5
GND
7
GND
9
GND
AD3
AD4
18
D
73
TMROUT0/PIO10
T
F
97
74
TMROUT1/PIO1
96
91
TXD
21
92
UCS/ONCE1
80
70
UZI/CLKSEL2/PIO26
20
89
VCC
15
88
VCC
38
86
VCC
44
85
VCC
61
83
VCC
84
PCS6/A2/PIO2
82
VCC
90
12
RD
29
WHB
65
35
RES
94
WLB
66
41
RXD
22
WR
28
64
S0/SREN
34
X1
36
87
S1/IMDIS
33
X2
37
R
A
Am186TMER and Am188TMER Microcontrollers Data Sheet
AD6
DRQ0
DRQ1
TMRIN0
TMROUT0
TMROUT1
TMRIN1
RES
GND
MCS3/ RFSH
MCS2
VCC
PCS 0
PCS 1
GND
PCS 2
PCS 3
VCC
PCS 5/A1
PCS 6/A2
LCS / ONCE 0
UCS / ONCE1
INT0
INT1/ SELECT
INT2/INTA 0
INT3/INTA 1/IRQ
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
Am188ER Microcontroller
14
15
VCC
AO14
AD7
16
17
23
24
D
26
27
28
29
30
31
32
SCLK
RD
ALE
ARDY
R
RFSH2/ADEN
WR
25
35
36
SDATA
SDEN1
A
S1/IMDIS
S0/SREN
GND
X1
X2
21
22
20
33
34
18
19
S2
AO15
S6/CLKSEL1
UZI/CLKSEL2
TXD
RXD
75
74
INT4
73
72
MCS0
DEN
71
70
DT/R
NMI
69
68
SRDY
HOLD
67
66
HLDA
65
64
GND
GND
63
62
A0
A1
61
60
VCC
A2
59
58
A3
A4
57
56
A5
A6
55
A7
54
53
A8
A9
52
51
A10
A11
T
F
49
50
AO13
SDEN0
99
98
12
13
A13
A12
10
11
47
48
AO12
AD5
GND
A15
A14
8
9
45
46
AO11
AD4
VCC
A17
A16
6
7
43
44
AO10
AD3
A18
4
5
41
42
AO9
AD2
39
40
2
3
CLKOUTB
GND
A19
AO8
AD1
37
38
1
VCC
CLKOUTA
AD0
100
TQFP CONNECTION DIAGRAM AND PINOUTS—Am188™ER MICROCONTROLLER
Top Side View—100-Pin Thin Quad Flat Pack (TQFP)
MCS1
WB
Notes:
Pin 1 is marked for orientation.
Am186TMER and Am188TMER Microcontrollers Data Sheet
19
TQFP PIN ASSIGNMENTS—Am188™ER MICROCONTROLLER
(Sorted by Pin Number)
Pin No. Name
20
Pin No. Name
Pin No. Name
Pin No. Name
1
AD0
26
SCLK/PIO20
51
A11
76
INT3/INTA1/IRQ
2
AO8
27
RFSH2/ADEN
52
A10
77
INT2/INTA0/PIO31
3
AD1
28
WR
53
A9
78
INT1/SELECT
4
AO9
29
RD
54
A8
79
INT0
5
AD2
30
ALE
55
A7
80
UCS/ONCE1
6
AO10
31
ARDY
56
A6
81
LCS/ONCE0
7
AD3
32
S2
57
A5
82
PCS6/A2/PIO2
8
AO11
33
S1/IMDIS
58
A4
83
PCS5/A1/PIO3
9
AD4
34
S0/SREN
59
A3
84
VCC
10
AO12
35
GND
60
A2
11
AD5
36
X1
61
VCC
12
GND
37
X2
62
A1
13
AO13
38
VCC
63
A0
14
AD6
39
CLKOUTA
64
GND
15
VCC
40
CLKOUTB
65
GND
16
AO14
41
GND
66
WB
17
AD7
42
A19/PIO9
67
HLDA
18
AO15
43
A18/PIO8
68
HOLD
19
S6/CLKSEL1/PIO29
44
VCC
69
20
UZI/CLKSEL2/PIO26
21
TXD/PIO27
22
RXD/PIO28
23
SDATA/PIO21
24
SDEN1/PIO23
25
SDEN0/PIO22
D
T
F
85
PCS3/PIO19
86
PCS2/PIO18
87
GND
88
PCS1/PIO17
89
PCS0/PIO16
90
VCC
91
MCS2/PIO24
92
MCS3/RFSH/PIO25
93
GND
SRDY/PIO6
94
RES
70
NMI
95
TMRIN1/PIO0
71
DT/R/PIO4
96
TMROUT1/PIO1
45
A17/PIO7
46
A16
47
A15
A
72
DEN/PIO5
97
TMROUT0/PIO10
48
A14
73
MCS0/PIO14
98
TMRIN0/PIO11
49
A13
74
MCS1/PIO15
99
DRQ1/PIO13
50
A12
75
INT4/PIO30
100
DRQ0/PIO12
R
Am186TMER and Am188TMER Microcontrollers Data Sheet
TQFP PIN ASSIGNMENTS—Am188™ER MICROCONTROLLER
(Sorted by Pin Name)
Pin Name
No.
Pin Name
No.
Pin Name
No.
Pin Name
No.
A0
63
AD5
11
GND
93
S1/IMDIS
33
A1
62
AD6
14
HLDA
67
S2
32
A2
60
AD7
17
HOLD
68
S6/CLKSEL1/PIO29
19
A3
59
ALE
30
INT0
79
SCLK/PIO20
26
A4
58
AO8
2
INT1/SELECT
78
SDATA/PIO21
23
A5
57
AO9
4
INT2/INTA0/PIO31
77
SDEN0/PIO22
25
A6
56
AO10
6
INT3/INTA1/IRQ
76
SDEN1/PIO23
24
A7
55
AO11
8
INT4/PIO30
75
SRDY/PIO6
69
A8
54
AO12
10
LCS/ONCE0
81
TMRIN0/PIO11
98
A9
53
AO13
13
MCS0/PIO14
A10
52
AO14
16
MCS1/PIO15
A11
51
AO15
18
MCS2/PIO24
A12
50
ARDY
31
MCS3/RFSH/PIO25
A13
49
CLKOUTA
39
NMI
A14
48
CLKOUTB
40
PCS0/PIO16
A15
47
DEN/PIO5
72
PCS1/PIO17
A16
46
DRQ0/PIO12
100
A17/PIO7
45
DRQ1/PIO13
99
A18/PIO8
43
DT/R/PIO4
71
A19/PIO9
42
GND
AD0
1
GND
AD1
3
GND
AD2
5
GND
7
GND
9
GND
AD3
AD4
D
T
F
73
TMRIN1/PIO0
95
74
TMROUT0/PIO10
97
91
TMROUT1/PIO1
96
92
TXD/PIO27
21
70
UCS/ONCE1
80
89
UZI/CLKSEL2
20
88
VCC
15
86
VCC
38
85
VCC
44
83
VCC
61
PCS6/A2/PIO2
82
VCC
84
RD
29
VCC
90
41
A
RES
94
WB
66
64
RFSH2/ADEN
27
WR
28
65
RXD/PIO28
22
X1
36
87
S0/SREN
34
X2
37
R
12
35
PCS2/PIO18
PCS3/PIO19
PCS5/A1/PIO3
Am186TMER and Am188TMER Microcontrollers Data Sheet
21
81
AD10
AD2
AD9
83
82
AD11
AD3
85
50
47
NMI
DT/R
49
46
SRDY
DEN
MCS0
45
48
44
HLDA
A3
A2
HOLD
36
43
35
A4
42
34
A5
WHB
WLB
33
A6
84
AD12
AD4
87
86
GND
AD5
89
88
AD6
AD13
90
VCC
92
91
AD7
AD14
94
93
AD15
95
96
UZI/CLKSEL2
S6/CLKSEL1
97
98
32
31
R
A8
A7
D
A12
A11
A10
A9
A
41
GND
A19
A18
VCC
A17
A16
A15
A14
A13
Notes:
Pin 1 is marked for orientation.
22
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
AD1
AD8
AD0
DRQ0
DRQ1
TMRIN0
TMROUT0
T
F
Am186ER Microcontroller
40
X1
X2
VCC
CLKOUTA
CLKOUTB
A0
GND
ARDY
S2
S1/IMDIS
S0/SREN
GND
39
RD
ALE
38
BHE/ADEN
WR
37
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VCC
A1
SDEN1
SDEN0
99
100
SDATA
RXD
TXD
PQFP CONNECTION DIAGRAM AND PINOUTS—Am186™ER MICROCONTROLLER
Top Side View—100-Pin Plastic Quad Flat Pack (PQFP)
Am186TMER and Am188TMER Microcontrollers Data Sheet
TMROUT1
TMRIN1
RES
GND
MCS3/RFSH
MCS2
VCC
PCS0
PCS1
GND
PCS2
PCS3
VCC
PCS5/A1
PCS6/A2
LCS/ONCE0
UCS/ONCE1
INT0
INT1/SELECT
INT2/INTA0
INT3/INTA1/IRQ
INT4
MCS1
PQFP PIN ASSIGNMENTS—Am186™ER MICROCONTROLLER
(Sorted by Pin Number)
Pin No. Name
Pin No. Name
Pin No. Name
Pin No. Name
1
SDEN1/PIO23
26
A13
51
MCS1/PIO15
76
DRQ1/PIO13
2
SDEN0/PIO22
27
A12
52
INT4/PIO30
77
DRQ0/PIO12
3
SCLK/PIO20
28
A11
53
INT3/INTA1/IRQ
78
AD0
4
BHE/ADEN
29
A10
54
INT2/INTA0/PIO31
79
AD8
5
WR
30
A9
55
INT1/SELECT
80
AD1
6
RD
31
A8
56
INT0
81
AD9
7
ALE
32
A7
57
UCS/ONCE1
82
AD2
8
ARDY
33
A6
58
LCS/ONCE0
83
AD10
9
S2
34
A5
59
PCS6/A2/PIO2
84
AD3
10
S1/IMDIS
35
A4
60
PCS5/A1/PIO3
11
S0/SREN
36
A3
61
VCC
12
GND
37
A2
62
PCS3/PIO19
13
X1
38
VCC
63
PCS2/PIO18
14
X2
39
A1
64
GND
15
VCC
40
A0
65
PCS1/PIO17
16
CLKOUTA
41
GND
66
PCS0/PIO16
17
CLKOUTB
42
WHB
67
VCC
18
GND
43
WLB
68
MCS2/PIO24
19
A19/PIO9
44
HLDA
69
20
A18/PIO8
45
21
VCC
46
22
A17/PIO7
47
23
A16
48
24
A15
49
25
A14
50
D
T
F
85
AD11
86
AD4
87
AD12
88
AD5
89
GND
90
AD13
91
AD6
92
VCC
93
AD14
MCS3/RFSH/PIO25
94
AD7
70
GND
95
AD15
71
RES
96
S6/CLKSEL1/PIO29
72
TMRIN1/PIO0
97
UZI/CLKSEL2/PIO26
DT/R/PIO4
73
TMROUT1/PIO1
98
TXD/PIO27
DEN/PIO5
74
TMROUT0/PIO10
99
RXD/PIO28
MCS0/PIO14
75
TMRIN0/PIO11
100
SDATA/PIO21
R
HOLD
SRDY/PIO6
NMI
A
Am186TMER and Am188TMER Microcontrollers Data Sheet
23
PQFP PIN ASSIGNMENTS—Am186™ER MICROCONTROLLER
(Sorted by Pin Name)
Pin Name
No.
Pin Name
No.
Pin Name
No.
Pin Name
A0
40
AD5
88
GND
89
S2
9
A1
39
AD6
91
HLDA
44
S6/CLKSEL1/PIO29
96
A2
37
AD7
94
HOLD
45
SCLK/PIO20
3
A3
36
AD8
79
INT0
56
SDATA/PIO21
100
A4
35
AD9
81
INT1/SELECT
55
SDEN0/PIO22
2
A5
34
AD10
83
INT2/INTA0/PIO31
54
SDEN1/PIO23
1
A6
33
AD11
85
INT3/INTA1/IRQ
53
SRDY/PIO6
46
A7
32
AD12
87
INT4/PIO30
52
TMRIN0/PIO11
75
A8
31
AD13
90
LCS/ONCE0
58
TMRIN1/PIO0
72
A9
30
AD14
93
MCS0/PIO14
A10
29
AD15
95
MCS1/PIO15
A11
28
ALE
7
MCS2/PIO24
A12
27
ARDY
8
MCS3/RFSH/PIO25
A13
26
BHE/ADEN
4
NMI
A14
25
CLKOUTA
16
PCS0/PIO16
A15
24
CLKOUTB
17
PCS1/PIO17
A16
23
DEN/PIO5
49
A17/PIO7
22
DRQ0/PIO12
77
A18/PIO8
20
DRQ1/PIO13
76
T
F
A19/PIO9
19
DT/R/PIO4
48
AD0
78
GND
12
AD1
80
GND
AD2
82
GND
84
GND
86
GND
AD3
AD4
24
D
No.
50
TMROUT0/PIO10
74
51
TMROUT1/PIO1
73
68
TXD/PIO27
98
69
UCS/ONCE1
57
47
UZI/CLKSEL2/PIO26
97
66
VCC
15
65
VCC
21
63
VCC
38
62
VCC
61
60
VCC
67
PCS6/A2/PIO2
59
VCC
92
RD
6
WHB
42
RES
71
WLB
43
41
RXD/PIO28
99
WR
5
64
S0/SREN
11
X1
13
70
S1/IMDIS
10
X2
14
R
18
A
PCS2/PIO18
PCS3/PIO19
PCS5/A1/PIO3
Am186TMER and Am188TMER Microcontrollers Data Sheet
81
AD10
AD2
AD9
83
82
AD11
AD3
85
AD1
AD8
AD0
DRQ0
DRQ1
TMRIN0
TMROUT0
50
49
47
NMI
DT/R
TMROUT1
TMRIN1
RES
GND
MCS3/RFSH
MCS2
VCC
PCS0
PCS1
GND
PCS2
PCS3
VCC
PCS5/A1
PCS6/A2
LCS/ONCE0
UCS/ONCE1
INT0
INT1/SELECT
INT2/INTA0
INT3/INTA1/IRQ
INT4
MCS1
DEN
MCS0
46
SRDY
48
45
A3
A2
44
36
HLDA
35
A4
HOLD
34
A5
43
33
A6
84
AD12
AD4
87
86
GND
AD5
89
88
AD6
AD13
90
VCC
92
91
AD7
AD14
94
93
AD15
95
96
UZI/CLKSEL2
S6/CLKSEL1
97
98
32
31
R
A8
A7
D
A12
A11
A10
A9
A
42
GND
A19
A18
VCC
A17
A16
A15
A14
A13
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
T
F
Am188ER Microcontroller
GND
WB
X1
X2
VCC
CLKOUTA
CLKOUTB
41
GND
40
S1/IMDIS
S0/SREN
A0
GND
ARDY
S2
39
RD
ALE
38
RFSH2/ADEN
WR
37
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VCC
A1
SDEN1
SDEN0
99
100
SDATA
RXD
TXD
PQFP CONNECTION DIAGRAM AND PINOUTS—Am188™ER MICROCONTROLLER
Top Side View—100-Pin Plastic Quad Flat Pack (PQFP)
Notes:
Pin 1 is marked for orientation.
Am186TMER and Am188TMER Microcontrollers Data Sheet
25
PQFP PIN ASSIGNMENTS—Am188™ER MICROCONTROLLER
(Sorted by Pin Number)
Pin No. Name
26
Pin No. Name
Pin No. Name
Pin No. Name
1
SDEN1/PIO23
26
A13
51
MCS1/PIO15
76
DRQ1/PIO13
2
SDEN0/PIO22
27
A12
52
INT4/PIO30
77
DRQ0/PIO12
3
SCLK/PIO20
28
A11
53
INT3/INTA1/IRQ
78
AD0
4
RFSH2/ADEN
29
A10
54
INT2/INTA0/PIO31
79
AO8
5
WR
30
A9
55
INT1/SELECT
80
AD1
6
RD
31
A8
56
INT0
81
AO9
7
ALE
32
A7
57
UCS/ONCE1
82
AD2
8
ARDY
33
A6
58
LCS/ONCE0
83
AO10
9
S2
34
A5
59
PCS6/A2/PIO2
84
AD3
10
S1/IMDIS
35
A4
60
PCS5/A1/PIO3
11
S0/SREN
36
A3
61
VCC
12
GND
37
A2
62
PCS3/PIO19
13
X1
38
VCC
63
PCS2/PIO18
14
X2
39
A1
64
GND
15
VCC
40
A0
65
PCS1/PIO17
16
CLKOUTA
41
GND
66
PCS0/PIO16
17
CLKOUTB
42
GND
67
VCC
18
GND
43
WB
68
MCS2/PIO24
19
A19/PIO9
44
HLDA
69
20
A18/PIO8
45
21
VCC
46
22
A17/PIO7
47
23
A16
48
24
A15
49
25
A14
50
D
T
F
85
AO11
86
AD4
87
AO12
88
AD5
89
GND
90
AO13
91
AD6
92
VCC
93
AO14
MCS3/RFSH/PIO25
94
AD7
70
GND
95
AO15
71
RES
96
S6/CLKSEL1/PIO29
72
TMRIN1/PIO0
97
UZI/CLKSEL2/PIO26
DT/R/PIO4
73
TMROUT1/PIO1
98
TXD/PIO27
DEN/PIO5
74
TMROUT0/PIO10
99
RXD/PIO28
MCS0/PIO14
75
TMRIN0/PIO11
100
SDATA/PIO21
R
HOLD
SRDY/PIO6
NMI
A
Am186TMER and Am188TMER Microcontrollers Data Sheet
PQFP PIN ASSIGNMENTS—Am188™ER MICROCONTROLLER
(Sorted by Pin Name)
Pin Name
No.
Pin Name
No.
Pin Name
No.
Pin Name
No.
A0
40
AD5
88
GND
89
S1/IMDIS
10
A1
39
AD6
91
HLDA
44
S2
9
A2
37
AD7
94
HOLD
45
S6/CLKSEL1/PIO29
96
A3
36
ALE
7
INT0
56
SCLK/PIO20
3
A4
35
AO8
79
INT1/SELECT
55
SDATA/PIO21
100
A5
34
AO9
81
INT2/INTA0/PIO31
54
SDEN0/PIO22
2
A6
33
AO10
83
INT3/INTA1/IRQ
53
SDEN1/PIO23
1
A7
32
AO11
85
INT4/PIO30
52
SRDY/PIO6
46
A8
31
AO12
87
LCS/ONCE0
58
TMRIN0/PIO11
75
A9
30
AO13
90
MCS0/PIO14
A10
29
AO14
93
MCS1/PIO15
A11
28
AO15
95
MCS2/PIO24
A12
27
ARDY
8
MCS3/RFSH/PIO25
A13
26
CLKOUTA
16
NMI
A14
25
CLKOUTB
17
PCS0/PIO16
A15
24
DEN/PIO5
49
PCS1/PIO17
A16
23
DRQ0/PIO12
77
PCS2/PIO18
A17/PIO7
22
DRQ1/PIO13
76
PCS3/PIO19
A18/PIO8
20
DT/R/PIO4
48
PCS5/A1/PIO3
A19/PIO9
19
GND
AD0
78
GND
AD1
80
GND
AD2
82
GND
84
GND
86
GND
AD3
AD4
D
R
A
50
TMRIN1/PIO0
T
F
72
51
TMROUT0/PIO10
74
68
TMROUT1/PIO1
73
69
TXD/PIO27
98
47
UCS/ONCE1
57
66
UZI/CLKSEL2/PIO26
97
65
VCC
15
63
VCC
21
62
VCC
38
60
VCC
61
12
PCS6/A2/PIO2
59
VCC
67
18
RD
6
VCC
92
41
RES
71
WB
43
42
RFSH2/ADEN
4
WR
5
64
RXD/PIO28
99
X1
13
70
S0/SREN
11
X2
14
Am186TMER and Am188TMER Microcontrollers Data Sheet
27
LOGIC SYMBOL—Am186™ER MICROCONTROLLER
Clocks
X1
RES
X2
INT4
CLKOUTA
INT3/INTA1/IRQ
CLKOUTB
INT2/INTA0
*
*
Reset Control and
Interrupt Service
INT1/SELECT
INT0
*
Address and
Address/Data Buses
20
A19–A0
16
AD15–AD0
*
S6/CLKSEL1
*
UZI/CLKSEL2
NMI
PCS6/A2
*
T
F
PCS5/A1
ALE
S2
S1/IMDIS
LCS/ONCE0
S0/SREN
MCS3/RFSH
HOLD
HLDA
RD
WR
Bus Control
*
DT/R
*
DEN
R
ARDY
SRDY
*
BHE/ADEN
D
Timer Control
Programmable
I/O Control
WHB
MCS2–MCS0
*
Memory and
Peripheral Control
*
3
*
UCS/ONCE1
A
2
DRQ1–DRQ0
*
DMA Control
TXD
*
RXD
*
Asynchronous
Serial Port Control
WLB
*
TMRIN0
*
TMROUT0
*
TMRIN1
*
TMROUT1
SDEN1–SDEN0
32
shared
**
PCS3–PCS0
*
4
PIO32–PIO0
2
*
SCLK
*
SDATA
*
Synchronous
Serial Port Control
Notes:
* These signals are the normal function of a pin that can be used as a PIO. See the pin descriptions beginning on page 30 and
Table 3 on page 36 for information on shared function.
** All PIO signals are shared with other physical pins.
28
Am186TMER and Am188TMER Microcontrollers Data Sheet
LOGIC SYMBOL—Am188™ER MICROCONTROLLER
Clocks
X1
RES
X2
INT4
CLKOUTA
INT3/INTA1/IRQ
CLKOUTB
INT2/INTA0
*
*
Reset Control and
Interrupt Service
INT1/SELECT
INT0
*
Address and
Address/Data Buses
20
A19–A0
8
AO15–AO8
8
AD7–AD0
NMI
*
S6/CLKSEL1
PCS6/A2
*
UZI/CLKSEL2
PCS5/A1
T
F
PCS3–PCS0
ALE
S2
S1/IMDIS
S0/SREN
HOLD
HLDA
RD
Bus Control
WR
*
*
DT/R
R
DEN
ARDY
*
D
Timer Control
Programmable
I/O Control
SRDY
RFSH2/ADEN
*
4
*
Memory and
Peripheral Control
LCS/ONCE0
MCS3/RFSH
MCS2–MCS0
*
3
*
UCS/ONCE1
A
2
DRQ1–DRQ0
*
DMA Control
TXD
*
RXD
*
Asynchronous
Serial Port Control
WB
*
TMRIN0
*
TMROUT0
*
TMRIN1
*
TMROUT1
SDEN1–SDEN0
32
shared
**
*
PIO31–PIO0
2
*
SCLK
*
SDATA
*
Synchronous
Serial Port Control
Notes:
* These signals are the normal function of a pin that can be used as a PIO. See the pin descriptions beginning on page 30 and
Table 3 on page 36 for information on shared function.
** All PIO signals are shared with other physical pins.
Am186TMER and Am188TMER Microcontrollers Data Sheet
29
PIN DESCRIPTIONS
Pins Used by Emulators
The following pins are used by emulators: A19–A0,
AO15–AO8, AD7–AD0, ALE, BHE/ADEN (on the
Am186ER microcontroller), CLKOUTA, RFSH2/ADEN
(on the Am188ER microcontroller), RD, S2, S1/IMDIS,
S0/SREN, S6/CLKSEL1, and UZI/CLKSEL2.
Emulators require that S6/CLKSEL1 and UZI/
CLKSEL2 be configured in their normal functionality,
that is, as S6 and UZI. If BHE/ADEN (on the Am186ER
microcontroller) or RFSH2/ADEN (on the Am188ER
microcontroller) is held Low during the rising edge of
RES, S6 and UZI are configured in their normal functionality and cannot be programmed as PIOs.
A19–A0
(A19/PIO9, A18/PIO8, A17/PIO7)
Address Bus (output, three-state, synchronous)
These pins supply nonmultiplexed memory or I/O addresses to the system one-half of a CLKOUTA period
earlier than the multiplexed address and data bus
(AD15–AD0 on the Am186ER microcontroller or
AO15–AO8 and AD7–AD0 on the Am188ER microcontroller). During a bus hold or reset condition, the address bus is in a high-impedance state.
AD7–AD0
Address and Data Bus (input/output, three-state,
synchronous, level-sensitive)
These time-multiplexed pins supply partial memory or
I/O addresses, as well as data, to the system. AD7–
AD0 supply the low-order 8 bits of an address to the
system during the first period of a bus cycle (t1). On a
write, these pins supply data to the system during the
remaining periods of that cycle (t2, t3, and t4). On a
read, these pins latch data at the end of t3.
D
R
Also, if S0/SREN (show read enable) was pulled Low
during reset or if the SR bit is set in the Internal Memory
Chip Select (IMCS) Register, these pins supply the
data read from internal memory during t3 and t4.
On the Am186ER microcontroller, AD7–AD0 combine
with AD15–AD8 to form a complete multiplexed address and 16-bit data bus.
On the Am188ER microcontroller, AD7–AD0 combine
with AO15–AO8 to form a complete multiplexed address bus while AD7–AD0 is the 8-bit data bus.
The address phase of these pins can be disabled. See
the ADEN description with the BHE/ADEN pin. When
WLB is negated, these pins are three-stated during t2,
t3, and t4.
During a bus hold or reset condition, the address and
data bus are in a high-impedance state.
30
During a power-on reset, the address and data bus
pins (AD15–AD0 for the Am186ER microcontroller,
AO15–AO8 and AD7–AD0 for the Am188ER microcontroller) can also be used to load system configuration
information into the internal reset configuration register. The system information is latched on the rising
edge of RES.
AD15–AD8 (Am186™ER Microcontroller)
Address and Data Bus (input/output, three-state,
synchronous, level-sensitive)
These time-multiplexed pins supply partial memory or
I/O addresses, as well as data, to the system. AD15–
AD8 supply the high-order 8 bits of an address to the
system during the first period of a bus cycle (t1). On a
write, these pins supply data to the system during the
remaining periods of that cycle (t 2, t3, and t4). On a
read, these pins latch data at the end of t3.
T
F
Also, if S0/SREN (show read enable) was pulled Low
during reset or if the SR bit is set in the Internal Memory
Chip Select (IMCS) Register, these pins supply the
data read from internal memory during t3 and t4.
On the Am186ER microcontroller, AD15–AD8 combine
with AD7–AD0 to form a complete multiplexed address
and 16-bit data bus.
A
The address phase of these pins can be disabled. See
the ADEN description with the BHE/ADEN pin. When
WHB is negated, these pins are three-stated during t2,
t3, and t4.
During a bus hold or reset condition, the address and
data bus is in a high-impedance state.
During a power-on reset, the address and data bus
pins (AD15–AD0 for the Am186ER microcontroller,
AO15–AO8 and AD7–AD0 for the Am188ER microcontroller) can also be used to load system configuration
information into the internal reset configuration register. The system information is latched on the rising
edge of RES.
AO15–AO8 (Am188™ER Microcontroller)
Address-Only Bus (output, three-state,
synchronous, level-sensitive)
On the Am188ER microcontroller, the address-only
bus (AO15–AO8) contains valid high-order address bits
from bus cycles t1–t4. These outputs are three-stated
during a bus hold or reset.
On the Am188ER microcontroller, AO15–AO8 combine
with AD7–AD0 to form a complete multiplexed address
bus while AD7–AD0 is the 8-bit data bus.
On the Am188ER microcontroller during a power-on
reset, the AO15–AO8 and AD7–AD0 pins can also be
used to load system configuration information into an
internal register for later use.
Am186TMER and Am188TMER Microcontrollers Data Sheet
ALE
Address Latch Enable (output, synchronous)
This pin indicates to the system that an address appears on the address and data bus (AD15–AD0 for
the Am186ER microcontroller or AO15–AO8 and
AD7–AD0 for the Am188ER microcontroller). The address is guaranteed valid on the trailing edge of ALE.
This pin is three-stated during ONCE mode.
ARDY
Asynchronous Ready (input, asynchronous,
level-sensitive)
This pin indicates to the microcontroller that the addressed memory space or I/O device will complete a
data transfer. The ARDY pin accepts a rising edge that
is asynchronous to CLKOUTA and is active High. The
falling edge of ARDY must be synchronized to
CLKOUTA. To always assert the ready condition to the
microcontroller, tie ARDY High. If the system does not
use ARDY, tie the pin Low to yield control to SRDY.
reason, the A0 signal cannot be used in place of the
AD0 signal to determine refresh cycles. PSRAM refreshes also provide an additional RFSH signal (see
the MCS3/RFSH pin description on page 33).
ADEN—If BHE/ADEN is held High or left floating during power-on reset, the address portion of the AD bus
(AD15–AD0) is enabled or disabled during LCS and
UCS bus cycles based on the DA bit in the LMCS and
UMCS registers. If the DA bit is set, the memory address is accessed on the A19–A0 pins. This mode of
operation reduces power consumption. For more information, see the Bus Operation section on page 41.
There is a weak internal pullup resistor on BHE/ADEN
so no external pullup is required.
BHE/ADEN
(Am186™ER Microcontroller Only)
If BHE/ADEN is held Low on power-on reset, the AD
bus drives both addresses and data. Changing the DA
bit of the LMCS and UMCS registers will have no effect.
(S6 and UZI also assume their normal functionality in
this instance. The PIO Mode and Direction registers
cannot reconfigure these pins as PIOs. See Table 3 on
page 36.) The pin is sampled within three crystal clock
cycles after the rising edge of RES. BHE/ADEN is
three-stated during bus holds and ONCE mode.
Bus High Enable (three-state, output, synchronous)
Address Enable (input, internal pullup)
Note: Once the above modes are set, they can be
changed only by resetting the processor.
BHE—During a memory access, this pin and the leastsignificant address bit (AD0 or A0) indicate to the system which bytes of the data bus (upper, lower, or both)
participate in a bus cycle. The BHE/ADEN and AD0
pins are encoded as shown in Table 2.
R
BHE is asserted during t 1 and remains asser ted
through t3 and tW. BHE does not need to be latched.
BHE is three-stated during bus hold and reset conditions.
On the Am186ER microcontroller, WLB and WHB implement the functionality of BHE and AD0 for high and
low byte write enables.
D
Table 2. Data Byte Encoding
BHE
AD0 Type of Bus Cycle
0
0
0
1
High Byte Transfer (Bits 15–8)
1
0
Low Byte Transfer (Bits 7–0)
1
1
Refresh
Word Transfer
A
CLKOUTA
T
F
Clock Output A (output, synchronous)
This pin supplies the internal clock to the system. Depending on the value of the Power-Save Control Register (PDCON), CLKOUTA operates at either the CPU
fundamental frequency (which varies with the divide by
two, times one, and times four clocking modes), the
power-save frequency, or is three-stated (see Figure 10
on page 48). CLKOUTA remains active during reset
and bus hold conditions.
CLKOUTB
Clock Output B (output, synchronous)
This pin supplies a clock to the system. Depending on
the value of the Power-Save Control Register (PDCON), CLKOUTB operates at either the CPU fundamental frequency (which varies with the divide by two,
times one, and times four clocking modes), the powersave frequency, or is three-stated (see Figure 10 on
page 48). CLKOUTB remains active during reset and
bus hold conditions.
DEN/PIO5
Data Enable (output, three-state, synchronous)
BHE/ADEN also signals DRAM refresh cycles when
using the multiplexed address and data (AD) bus. A refresh cycle is indicated when both BHE/ADEN and AD0
are High. During refresh cycles, the A bus and the AD
bus are not guaranteed to provide the same address
during the address phase of the AD bus cycle. For this
This pin supplies an output enable to an external databus transceiver. DEN is asserted during memory, I/O,
and interrupt acknowledge cycles. DEN is deasserted
when DT/R changes state. DEN is three-stated during
a bus hold or reset condition.
Am186TMER and Am188TMER Microcontrollers Data Sheet
31
DRQ1–DRQ0
(DRQ1/PIO13, DRQ0/PIO12)
DMA Requests (input, synchronous,
level-sensitive)
These pins indicate to the microcontroller that an external device is ready for DMA channel 1 or channel 0 to
perform a transfer. DRQ1–DRQ0 are level-triggered
and internally synchronized.
The DRQ signals are not latched and must remain active until serviced.
DT/R/PIO4
Data Transmit or Receive (output, three-state,
synchronous)
This pin indicates which direction data should flow
through an external data-bus transceiver. When DT/R
is asserted High, the microcontroller transmits data.
When this pin is deasserted Low, the microcontroller
receives data. DT/R is three-stated during a bus hold or
reset condition.
GND
Ground
The ground pins connect the system ground to the microcontroller.
HLDA
Bus Hold Acknowledge (output, synchronous)
When an external bus master requests control of the
local bus (by asserting HOLD), the microcontroller
completes the bus cycle in progress and then relinquishes control of the bus to the external bus master by
asserting HLDA and floating DEN, RD, WR, S2–S0,
AD15–AD0, S6, A19–A0, BHE, WHB, WLB, and DT/R,
and then driving the chip selects UCS, LCS, MCS3–
MCS0, PCS6–PCS5, and PCS3–PCS0 High.
D
R
When the external bus master has finished using the
local bus, it indicates this to the microcontroller by
deasserting HOLD. The microcontroller responds by
deasserting HLDA.
If the microcontroller requires access to the bus (that is,
for refresh), it will deassert HLDA before the external
bus master deasserts HOLD. The external bus master
must be able to deassert HOLD and allow the microcontroller access to the bus. See the timing diagrams
for bus hold on page 101. This pin is three-stated during ONCE mode.
HOLD
The Am186ER and Am188ER microcontrollers’ HOLD
latency time, the time between HOLD request and
HOLD acknowledge, is a function of the activity occurring in the processor when the HOLD request is received. A HOLD request is second only to DRAM or
PSRAM refresh requests in priority of activity requests
received by the processor. This implies that if a HOLD
request is received just as a DMA transfer begins, the
HOLD latency can be as great as four bus cycles. This
occurs if a DMA word transfer operation is taking place
(Am186ER microcontroller only) from an odd address
to an odd address. This is a total of 16 clock cycles or
more if wait states are required. In addition, if locked
transfers are performed, the HOLD latency time is increased by the length of the locked transfer.
INT0
Maskable Interrupt Request 0 (input,
asynchronous)
T
F
This pin indicates to the microcontroller that an interrupt request has occurred. If the INT0 pin is not
masked, the microcontroller transfers program execution to the location specified by the INT0 vector in the
microcontroller interrupt vector table.
Interrupt requests are synchronized internally and can
be edge-triggered or level-triggered. To guarantee interrupt recognition, the requesting device must continue asserting INT0 until the request is acknowledged.
A
INT1/SELECT
Maskable Interrupt Request 1 (input,
asynchronous)
Slave Select (input, asynchronous)
INT1—This pin indicates to the microcontroller that an
interrupt request has occurred. If INT1 is not masked,
the microcontroller transfers program execution to the
location specified by the INT1 vector in the microcontroller interrupt vector table.
Interrupt requests are synchronized internally and can
be edge-triggered or level-triggered. To guarantee interrupt recognition, the requesting device must continue asserting INT1 until the request is acknowledged.
SELECT—When the microcontroller interrupt control
unit is operating as a slave to an external master interrupt controller, this pin indicates to the microcontroller
that an interrupt type appears on the address and data
bus. The INT0 pin must indicate to the microcontroller
that an interrupt has occurred before the SELECT pin
indicates to the microcontroller that the interrupt type
appears on the bus.
Bus Hold Request (input, synchronous,
level-sensitive)
This pin indicates to the microcontroller that an external
bus master needs control of the local bus. For more information, see the HLDA pin description.
32
Am186TMER and Am188TMER Microcontrollers Data Sheet
INT2/INTA0/PIO31
INT4/PIO30
Maskable Interrupt Request 2 (input,
asynchronous)
Interrupt Acknowledge 0 (output, synchronous)
Maskable Interrupt Request 4 (input,
asynchronous)
INT2—This pin indicates to the microcontroller that an
interrupt request has occurred. If the INT2 pin is not
masked, the microcontroller transfers program execution to the location specified by the INT2 vector in the
microcontroller interrupt vector table.
Interrupt requests are synchronized internally and can
be edge-triggered or level-triggered. To guarantee interrupt recognition, the requesting device must continue asserting INT2 until the request is acknowledged.
INT2 becomes INTA0 when INT0 is configured in cascade mode.
INTA0—When the microcontroller interrupt control unit
is operating in cascade mode, this pin indicates to the
system that the microcontroller needs an interrupt type
to process the interrupt request on INT0. The peripheral issuing the interrupt request must provide the microcontroller with the corresponding interrupt type.
INT3/INTA1/IRQ
Maskable Interrupt Request 3
(input, asynchronous)
Interrupt Acknowledge 1 (output, synchronous)
Slave Interrupt Request (output, synchronous)
INT3—This pin indicates to the microcontroller that an
interrupt request has occurred. If the INT3 pin is not
masked, the microcontroller then transfers program execution to the location specified by the INT3 vector in
the microcontroller interrupt vector table.
R
Interrupt requests are synchronized internally, and can
be edge-triggered or level-triggered. To guarantee interrupt recognition, the requesting device must continue asserting INT3 until the request is acknowledged.
INT3 becomes INTA1 when INT1 is configured in cascade mode.
D
INTA1—When the microcontroller interrupt control unit
is operating in cascade mode, this pin indicates to the
system that the microcontroller needs an interrupt type
to process the interrupt request on INT1. The peripheral issuing the interrupt request must provide the microcontroller with the corresponding interrupt type.
IRQ—When the microcontroller interrupt control unit is
operating as a slave to an external master interrupt
controller, this pin lets the microcontroller issue an interrupt request to the external master interrupt controller.
This pin indicates to the microcontroller that an interrupt request has occurred. If the INT4 pin is not
masked, the microcontroller then transfers program execution to the location specified by the INT4 vector in
the microcontroller interrupt vector table.
Interrupt requests are synchronized internally and can
be edge-triggered or level-triggered. To guarantee interrupt recognition, the requesting device must continue asserting INT4 until the request is acknowledged.
LCS/ONCE0
Lower Memory Chip Select (output, synchronous,
internal pullup)
ONCE Mode Request 0 (input)
T
F
LCS—This pin indicates to the system that a memory
access is in progress to the lower memory block. The
size of the lower memory block is programmable up to
512 Kbyte. LCS is held High during a bus hold condition.
ONCE0—During reset, this pin and ONCE1 indicate to
the microcontroller the mode in which it should operate.
ONCE0 and ONCE1 are sampled on the rising edge of
RES. If both pins are asserted Low, the microcontroller
enters ONCE mode; otherwise, it operates normally.
A
In ONCE mode, all pins assume a high-impedance
state and remain in that state until a subsequent reset
occurs. To guarantee that the microcontroller does not
inadvertently enter ONCE mode, ONCE0 has a weak
internal pullup resistor that is active only during reset.
MCS3/RFSH/PIO25
Midrange Memory Chip Select 3
(output, synchronous, internal pullup)
Automatic Refresh (output, synchronous)
MCS3—This pin indicates to the system that a memory
access is in progress to the four th region of the
midrange memory block. The base address and size of
the midrange memory block are programmable. MCS3
is held High during a bus hold condition. In addition,
this pin has a weak internal pullup resistor that is active
during reset.
RFSH—This pin provides a signal timed for auto refresh to PSRAM devices. It is only enabled to function
as a refresh pulse when the PSRAM mode bit is set in
the LMCS Register. An active Low pulse is generated
for 1.5 clock cycles with an adequate deassertion period to ensure that overall auto refresh cycle time is
met.
Am186TMER and Am188TMER Microcontrollers Data Sheet
33
MCS2–MCS0
(MCS2/PIO24, MCS1/PIO15, MCS0/PIO14)
Midrange Memory Chip Selects (output,
synchronous, internal pullup)
These pins indicate to the system that a memory access is in progress to the corresponding region of the
midrange memory block. The base address and size of
the midrange memory block are programmable.
MCS2–MCS0 are held High during a bus hold condition. In addition, they have weak internal pullup resistors that are active during reset. Unlike the UCS and
LCS chip selects, the MCS outputs assert with the multiplexed AD address bus.
peripheral memory block (either I/O or memory address space). The base address of the peripheral
memory block is programmable. PCS3–PCS0 are held
High during a bus hold condition. They are also held
High during reset.
PCS4 is not available on the Am186ER and Am188ER
microcontrollers.
Unlike the UCS/LCS chip selects, the PCS outputs assert with the multiplexed AD address bus. Note also
that each peripheral chip select asser ts over a
256-byte address range, which is twice the address
range covered by peripheral chip selects in the
80C186/80C188 microcontrollers.
NMI
PCS5/A1/PIO3
Nonmaskable Interrupt (input, synchronous, edgesensitive)
Peripheral Chip Select 5 (output, synchronous)
Latched Address Bit 1 (output, synchronous)
This pin indicates to the microcontroller that an interrupt request has occurred. The NMI signal is the highest priority hardware interrupt and, unlike the INT4–
INT0 pins, cannot be masked. The microcontroller always transfers program execution to the location specified by the nonmaskable interrupt vector in the
microcontroller interrupt vector table when NMI is asserted.
PCS5—This pin indicates to the system that a memory
access is in progress to the sixth region of the peripheral memory block (either I/O or memory address
space). The base address of the peripheral memory
block is programmable. PCS5 is held High during a bus
hold condition. It is also held High during reset.
Although NMI is the highest priority interrupt source, it
does not participate in the priority resolution process of
the maskable interrupts. There is no bit associated with
NMI in the interrupt in-service or interrupt request registers. This means that a new NMI request can interrupt
an executing NMI interrupt service routine. As with all
hardware interrupts, the IF (interrupt flag) is cleared
when the processor takes the interrupt, disabling the
maskable interrupt sources. However, if maskable interrupts are reenabled by software in the NMI interrupt
service routine, via the STI instruction for example, an
NMI currently in service will not have any effect on the
priority resolution of maskable interrupt requests. For
this reason, it is strongly advised that the interrupt service routine for NMI does not enable the maskable interrupts.
D
R
An NMI transition from Low to High is latched and synchronized internally, and it initiates the interrupt at the
next instruction boundary. To guarantee that the interrupt is recognized, the NMI pin must be asserted for at
least one CLKOUTA period. Because NMI is rising
edge sensitive, holding the pin High during reset has no
effect on program execution.
PCS3–PCS0
(PCS3/PIO19, PCS2/PIO18,
PCS1/PIO17, PCS0/PIO16)
Peripheral Chip Selects (output, synchronous)
These pins indicate to the system that a memory access is in progress to the corresponding region of the
34
T
F
Unlike the UCS and LCS chip selects, the PCS outputs
assert with the multiplexed AD address bus. Note also
that each peripheral chip select asser ts over a
256-byte address range, which is twice the address
range covered by peripheral chip selects in the 80C186
and 80C188 microcontrollers.
A
A1—When the EX bit in the MCS and PCS auxiliary
register is 0, this pin supplies an internally latched address bit 1 to the system. During a bus hold condition,
A1 retains its previously latched value.
PCS6/A2/PIO2
Peripheral Chip Select 6 (output, synchronous)
Latched Address Bit 2 (output, synchronous)
PCS6—This pin indicates to the system that a memory
access is in progress to the seventh region of the peripheral memory block (either I/O or memory address
space). The base address of the peripheral memory
block is programmable. PCS6 is held High during a bus
hold condition or reset.
Unlike the UCS and LCS chip selects, the PCS outputs
assert with the multiplexed AD address bus. Note also
that each peripheral chip select asser ts over a
256-byte address range, which is twice the address
range covered by peripheral chip selects in earlier generations of the Am186/Am188 microcontrollers.
A2—When the EX bit in the MCS and PCS auxiliary
register is 0, this pin supplies an internally latched address bit 2 to the system. During a bus hold condition,
A2 retains its previously latched value.
Am186TMER and Am188TMER Microcontrollers Data Sheet
PIO31–PIO0 (Shared)
Programmable I/O Pins (input/output,
asynchronous, open-drain)
The Am186ER and Am188ER microcontrollers provide
32 individually programmable I/O pins. Each PIO can
be programmed with the following attributes: PIO function (enabled/disabled), direction (input/output), and
weak pullup or pulldown.
On the Am186ER and Am188ER microcontrollers, the
internal pullup resistor has a value of approximately
100 kohms. The internal pulldown resistor has a value
of approximately 100 kohms.
The pins that are multiplexed with PIO31–PIO0 are
listed in Table 3 and Table 4 on page 36.
After power-on reset, the PIO pins default to various
configurations. The column titled Power-On Reset Status in Table 3 and Table 4 lists the defaults for the PIOs.
The system initialization code must reconfigure any
PIOs as required.
If PIO29 (S6/CLKSEL1) is to be used in input mode, the
input device must not drive PIO29 Low during poweron reset. The pin defaults to a PIO input with pullup, so
it does not need to be driven High externally.
The A19–A17 address pins default to normal operation
on power-on reset, allowing the processor to correctly
begin fetching instructions at the boot address
FFFF0h. The DT/R, DEN, and SRDY pins also default
to normal operation on power-on reset.
RD
R
Read Strobe (output, synchronous, three-state)
This pin indicates to the system that the microcontroller
is performing a memory or I/O read cycle. RD is guaranteed not to be asserted before the address and data
bus is floated during the address-to-data transition. RD
is three-stated during bus holds and ONCE mode.
RES
D
Reset (input, asynchronous, level-sensitive)
This pin requires the microcontroller to perform a reset.
When RES is asserted, the microcontroller immediately terminates its present activity, clears its internal
logic, and CPU control is transferred to the reset address FFFF0h.
RES must be held Low for at least 1 ms.
RES can be asserted asynchronously to CLKOUTA because RES is synchronized internally. For proper initialization, V CC must be within specifications, and
CLKOUTA must be stable for more than four CLKOUTA
periods during which RES is asserted.
serted. This input is provided with a Schmitt trigger to
facilitate power-on RES generation via an RC network.
RFSH2/ADEN
(Am188™ER Microcontroller Only)
Refresh 2 (three-state, output, synchronous)
Address Enable (input, internal pullup)
RFSH2—Asserted Low to signify a DRAM refresh bus
cycle. The use of RFSH2/ADEN to signal a refresh is
not valid when PSRAM mode is selected. Instead, the
MCS3/RFSH signal is provided to the PSRAM. During
reset, this pin is a pullup. This pin is three-stated during
bus holds and ONCE mode.
ADEN—If RFSH2/ADEN is held High or left floating on
power-on reset, the AD bus (AO15–AO8 and AD7–AD0)
is enabled or disabled during the address portion of LCS
and UCS bus cycles based on the DA bit in the LMCS
and UMCS registers. If the DA bit is set, the memory address is accessed on the A19–A0 pins. This mode of operation reduces power consumption. For more
information, see the Bus Operation section on page 41.
There is a weak internal pullup resistor on RFSH2/
ADEN so no external pullup is required.
T
F
If RFSH2/ADEN is held Low on power-on reset, the AD
bus drives both addresses and data. Changing the DA
bit of the LMCS and UMCS registers will have no effect.
(S6 and UZI also assume their normal functionality in
this instance. The PIO Mode and Direction registers
cannot reconfigure these pins as PIOs. See Table 3
and Table 4 on page 36.) The pin is sampled within
three crystal clock cycles after the rising edge of RES.
RFSH2/ADEN is three-stated during bus holds and
ONCE mode.
A
Note: Once the above modes are set, they can be
changed only by resetting the processor.
RXD/PIO28
Receive Data (input, asynchronous)
This pin supplies asynchronous serial receive data
from the system to the internal UART of the microcontroller.
S2
Bus Cycle Status (output, three-state,
synchronous)
S2—This pin indicates to the system the type of bus
cycle in progress. S2 can be used as a logical memory
or I/O indicator. S2–S0 are three-stated during bus
holds, hold acknowledges, and ONCE mode. During
reset, these pins are pullups. The S2–S0 pins are encoded as shown in Table 5 on page 37.
The microcontroller begins fetching instructions approximately 6.5 CLKOUTA periods after RES is deas-
Am186TMER and Am188TMER Microcontrollers Data Sheet
35
Table 3. Numeric PIO Pin Assignments
PIO No.
0
Associated Pin
TMRIN1
Power-On Reset Status
Input with pullup
Table 4.
Alphabetic PIO Pin Assignments
Associated Pin
PIO No. Power-On Reset Status
(1)
7
Normal operation(3)
(1)
A17
1
TMROUT1
Input with pulldown
A18
8
Normal operation(3)
2
PCS6/A2
Input with pullup
A19(1)
9
Normal operation(3)
3
PCS5/A1
Input with pullup
DEN
5
Normal operation(3)
4
DT/R
Normal operation(3)
DRQ0
12
Input with pullup
5
DEN
Normal operation(3)
DRQ1
13
Input with pullup
SRDY
Normal operation
(4)
DT/R
4
Normal operation(3)
A17
Normal operation(3)
INT2
31
Input with pullup
(1)
A18
Normal operation
(3)
INT4
30
Input with pullup
9(1)
A19
Normal operation(3)
MCS0
14
Input with pullup
10
TMROUT0
Input with pulldown
MCS1
15
Input with pullup
11
TMRIN0
Input with pullup
MCS2
24
Input with pullup
12
DRQ0
Input with pullup
MCS3/RFSH
13
DRQ1
Input with pullup
PCS0
14
MCS0
Input with pullup
PCS1
15
MCS1
Input with pullup
PCS2
16
PCS0
Input with pullup
PCS3
17
PCS1
Input with pullup
PCS5/A1
18
PCS2
Input with pullup
PCS6/A2
19
PCS3
Input with pullup
6
7(1)
8
20
SCLK
Input with pullup
21
SDATA
Input with pullup
22
SDEN0
Input with pulldown
23
SDEN1
Input with pulldown
24
MCS2
Input with pullup
25
MCS3/RFSH
Input with pullup
26(1,2)
UZI/CLKSEL2
Input with pullup
D
R
T
F
25
Input with pullup
16
Input with pullup
17
Input with pullup
18
Input with pullup
19
Input with pullup
3
Input with pullup
2
Input with pullup
28
Input with pullup
29
Input with pullup
20
Input with pullup
21
Input with pullup
SDEN0
22
Input with pulldown
SDEN1
23
Input with pulldown
SRDY
6
Normal operation(4)
TMRIN0
11
Input with pullup
A
RXD
S6/CLKSEL1(1,2)
SCLK
SDATA
27
TXD
Input with pullup
TMRIN1
0
Input with pullup
28
RXD
Input with pullup
TMROUT0
10
Input with pulldown
S6/CLKSEL1
Input with pullup
TMROUT1
1
Input with pulldown
INT4
Input with pullup
TXD
27
Input with pullup
Input with pullup
UZI/CLKSEL2(1,2)
26
Input with pullup
29(1,2)
30
31
Notes:
INT2
Notes:
1. These pins are used by emulators. (Emulators also use
S2–S0, RES, NMI, CLKOUTA, BHE, ALE, AD15–AD0,
and A16–A0.)
1. These pins are used by emulators. (Emulators also use
S2–S0, RES, NMI, CLKOUTA, BHE, ALE, AD15–AD0,
and A16–A0.)
2. These pins revert to normal operation if BHE/ADEN
(Am186ER microcontroller) or RFSH2/ADEN (Am188ER
microcontroller) is held Low during power-on reset.
3. When used as a PIO, input with pullup option available.
4. When used as a PIO, input with pulldown option available.
2. These pins revert to normal operation if BHE/ADEN
(Am186ER microcontroller) or RFSH2/ADEN (Am188ER
microcontroller) is held Low during power-on reset.
3. When used as a PIO, input with pullup option available.
4. When used as a PIO, input with pulldown option available.
36
Am186TMER and Am188TMER Microcontrollers Data Sheet
S1/IMDIS
Bus Cycle Status (output, three-state,
synchronous)
Internal Memory Disable (input, internal pullup)
S1—This pin indicates to the system the type of bus
cycle in progress. S1 can be used as a data transmit or
receive indicator. S2–S0 are three-stated during bus
holds, hold acknowledges, and ONCE mode. During
reset, these pins are pullups. The S2–S0 pins are encoded as shown in Table 5.
IMDIS—If asserted during reset, this pin disables internal memory. Internal memory disable mode is provided
for emulation and debugging purposes.
S0/SREN
Bus Cycle Status (output, three-state,
synchronous)
Show Read Enable (input, internal pullup)
S0—This pin indicates to the system the type of bus
cycle in progress. S2–S0 are three-stated during bus
holds, hold acknowledges, and ONCE mode. During
reset, these pins are pullups. The S2–S0 pins are encoded as shown in Table 5.
SREN—If asserted during reset, this pin enables data
read from internal memory to be shown/driven on the
AD15–AD0 bus. Note that if a byte read is being shown,
the unused byte will also be driven on the AD15–AD0
bus.This mode is provided for emulation and debugging purposes.
R
Table 5. Bus Cycle Encoding
Bus Cycle
CLKSEL1—The clocking mode of the Am186ER and
Am188ER microcontrollers is controlled by UZI/
CLKSEL2/PIO26 and S6/CLKSEL1/PIO29. Both
CLKSEL2 and CLKSEL1 are held High during poweron reset because of an internal pullup resistor. This is
the default clocking mode—Times Four. If CLKSEL1 is
held Low during power-on reset, the chip enters the Divide by Two clocking mode where the fundamental
clock is derived by dividing the external clock input by
2. If Divide by Two mode is selected, the PLL is disabled. This pin is latched within three crystal clock cycles after the rising edge of RES. Refer to Reset
Waveforms on page 100 and Signals Related to Reset
Waveforms on page 100 to determine signal hold
times. See Table 6 on page 39 for more information on
the clocking modes.
If S6 is used as PIO29 in input mode, the device driving
PIO29 must not drive the pin Low during power-on reset.
S6/CLKSEL1/PIO29 defaults to a PIO input with pullup,
so the pin does not need to be driven High externally.
SCLK/PIO20
T
F
Serial Clock (output, synchronous)
This pin supplies the synchronous serial interface (SSI)
clock to a slave device, allowing transmit and receive
operations to be synchronized between the microcontroller and the slave. SCLK is derived from the microcontroller internal clock and then divided by 2, 4, 8, or
16 depending on register settings.
A
An access to any of the SSR or SSD registers activates SCLK for eight SCLK cycles (see Figure 14 and
Figure 15 on page 58). When SCLK is inactive, it is
held High by the microcontroller. SCLK is three-stated
during ONCE mode.
S2
S1
S0
0
0
0
Interrupt acknowledge
SDATA/PIO21
0
0
1
Read data from I/O
Serial Data (input/output, synchronous)
0
1
0
Write data to I/O
0
1
1
Halt
1
0
0
Instruction fetch
This pin transmits and receives synchronous serial interface (SSI) data to and from a slave device. When
SDATA is inactive, a weak keeper holds the last value
of SDATA on the pin.
1
0
1
Read data from memory
1
1
0
Write data to memory
1
1
1
None (passive)
D
S6/CLKSEL1/PIO29
Bus Cycle Status Bit 6 (output, synchronous)
Clock Select 1 (input, internal pullup)
S6—During the second and remaining periods of a
cycle (t2, t3, and t4), this pin is asserted High to indicate
a DMA-initiated bus cycle. During a bus hold or reset
condition, S6 is three-stated.
SDEN1/PIO23, SDEN0/PIO22
Serial Data Enables (output, synchronous)
These pins enable data transfers on port 1 and port 0
of the synchronous serial interface (SSI). The microcontroller asserts either SDEN1 or SDEN0 at the beginning of a transfer and deasserts it after the transfer
is complete. When SDEN1–SDEN0 are inactive, they
are held Low by the microcontroller. SDEN1–SDEN0
are three-stated during ONCE mode.
Am186TMER and Am188TMER Microcontrollers Data Sheet
37
SRDY/PIO6
UCS/ONCE1
Synchronous Ready (input, synchronous,
level-sensitive)
Upper Memory Chip Select (output, synchronous)
ONCE Mode Request 1 (input, internal pullup)
This pin indicates to the microcontroller that the addressed memory space or I/O device will complete a
data transfer. The SRDY pin accepts an active High
input synchronized to CLKOUTA.
UCS—This pin indicates to the system that a memory
access is in progress to the upper memory block. The
base address and size of the upper memory block are
programmable up to 512 Kbyte. UCS is held High during a bus hold condition.
Using SRDY instead of ARDY allows a relaxed system
timing because of the elimination of the one-half clock
period required to internally synchronize ARDY. To always assert the ready condition to the microcontroller,
tie SRDY High. If the system does not use SRDY, tie the
pin Low to yield control to ARDY. When SRDY is configured as P106, the internal SRDY signal is driven low.
After power-on reset, UCS is asserted because the microcontroller begins executing at FFFF0h and the default configuration for the UCS chip select is 64 Kbyte
from F0000h to FFFFFh.
This pin supplies a clock or control signal to the internal
microcontroller timer 0. After internally synchronizing a
Low-to-High transition on TMRIN0, the microcontroller
increments the timer. TMRIN0 must be tied High if not
being used.
ONCE1—During reset, this pin and ONCE0 indicate to
the microcontroller the mode in which it should operate.
ONCE0 and ONCE1 are sampled on the rising edge of
RES. If both pins are asserted Low, the microcontroller
enters ONCE mode. Otherwise, it operates normally. In
ONCE mode, all pins assume a high-impedance state
and remain in that state until a subsequent reset occurs. To guarantee the microcontroller does not inadvertently enter ONCE mode, ONCE1 has a weak
internal pullup resistor that is active only during a reset.
TMRIN1/PIO0
UZI/CLKSEL2/PIO26
Timer Input 1 (input, synchronous, edge-sensitive)
Upper Zero Indicate (output, synchronous)
TMRIN0/PIO11
Timer Input 0 (input, synchronous, edge-sensitive)
This pin supplies a clock or control signal to the internal
microcontroller timer 1. After internally synchronizing a
Low-to-High transition on TMRIN1, the microcontroller
increments the timer. TMRIN1 must be tied High if not
being used.
TMROUT0/PIO10
R
Timer Output 0 (output, synchronous)
This pin supplies the system with either a single pulse
or a continuous waveform with a programmable duty
cycle.
D
TMROUT1/PIO1
Timer Output 1 (output, synchronous)
This pin supplies the system with either a single pulse
or a continuous waveform with a programmable duty
cycle.
TXD/PIO27
Transmit Data (output, asynchronous)
This pin supplies asynchronous serial transmit data to
the system from the internal UART of the microcontroller.
38
A
T
F
UZI—This pin lets the designer determine if an access to the interrupt vector table is in progress by
ORing it with bits 15–10 of the address and data bus
(AD15–AD10 on the Am186ER microcontroller and
AO15–AO10 on the Am188ER microcontroller). UZI
is the logical AND of the inverted A19–A16 bits. UZI
is not held throughout the cycle. UZI is asserted in
the first period and deasserted in the second period
of a bus cycle. UZI/CLKSEL2 is three-stated during
bus holds and ONCE mode.
CLKSEL2—The clocking mode of the Am186ER and
Am188ER microcontrollers is controlled by UZI/
CLKSEL2/PIO26 and S6/CLKSEL1/PIO29 during reset. Both CLKSEL2 and CLKSEL1 are held High during
power-on reset because of an internal pullup resistor.
This is the default clocking mode—Times Four, which
is used if neither clock select is asserted Low during reset.
If CLKSEL2 is held Low during power-on reset, the microcontroller enters Times One mode.
This pin is latched within three crystal clock cycles after
the rising edge of RES. Refer to Reset Waveforms on
page 100 and Signals Related to Reset Waveforms on
page 100 to determine signal hold times. Note that
clock selection must be stable four clock cycles prior to
exiting reset (that is, RES going High). See Table 6 on
page 39 for specifics on the clocking modes and how to
specify them. UZI/CLKSEL2 is three-stated during bus
holds and ONCE mode.
Am186TMER and Am188TMER Microcontrollers Data Sheet
WR
Table 6. Clocking Modes
CLKSEL2
CLKSEL1
H
H
Times Four
H
L
Divide by Two
L
H
Times One
L
L
Reserved1
Clocking Mode
Notes:
1. The reserved clocking mode should not be used. Entering
the reserved clocking mode may cause unpredictable
system behavior.
VCC
Write Strobe (output, synchronous)
This pin indicates to the system that the data on the bus
is to be written to a memory or I/O device. WR is threestated during a bus hold or reset condition.
X1
Crystal Input (input)
This pin and the X2 pin provide connections for a fundamental mode crystal used by the internal oscillator
circuit. If providing an external clock source, connect
the source to X1 and leave X2 unconnected. Unlike the
rest of the pins on the Am186ER and Am188ER microcontrollers, X1 is not 5-V tolerant and has a maximum
input equal to VCC.
X2
Power Supply (input)
These pins supply power (+3.3 V) to the microcontroller.
WHB (Am186™ER Microcontroller Only)
Write High Byte (output, three-state, synchronous)
This pin and WLB indicate to the system which bytes of
the data bus (upper, lower, or both) participate in a
write cycle. In 80C186 designs, this information is provided by BHE, AD0, and WR. However, by using WHB
and WLB, the standard system interface logic and external address latch that were required are eliminated.
WHB is asserted with AD15–AD8. WHB is the logical
OR of BHE and WR. During reset, this pin is a pullup.
This pin is three-stated during bus holds and ONCE
mode.
R
WLB (Am186™ER Microcontroller Only)
WB (Am188™ER Microcontroller Only)
D
T
F
Crystal Output (output)
This pin and the X1 pin provide connections for a fundamental mode crystal used by the internal oscillator
circuit. If providing an external clock source, connect
the source to X1 and leave X2 unconnected. Unlike the
rest of the pins on the Am186ER and Am188ER microcontrollers, X2 is not 5-V tolerant.
A
Write Low Byte (output, three-state, synchronous)
Write Byte (output, three-state, synchronous)
WLB—This pin and WHB indicate to the system which
bytes of the data bus (upper, lower, or both) participate
in a write cycle. In 80C186 designs, this information is
provided by BHE, AD0, and WR. However, by using
WHB and WLB, the standard system interface logic
and external address latch that were required are eliminated.
WLB is asserted with AD7–AD0. WLB is the logical OR
of A0 and WR. This pin is three-stated during bus holds
and ONCE mode.
WB—On the Am188ER microcontroller, this pin indicates a write to the bus. WB uses the same early timing
as the nonmultiplexed address bus. WB is associated
with AD7–AD0. This pin is three-stated during bus
holds and ONCE mode.
Am186TMER and Am188TMER Microcontrollers Data Sheet
39
FUNCTIONAL DESCRIPTION
Shift
Left
4 Bits
The Am186ER and Am188ER microcontrollers are
based on the architecture of the original Am186 and
Am188 microcontrollers and they function in the enhanced mode of the Am186 and Am188 microcontrollers. Enhanced mode includes system features such as
power-save control.
Each of the 8086, 8088, 80186, and 80188 microcontrollers contains the same basic set of registers, instructions, and addressing modes. The Am186ER and
Am188ER microcontrollers are backward compatible
with the 80C186/80C188 and Am186/Am188 microcontrollers.
A full description of the Am186ER and Am188ER microcontrollers’ registers and instructions is included in
the Am186ER and Am188ER Microcontrollers User’s
Manual, order #21684.
Memory Organization
All instructions that address operands in memory must
specify the segment value and the 16-bit offset value.
For speed and compact instruction encoding, the segment register used for physical address generation is
implied by the addressing mode used (see Table 7).
D
Instructions
40
2
A
R
Table 7.
4
19
2
A
0
15
0
2
4 Segment
Logical
0 Base
Address
2 Offset
0
0
0
0
0
15
1
2
0
A
2
2
0
6
19
2
Physical Address
0
T
F
To Memory
Figure 3.
Memory is organized in sets of segments. Each segment is a linear contiguous sequence of 64K (216) 8-bit
bytes. Memory is addressed using a two-component
address consisting of a 16-bit segment value and a 16bit offset. The 16-bit segment values are contained in
one of four internal segment registers (CS, DS, SS, or
ES). The physical address is calculated by shifting the
segment value left by 4 bits and adding the 16-bit offset
value to yield a 20-bit physical address (see Figure 3).
This allows for a 1-Mbyte physical address size.
Memory Reference Needed
1
1
15
I/O Space
Two-Component Address Example
The I/O space consists of 64K 8-bit or 32K 16-bit ports.
Separate instructions (IN, INS and OUT, OUTS)
address the I/O space with either an 8-bit port address
specified in the instruction, or a 16-bit port address in
the DX register. Eight-bit port addresses are zeroextended such that A15–A8 are Low.
A
Segment Register Selection Rules
Segment Register Used Implicit Segment Selection Rule
Code (CS)
Instructions (including immediate data)
Local Data
Data (DS)
All data references
Stack
Stack (SS)
All stack pushes and pops;
any memory references that use BP Register
External Data (Global)
Extra (ES)
All string instruction references that use the DI Register as an index
Am186TMER and Am188TMER Microcontrollers Data Sheet
BUS OPERATION
BUS INTERFACE UNIT
The industry-standard 80C186/80C188 microcontrollers use a multiplexed address and data (AD) bus. The
address is present on the AD bus only during the t1
clock phase. The Am186ER and Am188ER microcontrollers continue to provide the multiplexed AD bus and,
in addition, provide a nonmultiplexed address (A) bus.
The A bus provides an address to the system for the
complete bus cycle (t1–t4).
The bus interface unit controls all accesses to external
peripherals and memory devices. External accesses
include those to memory devices, as well as those to
memory-mapped and I/O-mapped peripherals and the
peripheral control block. The Am186ER and Am188ER
microcontrollers provide an enhanced bus interface
unit with the following features:
For systems where power consumption is a concern,
the address can be disabled from being driven on the
AD bus on the Am186ER microcontroller and on the
AD and AO buses on the Am188ER microcontroller
during the normal address portion of the bus cycle for
accesses to UCS and/or LCS address spaces. In this
mode, the affected bus is placed in a high-impedance
state during the address portion of the bus cycle. This
feature is enabled through the DA bits in the UMCS and
LMCS registers. When address disable is in effect, the
number of signals that assert on the bus during all normal bus cycles to the associated address space is reduced, thus decreasing power consumption, reducing
processor switching noise, and preventing bus contention with memory devices and peripherals when operating at high clock rates. On the Am188ER
microcontroller, the address is driven on A015–A08
during the data portion of the bus cycle, regardless of
the setting of the DA bits.
If the ADEN pin is pulled Low during processor reset,
the value of the DA bits in the UMCS and LMCS registers is ignored and the address is driven on the AD bus
for all accesses, thus preserving the industry-standard
80C186 and 80C188 microcontrollers’ multiplexed address bus and providing support for existing emulation
tools.
D
R
Figure 4 on page 42 shows the affected signals during
a normal read or write operation for an Am186ER microcontroller. The address and data will be multiplexed
onto the AD bus.
Figure 5 on page 42 shows an Am186ER microcontroller bus cycle when address bus disable is in effect. This
results in having the AD bus operate in a nonmultiplexed data-only mode. The A bus will have the address during a read or write operation.
Figure 6 on page 43 shows the affected signals during a
normal read or write operation for an Am188ER microcontroller. The multiplexed address/data mode is compatible with the 80C188 microcontrollers and might be
used to take advantage of existing logic or peripherals.
n A nonmultiplexed address bus
n Separate byte write enables for high and low bytes
on the Am186ER microcontroller and a write enable
on the Am188ER microcontroller
n Pseudo Static RAM (PSRAM) support
The standard 80C186/80C188 multiplexed address
and data bus requires system interface logic and an external address latch. On the Am186ER and Am188ER
microcontrollers, new byte write enables, PSRAM control logic, and a new nonmultiplexed address bus can
reduce design costs by eliminating this external logic.
T
F
Nonmultiplexed Address Bus
The nonmultiplexed address bus (A19–A0) is valid onehalf CLKOUTA cycle in advance of the address on the
AD bus. When used in conjunction with the modified
UCS and LCS outputs and the byte write enable signals, the A19–A0 bus provides a seamless interface to
external SRAM, PSRAM, and Flash/EPROM memory
systems.
A
Byte Write Enables
The Am186ER microcontroller provides the WHB
(Write High Byte) and WLB (Write Low Byte) signals
which act as byte write enables. The Am188ER microcontroller provides the WB (Write Byte) signal which
acts as a write enable.
WHB is the logical AND of BHE and WR. WHB is Low
when both BHE and WR are Low. WLB is the logical
AND of A0 and WR. WLB is Low when A0 and WR are
both Low. WB is Low whenever a byte is written by the
Am188ER microcontroller.
The byte write enables are driven in conjunction with
the nonmultiplexed address bus as required for the
write timing requirements of common SRAMs.
Output Enable
The Am186ER and Am188ER microcontrollers provide
the RD (Read) signal which acts as an output enable.
The RD signal is Low when a word or byte is read by
the Am186ER or Am188ER microcontroller.
Figure 7 on page 43 shows an Am188ER microcontroller bus cycle when address bus disable is in effect. The
address and data is not multiplexed. The AD7–AD0
signals will have only data on the bus, while the A bus
will have the address during a read or write operation.
The AO bus will also have the address during t2–t4.
Am186TMER and Am188TMER Microcontrollers Data Sheet
41
t1
t2
t3
Address
Phase
t4
Data
Phase
CLKOUTA
A19–A0
Address
AD15–AD0
(Read)
Address
AD15–AD0
(Write)
Address
Data
Data
LCS or UCS
MCSx, PCSx
T
F
Figure 4. Am186™ER Microcontroller Address Bus—Normal Operation
A
t1
Address
Phase
CLKOUTA
A19–A0
D
AD7–AD0
(Read)
AD15–AD8
(Read)
AD15–AD0
(Write)
R
t2
t3
Data
Phase
t4
Address
Data
Data
Data
LCS or UCS
Figure 5. Am186™ER Microcontroller—Address Bus Disable in Effect
42
Am186TMER and Am188TMER Microcontrollers Data Sheet
t1
t2
t3
Address
Phase
t4
Data
Phase
CLKOUTA
A19–A0
Address
AD7–AD0
(Read)
Address
AO15–AO8
(Read or Write)
AD7–AD0
(Write)
Data
Address
Address
T
F
Data
LCS or UCS
MCSx, PCSx
A
Figure 6. Am188™ER Microcontroller Address Bus—Normal Operation
R
t1
t2
Address
Phase
D
CLKOUTA
A19–A0
AD7–AD0
(Read)
AO15–AO8
AD7–AD0
(Write)
t3
t4
Data
Phase
Address
Data
Address
Data
LCS or UCS
Figure 7. Am188™ER Microcontroller—Address Bus Disable in Effect
Am186TMER and Am188TMER Microcontrollers Data Sheet
43
Pseudo Static RAM (PSRAM) Support
Reading and Writing the PCB
The Am186ER and Am188ER microcontrollers support
the use of PSRAM devices in low memory chip-select
(LCS) space only. When PSRAM mode is enabled, the
timing for the LCS signal is modified by the chip-select
control unit to provide a CS precharge period during
PS RA M ac c es s es. T he 50 - MHz ti m in g of th e
Am186ER and Am188ER microcontrollers is appropriate to allow 70-ns PSRAM to run with one wait state.
PSRAM mode is enabled through a bit in the Low Memory Chip-Select (LMCS) Register. The PSRAM feature
is disabled on CPU reset.
Code intended to execute on the Am188ER microcontroller should perform all writes to the PCB registers as
byte writes. These writes will transfer 16 bits of data to
the PCB Register even if an 8-bit register is named in
the instruction. For example, out dx, al results in
the ax value being written to the port address in dx.
Reads to the PCB should be done as word reads. Code
written in this manner will run correctly on the
Am188ER and Am186ER microcontrollers.
In addition to the LCS timing changes for PSRAM precharge, the PSRAM devices also require periodic refresh of all internal row addresses to retain their data.
Although refresh of PSRAM can be accomplished several ways, the Am186ER and Am188ER microcontrollers implement auto refresh only.
The Am186ER and Am188ER microcontrollers generate RFSH, a refresh signal, to the PSRAM devices
when PSRAM mode is enabled. No refresh address is
required by the PSRAM when using the auto refresh
mechanism. The RFSH signal is multiplexed with the
MCS3 signal pin. When PSRAM mode is enabled,
MCS3 is not available for use as a chip-select signal.
The refresh control unit must be programmed before
accessing PSRAM in LCS space. The refresh counter
in the Clock Prescaler (CDRAM) Register must be configured with the required refresh interval value. The refresh counter reload value in the CDRAM Register
should not be set to less than 18 (12h) in order to provide time for processor cycles between refreshes. The
refresh address counter must be set to 000000h to prevent the MCS3–MCS0 or PCS6–PCS0 chip selects
from asserting. UCS may randomly assert during a
PSRAM refresh.
D
R
LCS is held High and the A bus is not used during refresh cycles. The LMCS Register must be configured to
external ready ignored (R2 = 1) with one wait state
(R1–R0 = 01b), and the PSRAM mode enable bit (SE)
must be set. The ending address of LCS space in the
LMCS Register must also be programmed.
PERIPHERAL CONTROL BLOCK (PCB)
The integrated peripherals of the Am186ER and
Am188ER microcontrollers are controlled by 16-bit
read/write registers. The peripheral registers are contained within an internal 256-byte control block. The
registers are physically located in the peripheral devices they control, but they are addressed as a single
256-byte block. Figure 9 on page 46 shows a map of
these registers.
Unaligned reads and writes to the PCB result in unpredictable behavior on both the Am186ER and Am188ER
microcontrollers.
For a complete description of all the registers in the
PCB, refer to the Am186ER and Am188ER Microcontrollers User’s Manual, order #21684.
The clock and power management unit of the
Am186ER and Am188ER microcontrollers includes a
phase-locked loop (PLL) and a second programmable
system clock output (CLKOUTB).
Phase-Locked Loop (PLL)
In a traditional 80C186/80C188 design, the internal clock
frequency is half the frequency of the crystal. Because of
the internal PLL on the Am186ER and Am188ER microcontrollers, the internal clock generated by both microcontrollers can operate at up to four times the frequency
of the crystal. The Am186ER and Am188ER microcontrollers operate in the following modes:
A
n Divide by Two—Frequency of the system clock is
half the frequency of the crystal with PLL disabled.
n Times One—Frequency of the system clock will be
the same as the external crystal with PLL enabled.
n Times Four—Frequency of the system clock is four
times the frequency of the crystal with PLL enabled.
The default Times Four mode must be used for processor
frequencies above 40 MHz. The Divide by Two mode
should be used for frequencies below 16 MHz. The clocking mode is selected using CLKSEL1 and CLKSEL2 on
reset. Table 8 provides the maximum and minimum frequencies for X1, X2, and CLKOUTA according to clocking
mode.
Table 8. Maximum and Minimum Clock
Frequencies
Mode
X1/X2
Max
X1/X2
Min
CLKOUTA
Max
CLKOUTA
Min
Divide by 2
40 MHz
30 MHz
20 MHz
15 MHz
Times 1
40 MHz
16 MHz
40 MHz
16 MHz
12.5 MHz 4 MHz
50 MHz
16 MHz
Times 4
44
T
F
CLOCK AND POWER MANAGEMENT
Am186TMER and Am188TMER Microcontrollers Data Sheet
Crystal-Driven Clock Source
The internal oscillator circuit of the Am186ER and
Am188ER microcontrollers is designed to function with
a parallel-resonant fundamental mode crystal. Because of the PLL, the crystal frequency can be twice,
equal to, or one quarter of the processor frequency. Do
not replace a crystal with an LC or RC equivalent. See
Figure 8 for a diagram of oscillator configurations.
The X1 and X2 signals are connected to an internal inverting amplifier (oscillator) that provides, along with
the external feedback loading, the necessary phase
shift. In such a positive feedback circuit, the inverting
amplifier has an output signal (X2) 180 degrees out of
phase of the input signal (X1).
The external feedback network provides an additional
180-degree phase shift. In an ideal system, the input to
X1 will have 360 or zero degrees of phase shift. The external feedback network is designed to be as close to
ideal as possible. If the feedback network is not providing necessary phase shift, negative feedback will
dampen the output of the amplifier and negatively affect the operation of the clock generator. Values for the
loading on X1 and X2 must be chosen to provide the
necessary phase shift and crystal operation.
Selecting a Crystal
When selecting a crystal, the load capacitance should
always be specified (CL). This value can cause variance in the oscillation frequency from the desired specified value (resonance). The load capacitance and the
loading of the feedback network have the following relationship:
CL = (C1 ⋅ C2) + CS
(C1 + C2)
D
X1
X2
R
where CS is the stray capacitance of the circuit. Placing
the crystal and CL in series across the inverting amplifier and tuning these values (C1, C2) allows the crystal
to oscillate at resonance. Finally, there is a relationship
between C1 and C2. To enhance the oscillation of the
inverting amplifier, these values need to be offset with
the larger load on the output (X2). Equal values of
these loads will tend to balance the poles of the inverting amplifier.
The characteristics of the inverting amplifier set limits
on the following parameters for crystals:
ESR (Equivalent Series Resistance)60-ohm max
Drive Level .......................... 500-mW max
The recommended range of values for C1 and C2 are
as follows:
C1 ........................................ 15 pF ± 20%
T
F
C2 ........................................ 22 pF ± 20%
The specific values for C1 and C2 must be determined
by the designer and are dependent on the characteristics of the chosen crystal and board design.
External Source Clock
Alternately, the internal oscillator can be driven by an
external clock source. The external clock source
should be connected to the input of the inverting amplifier (X1) with the output (X2) left unconnected. X1 and
X2 are not 5-V tolerant and X1 has a maximum input
equal to VCC.
A
C1
X1
Crystal
Oscillator
To PLL
C2
X2
Am188ER/
Am186ER
Microcontroller
Am188ER/
Am186ER
Microcontroller
a. External Clock Configuration
Oscillator
To PLL
b. Crystal Configuration
Notes:
X1 and X2 are not 5-V tolerant. The X1 maximum input is VCC.
Figure 8. Am186™ER and Am188™ER Microcontrollers Oscillator Configurations
Am186TMER and Am188TMER Microcontrollers Data Sheet
45
Offset
(Hexadecimal)
FE
F6
Register Name
Peripheral Control Block Relocation Register
w
w
Reset Configuration Register
* F4
Processor Release Level Register
F0
PDCON Register
w
** E6
w
Watchdog Timer Control Register
E4
Enable RCU Register
E2
Clock Prescaler Register
E0
Memory Partition Register
w
w
DA
DMA 1 Control Register
D8
DMA 1 Transfer Count Register
D6
DMA 1 Destination Address High Register
D4
DMA 1 Destination Address Low Register
D2
DMA 1 Source Address High Register
D0
DMA 1 Source Address Low Register
CA
DMA 0 Control Register
C8
DMA 0 Transfer Count Register
C6
DMA 0 Destination Address High Register
C4
DMA 0 Destination Address Low Register
C2
DMA 0 Source Address High Register
C0
R
DMA 0 Source Address Low Register
D
** AC
A
T
F
w
A8
w
Internal Memory Chip Select Register
Note: Gaps in offset addresses
indicate reserved registers. No
access should be made to reserved
registers.
PCS and MCS Auxiliary Register
A6
Midrange Memory Chip Select Register
A4
Peripheral Chip Select Register
A2
Low Memory Chip Select Register
A0
Upper Memory Chip Select Register
w
Changed from original Am186
microcontroller
w
88
Serial Port Baud Rate Divisor Register
86
Serial Port Receive Register
84
Serial Port Transmit Register
82
80
Serial Port Status Register
*
**
Changed from Am186EM and
Am188EM microcontrollers
New to the Am186ER and
Am188ER microcontrollers
Serial Port Control Register
Figure 9. Peripheral Control Block Register Map
46
Am186TMER and Am188TMER Microcontrollers Data Sheet
Offset
(Hexadecimal)
w
Register Name
7A
PIO Data 1 Register
78
PIO Direction 1 Register
76
74
PIO Mode 1 Register
PIO Data 0 Register
72
PIO Direction 0 Register
70
PIO Mode 0 Register
w
w
66
Timer 2 Mode/Control Register
62
Timer 2 Maxcount Compare A Register
Timer 2 Count Register
60
5E
Timer 1 Mode/Control Register
5C
Timer 1 Maxcount Compare B Register
Timer 1 Maxcount Compare A Register
5A
58
Timer 1 Count Register
Timer 0 Mode/Control Register
Timer 0 Maxcount Compare B Register
56
54
52
Timer 0 Maxcount Compare A Register
Timer 0 Count Register
50
w
44
Serial Port Interrupt Control Register
42
Watchdog Timer Interrupt Control Register
INT4 Control Register
40
3E
R
T
F
DMA 0 Interrupt Control Register
D
2E
2C
w
INT0 Control Register
DMA 1 Interrupt Control Register
38
30
A
INT3 Control Register
INT2 Control Register
INT1 Control Register
3C
3A
36
34
32
w
Timer Interrupt Control Register
Interrupt Status Register
Interrupt Request Register
In-service Register
2A
Priority Mask Register
28
Interrupt Mask Register
26
Poll Status Register
24
22
Poll Register
End-of-Interrupt Register
20
18
Interrupt Vector Register
Synchronous Serial Receive Register
16
Synchronous Serial Transmit 0 Register
14
Synchronous Serial Transmit 1 Register
12
Synchronous Serial Enable Register
10
Synchronous Serial Status Register
Notes: Gaps in offset addresses
indicate reserved registers. No
access should be made to reserved
registers.
Changed from original Am186
microcontroller
Figure 9. Peripheral Control Block Register Map (Continued)
Am186TMER and Am188TMER Microcontrollers Data Sheet
47
PSEN1
Power-Save
Divisor1
(/1 to /128)
CLKSEL2
CAF1
CAD1
Mux
PLL
1x or 4x
CPU Clock
Mux
CLKOUTA
Mux
Fundamental
Clock
X1, X2
Input Clock
CBF1
÷2
Mux
CLKSEL1
CBD1
Time
Delay
6 ± 2.5ns
CLKOUTB
Notes:
1. Set via PDCON Register
Figure 10. Clock Organization
System Clocks
The base system clock of the original Am186/Am188
microcontrollers is renamed CLKOUTA and the additional output is called CLKOUTB. CLKOUTA and CLKOUTB operate at either the fundamental processor
frequency or the CPU clock (power-save) frequency.
Figure 10 shows the organization of the clocks.
The second clock output (CLKOUTB) allows one clock
to run at the fundamental frequency and the other clock
to run at the CPU (power-save) frequency. Individual
drive enable bits allow selective enabling of just one, or
both, of these clock outputs.
Power-Save Operation
R
T h e Pow e r - S ave m o d e o f t h e A m 1 8 6 E R a n d
Am188ER microcontrollers reduces power consumption and heat dissipation, thereby extending battery life
in portable systems. In Power-Save mode, operation of
the CPU and internal peripherals continues at a slower
clock frequency. When a hardware interrupt occurs, the
microcontroller automatically returns to its normal operating frequency. The microcontroller remains in
Power-Save mode for software interrupts and traps.
D
Note: Power-save operation requires that clockdependent peripherals be reprogrammed for clock
frequency changes. Software drivers must be aware of
clock frequency.
T
F
as RES is active. After RES becomes inactive and an
internal processing interval elapses, the microcontroller begins execution with the instruction at physical location FFFF0h. RES also sets some registers to
predefined values. Note that all clock selection (S6/
CLKSEL1 and UZI/CLKSEL2) must be stable four
clocks prior to the deassertion of RES. Activating the
PLL will require 1 ms to achieve a stable clock.
A
Reset Configuration Register
When the RES input is asserted Low, the contents of
the address/data bus (AD15–AD0) are written into the
Reset Configuration Register. The system can place
configuration information on the address/data bus
using weak external pullup or pulldown resistors, or
using an external driver that is enabled during reset.
The processor does not drive the address/data bus
during reset.
For example, the Reset Configuration Register could
be used to provide the software with the position of a
configuration switch in the system. Using weak external
pullup and pulldown resistors on the address and data
bus, the system would provide the microcontroller with
a value corresponding to the position of the jumper during a reset.
The Reset Configuration Register can only be modified
during reset. This register is read-only during normal
operation.
Initialization and Processor Reset
Processor initialization or startup is accomplished by
driving the RES input pin Low. RES must be held Low
for 1 ms during power-up to ensure proper device initialization. RES forces the Am186ER and Am188ER
microcontrollers to terminate all execution and local
bus activity. No instruction or bus activity occurs as long
48
Am186TMER and Am188TMER Microcontrollers Data Sheet
CHIP-SELECT UNIT
The Am186ER and Am188ER microcontrollers contain
logic that provides programmable chip-select generation for both memories and peripherals. The logic can
be programmed to provide external ready and waitstate generation and latched address bits A1 and A2.
The chip-select lines are active for all memory and I/O
cycles in their programmed areas, whether they are
generated by the CPU or by the integrated DMA unit.
Chip-Select Timing
The timing for the UCS and LCS outputs is modified
from the original Am186 microcontroller. These outputs
now assert in conjunction with the nonmultiplexed address bus for normal memory timing. To enable these
outputs to be available earlier in the bus cycle, the number of programmable memory size selections has been
reduced.
Ready and Wait-State Programming
The Am186ER and Am188ER microcontrollers can be
programmed to sense a ready signal for each of the external peripheral or memory chip-select lines. The external ready signal can be either the ARDY or SRDY
signal as shown in Figure 11. For diagrams of the synchronous ready waveforms and asynchronous ready
waveforms, refer to page 97. Each external chip-select
ARDY
CLKOUTA
D
SRDY
D
R
control register (UMCS, LMCS, MMCS, PACS, and
MPCS) contains a single-bit field that determines
whether the external ready signal is required or ignored. The internal memory ignores the external ready
signal.
The number of wait states to be inserted for each access to an external peripheral or memory region is programmable. The chip-select control registers for UCS,
LCS, MCS3–MCS0, PCS6, and PCS5 contain a two-bit
field that determines the number of wait states from
zero to three to be inserted. PCS3–PCS0 use three bits
to provide additional values of 5, 7, 9, and 15 wait
states. The chip-select control register for internal
memory always specifies no wait states.
When external ready is required, internally programmed wait states will always complete before external ready can terminate or extend a bus cycle. For
example, if the internal wait states are set to insert two
wait states, the processor samples the external ready
pin during the first wait cycle. If external ready is asserted at that time, the access completes after six cycles (four cycles plus two wait states). If external ready
is not asserted during the first wait state, the access is
extended until ready is asserted, which is followed by
one more wait state followed by t4.
A
Q
T
F
Bus Ready
Rising Edge
D
Q
Falling Edge
D
Q
Falling Edge
Figure 11. ARDY and SRDY Synchronization Logic Diagram
Am186TMER and Am188TMER Microcontrollers Data Sheet
49
Memory Maps
There are several possible ways to configure the address space of the Am186ER and Am188ER microcon-
trollers. Four of the most popular configurations are
shown in Figure 12.
1 Mbyte
1 Mbyte
External Flash
(UCS)
External Flash
(UCS)
1 Mbyte
1 Mbyte
768 Kbytes
External Flash
(UCS)
External Flash
(UCS)
Internal RAM
512 Kbytes
512 Kbytes
768 Kbytes
544 Kbytes
512 Kbytes
External RAM
(MCS3–MCS0)
256 Kbytes
External RAM
(LCS)
External RAM
(MCS)
32 Kbytes
Internal RAM
512 Kbytes Flash
No External RAM
32 Kbytes
Internal RAM
0 Kbyte
0 Kbyte
256 Kbytes Flash
Internal RAM at 0
32 Kbytes External RAM
Internal RAM
A
Figure 12. Example Memory Maps
D
50
0 Kbyte
0 Kbyte
512 Kbytes Flash
Internal RAM at 0
256 Kbytes External RAM
Shaded areas represent open memory that can be used by
other chip selects and the PCB, if located in memory.
R
T
F
32 Kbytes
256 Kbytes Flash
512 Kbytes External RAM
Internal RAM Located
Above External RAM
Am186TMER and Am188TMER Microcontrollers Data Sheet
Chip-Select Overlap
Although programming the various chip selects on the
Am186ER microcontroller so that multiple chip select
signals are asserted for the same physical address is
not recommended, it may be unavoidable in some systems. In such systems, the chip selects whose assertions overlap must have the same configuration for
ready (external ready required or not required) and the
number of wait states to be inserted into the cycle by
the processor.
The peripheral control block (PCB) and the internal
memory are both accessed using internal signals.
These internal signals function as chip selects configured with zero wait states and no external ready. Therefore, the PCB and inter nal memor y can be
programmed to addresses that overlap external chip
select signals if those external chip selects are programmed to zero wait states with no external ready required.
When overlapping an additional chip select with either
the LCS or UCS chip selects, it must be noted that setting the Disable Address (DA) bit in the LMCS or UMCS
register will disable the address from being driven on
the AD bus for all accesses for which the associated
chip select is asserted, including any accesses for
which multiple chip selects assert.
The MCS and PCS chip select pins can be configured
as either chip selects (normal function) or as PIO inputs
or outputs. It should be noted; however, that the ready
and wait state generation logic for these chip selects is
in effect regardless of their configurations as chip selects or PIOs. This means that if these chip selects are
enabled (by a write to the MMCS and MPCS for the
MCS chip selects, or by a write to the PACS and MPCS
registers for the PCS chip selects), the ready and wait
state programming for these signals must agree with
the programming for any other chip selects with which
their assertion would overlap if they were configured as
chip selects.
D
R
Although the PCS4 signal is not available on an external pin, the ready and wait state logic for this signal still
exists internal to the part. For this reason, the PCS4 address space must follow the rules for overlapping chip
selects. The ready and wait-state logic for PCS6–PCS5
is disabled when these signals are configured as address bits A2–A1.
Failure to configure overlapping chip selects with the
same ready and wait state requirements may cause the
processor to hang with the appearance of waiting for a
ready signal. This behavior may occur even in a system
in which ready is always asserted (ARDY or SRDY tied
High).
Configuring PCS in I/O space with LCS or any other chip
select configured for memory address 0 is not consid-
ered overlapping of the chip selects. Overlapping chip
selects refers to configurations where more than one
chip select asserts for the same physical address.
Upper Memory Chip Select
The Am186ER and Am188ER microcontrollers provide
a UCS chip select for the top of memory. On reset, the
Am186ER and Am188ER microcontrollers begin fetching and executing instructions starting at memory location FFFF0h. Therefore, upper memory is usually used
as instruction memory. To facilitate this usage, UCS defaults to active on reset, with a default memory range of
64 Kbyte from F0000h to FFFFFh, with external ready
required and three wait states automatically inserted.
The UCS memory range always ends at FFFFFh. The
lower boundary is programmable. The Upper Memory
Chip Select is configured through the Upper Memory
Chip Select (UMCS) Register.
T
F
During the address phase of a bus cycle when UCS is
asserted, the DA bit in the UMCS Register enables or
disables the AD15–AD0 bus. If the DA bit is set to 1,
AD15–AD0 is not driven during the address phase of a
bus cycle when UCS is asserted. If DA is cleared to 0,
AD15–AD0 is driven during the address phase of a bus
cycle. Disabling AD15–AD0 reduces power consumption and eliminates potential bus conflicts with memory
or peripherals at high clock rates. The DA bit in the
UMCS Register defaults to 0 at power-on reset.
A
Low Memory Chip Select
The Am186ER and Am188ER microcontrollers provide
an LCS chip select for the bottom of memory. Because
the interrupt vector table is located at the bottom of
memory starting at 00000h, the LCS pin has traditionally been used to control data memory. The LCS pin is
not active on reset. The Am186ER and Am188ER microcontrollers also allow the IMCS Register and internal memory to be programmed to address 0. This
would allow the internal memory to be used for the interrupt vector table and data memory.
Midrange Memory Chip Selects
The Am186ER and Am188ER microcontrollers provide
four chip selects, MCS3–MCS0, for use in a user-locatable memory block. The base address of the memory
block can be located anywhere within the 1-Mbyte
memory address space, exclusive of the areas associated with the UCS and LCS chip selects, as well as the
address range of the Peripheral Chip Selects, PCS6,
PCS5, and PCS3–PCS0, if they are mapped to memory. The MCS address range can overlap the PCS address range if the PCS chip selects are mapped to I/O
space.
Unlike the UCS and LCS chip selects, the MCS outputs
assert with the multiplexed AD address bus.
Am186TMER and Am188TMER Microcontrollers Data Sheet
51
Peripheral Chip Selects
The Am186ER and Am188ER microcontrollers provide
six chip selects, PCS6–PCS5 and PCS3–PCS0, for
use within a user-locatable memory or I/O block. PCS4
is not available on the Am186ER and Am188ER microcontrollers. The base address of the memory block can
be located anywhere within the 1-Mbyte memory address space, exclusive of the areas associated with the
UCS, LCS, and MCS chip selects, or they can be configured to access the 64-Kbyte I/O space.
The PCS pins are not active on reset. PCS6–PCS5 can
have from zero to three wait states. PCS3–PCS0 can
have four additional wait-state values—5, 7, 9, and 15.
Unlike the UCS and LCS chip selects, the PCS outputs
assert with the multiplexed AD address bus. Note also
that each peripheral chip select asser ts over a
256-byte address range, which is twice the address
range covered by peripheral chip selects in the 80C186
and 80C188 microcontrollers.
INTERNAL MEMORY
The Am186ER and Am188ER microcontrollers provide
32 Kbyte of on-chip RAM. The integration of memory
helps to reduce the overall cost, power, and size of system designs. The internal memory also improves reliability with fewer connections and eases inventory
management and system qualification because of the
integrated supply.
The internal RAM for the Am186ER microcontroller is a
16K x 16-bit-wide array (32 Kbyte) which provides the
same performance as 16-bit external zero-wait-state
RAM. For the Am188ER microcontroller, the internal
RAM is a 32K x 8-bit-wide array (32 Kbyte) that provides the same performance as 8-bit external zero
wait-state RAM.
D
R
Interaction with External RAM
The Am186ER and Am188ER microcontrollers include
an Internal Memory Chip Select (IMCS) Register to
control the mapping of the internal RAM. The internal
address space can be located at any 32-Kbyte boundary within the 1-Mbyte memory address space, provided that it does not overlap any external chip selects.
If an overlap does occur, the external chip select must
be set to 0 wait states and to ignore external ready. If
the internal and external chip selects overlap, both will
be active, but the internal memory data will be used on
reads. Writes, with all the corresponding external control signals, will occur to both devices. Special system
consideration must be made for show read cycles,
since those cycles will drive data out on reads.
The base address of the internal RAM is determined by
the value of bits BA19–BA15 in the IMCS Register. Because the interrupt vector table is located at 00000h, it
is not unusual to store the interrupt vector table in the
internal RAM for faster access, and thus program the
IMCS Register for a base address of 0. However, this
scenario may lead to a memory address overlap between the IMCS and low memory chip select (LMCS)
registers, as the base address of the LMCS Register is
always 0 if activated.
Emulator and Debug Modes
There are two debug modes associated with the internal memory. One mode allows users to disable the internal RAM, and the other mode makes it possible to
drive data on the external data bus during internal RAM
read cycles.
Normal operation of internal RAM has all control signals
for reads and writes and data for writes visible externally.
Accesses to internal memory can be detected externally
by comparing the address on A19–A0 with the address
space of the internal memory.
T
F
Internal Memory Disable
When this mode is activated, the internal RAM is disabled and all accesses into the internal memory space
are made externally for debugging purposes. This
mode is activated by pulling the S1/IMDIS pin Low during reset. To use this debug mode, internal memory
space must first be activated via the IMCS Register.
A
Show Read Enable
When this mode is activated, the data from the internal
RAM read cycles are driven on the AD15–AD0 bus.
Note that if a byte read is being shown, the unused byte
will also be driven on the AD15–AD0 bus. This mode
can be activated externally by pulling the S0/SREN pin
Low during reset or by setting the SR bit in the IMCS
Register. If this feature is activated externally using the
SREN pin, the value of the SR bit is ignored. Many emulators assert the SREN pin.
During an internal memory read with show read enabled, the address will be driven on the AD bus during
t1 and t2. The data being read will be driven on the AD
bus during t3 and t4 by the Am186ER or Am188ER microcontrollers. Special system care must be taken to
avoid bus contention, because normal reads have the
AD bus three-stated during t2, t3, and t4. It is best to ensure that no external device overlaps the internal memory space.
If internal and external chip selects overlap and the external chip selects are not set to 0 wait states and to ignore external ready, the results are unpredictable.
Because of the many potential problems with overlapping chip selects, this practice is not recommended.
52
Am186TMER and Am188TMER Microcontrollers Data Sheet
REFRESH CONTROL UNIT
The Refresh Control Unit (RCU) automatically generates
refresh bus cycles. After a programmable period of time,
the RCU generates a memory read request to the bus interface unit. If the address generated during a refresh bus
cycle is within the range of a properly programmed chip
select, that chip select (with the exception of UCS and
LCS) is activated when the bus interface unit executes the
refresh bus cycle. The ready logic and wait states programmed for the region are also in force. If no chip select
is activated, then external ready is required to terminate
the refresh bus cycle.
If the HLDA pin is active when a refresh request is generated (indicating a bus hold condition), then the
Am186ER and Am188ER microcontrollers deactivate
the HLDA pin in order to perform a refresh cycle. The
external bus master must remove the HOLD signal for
at least one clock in order to allow the refresh cycle to
execute. The sequence of HLDA going inactive while
HOLD is being held active can be used to signal a
pending refresh request.
The Am186ER and Am188ER microcontrollers’ HOLD
latency time, the period between HOLD request and
HOLD acknowledge, is a function of the activity occurring in the processor when the HOLD request is received. A HOLD request is second only to DRAM
refresh requests in priority of activity requests received
by the processor. For example, in the case of a DMA
transfer, the HOLD latency can be as great as four bus
cycles. This occurs if a DMA word transfer operation is
taking place from an odd address to an odd address
(Am186ER microcontroller only). This is a total of 16 or
more clock cycles if wait states are required. In addition,
if locked transfers are performed, the HOLD latency
time is increased by the length of the locked transfer.
D
R
INTERRUPT CONTROL UNIT
The Am186ER and Am188ER microcontrollers can receive interrupt requests from a variety of sources, both
internal and external. The internal interrupt controller
arranges these requests by priority and presents them
one at a time to the CPU.
There are six external interrupt sources on the
Am186ER/Am188ER microcontrollers—five maskable
interrupt pins and one nonmaskable interrupt pin. In addition, there are six total internal interrupt sources—
three timers, two DMA channels, and the asynchronous
serial port—that are not connected to external pins.
The Am186ER and Am188ER microcontrollers provide
three interrupt sources not present on the Am186 and
Am188 microcontrollers. The first is an additional external interrupt pin (INT4), which operates much like the
already existing interrupt pins (INT3–INT0). The second is an internal maskable watchdog timer interrupt.
The third is an internal interrupt from the asynchronous
serial port.
The five maskable interrupt request pins can be used
as direct interrupt requests. Plus, INT3–INT0 can be
cascaded with an 82C59A-compatible external interrupt controller if more inputs are needed. An external
interrupt controller can be used as the system master
by programming the internal interrupt controller to operate in slave mode. In all cases, nesting can be enabled so that ser vice routines for lower priority
interrupts are interrupted by a higher priority interrupt.
Programming the Interrupt Control Unit
The Am186ER and Am188ER microcontrollers provide
two methods for masking and unmasking the maskable
interrupt sources. Each interrupt source has an interrupt control register (offsets 32h–44h) that contains a
mask bit specific to that interrupt. In addition, the Interrupt Mask Register (offset 28h) is provided as a single
source to access all of the mask bits. While changing a
mask bit in either the mask register or the individual
register will change the corresponding mask bit in the
other register, there is a difference in exactly how the
mask is updated.
T
F
If the Interrupt Mask Register is written while interrupts
are enabled, it is possible that an interrupt could occur
while the register is in an undefined state. This can
cause interrupts to be accepted even though they were
masked both before and after the write to the Interrupt
Mask Register. Therefore, the Interrupt Mask Register
should only be written when interrupts are disabled.
Mask bits in the individual interrupt control registers
can be written while interrupts are enabled, and there
will be no erroneous interrupt operation.
A
TIMER CONTROL UNIT
There are three 16-bit programmable timers in the
Am186ER and Am188ER microcontrollers. Timer 0 and
timer 1 are connected to four external pins (each has an
input and an output). These two timers can be used to
count, time external events, or generate nonrepetitive or
variable-duty-cycle waveforms. In addition, timer 1 can
be configured as a watchdog timer interrupt.
Note that a hardware watchdog timer (WDT) has been
added to the Am186ER and Am188ER microcontrollers.
Use of the WDT is recommended for applications requiring this reset functionality. To maintain compatibility with
previous versions of the Am186ER and Am188ER microcontrollers, Timer 1 can be configured as a watchdog
timer and can generate a maskable watchdog timer interrupt. The maskable watchdog timer interrupt provides
a mechanism for detecting software crashes or hangs.
The TMROUT1 output is internally connected to the
watchdog timer interrupt. The TIMER1 Count Register
must then be reloaded at intervals less than the TIMER1
max count to assure the watchdog interrupt is not taken.
Am186TMER and Am188TMER Microcontrollers Data Sheet
53
If the code crashes or hangs, the TIMER1 countdown
will cause a watchdog interrupt.
Timer 2 is not connected to any external pins. It can be
used for real-time coding and time-delay applications.
It can also be used as a prescale to timers 0 and 1, or
as a DMA request source.
The timers are controlled by eleven 16-bit registers in
the peripheral control block. A timer’s timer-count register contains the current value of that timer. The timercount register can be read or written with a value at any
time, whether the timer is running or not. The microcontroller increments the value of the timer-count register
each time a timer event occurs.
Each timer also has a maximum-count register that defines the maximum value the timer will reach. When the
timer reaches the maximum value, it resets to 0 during
the same clock cycle—the value in the maximum-count
register is never stored in the timer-count register. Also,
timers 0 and 1 have a secondary maximum-count register. Using both the primary and secondary maximumcount registers lets the timer alternate between two
maximum values.
If the timer is programmed to use only the primary maximum-count register, the timer output pin switches Low
for one clock cycle after the maximum value is reached.
If the timer is programmed to use both of its maximumcount registers, the output pin indicates which maximum-count register is currently in control, thereby creating a waveform. The duty cycle of the waveform
depends on the values in the maximum-count registers.
R
Each timer is serviced every fourth clock cycle, so a
timer can operate at a speed of up to one-quarter the
internal clock frequency. A timer can be clocked externally at this same frequency; however, because of internal synchronization and pipelining of the timer
circuitry, the timer output may take up to six clock cycles to respond to the clock or gate input.
D
WATCHDOG TIMER
The Am186ER/Am188ER microcontrollers provide a
hardware watchdog timer. The Watchdog Timer (WDT)
can be used to regain control of the system when software fails to respond as expected. The WDT is inactive
after reset. It can be modified only once by a keyed sequence of writes to the Watchdog Timer Control Register (WDTCON) following reset. This single write can
either disable the timer or modify the timeout period
and the action taken upon timeout. A keyed sequence
is also required to reset the current WDT count. This
behavior ensures that randomly executing code will not
prevent a WDT event from occurring.
The WDT supports up to a 1.34-second timeout period
in a 50-MHz system.
54
The WDT can be configured to cause either an NMI interrupt or a system reset upon timeout. If the WDT is
configured for NMI, the NMIFLAG in the WDTCON
Register is set when the NMI is generated. The NMI interrupt service routine (ISR) should examine this flag to
determine if the interrupt was generated by the WDT or
by an external source. If the NMIFLAG is set, the ISR
should clear the flag by writing the correct keyed sequence to the WDTCON Register. If the NMIFLAG is
set when a second WDT timeout occurs, a WDT system reset is generated rather than a second NMI event.
When the processor takes a WDT reset, either because of a single WDT event with the WDT configured
to generate resets or due to a WDT event with the NMIFLAG set, the RSTFLAG in the WDTCON Register is
set. This allows system initialization code to differentiate between a hardware reset and a WDT reset and
take appropriate action. The RSTFLAG is cleared
when the WDTCON Register is read or written. The
processor does not resample external pins during a
WDT reset. This means that the clocking, the Reset
Configuration Register, and any other features that are
user-selectable during reset do not change when a
WDT system reset occurs. PIO Mode and PIO Direction registers are not affected and PIO data is undefined. All other activities are identical to those of a
normal system reset.
A
T
F
Note: The Watchdog Timer (WDT) is inactive after
reset.
DIRECT MEMORY ACCESS
Direct memory access (DMA) permits transfer of data
between memory and peripherals without CPU involvement. The DMA unit in the Am186ER and Am188ER
microcontrollers, shown in Figure 13, provides two
high-speed DMA channels. Data transfers can occur
between memory and I/O spaces (e.g., memory to I/O)
or within the same space (e.g., memory-to-memory or
I/O-to-I/O). Additionally, bytes (also words on the
Am186ER microcontroller) can be transferred to or
from even or odd addresses. Only two bus cycles (a
minimum of eight clocks) are necessary for each data
transfer.
Each channel accepts a DMA request from one of the
four sources: the channel request pin (DRQ1–DRQ0),
Timer 2, a serial port, or system software. The two
DMA channels can be programmed with different priorities to resolve simultaneous DMA requests, and transfers on one channel can interrupt the other channel.
The DMA channels can be directly connected to the
asynchronous serial port. DMA and serial port transfer
is accomplished by programming the DMA controller to
perform transfers between a data source in memory or
I/O space and a serial port transmit or receive register.
Am186TMER and Am188TMER Microcontrollers Data Sheet
DMA Operation
Each channel has six registers in the peripheral control
block that define specific channel operations. The DMA
registers consist of a 20-bit source address (two registers), a 20-bit destination address (two registers), a 16bit transfer count register, and a 16-bit control register.
The DMA transfer count register (DTC) specifies the
number of DMA transfers to be performed. Up to 64K
transfers can be performed with automatic termination.
The DMA control registers define the channel operation. All registers can be modified during any DMA activity. Any changes made to the DMA registers are
reflected immediately in DMA operation.
For DMA from the asynchronous serial port, the receive data register address, either I/O-mapped or
memory-mapped, should be specified as a byte source
for the DMA by writing the address of the register into
the DMA Source and DMA Source High registers. The
source address (the address of the receive data register) should be configured as a constant throughout the
DMA. The asynchronous serial port receiver acts as
the synchronizing device; therefore, the DMA channel
should be configured as source- synchronized.
DMA Channel Control Registers
Each DMA control register determines the mode of operation for the particular DMA channel. This register
specifies the following:
The Am188ER microcontroller’s maximum DMA transfer rates are half that of those listed in Table 9 for the
Am186ER microcontroller.
n Mode of synchronization
Table 9.
n Whether an interrupt is generated after the last
transfer
Am186ER Microcontroller Maximum DMA
Transfer Rates
Synchronization Type
Maximum DMA
Transfer Rate (Mbyte/s)
50
MHz
40
MHz
33
MHz
25
MHz
Unsynchronized
12.5
10
8.25
6.25
Source Synch
12.5
10
8.25
6.25
Destination Synch
(CPU needs bus)
8.33
6.6
5.5
4.16
Destination Synch
(CPU does not need bus)
10.00
8
6.6
5
R
Asynchronous Serial Port/DMA Transfers
The enhanced Am186ER/Am188ER microcontrollers
can DMA to and from the asynchronous serial port.
This is accomplished by programming the DMA controller to perform transfers between a data buffer (located either in memor y or I/O space) and an
asynchronous serial por t data register (SPTD or
SPRD). Note that when a DMA channel is in use by the
asynchronous serial port, the corresponding external
DMA request signal is deactivated.
D
For DMA to the asynchronous serial port, the transmit
data register address, either I/O-mapped or memorymapped, should be specified as a byte destination for
the DMA by writing the address of the register into the
DMA destination low and DMA destination high registers. The destination address (the address of the transmit data register) should be configured as a constant
throughout the DMA operation. The asynchronous serial port transmitter acts as the synchronizing device;
therefore, the DMA channel should be configured as
destination-synchronized.
n Whether bytes or words are transferred (Am186ER
microcontroller only)
T
F
n Whether DMA activity ceases after a programmed
number of DMA cycles
n Relative priority of the DMA channel with respect to
the other DMA channel
n Whether the source address is incremented, decremented, or maintained constant after each transfer
A
n Whether the source address addresses memory or
I/O space
n Whether the destination address is incremented,
decremented, or maintained constant after transfers
n Whether the destination address addresses memory or I/O space
DMA Priority
The DMA channels can be programmed so that one
channel is always given priority over the other, or they
can be programmed to alternate cycles when both
have DMA requests pending. DMA cycles always have
priority over internal CPU cycles, except between
locked memory accesses or word accesses to odd
memory locations. However, an external bus hold takes
priority over an internal DMA cycle.
Because an interrupt request, other than an NMI, cannot suspend a DMA operation and the CPU cannot access memory during a DMA cycle, interrupt latency
time suffers during sequences of continuous DMA cycles. An NMI request, however, causes all internal
DMA activity to halt. This allows the CPU to respond
quickly to the NMI request.
Am186TMER and Am188TMER Microcontrollers Data Sheet
55
20-bit Adder/Subtractor
Adder Control
Logic
Timer Request
DRQ1/Serial Port
20
Request
Selection
Logic
Transfer Counter Ch. 1
Destination Address Ch. 1
Source Address Ch. 1
Transfer Counter Ch. 0
Destination Address Ch. 0
Source Address Ch. 0
DMA
Control
Logic
Interrupt
Request
Channel Control Register 1
Channel Control Register 0
20
16
Internal Address/Data Bus
Figure 13. DMA Unit Block Diagram
ASYNCHRONOUS SERIAL PORT
The Am186ER and Am188ER microcontrollers provide
an asynchronous serial port. The asynchronous serial
port is a two-pin interface that permits full-duplex bidirectional data transfer. The asynchronous serial port
supports the following features:
n Full-duplex operation
n 7-bit or 8-bit data transfers
D
n Odd, even, or no parity
n 1 or 2 stop bits
R
If additional RS-232 signals are required, they can be
created with available PIO pins. The asynchronous serial port transmit and receive sections are double buffered. Break character, framing, parity, and overrun
error detection are provided. Exception interrupt generation is programmable by the user.
The transmit/receive clock is based on the internal processor clock, which is divided down internally to the serial port operating frequency. The serial port permits 7bit and 8-bit data transfers. DMA transfers using the serial port are supported.
The serial port generates one interrupt for any of three
serial port events—transmit complete, data received,
and receive error.
The serial port can be used in power-save mode, but
the software must adjust the transfer rate to correctly
56
DRQ0/Serial Port
A
T
F
reflect the new internal operating frequency and must
ensure that the serial port does not receive any information while the frequency is being changed.
DMA Transfers through the Serial Port
The DMA channels can be directly connected to the
asynchronous serial port. DMA and serial port transfer
is accomplished by programming the DMA controller to
perform transfers between a memory or I/O space and
a serial port transmit or receive register. For more information see the DMA control register descriptions in the
Am186ER and Am188ER Microcontrollers User’s Manual, order #21684.
SYNCHRONOUS SERIAL INTERFACE
The synchronous serial interface (SSI) enables the
Am186ER and Am188ER microcontrollers to communicate with application-specific integrated circuits (ASICs)
that require reprogrammability but are short on pins.
This four-pin interface permits half-duplex, bidirectional
data transfer at speeds of up to 25 Mbit/s.
Unlike the asynchronous serial port, the SSI operates
in a master/slave configuration. The Am186ER and
Am188ER microcontrollers are the master ports.
The SSI interface provides four pins for communicating
with system components: two enables (SDEN0 and
SDEN1), a clock (SCLK), and a data pin (SDATA). Five
Am186TMER and Am188TMER Microcontrollers Data Sheet
registers are used to control and monitor the interface.
Refer to Figure 14 and Figure 15 on page 58 for diagrams of SSI reads and writes.
Four-Pin Interface
The two enable pins SDEN1–SDEN0 can be used directly as enables for up to two peripheral devices.
Transmit and receive operations are synchronized between the master (Am186ER or Am188ER microcontroller) and slave (peripherals) by means of the SCLK
output. SCLK is derived from the internal processor
clock and is the processor clock divided by 2, 4, 8, or
16.
PROGRAMMABLE I/O (PIO) PINS
There are 32 pins on the Am186ER and Am188ER microcontrollers that are available as multipurpose signals. Table 3 and Table 4 on page 36 list the PIO pins.
Each of these pins can be used as a user-programmable input or output signal if the normal shared function
is not needed.
If a pin is enabled to function as a PIO signal, the preassigned signal function is disabled and does not affect
the level on the pin. A PIO signal can be configured to
operate as an input (with or without a weak pullup or
pulldown), as an output, or as an open-drain output.
Configuration as an open-drain output is accomplished
by keeping the appropriate PDATA bits constant in the
PIO data register and writing the data value into its associated bit position in the PIO direction register, so the
output is either driving Low or is disabled, depending
on the data.
D
R
After power-on reset, the PIO pins default to various
configurations. The column titled Power-On Reset Status in Table 3 and Table 4 on page 36 lists the defaults
for the PIOs. The system initialization code must reconfigure the PIOs as required.
Note: WDT reset does not reset PIO registers.
The A19–A17 address pins default to normal operation
on power-on reset, allowing the processor to correctly
begin fetching instructions at the boot address
FFFF0h. The DT/R, DEN, and SRDY pins also default
to normal operation on power-on reset.
Note that emulators use A19, A18, A17, S6, and UZI.
System designers using these signals as PIOs should
check with their emulator vendor for limitations on emulator operation.
If the AD15–AD0 bus override is enabled on power-on
reset, then S6/CLKSEL2 and UZI/CLKSEL1 revert to
normal operation instead of PIO input with pullup. Many
emulators assert the ADEN override. If BHE/ADEN
( A m 1 8 6 E R m i c r o c o n t r o l l e r ) o r RF S H 2 / A D E N
(Am188ER microcontroller) is held Low during poweron reset, the AD15–AD0 bus override is enabled.
A
T
F
Am186TMER and Am188TMER Microcontrollers Data Sheet
57
PB=0
DR/DT=0
PB=1
DR/DT=0
PB=0
DR/DT=1
PB=1
DR/DT=0
PB=0
DR/DT=1
PB=1
DR/DT=0
PB=0
DR/DT=1
PB=0
DR/DT=0
SDEN1 or
SDEN0
SCLK
SDATA
Poll SSS for
PB=0
Write to SSD
Write to SSC,
bit DE=1
Poll SSS for
PB=0
Poll SSS for
PB=0
Write to SSD
Write to SSD
Write to SSC, bit
DE=0
T
F
Figure 14. Synchronous Serial Interface Multiple Write
PB=0
DR/DT=0
PB=0
DR/DT=1
PB=1
DR/DT=0
SDEN1 or
SDEN0
SCLK
SDATA
D
R
Poll SSS for
PB=0
Write to SSD
Write to SSC,
bit DE=1
A
PB=1
DR/DT=0
PB=0
DR/DT=1
PB=1
DR/DT=0
Read from
SSR
Write to SSC,
bit DE=0
Figure 15. Synchronous Serial Interface Multiple Read
58
PB=0
DR/DT=0
Poll SSS for
PB=0
Poll SSS for
PB=0
Read from SSR
(dummy)
PB=0
DR/DT=1
Am186TMER and Am188TMER Microcontrollers Data Sheet
Read from SSR
LOW-VOLTAGE OPERATION
The low-voltage operation of the Am186ER and
Am188ER microcontrollers is an enabling technology
for the design of portable systems with long battery life.
This capability, combined with CPU clock management,
enables design of very low-power computing systems.
Low-Voltage Standard
Industry standards for low-voltage operation are
emerging to facilitate the design of components that
will make up a complete low-voltage system. As a
guideline, the Am186ER and Am188ER microcontroller specifications follow the first article or regulated version of the JEDEC 8.0 low-voltage proposal. This
standard proposal calls for a VCC range of 3.3 V ± 10%.
5-V supply, then the 5-V circuitry in the system may
start driving the processor’s inputs above the maximum levels (V CC + 2.6 V). The system design
should ensure that the 5-V supply does not exceed
2.6 V above the 3.3-V supply during a power-on sequence.
n Preferably, all inputs will be driven by sources that
can be three-stated during a system reset condition.
The system reset condition should persist until stable VCC conditions are met. This should help ensure
that the maximum input levels are not exceeded
during power-up conditions.
n Preferably, all pullup resistors will be tied to the
3.3-V supply, which will ensure that inputs requiring
pullups are not over stressed during power-up.
Power Savings
CMOS dynamic power consumption is proportional to
the square of the operating voltage multiplied by capacitance and operating frequency. Static CPU operation
can reduce power consumption by enabling the system
designer to reduce operating frequency when possible.
However, operating voltage is always the dominant factor in power consumption. By reducing the operating
voltage from 5 V to 3.3 V for any device, the power
consumed is reduced by 56%.
Reduction of CPU and core logic operating voltage dramatically reduces overall system power consumption.
Additional power savings can be realized as low-voltage
mass storage and peripheral devices become available.
R
Two basic strategies exist in designing systems containing the Am186ER and Am188ER microcontrollers.
The first strategy is to design a homogenous system in
which all logic components operate at 3.3 V. This provides the lowest overall power consumption. However,
system designers may need to include devices for
which 3.3-V versions are not available. In the second
strategy, the system designer must then design a
mixed 5-V/3.3-V system. This compromise enables the
system designer to minimize the core logic power consumption while still including functionality of the 5-V
features. The choice of a mixed voltage system design
also involves balancing design complexity with the
need for the additional features.
D
A
T
F
Input/Output Circuitry
To accommodate current 5-V systems, the Am186ER
and Am188ER microcontrollers have 5-V tolerant I/O
drivers. The drivers produce TTL-compatible drive output (minimum 2.4-V logic High) and receive TTL and
CMOS levels (up to VCC + 2.6 V). The following are
some design issues that should be considered when
upgrading an Am186ER microcontroller 5-V design:
n During power-up, if the 3.3-V supply has a significant delay in achieving stable operation relative to
Am186TMER and Am188TMER Microcontrollers Data Sheet
59
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Temperature under bias:
TC (Commercial) ............................ 0°C to +100°C
Commercial (TC) ........................0°C to + 100°C
Industrial* (TA) ..............................–40°C to + 85°C
Storage temperature ..................–65°C to + 125°C
VCC up to 50 MHz ............................. 3.3 V ± 0.3 V
Voltage on any pin with
respect to ground.......................... –0.5 V to VCC + 2.6 V*
Where: TC = case temperature
TA = ambient temperature
Notes:
Notes:
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
Operating Ranges define those limits between which the
functionality of the device is guaranteed.
*Industrial versions of Am186ER and Am188ER microcontrollers are available in 25- and 33-MHz operating frequencies only.
*X1 and X2 are not 5-V-tolerant and have a range of –0.5 V to
VCC.
DC CHARACTERISTICS OVER COMMERCIAL AND INDUSTRIAL OPERATING RANGES
T
F
Preliminary
Symbol Parameter Description
Notes
VIL
Input Low Voltage
VIH
Input High Voltage
VIH
Clock Input High Voltage (X2, X1)
VOL
Output Low Voltage
IOL = 4.0 mA
VOH
Output High Voltage
IOH = –1.0 mA
ICC
Power Supply Current
Note 8
ILI
Input Leakage Current
Note 1
Note 2
IIH
Input Leakage Current
IIL
Input Leakage Current
ILO
Output Leakage Current
CIN
Input Capacitance
COUT
D
I/O Capacitance
R
A
Min
Max
Unit
–0.3
0.8
V
2.0
VCC + 2.6
V
VCC
V
0.45
V
2.4
5.0
mA/
MHz
±15
±50
µA
Note 3
200
µA
Note 4
–400
µA
Note 5
Note 6
±15
±50
µA
FC =1 MHz (Note 7)
10
pF
FC =1 MHz (Note 7)
14
pF
Notes:
1. This parameter is for inputs without pullup or pulldown resistors and for which 0 ≤ VIN ≤ VCC.
2. This parameter is for inputs without pullup or pulldown resistors and for which 0 ≤ VIN ≤ 5 V.
3. This parameter is for inputs with pulldown resistors and for which VIH = 2.4 V.
4. This parameter is for inputs with pullup resistors and for which VIL = 0.45 V.
5. This parameter is for three-state outputs where VEXT is driven on the three-state output and 0 ≤ VEXT ≤ VCC.
6. This parameter is for three-state outputs where VEXT is driven on the three-state output and 0 ≤ VEXT ≤ 5 V.
7. This parameter has not been fully tested.
8. Current is measured with the device in RESET with X1 and X2 driven and all other non-power pins open
but held High or Low.
60
V
Am186TMER and Am188TMER Microcontrollers Data Sheet
THERMAL CHARACTERISTICS
TQFP Package
The Am186ER and Am188ER microcontrollers are
specified for operation with case temperature ranges
from 0°C to +100°C for a commercial temperature
device. Case temperature is measured at the top
center of the package as shown in Figure 16. The
various temperatures and thermal resistances can be
determined using the equations in Figure 17 with
information given in Table 10.
The variable P is power in watts. Typical power
supply current (ICC) for the Am186ER and Am188ER
microcontrollers is 3.7 mA per MHz of clock frequency.
θJA
θCA
TC
θ JA is the sum of θ JC and θ CA . θ JC is the internal
thermal resistance of the assembly. θCA is the case to
ambient thermal resistance.
θJC
θJA = θJC + θCA
Figure 16. Thermal Resistance (°C/Watt)
θJA = θJC + θCA
P = ICC ⋅ freq (MHz) ⋅ VCC
TJ = TC + (P ⋅ θJC)
TJ = TA + (P ⋅ θJA)
⋅ θJC)
⋅ θCA)
TA = TJ – (P ⋅ θJA)
TA = TC – (P ⋅ θCA)
TC = TJ – (P
TC = TA + (P
A
T
F
Figure 17. Thermal Characteristics Equations
R
Table 10.
D
Package/Board
PQFP/2-Layer
TQFP/2-Layer
PQFP/4-Layer
to 6-Layer
TQFP/4-Layer
to 6-Layer
Thermal Characteristics (°C/Watt)
Airflow
(Linear Feet
per Minute)
0 fpm
200 fpm
400 fpm
600 fpm
0 fpm
200 fpm
400 fpm
600 fpm
0 fpm
200 fpm
400 fpm
600 fpm
0 fpm
200 fpm
400 fpm
600 fpm
θJC
θCA
θJA
7
7
7
7
10
10
10
10
5
5
5
5
6
6
6
6
38
32
28
26
46
36
30
28
18
16
14
12
24
22
20
18
45
39
35
33
56
46
40
38
23
21
19
17
30
28
26
24
Am186TMER and Am188TMER Microcontrollers Data Sheet
61
Table 12. Junction Temperature Calculation
Typical Ambient Temperatures
The typical ambient temperature specifications are
based on the following assumptions and calculations:
The commercial operating range of the Am186ER and
Am188ER microcontrollers is a case temperature TC of
0 to 100 degrees Centigrade. TC is measured at the top
center of the package. An increase in the ambient
temperature causes a proportional increase in TC.
The 50-MHz microcontroller is specified as 3.3 V, plus
or minus 10%. Therefore, 3.6 V is used for calculating
typical power consumption on the 50-MHz
microcontroller.
Typical power supply current (ICC) in normal usage is
estimated at 3.7 mA per MHz of microcontroller clock
rate.
Typical power consumption can be calculated using the
following formula:
(Watts) = (3.7 mA/MHz) ⋅ 50 MHz ⋅ (3.6 V/1000)
Table 11 shows the variables that are used to calculate
the typical power consumption value for each version
of the Am186ER and Am188ER microcontrollers.
Table 11.
Typical Power Consumption Calculation
P = MHz ⋅ ICC ⋅ Volts / 1000
MHz
Typical ICC
Volts
Typical
Power (P)
in Watts
50
3.7
3.6
0.662
40
3.7
3.6
0.522
33
3.7
3.6
0.432
25
3.7
3.6
0.342
D
R
Thermal resistance is a measure of the ability of a
package to remove heat from a semiconductor device.
A safe operating range for the device can be calculated
using the following formulas from Figure 17 and the
variables in Table 10.
By using the maximum case rating T C, the typical
power consumption value from Table 11, and θJC from
Table 10, the junction temperature TJ can be calculated
by using the following formula from Figure 17.
TJ = TC + (P ⋅ θJC)
Table 12 shows TJ values for the various versions of the
Am186ER and Am188ER microcontrollers. The
Speed/Pkg/Board column in Table 12 indicates the
clock speed in MHz, the type of package (P for PQFP
and T for TQFP), and the type of board (2 for 2-layer
and 4–6 for 4-layer to 6-layer).
62
TJ = TC + (P ⋅ θJC)
Speed/
Pkg/
Board
TC
P
θJC
TJ
50/P2
100
0.662
7
104.6
50/T2
100
0.662
10
106.6
50/P4–6
100
0.662
5
103.3
50/T4–6
100
0.662
6
104.0
40/P2
100
0.522
7
103.7
40/T2
100
0.522
10
105.2
40/P4–6
100
0.522
5
102.6
40/T4–6
100
0.522
6
103.1
33/P2
100
0.432
7
103.0
33/T2
100
0.432
10
104.3
33/P4–6
100
0.432
5
102.2
33/T4–6
100
0.432
6
102.6
25/P2
100
0.342
7
102.4
25/T2
100
0.342
10
103.4
25/P4–6
100
0.342
5
101.7
25/T4–6
100
0.342
6
102.1
T
F
By using T J from Table 12, the typical power
consumption value from Table 11, and a θJA value from
Table 10, the typical ambient temperature TA can be
calculated using the following formula from Figure 17.
A
TA = TJ – (P ⋅ θJA)
For example, TA for a 50-MHz PQFP design with a
2-layer board and 0 fpm airflow is calculated as follows:
TA = 104.6 – (0.662 ⋅ 45)
TA = 74.81
In this calculation, TJ comes from Table 12, P comes
from Table 11, and θJA comes from Table 10. See Table
13.
TA for a 33-MHz TQFP design with a 4-layer to 6-layer
board and 200 fpm airflow is calculated as follows:
TA = 102.6 – (0.432 ⋅ 28)
TA = 90.5
See Table 16 for the result of this calculation.
Table 13 through Table 16 and Figure 18 through
F i g u r e 2 1 s h o w TA b a s e d o n t h e p r e c e d i n g
assumptions and calculations for a range of θJA values
with airflow from 0 linear feet per minute to 600 linear
feet per minute.
Am186TMER and Am188TMER Microcontrollers Data Sheet
Table 13 shows typical maximum ambient temperatures in degrees Centigrade for a PQFP package used with a
2-layer board. The typical ambient temperatures are based on a 100-degree Centigrade maximum case
temperature. Figure 18 illustrates the typical temperatures in Table 13.
Table 13.
Typical Ambient Temperatures for PQFP with Two-Layer Board
Linear Feet per Minute Airflow
Microcontroller
Speed
Typical Power
(Watts)
0 fpm
200 fpm
400 fpm
600 fpm
50 MHz
0.662
74.81
78.8
81.43
82.8
40 MHz
0.522
80.2
83.3
85.4
86.5
33 MHz
0.432
83.56
86.2
87.9
88.7
25 MHz
0.342
87.0
89.1
90.4
91.1
94
Typical Ambient Temperature (Degrees C)
92
Legend:
■ 50 MHz
● 40 MHz
✵ 33 MHz
◆ 25 Mhz
T
F
◆
◆
90
◆
✶
✶
88
◆
✶
86
84
✶
82
80
●
●
R
■
78
D
76
■
74
0 fpm
200 fpm
A
●
●
■
■
400 fpm
600 fpm
Airflow (Linear Feet Per Minute)
Figure 18. Typical Ambient Temperatures for PQFP with Two-Layer Board
Am186TMER and Am188TMER Microcontrollers Data Sheet
63
Table 14 shows typical maximum ambient temperatures in degrees Centigrade for a TQFP package used with a
2-layer board. The typical ambient temperatures are based on a 100-degree Centigrade maximum case
temperature. Figure 19 illustrates the typical temperatures in Table 14.
Table 14.
Typical Ambient Temperatures for TQFP with Two-Layer Board
Linear Feet per Minute Airflow
Microcontroller
Speed
Typical Power
(Watts)
0 fpm
200 fpm
400 fpm
600 fpm
50 MHz
0.662
69.5
76.1
80.1
81.4
40 MHz
0.522
76.0
81.2
84.3
85.4
33 MHz
0.432
80.1
84.4
87.0
87.9
25 MHz
0.342
84.2
87.7
89.7
90.4
95
Typical Ambient Temperature (Degrees C)
90
Legend:
■ 50 MHz
● 40 MHz
✵ 33 MHz
◆ 25 Mhz
◆
◆
85
◆
✶
●
80
✶
●
75
D
70
R
■
✶
A
T
F
✶
●
●
■
■
■
65
0 fpm
200 fpm
400 fpm
Airflow (Linear Feet Per Minute)
Figure 19. Typical Ambient Temperatures for TQFP with Two-Layer Board
64
◆
Am186TMER and Am188TMER Microcontrollers Data Sheet
600 fpm
Table 15 shows typical maximum ambient temperatures in degrees Centigrade for a PQFP package used with a
4-layer to 6-layer board. The typical ambient temperatures are based on a 100-degree Centigrade maximum case
temperature. Figure 20 illustrates the typical temperatures in Table 15.
Table 15. Typical Ambient Temperatures for PQFP with Four-Layer to Six-Layer Board
Linear Feet per Minute Airflow
Microcontroller
Speed
Typical Power
(Watts)
0 fpm
200 fpm
400 fpm
600 fpm
50 MHz
0.662
88.0
89.4
90.7
92.0
40 MHz
0.522
90.6
91.6
92.7
93.7
33 MHz
0.432
92.3
93.1
93.9
94.9
25 MHz
0.342
93.8
94.5
95.2
95.9
97
Typical Ambient Temperature (Degrees C)
96
Legend:
■ 50 MHz
● 40 MHz
✵ 33 MHz
◆ 25 Mhz
◆
95
✶
◆
94
✶
◆
✶
93
92
✶
●
91
●
90
R
■
89
D
88
T
F
◆
■
87
0 fpm
200 fpm
A
●
●
■
■
400 fpm
600 fpm
Airflow (Linear Feet Per Minute)
Figure 20. Typical Ambient Temperatures for PQFP with Four-Layer to Six-Layer Board
Am186TMER and Am188TMER Microcontrollers Data Sheet
65
Table 16 shows typical maximum ambient temperatures in degrees Centigrade for a TQFP package used with a
4-layer to 6-layer board. The typical ambient temperatures are based on a 100-degree Centigrade maximum case
temperature. Figure 21 illustrates the typical temperatures in Table 16.
Table 16.
Typical Ambient Temperatures for TQFP with Four-Layer to Six-Layer Board
Linear Feet per Minute Airflow
Microcontroller
Speed
Typical Power
(Watts)
0 fpm
200 fpm
400 fpm
600 fpm
50 MHz
0.662
84.1
85.5
86.8
88.1
40 MHz
0.522
87.44
88.5
89.5
90.6
33 MHz
0.432
89.64
90.5
91.4
92.2
25 MHz
0.342
91.84
92.5
93.2
93.9
97
96
Typical Ambient Temperature (Degrees C)
95
94
◆
◆
93
◆
92
◆
91
R
✶
90
T
F
✶
89
D
88
●
87
A
✶
✶
●
●
●
■
■
86
Legend:
■ 50 MHz
● 40 MHz
✵ 33 MHz
◆ 25 Mhz
■
85
84
■
0 fpm
200 fpm
400 fpm
600 fpm
Airflow (Linear Feet Per Minute)
Figure 21. Typical Ambient Temperatures for TQFP with Four-Layer to Six-Layer Board
66
Am186TMER and Am188TMER Microcontrollers Data Sheet
COMMERCIAL AND INDUSTRIAL SWITCHING CHARACTERISTICS AND WAVEFORMS
In the switching waveforms that follow, several
abbreviations are used to indicate the specific periods
of a bus cycle. These periods are referred to as time
states. A typical bus cycle is composed of four
consecutive time states: t1, t2, t3, and t4. Wait states,
which represent multiple t3 states, are referred to as tw
states. When no bus cycle is pending, an idle (ti) state
occurs.
I n th e sw i t c h i ng pa r a me t e r d e s c r i p ti o n s, t h e
multiplexed address is referred to as the AD address
bus; the nonmultiplexed address is referred to as the A
address bus.
Key to Switching Waveforms
WAVEFORM
D
R
INPUT
OUTPUT
Must be
Steady
Will be
Steady
May
Change
from H to L
Will be
Changing
from H to L
May
Change
from L to H
Will be
Changing
from L to H
Don’t Care,
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center
Line is HighImpedance
Off State
Invalid
Invalid
A
T
F
Am186TMER and Am188TMER Microcontrollers Data Sheet
67
Alphabetical Key to Switching Parameter Symbols
Parameter
Symbol
No.
Description
tARYCH
49
ARDY Resolution Transition Setup Time
Parameter
Symbol
tCLDX
No.
Description
2
Data in Hold
tARYCHL
51
ARDY Inactive Holding Time
tCLEV
71
CLKOUTA Low to SDEN Valid
tARYLCL
52
ARDY Setup Time
tCLHAV
62
HLDA Valid Delay
tAVBL
87
A Address Valid to WHB, WLB Low
tCLRF
82
CLKOUTA High to RFSH Invalid
tAVCH
14
AD Address Valid to Clock High
tCLRH
27
RD Inactive Delay
tAVLL
12
AD Address Valid to ALE Low
tCLRL
25
RD Active Delay
tAVRL
66
A Address Valid to RD Low
tCLSH
4
Status Inactive Delay
tAVWL
65
A Address Valid to WR Low
tCLSL
72
CLKOUTA Low to SCLK Low
tAZRL
24
AD Address Float to RD Active
tCLSRY
48
SRDY Transition Hold Time
tCH1CH2
45
CLKOUTA Rise Time
tCLTMV
55
Timer Output Delay
tCHAV
68
CLKOUTA High to A Address Valid
tCOAOB
83
CLKOUTA to CLKOUTB Skew
tCHCK
38
X1 High Time
tCVCTV
20
Control Active Delay 1
tCHCL
44
CLKOUTA High Time
tCVCTX
31
21
tCHCSV
67
CLKOUTA High to LCS/UCS Valid
tCVDEX
tCHCSX
18
MCS/PCS Inactive Delay
tCXCSX
17
tCHCTV
22
Control Active Delay 2
tDVCL
1
tCHCV
64
Command Lines Valid Delay (after Float)
tDVSH
75
19
T
F
Control Inactive Delay
DEN Inactive Delay
MCS/PCS Hold from Command Inactive
Data in Setup
Data Valid to SCLK High
tCHCZ
63
Command Lines Float Delay
tDXDL
tCHDX
8
Status Hold Time
tHVCL
58
tCHLH
9
ALE Active Delay
tINVCH
53
tCHLL
11
ALE Inactive Delay
tINVCL
54
tLCRF
86
tLHAV
23
ALE High to Address Valid
tLHLL
10
ALE Width
tCHRFD
79
CLKOUTA High to RFSH Valid
tCHSV
3
Status Active Delay
tCICOA
69
X1 to CLKOUTA Skew
tCICOB
70
X1 to CLKOUTB Skew
R
A
DEN Inactive to DT/R Low
HOLD Setup
Peripheral Setup Time
DRQ Setup Time
LCS Inactive to RFSH Active Delay
tLLAX
13
AD Address Hold from ALE Inactive
tLOCK
61
Maximum PLL Lock Time
tLRLL
84
LCS Precharge Pulse Width
tRESIN
57
RES Setup Time
tCKHL
39
X1 Fall Time
tCKIN
36
X1 Period
40
X1 Rise Time
46
CLKOUTA Fall Time
tRFCY
85
RFSH Cycle Time
50
ARDY Active Hold Time
tRHAV
29
RD Inactive to AD Address Active
5
AD Address Valid Delay
tRHDX
59
RD High to Data Hold on AD Bus
6
Address Hold
tRHLH
28
RD Inactive to ALE High
15
AD Address Float Delay
tRLRH
26
RD Pulse Width
tCKLH
tCL2CL1
tCLARX
tCLAV
tCLAX
tCLAZ
D
43
CLKOUTA Low Time
tSHDX
77
SCLK High to SPI Data Hold
tCLCK
37
X1 Low Time
tSLDV
78
SCLK Low to SPI Data Valid
tCLCL
42
CLKOUTA Period
tSRYCL
47
SRDY Transition Setup Time
tCLCLX
80
LCS Inactive Delay
tWHDEX
35
WR Inactive to DEN Inactive
tCLCH
tCLCSL
81
LCS Active Delay
tWHDX
34
Data Hold after WR
tCLCSV
16
MCS/PCS Active Delay
tWHLH
33
WR Inactive to ALE High
tCLDOX
30
Data Hold Time
tWLWH
32
WR Pulse Width
tCLDV
7
Data Valid Delay
Notes:
The following parameters are not defined or used at this time: 41, 56, 60, 73, 74, and 76.
68
Am186TMER and Am188TMER Microcontrollers Data Sheet
Numerical Key to Switching Parameter Symbols
Number
Parameter
Symbol Description
Number
Parameter
Symbol
Description
tCLCH
CLKOUTA Low Time
1
tDVCL
Data in Setup
43
2
tCLDX
Data in Hold
44
tCHCL
CLKOUTA High Time
3
tCHSV
Status Active Delay
45
tCH1CH2
CLKOUTA Rise Time
4
tCLSH
Status Inactive Delay
46
tCL2CL1
CLKOUTA Fall Time
5
tCLAV
AD Address Valid Delay
47
tSRYCL
SRDY Transition Setup Time
SRDY Transition Hold Time
6
tCLAX
Address Hold
48
tCLSRY
7
tCLDV
Data Valid Delay
49
tARYCH
ARDY Resolution Transition Setup Time
8
tCHDX
Status Hold Time
50
tCLARX
ARDY Active Hold Time
9
tCHLH
ALE Active Delay
51
tARYCHL
ARDY Inactive Holding Time
ARDY Setup Time
10
tLHLL
ALE Width
52
tARYLCL
11
tCHLL
ALE Inactive Delay
53
tINVCH
Peripheral Setup Time
12
tAVLL
AD Address Valid to ALE Low
54
tINVCL
DRQ Setup Time
13
tLLAX
AD Address Hold from ALE Inactive
55
tCLTMV
14
tAVCH
AD Address Valid to Clock High
57
tRESIN
15
tCLAZ
AD Address Float Delay
58
tHVCL
16
tCLCSV
MCS/PCS Active Delay
59
tRHDX
17
tCXCSX
MCS/PCS Hold from Command
Inactive
61
tLOCK
18
tCHCSX
MCS/PCS Inactive Delay
62
tCLHAV
19
tDXDL
DEN Inactive to DT/R Low
20
tCVCTV
Control Active Delay 1
21
tCVDEX
DEN Inactive Delay
22
tCHCTV
Control Active Delay 2
R
23
tLHAV
ALE High to Address Valid
24
tAZRL
AD Address Float to RD Active
25
tCLRL
RD Active Delay
26
tRLRH
RD Pulse Width
D
A
63
tCHCZ
64
tCHCV
65
tAVWL
T
F
Timer Output Delay
RES Setup Time
HOLD Setup
RD High to Data Hold on AD Bus
Maximum PLL Lock Time
HLDA Valid Delay
Command Lines Float Delay
Command Lines Valid Delay (after Float)
A Address Valid to WR Low
66
tAVRL
67
tCHCSV
68
tCHAV
CLKOUTA High to Address Valid
69
tCICOA
X1 to CLKOUTA Skew
70
tCICOB
X1 to CLKOUTB Skew
CLKOUTA Low to SDEN Valid
A Address Valid to RD Low
CLKOUTA High to LCS/UCS Valid
27
tCLRH
RD Inactive Delay
71
tCLEV
28
tRHLH
RD Inactive to ALE High
72
tCLSL
CLKOUTA Low to SCLK Low
29
tRHAV
RD Inactive to AD address Active
75
tDVSH
Data Valid to SCLK High
30
tCLDOX
Data Hold Time
77
tSHDX
SCLK High to SPI Data Hold
SCLK Low to SPI Data Valid
31
tCVCTX
Control Inactive Delay
78
tSLDV
32
tWLWH
WR Pulse Width
79
tCHRFD
CLKOUTA High to RFSH Valid
33
tWHLH
WR Inactive to ALE High
80
tCLCLX
LCS Inactive Delay
34
tWHDX
Data Hold after WR
81
tCLCSL
LCS Active Delay
CLKOUTA High to RFSH Invalid
35
tWHDEX
WR Inactive to DEN Inactive
82
tCLRF
36
tCKIN
X1 Period
83
tCOAOB
37
tCLCK
X1 Low Time
84
tLRLL
LCS Precharge Pulse Width
38
tCHCK
X1 High Time
85
tRFCY
RFSH Cycle Time
LCS Inactive to RFSH Active Delay
A Address Valid to WHB, WLB Low
39
tCKHL
X1 Fall Time
86
tLCRF
40
tCKLH
X1 Rise Time
87
tAVBL
42
tCLCL
CLKOUTA Period
CLKOUTA to CLKOUTB Skew
Notes:
The following parameters are not defined or used at this time: 41, 56, 60, 73, 74, and 76.
Am186TMER and Am188TMER Microcontrollers Data Sheet
69
Switching Characteristics over Commercial and Industrial Operating Ranges
Read Cycle (25 MHz and 33 MHz)
Preliminary
Parameter
No.
Symbol Description
General Timing Requirements
1
tDVCL
Data in Setup
2
tCLDX
Data in Hold(c)
General Timing Responses
3
tCHSV
Status Active Delay
4
tCLSH
Status Inactive Delay
5
tCLAV
AD Address Valid Delay
7
tCLDV
Data Valid Delay
8
tCHDX
Status Hold Time
9
tCHLH
ALE Active Delay
tLHLL
ALE Width
11
tCHLL
ALE Inactive Delay
13
tAVLL
tLLAX
Max
10
3
0
0
0
0
0
20
20
20
20
Low(a)
AD Address Hold from ALE
tCLCH
Inactive(a)
tCHCL
0
tAVCH
AD Address Valid to Clock High
tCLAZ
AD Address Float Delay
tCLAX =0
20
16
tCLCSV
MCS/PCS Active Delay
0
20
17
tCXCSX
MCS/PCS Hold from Command
Inactive(a)
18
tCHCSX
MCS/PCS Inactive Delay
tDXDL
DEN Inactive to DT/R
20
tCVCTV
Control Active Delay 1(b)
21
tCVDEX
DEN Inactive Delay
22
23
tCHCTV
tLHAV
0
2(b)
ALE High to Address Valid
Read Cycle Timing Responses
D
20
0
R
Control Active Delay
A
tCLCH
ns
tCLCH
0
ns
15
0
ns
15
ns
0
20
2tCLCL –15=65
0
0
ns
ns
15
2tCLCL –15=45
20
0
ns
ns
15
ns
tCLCH –3
tCLCH –3
ns
tCLCL –10=30
tCLCL –10=20
ns
0
0
ns
2tCLCL –15=65
2tCLCL –15=45
ns
20
0
15
ns
20
0
15
ns
67
tCHCSV
CLKOUTA High to LCS/UCS Valid
0
68
tCHAV
CLKOUTA High to A Address Valid
0
Notes:
All timing parameters are measured at VCC /2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with CL =50 pF. For switching tests, VIL =0.3 V and VIH =VCC –0.3 V.
a
Testing is performed with equal loading on referenced pins.
b
This parameter applies to the DEN, INTA1–INTA0, WR, WHB, and WLB signals.
c
If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly.
70
ns
0
10
RD Inactive Delay
A Address Valid to RD Low
15
20
tCLRH
tAVRL
0
0
27
66
ns
15
RD Pulse Width
RD High to Data Hold on AD
15
ns
tRLRH
tRHDX
ns
tCLAX =0
15
26
59
ns
0
0
Bus(c)
tCHCL
20
RD Active Delay
RD Inactive to AD Address Active(a)
ns
0
tCLRL
RD Inactive to ALE
tCLCH
ns
25
tRHAV
ns
15
0
tRHLH
T
F
ns
15
0
AD Address Float to RD Active
29
15
ns
ns
ns
ns
ns
ns
20
tAZRL
28
15
15
15
15
0
24
High(a)
Unit
ns
ns
0
15
Low(a)
Max
tCLCL –10=20
14
19
0
0
0
0
0
20
20
AD Address Valid to ALE
33 MHz
Min
8
3
tCLCL –10=30
10
12
25 MHz
Min
Am186TMER and Am188TMER Microcontrollers Data Sheet
Switching Characteristics over Commercial and Industrial Operating Ranges
Read Cycle (40 MHz and 50 MHz)
Preliminary
40 MHz
Min
Max
Parameter
No.
Symbol Description
General Timing Requirements
1
tDVCL
Data in Setup
2
tCLDX
Data in Hold(c)
General Timing Responses
3
tCHSV
Status Active Delay
4
tCLSH
Status Inactive Delay
5
tCLAV
AD Address Valid Delay
7
tCLDV
Data Valid Delay
8
tCHDX
Status Hold Time
9
tCHLH
ALE Active Delay
5
2
0
0
0
0
0
ALE Width
11
tCHLL
ALE Inactive Delay
12
tAVLL
AD Address Valid to ALE Low(a)
tCLCH
13
tLLAX
AD Address Hold from ALE
Inactive(a)
tCHCL
14
tAVCH
AD Address Valid to Clock High
15
tCLAZ
AD Address Float Delay
tCLAX =0
tCLCSV
MCS/PCS Active Delay
0
17
tCXCSX
MCS/PCS Hold from Command
Inactive(a)
18
tCHCSX
MCS/PCS Inactive Delay
19
20
tDXDL
tCVCTV
Low(a)
R
Control Active Delay
1(b)
21
tCVDEX
DEN Inactive Delay
22
tCHCTV
Control Active Delay 2(b)
23
tLHAV
ALE High to Address Valid
D
0
0
RD Inactive to ALE
29
tRHAV
RD Inactive to AD Address
Active(a)
59
tRHDX
RD High to Data Hold on AD Bus(c)
A Address Valid to RD Low
ns
tCHCL
ns
0
ns
0
10
ns
0
10
ns
tCLCH
0
ns
10
0
ns
ns
ns
14
14
ns
0
12
0
10
ns
7.5
5
ns
0
0
ns
0
tRHLH
ns
10
0
28
10
tCLCH
0
2tCLCL –10=40
High(a)
T
F
ns
0
RD Active Delay
RD Inactive Delay
10
ns
ns
ns
ns
ns
ns
12
tCLRL
RD Pulse Width
10
10
10
10
0
25
tCLRH
12
0
AD Address Float to RD Active
tRLRH
12
A
0
tAZRL
27
12
tCLCH
24
26
0
0
0
0
0
Unit
ns
ns
15
12
DEN Inactive to DT/R
Read Cycle Timing Responses
12
12
12
12
tCLCL –5=20
tLHLL
Max
5
2
12
10
16
50 MHz
Min
10
0
10
35
12
0
ns
ns
10
ns
tCLCH –2
tCLCH –2
ns
tCLCL –5=20
15
ns
0
0
ns
2 • tCLCL –10=40
2 • tCLCL –10=30
66
tAVRL
67
tCHCSV
CLKOUTA High to LCS/UCS Valid
0
12
0
10
ns
ns
68
tCHAV
CLKOUTA High to A Address Valid
0
10
0
10
ns
Notes:
All timing parameters are measured at VCC /2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with CL =50 pF. For switching tests, VIL =0.3 V and VIH =VCC –0.3 V.
a
Testing is performed with equal loading on referenced pins.
b
This parameter applies to the DEN, INTA1–INTA0, WR, WHB, and WLB signals.
c
If either specification 2 or specification 59 is met with respect to data hold time, the part will function correctly.
Am186TMER and Am188TMER Microcontrollers Data Sheet
71
Read Cycle Waveforms
t1
t2
t3
t4
tW
CLKOUTA
66
A19–A0
Address
8
68
S6
S6
S6
14
1
7
AD15–AD0*,
AD7–AD0**
Address
Data
2
AO15–AO8**
23
29
11
9
59
ALE
15
10
RD
BHE*
26
A
25
BHE
67
13
LCS, UCS
R
16
MCS1–MCS0,
PCS6–PCS5,
PCS3–PCS0
D
19
DT/R
20
3
27
4
18
17
21
22
S2–S0
28
24
12
5
DEN
T
F
Address
4
Status
7
UZI
Notes:
*
Am186ER microcontroller only
**
Am188ER microcontroller only
72
Am186TMER and Am188TMER Microcontrollers Data Sheet
22
Switching Characteristics over Commercial and Industrial Operating Ranges
Write Cycle (25 MHz and 33 MHz)
Preliminary
Parameter
No. Symbol Description
General Timing Responses
3
tCHSV Status Active Delay
4
tCLSH Status Inactive Delay
5
tCLAV AD Address Valid Delay
7
tCLDV Data Valid Delay
8
tCHDX Status Hold Time
9
tCHLH ALE Active Delay
25 MHz
Min
0
0
0
0
0
tLHLL
ALE Width
11
tCHLL
ALE Inactive Delay
12
tAVLL
AD Address Valid to ALE Low(a)
tCHCL
AD Address Hold
14
tAVCH
AD Address Valid to Clock High
0
tCLCSV
MCS/PCS Active Delay
0
17
tCXCSX
MCS/PCS Hold from Command
Inactive(a)
18
tCHCSX
MCS/PCS Inactive Delay
20
23
DEN Inactive to DT/R
tCVCTV
tLHAV
Control Active Delay
1(b)
ALE High to Address Valid
Write Cycle Timing Responses
tCLDOX
Data Hold Time
31
tCVCTX
Control Inactive Delay(b)
32
tWLWH
WR Pulse Width
tWHLH
WR Inactive to ALE
Data Hold after
R
High(a)
WR(a)
34
tWHDX
35
tWHDEX WR Inactive to DEN Inactive(a)
D
0
20
0
20
15
0
ns
ns
ns
ns
ns
ns
ns
15
20
2tCLCL –10=70
ns
tCLCH
ns
tCHCL
ns
0
ns
T
F
0
15
0
0
15
ns
ns
15
10
ns
ns
0
0
ns
ns
0
A
0
15
15
15
15
tCLCH
0
30
33
20
tCLCH
Low(a)
Unit
15
20
from ALE Inactive(a)
Max
tCLCL –10=20
tCLCH
tLLAX
tDXDL
0
0
0
0
0
20
13
19
20
20
20
20
tCLCL –10=30
10
16
Max
33 MHz
Min
ns
15
ns
2tCLCL –10=50
ns
tCLCH –2
tCLCH –2
ns
tCLCL –10=30
tCLCL –10=20
ns
tCLCH –3
tCLCH –5
ns
tCLCL +tCHCL –3
tCLCL +tCHCL –3
ns
65
tAVWL
A Address Valid to WR Low
67
tCHCSV
CLKOUTA High to LCS/UCS Valid
0
20
0
15
ns
CLKOUTA High to A Address Valid
0
20
0
15
ns
A Address Valid to WHB, WLB Low
tCHCL –3
20
tCHCL –3
15
ns
68
tCHAV
87
tAVBL
Notes:
All timing parameters are measured at VCC /2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with CL =50 pF. For switching tests, VIL =0.3 V and VIH =VCC –0.3 V.
a
Testing is performed with equal loading on referenced pins.
b
This parameter applies to the DEN, INTA1–INTA0, WR, WHB, and WLB signals.
Am186TMER and Am188TMER Microcontrollers Data Sheet
73
Switching Characteristics over Commercial and Industrial Operating Ranges
Write Cycle (40 MHz and 50 MHz)
Preliminary
Parameter
No.
Symbol Description
General Timing Responses
3
tCHSV
Status Active Delay
4
tCLSH
Status Inactive Delay
5
tCLAV
AD Address Valid Delay
7
tCLDV
Data Valid Delay
8
tCHDX
Status Hold Time
9
tCHLH
ALE Active Delay
40 MHz
Min
0
0
0
0
0
tCLCL –5=20
tLHLL
ALE Width
11
tCHLL
ALE Inactive Delay
12
tAVLL
AD Address Valid to ALE Low(a)
Inactive(a)
tCHCL
AD Address Hold from ALE
14
tAVCH
AD Address Valid to Clock High
0
tCLCSV
MCS/PCS Active Delay
0
17
tCXCSX
MCS/PCS Hold from Command
Inactive(a)
18
tCHCSX
MCS/PCS Inactive Delay
20
23
tCVCTV
tLHAV
DEN Inactive to DT/R
Control Active Delay
1(b)
ALE High to Address Valid
Write Cycle Timing Responses
tCLDOX
Data Hold Time
31
tCVCTX
Control Inactive Delay(b)
32
tWLWH
WR Pulse Width
tWHLH
0
12
0
A
0
R
WR Inactive to ALE
High(a)
WR(a)
ns
ns
ns
ns
ns
ns
ns
10
12
ns
tCHCL
ns
0
ns
T
F
0
10
0
0
10
10
ns
ns
ns
10
ns
2tCLCL –10=40
35
ns
tCLCH –2
tCLCH –2
ns
tCLCL –10=15
12
ns
tCLCH
tCLCH
ns
tCLCL+tCHCL–1.25
tCLCL+tCHCL–1.25
ns
34
tWHDX
Data Hold after
35
tWHDEX
WR Inactive to DEN Inactive(a)
65
tAVWL
A Address Valid to WR Low
67
tCHCSV
CLKOUTA High to LCS/UCS Valid
0
12
0
10
ns
10
0
10
ns
12
tCHCL –1.25
10
ns
D
68
tCHAV
CLKOUTA High to A Address Valid
0
87
tAVBL
A Address Valid to WHB, WLB Low
tCHCL –1.25
Notes:
All timing parameters are measured at VCC /2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with CL =50 pF. For switching tests, VIL =0.3 V and VIH =VCC –0.3 V.
a
Testing is performed with equal loading on referenced pins.
b
This parameter applies to the DEN, INTA1–INTA0, WR, WHB, and WLB signals.
74
ns
ns
0
0
ns
ns
5
12
ns
tCLCH
0
7.5
0
10
10
10
10
tCLCH
0
30
33
12
tCLCH
Low(a)
Unit
10
12
tLLAX
tDXDL
0
0
0
0
0
Max
15
tCLCH
13
19
12
12
12
12
12
10
16
Max
50 MHz
Min
Am186TMER and Am188TMER Microcontrollers Data Sheet
Write Cycle Waveforms
t1
t2
t3
t4
tW
CLKOUTA
65
A19–A0
Address
68
S6
8
S6
S6
14
7
AD15–AD0*,
AD7–AD0**
30
Address
Data
AO15–AO8**
23
11
9
34
13
ALE
31
10
33
32
WR
12
20
WHB*, WLB
WB
20
87
5
BHE*
67
LCS, UCS
DT/R
S2–S0
R
16
MCS3–MCS0,
PCS6–PCS5,
PCS3–PCS0
DEN
T
F
Address
D
A
31
4
BHE
18
17
35
31
19
Status
3
7
4
UZI
Notes:
*
Am186ER microcontroller only
**
Am188ER microcontroller only
Am186TMER and Am188TMER Microcontrollers Data Sheet
75
Switching Characteristics over Commercial and Industrial Operating Ranges
Internal RAM Show Read Cycle (25 MHz and 33 MHz)
Preliminary
Parameter
No.
Symbol Description
General Timing Responses
tCLAV
5
AD Address Valid Delay
25 MHz
Min
33 MHz
Min
Max
Max
Unit
0
20
0
15
ns
0
20
0
15
ns
7
tCLDV
Data Valid Delay
9
tCHLH
ALE Active Delay
20
15
ns
11
tCHLL
ALE Inactive Delay
20
15
ns
Read Cycle Timing Responses
tCLRL
25
RD Active Delay
0
20
0
15
ns
27
tCLRH
RD Inactive Delay
0
20
0
15
ns
68
tCHAV
CLKOUTA High to A Address Valid
0
20
0
15
ns
T
F
Switching Characteristics over Commercial and Industrial Operating Ranges
Internal RAM Show Read Cycle (40 MHz and 50 MHz)
Preliminary
Parameter
No.
Symbol Description
General Timing Responses
tCLAV
5
AD Address Valid Delay
7
tCLDV
Data Valid Delay
9
tCHLH
ALE Active Delay
11
tCHLL
ALE Inactive Delay
Read Cycle Timing Responses
tCLRL
25
RD Active Delay
tCLRH
RD Inactive Delay
68
tCHAV
CLKOUTA High to A Address Valid
D
76
R
27
40 MHz
Min
Max
0
12
0
12
A
12
12
50 MHz
Min
Max
Unit
0
10
ns
0
10
ns
10
ns
10
ns
0
10
0
10
ns
0
12
0
10
ns
0
10
0
10
ns
Am186TMER and Am188TMER Microcontrollers Data Sheet
Internal RAM Show Read Cycle Waveform
t1
t2
t3
t4
CLKOUTA
68
68
A19–A0
Address
AD15–AD0
Data
Address
5
7
5
ALE
9
11
RD
LCS, UCS
MCS3–MCS0,
PCS6–PCS5,
PCS3–PCS0
25
D
R
A
T
F
Am186TMER and Am188TMER Microcontrollers Data Sheet
27
77
Switching Characteristics over Commercial and Industrial Operating Ranges
PSRAM Read Cycle (25 MHz and 33 MHz)
Preliminary
Parameter
No.
Symbol Description
General Timing Requirements
tDVCL
1
Data in Setup
2
tCLDX
Data in
25 MHz
Min
Hold(b)
General Timing Responses
tCLAV
5
AD Address Valid Delay
Max
ns
3
3
ns
0
20
0
15
ns
20
0
15
ns
tCLDV
Data Valid Delay
0
8
Status Hold Time
0
9
tCHLH
ALE Active Delay
10
tLHLL
ALE Width
11
tCHLL
ALE Inactive Delay
23
tLHAV
ALE High to Address Valid
15
80
tCLCLX
LCS Inactive Delay
0
20
81
tCLCSL
LCS Active Delay
0
20
84
tLRLL
25
RD Active Delay
26
tRLRH
RD Pulse Width
27
tCLRH
RD Inactive Delay
0
20
tCLCL –10=30
0
A
20
2tCLCL –15=65
0
High(a)
28
tRHLH
59
tRHDX
RD High to Data Hold on AD
66
tAVRL
A Address Valid to RD Low
68
tCHAV
CLKOUTA High to A Address Valid
RD Inactive to ALE
20
tCLCH –3
Bus(b)
R
T
F
15
ns
15
ns
0
15
ns
tCLCL + tCLCH –3
ns
0
ns
0
15
2tCLCL –15=45
0
ns
ns
15
ns
tCLCH –3
ns
0
0
ns
2tCLCL –15=65
2tCLCL –15=45
ns
0
20
0
a
Testing is performed with equal loading on referenced pins.
b
If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly.
78
ns
0
15
Notes:
All timing parameters are measured at VCC /2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with CL =50 pF. For switching tests, VIL =0.3 V and VIH =VCC –0.3 V.
D
ns
ns
10
tCLCL + tCLCH –3
0
ns
15
tCLCL –10=20
20
LCS Precharge Pulse Width
Unit
8
tCHDX
Read Cycle Timing Responses
tAZRL
24
AD Address Float to RD Active
Max
10
7
tCLRL
33 MHz
Min
Am186TMER and Am188TMER Microcontrollers Data Sheet
ns
Switching Characteristics over Commercial and Industrial Operating Ranges
PSRAM Read Cycle (40 MHz and 50 MHz)
Preliminary
Parameter
No.
Symbol Description
General Timing Requirements
tDVCL
1
Data in Setup
2
tCLDX
Data in
40 MHz
Min
Hold(b)
General Timing Responses
tCLAV
5
AD Address Valid Delay
Max
50 MHz
Min
5
ns
2
2
ns
0
12
0
10
ns
12
0
10
ns
tCLDV
Data Valid Delay
0
8
tCHDX
Status Hold Time
0
9
tCHLH
ALE Active Delay
10
tLHLL
ALE Width
11
tCHLL
ALE Inactive Delay
23
tLHAV
ALE High to Address Valid
80
tCLCLX
LCS Inactive Delay
0
12
81
tCLCSL
LCS Active Delay
0
12
84
tLRLL
0
12
tCLCL –5=20
25
tCLRL
RD Active Delay
26
tRLRH
RD Pulse Width
7.5
27
tCLRH
RD Inactive Delay
0
A
10
2tCLCL –10=40
0
High(a)
28
tRHLH
59
tRHDX
RD High to Data Hold on AD
66
tAVRL
A Address Valid to RD Low
68
tCHAV
CLKOUTA High to A Address Valid
RD Inactive to ALE
tCLCH –1.25
Bus(b)
R
T
F
10
ns
ns
0
10
ns
0
10
ns
tCLCL + tCLCH –1
ns
0
ns
0
10
35
12
ns
ns
5
tCLCL + tCLCH –1.25
0
ns
10
15
12
LCS Precharge Pulse Width
Unit
5
7
Read Cycle Timing Responses
tAZRL
24
AD Address Float to RD Active
Max
0
ns
ns
10
ns
tCLCH –1
ns
0
0
ns
2tCLCL –10=40
2tCLCL –10=30
ns
0
10
0
10
ns
Notes:
All timing parameters are measured at VCC /2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with CL =50 pF. For switching tests, VIL =0.3 V and VIH =VCC –0.3 V.
D
a
Testing is performed with equal loading on referenced pins.
b
If either specification 2 or specification 59 is met with respect to data hold time, the part will function correctly.
Am186TMER and Am188TMER Microcontrollers Data Sheet
79
PSRAM Read Cycle Waveforms
t1
t2
t3
t4
t1
tW
CLKOUTA
66
A19–A0
Address
8
68
S6
S6
S6
1
7
AD15–AD0*,
AD7–AD0**
Address
Data
Address
T
F
2
AO15–AO8**
Address
23
9
11
59
ALE
10
26
RD
27
5
LCS
80
81
84
Notes:
D
*
Am186ER microcontroller only
**
Am188ER microcontroller only
80
28
24
R
A
25
27
80
Am186TMER and Am188TMER Microcontrollers Data Sheet
Switching Characteristics over Commercial and Industrial Operating Ranges
PSRAM Write Cycle (25 MHz and 33 MHz)
Preliminary
Parameter
No. Symbol Description
General Timing Responses
tCLAV AD Address Valid Delay
5
25 MHz
Min
Max
0
15
ns
20
0
15
ns
Data Valid Delay
0
8
tCHDX
Status Hold Time
0
9
tCHLH
ALE Active Delay
10
tLHLL
ALE Width
11
tCHLL
ALE Inactive Delay
23
tLHAV
ALE High to Address Valid
20
tCVCTV
Control Active Delay
0
20
80
tCLCLX
LCS Inactive Delay
0
20
81
tCLCSL
LCS Active Delay
0
20
84
tLRLL
20
15
Control Inactive
tWLWH
WR Pulse Width
tWHLH
34
tWHDX
65
tAVWL
68
tCHAV
87
tAVBL
WR Inactive to ALE
Data Hold after
0
WR(a)
A Address Valid to WR Low
CLKOUTA High to A
Address Valid
A Address Valid to WHB, WLB
Low
20
A
tCLCH –2
tCLCL –10=30
tCLCL +tCHCL –3
R
ns
15
ns
15
ns
10
ns
T
F
0
15
ns
0
15
ns
0
2tCLCL –10=70
High(a)
ns
tCLCL + tCLCH –3
0
32
15
0
tCLCL + tCLCH –3
Delay(b)
ns
tCLCL –10=20
20
LCS Precharge Pulse Width
31
33
0
tCLCL –10=30
Write Cycle Timing Responses
tCLDOX Data Hold Time
30
Unit
20
tCLDV
1(b)
Max
0
7
tCVCTX
33 MHz
Min
0
ns
15
ns
2tCLCL –10=50
ns
tCLCH –2
ns
tCLCL –10=20
ns
tCLCL +tCHCL –3
ns
0
20
0
15
ns
tCHCL –3
20
tCHCL –3
15
ns
Notes:
All timing parameters are measured at VCC /2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with CL =50 pF. For switching tests, VIL =0.3 V and VIH =VCC –0.3 V.
D
a
Testing is performed with equal loading on referenced pins.
b
This parameter applies to the DEN, WR, WHB and WLB signals.
Am186TMER and Am188TMER Microcontrollers Data Sheet
81
Switching Characteristics over Commercial and Industrial Operating Ranges
PSRAM Write Cycle (40 MHz and 50 MHz)
Preliminary
Parameter
No.
Symbol Description
General Timing Responses
tCLAV
5
AD Address Valid Delay
40 MHz
Min
Max
0
10
ns
12
0
10
ns
Data Valid Delay
0
8
tCHDX
Status Hold Time
0
9
tCHLH
ALE Active Delay
10
tLHLL
ALE Width
11
tCHLL
ALE Inactive Delay
0
12
tCLCL –5=20
20
tCVCTV
23
tLHAV
ALE High to Address Valid
80
tCLCLX
LCS Inactive Delay
0
12
81
tCLCSL
LCS Active Delay
0
12
84
tLRLL
LCS Precharge Pulse Width
0
Control Inactive
32
tWLWH
WR Pulse Width
33
tWHLH
High(a)
WR(a)
34
tWHDX
65
tAVWL
A Address Valid to WR Low
68
tCHAV
CLKOUTA High to A Address Valid
87
tAVBL
A Address Valid to WHB, WLB Low
Data Hold after
R
0
10
ns
10
ns
T
F
10
ns
0
10
ns
0
0
12
A
tCLCH –2
tCLCL –10=15
tCLCL +tCHCL–1.25
0
10
tCHCL –1.25
18
ns
0
tCLCL + tCLCH –1
0
0
ns
10
Testing is performed with equal loading on referenced pins.
b
This parameter applies to the DEN, WR, WHB and WLB signals.
82
D
ns
35
ns
tCLCH –2
ns
12
ns
tCLCL+tCHCL–1.25
ns
0
10
ns
tCHCL –1.25
15
ns
Notes:
All timing parameters are measured at VCC /2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with CL =50 pF. For switching tests, VIL =0.3 V and VIH =VCC –0.3 V.
a
ns
ns
5
2tCLCL –10=40
WR Inactive to ALE
10
tCLCL + tCLCH –1.25
Delay(b)
31
12
7.5
Write Cycle Timing Responses
tCLDOX Data Hold Time
30
ns
15
12
Control Active Delay
Unit
12
tCLDV
1(b)
Max
0
7
tCVCTX
50 MHz
Min
Am186TMER and Am188TMER Microcontrollers Data Sheet
PSRAM Write Cycle Waveforms
t1
t2
t3
t1
t4
tW
CLKOUTA
65
A19–A0
Address
68
8
S6
S6
S6
7
AD15–AD0*,
AD7–AD0**
Data
30
Address
Data
AO15–AO8**
Address
23
11
9
ALE
10
33
32
WR
5
31
20
20
WHB*, WLB*
WB**
LCS
87
80
R
84
Notes:
D
*
Am186ER microcontroller only
**
Am188ER microcontroller only
T
F
34
81
A
Am186TMER and Am188TMER Microcontrollers Data Sheet
31
80
83
Switching Characteristics over Commercial and Industrial Operating Ranges
PSRAM Refresh Cycle (25 MHz and 33 MHz)
Preliminary
Parameter
No.
Symbol Description
General Timing Responses
tCHLH
9
ALE Active Delay
25 MHz
Min
Max
33 MHz
Min
20
10
tLHLL
ALE Width
tCLCL –10=30
11
tCHLL
ALE Inactive Delay
26
tRLRH
RD Pulse Width
27
tCLRH
RD Inactive Delay
0
20
2tCLCL –15=65
0
High(a)
20
tRHLH
RD Inactive to ALE
tCLCH –3
80
tCLCLX
LCS Inactive Delay
0
20
81
tCLCSL
LCS Active Delay
0
20
0
20
0
20
82
tCLRF
CLKOUTA High to RFSH Invalid
85
tRFCY
RFSH Cycle Time
6 x tCLCL
86
tLCRF
LCS Inactive to RFSH Active Delay
2tCLCL –3
15
ns
0
ns
15
ns
15
ns
2tCLCL –15=45
28
Refresh Timing Cycle Parameters
tCLRFD CLKOUTA Low to RFSH Valid
79
Unit
tCLCL –10=20
20
Read/Write Cycle Timing Responses
tCLRL
25
RD Active Delay
Max
0
ns
15
tCLCH –3
A
ns
ns
T
F
0
15
ns
0
15
ns
0
15
ns
0
15
ns
6 x tCLCL
ns
2tCLCL –3
ns
Notes:
All timing parameters are measured at VCC /2 with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions
are with CL =50 pF. For switching tests, VIL =0.3 V and VIH =VCC –0.3 V.
a
Testing is performed with equal loading on referenced pins.
D
84
R
Am186TMER and Am188TMER Microcontrollers Data Sheet
Switching Characteristics over Commercial and Industrial Operating Ranges
PSRAM Refresh Cycle (40 MHz and 50 MHz)
Preliminary
Parameter
No.
Symbol Description
General Timing Responses
tCHLH
9
ALE Active Delay
40 MHz
Min
Max
50 MHz
Min
12
10
tLHLL
ALE Width
tCLCL –5=20
11
tCHLL
ALE Inactive Delay
26
tRLRH
RD Pulse Width
27
tCLRH
RD Inactive Delay
0
10
2tCLCL –10=40
0
High(a)
tRHLH
RD Inactive to ALE
80
tCLCLX
LCS Inactive Delay
0
12
81
tCLCSL
LCS Active Delay
0
12
0
12
0
12
82
tCLRF
CLKOUTA High to RFSH Invalid
85
tRFCY
RFSH Cycle Time
86
tLCRF
LCS Inactive to RFSH Active Delay
10
ns
0
ns
10
ns
10
ns
35
12
28
tCLCH –2
Refresh Timing Cycle Parameters
tCLRFD CLKOUTA Low to RFSH Valid
79
Unit
15
12
Read/Write Cycle Timing Responses
tCLRL
25
RD Active Delay
Max
0
ns
10
tCLCH –2
6 x tCLCL
2tCLCL –1.25
A
ns
ns
T
F
0
10
ns
0
10
ns
0
10
ns
0
10
ns
6 x tCLCL
ns
2tCLCL –1.25
ns
Notes:
All timing parameters are measured at VCC /2 with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions
are with CL =50 pF. For switching tests, VIL =0.3 V and VIH =VCC –0.3 V.
a
Testing is performed with equal loading on referenced pins.
D
R
Am186TMER and Am188TMER Microcontrollers Data Sheet
85
PSRAM Refresh Cycle Waveforms
t1
t2
t3
t4
t1
tW *
CLKOUTA
A19–A0
Address
11
9
ALE
10
27
28
26
RD
80
27
25
LCS
79
RFSH
82
85
86
A
T
F
Note:
* The period tw is fixed at three wait states for PSRAM auto refresh only.
D
86
R
81
Am186TMER and Am188TMER Microcontrollers Data Sheet
Switching Characteristics over Commercial and Industrial Operating Ranges
Interrupt Acknowledge Cycle (25 MHz and 33 MHz)
Preliminary
Parameter
No.
Symbol Description
General Timing Requirements
tDVCL
1
Data in Setup
2
tCLDX
25 MHz
Min
Data in Hold
General Timing Responses
tCHSV
3
Status Active Delay
Max
33 MHz
Min
Max
Unit
10
8
ns
3
3
ns
0
20
0
15
ns
tCLSH
Status Inactive Delay
0
20
0
15
ns
7
tCLDV
Data Valid Delay
0
20
0
15
ns
8
tCHDX
Status Hold Time
0
9
tCHLH
ALE Active Delay
10
tLHLL
ALE Width
11
tCHLL
ALE Inactive Delay
12
tAVLL
AD Address Invalid to ALE
15
tCLAZ
AD Address Float Delay
4
19
tDXDL
0
20
tCLCL –10=30
DEN Inactive to DT/R
tCLCH
tCLAX =0
Low(a)
0
1(b)
20
tCVCTV
Control Active Delay
21
tCVDEX
DEN Inactive Delay
22
tCHCTV
Control Active Delay 2(c)
23
tLHAV
ALE High to Address Valid
Delay(b)
31
tCVCTX
Control Inactive
68
tCHAV
CLKOUTA High to A Address Valid
R
15
tCLAX =0
20
0
20
A
20
15
0
20
0
20
ns
ns
15
0
0
0
ns
tCLCH
20
ns
T
F
tCLCL –10=20
20
Low(a)
ns
15
ns
ns
0
15
ns
0
15
ns
0
15
ns
10
ns
0
15
ns
0
15
ns
Notes:
All timing parameters are measured at VCC /2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with CL =50 pF. For switching tests, VIL =0.3 V and VIH =VCC –0.3 V.
a
Testing is performed with equal loading on referenced pins.
b
This parameter applies to the INTA1–INTA0 signals.
c
This parameter applies to the DEN and DT/R signals.
D
Am186TMER and Am188TMER Microcontrollers Data Sheet
87
Switching Characteristics over Commercial Operating Ranges
Interrupt Acknowledge Cycle (40 MHz and 50 MHz)
Preliminary
Parameter
No.
Symbol Description
General Timing Requirements
tDVCL
1
Data in Setup
2
tCLDX
40 MHz
Min
Data in Hold
General Timing Responses
tCHSV
3
Status Active Delay
Max
50 MHz
Min
Max
5
5
ns
2
2
ns
0
12
0
10
ns
4
tCLSH
Status Inactive Delay
0
12
0
10
ns
7
tCLDV
Data Valid Delay
0
12
0
10
ns
8
tCHDX
Status Hold Time
0
9
tCHLH
ALE Active Delay
10
tLHLL
ALE Width
11
tCHLL
ALE Inactive Delay
12
tAVLL
AD Address Invalid to ALE Low(a)
15
tCLAZ
AD Address Float Delay
tDXDL
20
tCVCTV
Control Active Delay
21
tCVDEX
DEN Inactive Delay
tCHCTV
0
12
tCLCL –5=20
19
22
12
DEN Inactive to DT/R
Control Active Delay
tCLAX =0
2(c)
23
tLHAV
31
tCVCTX
Control Inactive
68
tCHAV
CLKOUTA High to A Address Valid
ALE High to Address Valid
Delay(b)
R
12
12
0
14
A
0
T
F
12
0
12
7.5
0
12
0
10
a
Testing is performed with equal loading on referenced pins.
b
This parameter applies to the INTA1–INTA0 signals.
c
This parameter applies to the DEN and DT/R signals.
D
ns
ns
10
0
0
ns
ns
tCLCH
0
1(b)
10
15
tCLCH
Low(a)
ns
ns
ns
0
10
ns
0
14
ns
0
10
ns
5
ns
0
10
ns
0
10
ns
Notes:
All timing parameters are measured at VCC /2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with CL =50 pF. For switching tests, VIL =0.3 V and VIH =VCC –0.3 V.
88
Unit
Am186TMER and Am188TMER Microcontrollers Data Sheet
Interrupt Acknowledge Cycle Waveforms
t1
t2
t3
t4
tW
CLKOUTA
68
A19–A0
Address
7
S6
8
S6
S6
1
AD15–AD0*,
AD7–AD0**
2 (b)
12
Ptr
15
AO15–AO8**
Address
23
9
ALE
10
11
T
F
4
BHE*
BHE
31
INTA1–INTA0
20
DEN
22
DT/R
19 (c)
R
3
S2–S0
Notes:
D
*
Am186ER microcontroller only
**
Am188ER microcontroller only
A
21
22
4 (a)
22 (d)
Status
a The status bits become inactive in the state preceding t4.
b The data hold time lasts only until the interrupt acknowledge signal deasserts, even if the interrupt acknowledge
transition occurs prior to tCLDX (min).
c This parameter applies to an interrupt acknowledge cycle that follows a write cycle.
d If followed by a write cycle, this change occurs in the state preceding that write cycle.
Am186TMER and Am188TMER Microcontrollers Data Sheet
89
Switching Characteristics over Commercial and Industrial Operating Ranges
Software Halt Cycle (25 MHz and 33 MHz)
Preliminary
Parameter
No.
Symbol Description
General Timing Responses
tCHSV
3
Status Active Delay
25 MHz
Min
33 MHz
Min
Max
Max
Unit
0
20
0
15
ns
tCLSH
Status Inactive Delay
0
20
0
15
ns
5
tCLAV
AD Address Invalid Delay
0
20
0
15
ns
9
tCHLH
ALE Active Delay
15
ns
10
tLHLL
ALE Width
11
tCHLL
ALE Inactive Delay
4
20
tCLCL –10=30
tCLCL –10=20
20
Low(a)
19
tDXDL
22
tCHCTV
Control Active Delay
68
tCHAV
CLKOUTA High to A Address Invalid
DEN Inactive to DT/R
15
0
2(b)
ns
0
0
20
0
20
ns
ns
0
15
ns
0
15
ns
T
F
Notes:
All timing parameters are measured at VCC /2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with CL =50 pF. For switching tests, VIL =0.3 V and VIH =VCC –0.3 V.
a
Testing is performed with equal loading on referenced pins.
b
This parameter applies to the DEN signal.
Switching Characteristics over Commercial and Industrial Operating Ranges
Software Halt Cycle (40 MHz and 50 MHz)
A
Preliminary
Parameter
No.
Symbol Description
General Timing Responses
tCHSV
3
Status Active Delay
R
40 MHz
Min
Max
50 MHz
Min
Max
Unit
0
12
0
10
ns
0
12
0
10
ns
0
12
0
10
ns
10
ns
4
tCLSH
Status Inactive Delay
5
tCLAV
AD Address Invalid Delay
9
tCHLH
ALE Active Delay
10
tLHLL
ALE Width
11
tCHLL
ALE Inactive Delay
19
tDXDL
22
tCHCTV
Control Active Delay 2(b)
0
12
0
10
ns
68
tCHAV
CLKOUTA High to A Address Invalid
0
10
0
10
ns
D
DEN Inactive to DT/R Low
12
tCLCL –5=20
(a)
15
12
0
ns
10
0
ns
Notes:
All timing parameters are measured at VCC /2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with CL =50 pF. For switching tests, VIL =0.3 V and VIH =VCC –0.3 V.
a
Testing is performed with equal loading on referenced pins.
b
This parameter applies to the DEN signal.
90
Am186TMER and Am188TMER Microcontrollers Data Sheet
ns
Software Halt Cycle Waveforms
t1
t2
ti
ti
CLKOUTA
68
A19–A0
Invalid Address
5
S6, AD15–AD0*,
AD7–AD0**,
AO15-AO8**
Invalid Address
10
ALE
9
11
DEN
19
DT/R
22
S2–S0
4
Status
3
Notes:
*
Am186ER microcontroller only
**
Am188ER microcontroller only
D
R
A
T
F
Am186TMER and Am188TMER Microcontrollers Data Sheet
91
Switching Characteristics over Commercial and Industrial Operating Ranges
Clock (25 MHz)
Preliminary
25 MHz
Min
Parameter
No.
Symbol Description
CLKIN Requirements for Times One Mode
tCKIN
36
X1 Period(a)
37
tCLCK
X1 Low Time (1.5
V)(a)
X1 High Time (1.5
V)(a)
40
38
tCHCK
39
tCKHL
X1 Fall Time (3.5 to 1.0
40
tCKLH
X1 Rise Time (1.0 to 3.5 V)(a)
37
tCLCK
X1 Low Time (1.5
V)(a)
X1 High Time (1.5
V)(a)
60
ns
ns
15
ns
20
5
ns
5
ns
33
ns
10
38
tCHCK
39
tCKHL
X1 Fall Time (3.5 to 1.0
40
tCKLH
X1 Rise Time (1.0 to 3.5 V)(a)
CLKOUT Timing
tCLCL
42
Unit
15
V)(a)
CLKIN Requirements for Divide by Two Mode
tCKIN
36
X1 Period(a)
Max
10
V)(a)
CLKOUTA Period
40
ns
T
F
ns
5
ns
5
ns
ns
43
tCLCH
CLKOUTA Low Time (CL =50 pF)
0.5tCLCL –2=18
ns
44
tCHCL
CLKOUTA High Time (CL =50 pF)
0.5tCLCL –2=18
ns
45
tCH1CH2
CLKOUTA Rise Time (1.0 to 3.5 V)
46
tCL2CL1
CLKOUTA Fall Time (3.5 to 1.0 V)
61
tLOCK
Maximum PLL Lock Time
69
tCICOA
X1 to CLKOUTA Skew
70
tCICOB
X1 to CLKOUTB Skew
R
A
3
ns
3
ns
1
ms
20
ns
34
ns
Notes:
All timing parameters are measured at VCC /2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with CL =50 pF. For switching tests, VIL =0.3 V and VIH =VCC –0.3 V.
a
The specifications for CLKIN are applicable to the Divide by Two and Times One modes.
D
The Times One mode should be used for operations from 16 MHz to 20 MHz. The Times Four mode should
be used for operations above 20 MHz.
92
Am186TMER and Am188TMER Microcontrollers Data Sheet
Switching Characteristics over Commercial and Industrial Operating Ranges
Clock (33 MHz)
Parameter
No.
Symbol Description
CLKIN Requirements for Times Four Mode
tCKIN
36
X1 Period(a)
37
tCLCK
X1 Low Time (1.5
V)(a)
X1 High Time (1.5
V)(a)
38
tCHCK
39
tCKHL
X1 Fall Time (3.5 to 1.0
40
tCKLH
X1 Rise Time (1.0 to 3.5 V)(a)
Preliminary
33 MHz
Min
Max
Unit
120
125
ns
55
ns
55
ns
V)(a)
CLKIN Requirements for Times One Mode
tCKIN
36
X1 Period(a)
30
X1 Low Time (1.5
V)(a)
10
X1 High Time (1.5
V)(a)
37
tCLCK
38
tCHCK
39
tCKHL
X1 Fall Time (3.5 to 1.0
40
tCKLH
X1 Rise Time (1.0 to 3.5 V)(a)
10
V)(a)
CLKIN Requirements for Divide by Two Mode
tCKIN
36
X1 Period(a)
37
tCLCK
X1 Low Time (1.5
2.5
V)(a)
2.5
38
tCHCK
X1 High Time (1.5
39
tCKHL
X1 Fall Time (3.5 to 1.0 V)(a)
40
tCKLH
X1 Rise Time (1.0 to 3.5 V)(a)
CLKOUT Timing
tCLCL
42
CLKOUTA Period
tCLCH
CLKOUTA Low Time (CL =50 pF)
44
tCHCL
CLKOUTA High Time (CL =50 pF)
45
tCH1CH2
CLKOUTA Rise Time (1.0 to 3.5 V)
46
tCL2CL1
CLKOUTA Fall Time (3.5 to 1.0 V)
61
tLOCK
69
70
43
15
V)(a)
R
A
30
5
ns
5
ns
60
ns
ns
T
F
ns
5
ns
5
ns
33
ns
ns
ns
5
ns
5
ns
ns
0.5tCLCL –1.5=13.5
ns
0.5tCLCL –1.5=13.5
ns
3
ns
3
ns
Maximum PLL Lock Time
1
ms
tCICOA
X1 to CLKOUTA Skew
20
ns
tCICOB
X1 to CLKOUTB Skew
26
ns
D
Notes:
All timing parameters are measured at VCC /2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with CL =50 pF. For switching tests, VIL =0.3 V and VIH =VCC –0.3 V.
a
The Times One mode should be used for operations from 16 MHz to 20 MHz. The Times Four mode should
be used for operations above 20 MHz.
Am186TMER and Am188TMER Microcontrollers Data Sheet
93
Switching Characteristics over Commercial and Industrial Operating Ranges
Clock (40 MHz and 50 MHz)
Preliminary
Parameter
No.
Symbol Description
CLKIN Requirements for Times Four Mode
tCKIN
36
X1 Period(a)
37
tCLCK
X1 Low Time (1.5
V)(a)
X1 High Time (1.5
V)(a)
38
tCHCK
39
tCKHL
X1 Fall Time (3.5 to 1.0
40
tCKLH
X1 Rise Time (1.0 to 3.5 V)(a)
37
tCLCK
X1 Low Time (1.5
X1 High Time (1.5
V)(a)
39
tCKHL
X1 Fall Time (3.5 to 1.0
40
tCKLH
X1 Rise Time (1.0 to 3.5 V)(a)
X1 Low Time (1.5
X1 High Time (1.5
V)(a)
ns
45
35
ns
5
5
ns
5
5
ns
60
ns
ns
5
5
12.5
39
tCKHL
33
X1 Fall Time (3.5 to 1.0
40
tCKLH
X1 Rise Time (1.0 to 3.5 V)(a)
1.25
V)(a)
CLKOUTA Period
A
T
F
Not Supported
Not Supported
5
5
25
ns
ns
ns
ns
ns
ns
ns
ns
20
ns
tCLCH
CLKOUTA Low Time (CL =50 pF)
0.5tCLCL–1.25=11.25
0.5tCLCL –1=9
ns
44
tCHCL
CLKOUTA High Time (CL =50 pF)
0.5tCLCL–1.25=11.25
0.5tCLCL –1=9
ns
45
tCH1CH2
CLKOUTA Rise Time (1.0 to 3.5 V)
46
tCL2CL1
CLKOUTA Fall Time (3.5 to 1.0 V)
61
tLOCK
69
70
R
3
3
ns
3
3
ns
Maximum PLL Lock Time
1
1
ms
tCICOA
X1 to CLKOUTA Skew
20
15
ns
tCICOB
X1 to CLKOUTB Skew
24
21
ns
D
Notes:
All timing parameters are measured at VCC /2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with CL =50 pF. For switching tests, VIL =0.3 V and VIH =VCC –0.3 V.
94
125
ns
1.25
tCHCK
43
a
Unit
35
7.5
38
CLKOUT Timing
tCLCL
42
80
Max
45
V)(a)
CLKIN Requirements for Divide by Two Mode
tCKIN
36
X1 Period(a)
tCLCK
125
50 MHz
Min
7.5
tCHCK
37
100
25
38
V)(a)
Max
V)(a)
CLKIN Requirements for Times One Mode
tCKIN
36
X1 Period(a)
V)(a)
40 MHz
Min
The Times One mode should be used for operations from 16 MHz to 20 MHz. The Times Four mode should
be used for operations above 20 MHz.
Am186TMER and Am188TMER Microcontrollers Data Sheet
Clock Waveforms—Active Mode
X2
36
37
38
X1
40
39
46
45
CLKOUTA
(Divide by one)
69
42
44
43
CLKOUTB
70
Clock Waveforms—Power-Save Mode
X2
X1
CLKOUTA
(Divide by four)
CLKOUTB *
CLKOUTB **
Notes:
*
D
R
A
T
F
The CLKOUTB Output Frequency (CBF) bit in the Power Save Control Register (PDCON) is set to 1.
** The CLKOUTB Output Frequency (CBF) bit in the Power Save Control Register (PDCON) is cleared to 0.
Am186TMER and Am188TMER Microcontrollers Data Sheet
95
Switching Characteristics over Commercial and Industrial Operating Ranges
Ready and Peripheral Timing (25 MHz and 33 MHz)
Preliminary
25 MHz
33 MHz
Min
Max
Min
Max
Parameter
No.
Symbol Description
Ready and Peripheral Timing Requirements
tSRYCL
47
SRDY Transition Setup Time(a)
Time(a)
tCLSRY
SRDY Transition Hold
49
tARYCH
ARDY Resolution Transition Setup Time(b)
50
tCLARX
ARDY Active Hold
51
tARYCHL
ARDY Inactive Holding Time
48
52
tARYLCL
53
tINVCH
54
tINVCL
ARDY Setup
Time(a)
Peripheral Setup
DRQ Setup
Time(a)
Time(b)
Time(b)
Unit
10
8
ns
3
3
ns
10
8
ns
4
4
ns
4
4
ns
15
10
ns
10
8
ns
10
8
ns
Peripheral Timing Responses
tCLTMV
55
Timer Output Delay
20
T
F
15
ns
Notes:
All timing parameters are measured at VCC /2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with CL =50 pF. For switching tests, VIL =0.3 V and VIH =VCC –0.3 V.
a
This timing must be met to guarantee proper operation.
b
This timing must be met to guarantee recognition at the clock edge.
A
Switching Characteristics over Commercial and Industrial Operating Ranges
Ready and Peripheral Timing (40 MHz and 50 MHz)
R
Parameter
No.
Symbol Description
Ready and Peripheral Timing Requirements
tSRYCL SRDY Transition Setup Time(a)
47
48
tCLSRY
SRDY Transition Hold
D
Time(a)
Time(b)
Preliminary
40 MHz
50 MHz
Min
Max
Min
Max
Unit
5
5
ns
2
2
ns
5
5
ns
49
tARYCH
50
tCLARX
ARDY Active Hold Time
3
3
ns
51
tARYCHL
ARDY Inactive Holding Time
5
5
ns
5
5
ns
5
5
ns
5
5
ns
52
tARYLCL
53
tINVCH
54
tINVCL
ARDY Resolution Transition Setup
ARDY Setup
(a)
Time(a)
Peripheral Setup
DRQ Setup
Time(b)
Time(b)
Peripheral Timing Responses
tCLTMV Timer Output Delay
55
12
10
Notes:
All timing parameters are measured at VCC /2 with 50 pF loading on CLKOUTA unless otherwise noted. All
output test conditions are with CL =50 pF. For switching tests, VIL =0.3 V and VIH =VCC –0.3 V.
a
This timing must be met to guarantee proper operation.
b
This timing must be met to guarantee recognition at the clock edge.
96
Am186TMER and Am188TMER Microcontrollers Data Sheet
ns
Synchronous Ready Waveforms
Case 11
tW
tW
tW
t4
Case 21
t3
tW
tW
t4
Case 31
t2
t3
tW
t4
Case 41
t1
t2
t3
t4
Case 52
t1
t2
t3
tw
t4
CLKOUTA
47
SRDY (Normally NotReady System)
48
SRDY (Normally
Ready System)
Notes:
1. Normally not-ready system.
2. Normally ready system.
Asynchronous Ready Waveforms
CLKOUTA
Case 11
tW
Case 21
t3
Case 31
t2
Case 41
t1
Case 52
t1
D
ARDY (Normally
Not-Ready System)
R
A
tW
T
F
tW
t4
tW
t4
t3
tW
t4
t2
t3
t4
t2
t3
tw
tW
49
t4
50
49
ARDY (Normally
Ready System)
50
51
52
Notes:
1. Normally not-ready system.
2. Normally ready system.
Am186TMER and Am188TMER Microcontrollers Data Sheet
97
Peripheral Waveforms
CLKOUTA
53
INT4–INT0, NMI,
TMRIN1–TMRIN0
54
DRQ1–DRQ0
55
TMROUT1–
TMROUT0
D
98
R
A
T
F
Am186TMER and Am188TMER Microcontrollers Data Sheet
Switching Characteristics over Commercial and Industrial Operating Ranges
Reset and Bus Hold (25 MHz and 33 MHz)
Preliminary
25 MHz
33 MHz
Min
Max
Min
Max
Parameter
No.
Symbol Description
Reset and Bus Hold Timing Requirements
tCLAV
5
AD Address Valid Delay
Unit
0
20
0
15
ns
20
0
15
ns
15
tCLAZ
AD Address Float Delay
0
57
tRESIN
RES Setup Time
10
8
ns
58
tHVCL
10
8
ns
HOLD
Setup(a)
Reset and Bus Hold Timing Responses
tCLHAV
62
HLDA Valid Delay
15
ns
63
tCHCZ
Command Lines Float Delay
0
20
20
0
15
ns
64
tCHCV
Command Lines Valid Delay (after Float)
20
15
ns
T
F
Notes:
All timing parameters are measured at VCC /2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with CL =50 pF. For switching tests, VIL =0.3 V and VIH =VCC –0.3 V.
a
This timing must be met to guarantee recognition at the next clock.
Switching Characteristics over Commercial and Industrial Operating Ranges
Reset and Bus Hold (40 MHz and 50 MHz)
Parameter
No.
Symbol Description
Reset and Bus Hold Timing Requirements
tCLAV
5
AD Address Valid Delay
R
15
tCLAZ
AD Address Float Delay
57
tRESIN
RES Setup Time
58
tHVCL
HOLD
Setup(a)
A
Preliminary
40 MHz
Min
Max
50 MHz
Min
Max
Unit
0
12
0
10
ns
0
12
0
10
ns
5
5
ns
5
5
ns
Reset and Bus Hold Timing Responses
D
62
tCLHAV
HLDA Valid Delay
63
tCHCZ
Command Lines Float Delay
tCHCV
Command Lines Valid Delay (after Float)
64
0
12
0
10
ns
12
10
ns
12
10
ns
Notes:
All timing parameters are measured at VCC /2 with 50 pF loading on CLKOUTA, unless otherwise noted. All
output test conditions are with CL =50 pF. For switching tests, VIL =0.3 V and VIH =VCC –0.3 V.
a
This timing must be met to guarantee recognition at the next clock.
Am186TMER and Am188TMER Microcontrollers Data Sheet
99
Reset Waveforms
X1
57
57
RES
CLKOUTA
Note:
RES must be held Low for 1 ms during power-up to ensure proper device initialization. Activating the PLL will require 1 ms
to achieve a stable clock.
Signals Related to Reset Waveforms
RES
CLKOUTA
BHE/ADEN*,
RFSH2/ADEN*,
S6/CLKSEL1* **,
UZI/CLKSEL2**
S1/IMDIS*,
and S0/SREN*
AD15–AD0 (186)
AO15–AO8,
AD7–AD0 (188)
R
Three-State
D
S6/CLKSEL1***,
UZI/CLKSEL2***
Notes:
Divide by Two and Times One Modes
A
T
F
Three-State
Times Four Mode
Three-State
* Because BHE, RFSH2, S6, UZI, S1, and S0 are not driven for 6.5 clocks after reset, their alternate functions can be
asserted with external pulldown resistors.
** In Divide by Two mode and Times One mode, S6/CLKSEL1 and UZI/CLKSEL2 must be held for 3 clock cycles after
reset negates.
***In Times Four mode, S6/CLKSEL1 and UZI/CLKSEL2 must be held for 5 clock cycles after reset negates.
100
Am186TMER and Am188TMER Microcontrollers Data Sheet
Bus Hold Waveforms—Entering
Case 1
ti
ti
ti
Case 2
t4
ti
ti
CLKOUTA
58
HOLD
62
HLDA
15
AD15–AD0, DEN
63
A19–A0, S6, RD,
WR, BHE,
DT/R, S2-S0
WHB, WLB
Bus Hold Waveforms—Leaving
CLKOUTA
Case 1
ti
Case 2
ti
R
58
HOLD
HLDA
D
A
ti
ti
T
F
ti
t1
t4
t1
62
5
AD15–AD0, DEN
A19–A0, S6, RD,
WR, BHE,
DT/R, S2–S0
WHB, WLB
64
Am186TMER and Am188TMER Microcontrollers Data Sheet
101
Switching Characteristics over Commercial and Industrial Operating Ranges
Synchronous Serial Interface (SSI) (25 MHz and 33 MHz)
Parameter
No.
Symbol Description
Synchronous Serial Port Timing Requirements
tDVSH
75
Data Valid to SCLK High
77
tSHDX
SCLK High to SPI Data Hold
Preliminary
25 MHz
33 MHz
Min
Max
Min
Max
Unit
10
8
ns
3
2
ns
Synchronous Serial Port Timing Responses
CLKOUTA Low to
71
tCLEV
SDEN1 or SDEN0 Valid
20
0
15
ns
72
tCLSL
CLKOUTA Low to SCLK Low
20
0
15
ns
78
tSLDV
SCLK Low to Data Valid
20
0
15
ns
Note:
All timing parameters are measured at VCC /2 with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions
are with CL =50 pF. For switching tests, VIL =0.3 V and VIH =VCC –0.3 V.
T
F
Switching Characteristics over Commercial and Industrial Operating Ranges
Synchronous Serial Interface (SSI) (40 MHz and 50 MHz)
Preliminary
Parameter
No.
Symbol Description
Synchronous Serial Port Timing Requirements
tDVSH
75
Data Valid to SCLK High
77
tSHDX
SCLK High to SPI Data Hold
R
Synchronous Serial Port Timing Responses
CLKOUTA Low to
tCLEV
71
SDEN1 or SDEN0 Valid
tCLSL
72
CLKOUTA Low to SCLK Low
78
tSLDV
SCLK Low to Data Valid
D
40 MHz
Min
Max
A
5
2
50 MHz
Min
Max
Unit
5
ns
2
ns
0
12
0
10
ns
0
12
0
10
ns
0
12
0
10
ns
Note:
All timing parameters are measured at VCC /2 with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions
are with CL =50 pF. For switching tests, VIL =0.3 V and VIH =VCC –0.3 V.
102
Am186TMER and Am188TMER Microcontrollers Data Sheet
Synchronous Serial Interface (SSI) Waveforms
CLKOUTA
71
SDEN1 or SDEN0
72
72
SCLK
SDATA (RX)
DATA
77
75
SDATA (TX)
DATA
78
T
F
Note:
SDATA is bidirectional and used for either transmit (TX) or receive (RX). Timing is shown separately for each case.
D
R
A
Am186TMER and Am188TMER Microcontrollers Data Sheet
103
TQFP PHYSICAL DIMENSIONS
PQL 100, Trimmed and Formed
Thin Quad Flat Pack
100
1
15.80
16.20
13.80
14.20
13.80
14.20
15.80
16.20
1.35
1.45
D
1.00 REF.
0.17
0.27
R
A
T
F
11° – 13°
1.60 MAX
0.50 BSC
11° – 13°
Notes:
1. All measurements are in millimeters, unless otherwise noted.
2. Not to scale; for reference only.
104
Am186TMER and Am188TMER Microcontrollers Data Sheet
16-038-PQT-2_AI
PQL100
9.3.96 lv
PQFP PHYSICAL DIMENSIONS
PQR 100, Trimmed and Formed
Plastic Quad Flat Pack
Pin 100
12.35
REF
13.90
14.10
17.00
17.40
Pin 80
Pin 1 I.D.
T
F
18.85
REF
19.90
20.10
23.00
23.40
Pin 30
2.70
2.90
0.25
MIN
D
R
A
0.65 BASIC
Pin 50
3.35
MAX
SEATING PLANE
16-038-PQR-1_AH
PQR100
DP92
6-20-96 lv
Notes:
1. All measurements are in millimeters, unless otherwise noted.
2. Not to scale; for reference only.
Am186TMER and Am188TMER Microcontrollers Data Sheet
105
D
106
R
A
T
F
Am186TMER and Am188TMER Microcontrollers Data Sheet
INDEX
A
C
A17/PIO7, 30
A18/PIO8, 30
A19/PIO9, 30
absolute maximum ratings, 60
active mode
clock waveforms, 95
AD15–AD8, 30
AD7–AD0, 30
address bus
Am186ER
disable in effect, 42
normal operation, 42
Am188ER
disable in effect, 43
ALE, 31
alphabetic PIO pin assignments, 36
ambient temperatures
ambient, 62
PQFP with four-to-six layer board, 65
PQFP with two-layer board, 63
TQFP with four-to-six layer boards, 66
TQFP with two-layer board, 64
AO15–AO8, 30
application considerations, 14
ARDY, 31
asynchronous ready waveforms, 97
asynchronous serial port, 56
B
BHE/ADEN, 31
block diagram
Am186ER, 2
Am188ER, 3
bus cycle encoding, 37
bus hold waveforms
entering, 101
leaving, 101
bus interface unit, 41
bus operation, 41
byte write enables, 41
chip-select
low memory, 51
overlap, 51
timing, 49
unit, 49
upper memory, 51
chip-selects
midrange memory, 51
peripheral, 52
CLKOUTA, 31
CLKOUTB, 31
clock (25 MHz), 92
clock (33 MHz), 93
clock (40 and 50 MHz), 94
clock and power management, 44
clock frequencies
minimum and maximum, 44
clock generation, 14
clock organization, 48
clock source
crystal driven, 45
clock waveforms
active mode, 95
power-save mode, 95
clocking modes, 39
commercial operating ranges, 60
comparison
Am186ER and 80C186 microcontrollers, 15
crystal
selecting, 45
crystal-driven clock source, 45
customer support, 13
documentation and literature, 13
hotline and web, 13
literature ordering, 13
third-party development support products, 13
web home page, 13
Am186™CC Communications Controller Data Sheet
Index-1
D
H
DC characteristics, 60
demonstration board products, 13
DEN/PIO5, 31
description, 1
functional, 40
direct memory access, 54
DMA
Am186ER maximum transfer rates, 55
asynchronous serial port transfers, 55
channel control registers, 55–56
operation, 55
priority, 55–56
transfers through serial port, 56
unit block diagram, 56
documentation
See customer support.
DRQ1–DRQ0, 32
DT/R/PIO4, 32
E
emulator and debug modes, 52
internal memory disable, 52
show read enable, 52
external source clock, 45
HLDA, 32
HOLD, 32
hotline and world wide web support, 13
I
I/O circuitry, 59
I/O space, 40
industrial operating ranges, 60
initialization and processor reset, 48
input/output circuitry, 59
INT0, 32
INT1/SELECT, 32
INT2/INTA0/PIO31, 33
INT3/INTA1/IRQ, 33
INT4/PIO30, 33
interaction with external RAM, 52
internal memory, 52
internal memory disable, 52
internal RAM show read cycle waveform, 77
interrupt acknowledge cycle (25 and 33 MHz), 87
interrupt acknowledge cycle (40 and 50 MHz), 88
interrupt acknowledge cycle waveforms, 89
interrupt control unit, 53
programming, 53
F
features
3.3-V operation with 5-V-tolerant I/O, 14
available native development tools, applications, and
system software, 1
enhanced bus interface, 1
enhanced functionality, 1, 14
enhanced integrated peripherals, 1
enhanced performance, 14
faster access to memory and clock input modes, 1
integrated RAM, 14
memory integration, 1
software-compatible, 1
x86 software compatibility, 14
four-pin interface, 57
functional description, 40
J
junction temperature calculation, 62
L
LCS/ONCE0, 33
literature
See customer support.
logic diagram
ARDY and SRDY synchronization, 49
low memory chip select, 51
low-voltage operation, 57
low-voltage standard, 59
G
GND, 32
Index-2
Am186™CC Communications Controller Data Sheet
M
MCS2–MCS0, 34
MCS3/RFSH/PIO25, 33
memory interface, 14
example, 15
memory maps, 50
diagram, 50
memory organization, 40
midrange memory chip selects, 51
modes
emulator and debug, 52
N
NMI, 34
nonmultiplexed address bus, 41
numeric PIO pin assignments, 36
O
operating ranges, 60
commercial and industrial, 60
operation
low-voltage, 57
ordering information, 4
oscillator configurations, 45
output enable, 41
P
PCB, 44
reading and writing, 44
PCS0/PIO16, 34
PCS1/PIO17, 34
PCS2/PIO18, 34
PCS3/PIO19, 34
PCS3–PCS0, 34
PCS5/A1/PIO3, 34
PCS6/A2/PIO2, 34
peripheral chip selects, 52
peripheral control block, 44
peripheral waveforms, 98
phase-locked loop, 44
pins
A19–A0, 30
AD15–AD8, 30
AD7–AD0, 30
ALE, 31
alphabetic PIO assignments, 36
AO15–AO8, 30
ARDY, 31
BHE/ADEN, 31
CLKOUTA, 31
CLKOUTB, 31
clocking modes, 39
DEN/PIO5, 31
descriptions, 30
DRQ1–DRQ0, 32
DT/R/PIO4, 32
GND, 32
HLDA, 32
HOLD, 32
INT0, 32
INT1/SELECT, 32
INT2/INTA0/PIO31, 33
INT3/INTA1/IRQ, 33
INT4/PIO30, 33
LCS/ONCE0, 33
MCS2–MCS0, 34
MCS3/RFSH/PIO25, 33
NMI, 34
numeric PIO assignments, 36
PCS0/PIO16, 34
PCS1/PIO17, 34
PCS3–PCS0, 34
PCS6/A2/PIO2, 34
PIO, 57
PIO31–PIO0, 35
RD, 35
RES, 35
RFSH2/ADEN, 35
RXD/PIO28, 35
S0/SREN, 37
S1/IMDIS, 37
S2, 35
S6/CLKSEL1/PIO29, 37
SCLK/PIO20, 37
SDATA/PIO21, 37
SDEN0/PIO22, 37
SDEN1/PIO23, 37
SRDY/PIO6, 38
TMRIN0/PIO11, 38
TMRIN1/PIO0, 38
TMROUT0/PIO10, 38
TMROUT1/PIO1, 38
TXD/PIO27, 38
UCS/ONCE1, 38
used by emulators, 30
UZI/CLKSEL2/PIO26, 38
VCC, 39
WB (Am188ER microcontroller only), 39
WHB, 39
WLB (Am186ER microcontroller only), 39
WR, 39
X1, 39
X2, 39
PIO31–PIO0, 35
plastic quad flat pack, 105
Am186™CC Communications Controller Data Sheet
Index-3
PLL, 44
power consumption calculation, 62
power savings, 59
power-save mode
clock waveforms, 95
power-save operation, 48
PQFP connection diagram and pinouts
Am186ER, 22
Am188ER, 25
PQFP physical dimensions, 105
PQFP pin assignments
Am186ER
sorted by pin name, 24
sorted by pin number, 23
Am188ER
sorted by pin name, 27
sorted by pin number, 26
programmable I/O (PIO) pins, 57
programming
interrupt control unit, 53
ready and wait-state, 49
pseudo static RAM
support, 44
PSRAM
support, 44
PSRAM read cycle (25 and 33 MHz), 78
PSRAM read cycle (40 and 50 MHz), 79
PSRAM read cycle waveforms, 80
PSRAM refresh cycle (25 and 33 MHz), 84
PSRAM refresh cycle (40 and 50 MHz), 85
PSRAM refresh cycle waveforms, 86
PSRAM write cycle
waveforms, 83
PSRAM write cycle (25 and 33 MHz), 81
PSRAM write cycle (40 and 50 MHz), 82
R
RAM
interaction with external, 52
RD, 35
read cycle waveforms, 72
ready and peripheral timing (25 and 33 MHz), 96
ready and peripheral timing (40 and 50 MHz), 96
ready and wait-state programming, 49
refresh control unit, 53
related documents, 13
RES, 35
reset
initialization and processor, 48
reset and bus hold (25 and 33 MHz), 99
reset and bus hold (40 and 50 MHz), 99
Index-4
reset configuration register, 48
reset waveforms, 100
related signals, 100
revision history, 10
RFSH2/ADEN, 35
RXD/PIO28, 35
S
S0/SREN, 37
S1/IMDIS, 37
S2, 35
S6/CLKSEL1/PIO29, 37
SCLK/PIO20, 37
SDATA/PIO21, 37
SDEN0/PIO22, 37
SDEN1/PIO23, 37
serial ports
DMA transfers, 55
software halt cycle (25 and 33 MHz), 90
software halt cycle (40 and 50 MHz), 90
software halt cycle waveforms, 91
source clock
external, 45
SRDY/PIO6, 38
SSI, 102
multiple read, 58
multiple write, 58
waveforms, 103
support, 13
switching characteristics
clock (25 MHz), 92
clock (33 MHz), 93
clock (40 and 50 MHz), 94
commercial, 67
industrial, 67
internal RAM show read cycle (25 and 33 MHz), 76
interrupt acknowledge cycle (25 and 33 MHz), 87
interrupt acknowledge cycle (40 and 50 MHz), 88
PSRAM read cycle (25 and 33 MHz), 78
PSRAM read cycle (40 and 50 MHz), 79
PSRAM refresh cycle (25 and 33 MHz), 84
PSRAM refresh cycle (40 and 50 MHz), 85
PSRAM write cycle (25 and 33 MHz), 81
PSRAM write cycle (40 and 50 MHz), 82
read cycle (25 and 33 MHz), 70
read cycle (40 and 50 MHz), 71
ready and peripheral timing (25 and 33 MHz), 96
ready and peripheral timing (40 and 50 MHz), 96
reset and bus hold (25 and 33 MHz), 99
reset and bus hold (40 and 50 MHz), 99
software halt cycle (25 and 33 MHz), 90
software halt cycle (40 and 50 MHz), 90
Am186™CC Communications Controller Data Sheet
synchronous serial interface (25 and 33 MHz), 102
synchronous serial interface (40 and 50 MHz), 102
write cycle (25 and 33 MHz), 72–73
write cycle (40 and 50 MHz), 74, 76
switching parameter symbols
alphabetical key, 68
numerical key, 69
switching waveforms
key, 67
synchronous ready waveforms, 97
synchronous serial interface, 56
multiple read, 58
multiple write, 58
synchronous serial interface (25 and 33 MHz), 102
synchronous serial interface (40 and 50 MHz), 102
synchronous serial interface waveforms, 103
T
thermal characteristics, 61
thermal characteristics equations, 61
thermal resistance, 61
thin quad flat pack, 104
third-party development support products, 13
timer control unit, 53
TMRIN0/PIO11, 38
TMRIN1/PIO0, 38
TMROUT0/PIO10, 38
TMROUT1/PIO1, 38
TQFP connection diagram and pinouts
Am186ER, 16
Am188ER, 19
TQFP package, 61
TQFP physical dimensions, 104
TQFP pin assignments
Am186ER, 19
sorted by pin name, 18
sorted by pin number, 17
Am188ER
sorted by pin name, 21
sorted by pin number, 20
two-component address, 40
TXD/PIO27, 38
typical ambient temperatures, 62
V
VCC, 39
W
watchdog timer, 54
waveform
internal RAM show read, 77
waveforms, 67
asynchronous ready, 97
bus hold
entering, 101
leaving, 101
interrupt acknowledge cycle, 89
peripheral, 98
PSRAM read cycle, 80
PSRAM refresh cycle, 86
PSRAM write cycle, 83
read cycle, 72
reset, 100
signals related to reset, 100
software halt cycle, 91
SSI, 103
synchronous ready, 97
synchronous serial interface, 103
write cycle, 75
WB (Am188ER microcontroller only), 39
WHB, 39
WLB (Am186ER microcontroller only), 39
world wide web support, 13
WR, 39
write cycle waveforms, 75
www
home page, 13
support, 13
X
X1, 39
X2, 39
U
UCS/ONCE1, 38
upper memory chip select, 51
UZI/CLKSEL2/PIO26, 38
Am186™CC Communications Controller Data Sheet
Index-5
Trademarks
 2000 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
Am386, Am5x86, and Am486 are registered trademarks, and Am186, Am188, E86, Élan, and AMD-K6 are trademarks of Advanced Micro
Devices, Inc.
FusionE86 is a service mark of Advanced Micro Devices, Inc.
Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Disclaimer
The contents of this document are provided in connection with Advanced Micro Devices, Inc. ("AMD") products. AMD makes no representations
or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in AMD's Standard Terms and Conditions of Sale, AMD assumes no
liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of
merchantability, fitness for a particular purpose, or infringement of any intellectual property right.
AMD's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the
body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD's product could create a
situation where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue or make
changes to its products at any time without notice.
© 2000 Advanced Micro Devices, Inc.
All rights reserved.
Am186™CC Communications Controller Data Sheet