ON MC74HC4852ADTR2G Analog multiplexers/demultiplexers with injection current effect control Datasheet

MC74HC4851A,
MC74HC4852A
Analog Multiplexers/
Demultiplexers with
Injection Current Effect
Control
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MARKING
DIAGRAMS
Automotive Customized
These devices are pin compatible to standard HC405x and
MC1405xB analog mux/demux devices, but feature injection current
effect control. This makes them especially suited for usage in
automotive applications where voltages in excess of normal logic
voltage are common.
The injection current effect control allows signals at disabled analog
input channels to exceed the supply voltage range without affecting
the signal of the enabled analog channel. This eliminates the need for
external diode/ resistor networks typically used to keep the analog
channel signals within the supply voltage range.
The devices utilize low power silicon gate CMOS technology. The
Channel Select and Enable inputs are compatible with standard CMOS
outputs.
Features
•
•
•
•
•
•
16
PDIP−16
N SUFFIX
CASE 648
16
1
1
16
SOIC−16
D SUFFIX
CASE 751B
16
1
HC485xAG
AWLYWW
1
16
SOIC−16 WIDE
DW SUFFIX
CASE 751G
16
Injection Current Cross−Coupling Less than 1mV/mA (See Figure 9)
Pin Compatible to HC405X and MC1405XB Devices
Power Supply Range (VCC − GND) = 2.0 to 6.0 V
In Compliance With the Requirements of JEDEC Standard No. 7A
Chip Complexity: 154 FETs or 36 Equivalent Gates
Pb−Free Packages are Available*
MC74HC485xAN
AWLYYWWG
1
HC4851A
AWLYWWG
1
16
16
1
TSSOP−16
DT SUFFIX
CASE 948F
HC48
5xA
ALYWG
G
1
x
= 1 or 2
A
= Assembly Location
L, WL
= Wafer Lot
Y, YY
= Year
W, WW = Work Week
G
= Pb−Free Package
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2005
June, 2005 − Rev. 6
1
Publication Order Number:
MC74HC4851A/D
MC74HC4851A, MC74HC4852A
FUNCTION TABLE − MC74HC4851A
Control Inputs
13
X0
14
X1
15
X2
ANALOG
12
MULTIPLEXER/
INPUTS/ X3
DEMULTIPLEXER
OUTPUTS X4 1
5
X5
2
X6
4
X7
11
A
CHANNEL
10
B
SELECT
9
INPUTS
C
6
ENABLE
PIN 16 = VCC
PIN 8 = GND
3
X
Select
B
A
Enable
C
L
L
L
L
L
L
L
L
H
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
X
COMMON
OUTPUT/
INPUT
ON Channels
L
H
L
H
L
H
L
H
X
X0
X1
X2
X3
X4
X5
X6
X7
NONE
VCC
X2
X1
X0
X3
A
B
C
16
15
14
13
12
11
10
9
6
7
8
GND
Figure 1. MC74HC4851A Logic Diagram
Single−Pole, 8−Position Plus Common Off
1
2
3
4
5
X4
X6
X
X7
X5
Enable NC
Figure 2. MC74HC4851A 16−Lead Pinout (Top View)
FUNCTION TABLE − MC74HC4852A
Control Inputs
Enable
B
Select
A
L
L
L
L
H
L
L
H
H
X
L
H
L
H
X
ON Channels
12
ANALOG
INPUTS/OUTPUTS
CHANNEL-SELECT
INPUTS
X0
14
X1
15
X2
11
X3
Y0
Y1
Y2
Y3
A
B
ENABLE
X SWITCH
13
X
COMMON
OUTPUTS/INPUTS
1
Y SWITCH
3
NONE
Y
4
10
9
X0
X1
X2
X3
X = Don’t Care
5
2
Y0
Y1
Y2
Y3
PIN 16 = VCC
PIN 8 = GND
VCC
X2
X1
X
X0
X3
A
B
16
15
14
13
12
11
10
9
6
7
8
GND
6
Figure 3. MC74HC4852A Logic Diagram
Double−Pole, 4−Position Plus Common Off
1
2
3
4
5
Y0
Y2
Y
Y3
Y1
Enable NC
Figure 4. MC74HC4852A 16−Lead Pinout (Top View)
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2
MC74HC4851A, MC74HC4852A
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MAXIMUM RATINGS
Symbol
Value
Unit
VCC
Positive DC Supply Voltage
(Referenced to GND)
–0.5 to + 7.0
V
Vin
DC Input Voltage (Any Pin)
(Referenced to GND)
–0.5 to VCC + 0.5
V
DC Current, Into or Out of Any Pin
$25
mA
PD
Power Dissipation in Still Air,
750
500
450
mW
Tstg
Storage Temperature Range
–65 to + 150
°C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package
I
Parameter
Plastic DIP†
SOIC Package†
TSSOP Package†
°C
260
Maximum ratings are those values beyond which device damage can occur. Maximum ratings
applied to the device are individual stress limit values (not normal operating conditions) and are
not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
†Derating — Plastic DIP: – 10 mW/°C from 65° to 125°C
SOIC Package: – 7 mW/°C from 65° to 125°C
TSSOP Package: − 6.1 mW/°C from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor
High−Speed CMOS Data Book (DL129/D).
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
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RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
VCC
Positive DC Supply Voltage
(Referenced to GND)
2.0
6.0
V
Vin
DC Input Voltage (Any Pin)
(Referenced to GND)
GND
VCC
V
Static or Dynamic Voltage Across Switch
0.0
1.2
V
TA
Operating Temperature Range, All Package Types
– 55
+ 125
°C
tr, tf
Input Rise/Fall Time
(Channel Select or Enable Inputs)
0
0
0
1000
500
400
ns
VIO*
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
*For voltage drops across switch greater than 1.2 V (switch on), excessive VCC current may be
drawn; i.e., the current out of the switch may contain both VCC and switch input components. The
reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
DC CHARACTERISTICS — Digital Section (Voltages Referenced to GND) VEE = GND, Except Where Noted
Symbol
Parameter
Condition
Guaranteed Limit
VCC
V
−55 to 25°C
≤85°C
≤125°C
Unit
VIH
Minimum High−Level Input Voltage,
Channel−Select or Enable Inputs
Ron = Per Spec
2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
V
VIL
Maximum Low−Level Input Voltage,
Channel−Select or Enable Inputs
Ron = Per Spec
2.0
3.0
4.5
6.0
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
V
Iin
Maximum Input Leakage Current on Digital Pins
(Enable/A/B/C)
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
mA
ICC
Maximum Quiescent Supply Current
(per Package)
Vin(digital) = VCC or GND
Vin(analog) = GND
6.0
2
20
40
mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
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3
MC74HC4851A, MC74HC4852A
DC CHARACTERISTICS — Analog Section
Guaranteed Limit
Symbol
Ron
DRon
Ioff
Ion
Parameter
Condition
VCC
−55 to 25°C
≤85°C
≤125°C
Unit
Maximum “ON” Resistance
Vin = VIL or VIH;VIS = VCC to
GND; IS ≤ 2.0 mA
2.0
3.0
4.5
6.0
1700
1100
550
400
1750
1200
650
500
1800
1300
750
600
W
Delta “ON” Resistance
Vin = VIL or VIH; VIS = VCC/2
IS ≤ 2.0 mA
2.0
3.0
4.5
6.0
300
160
80
60
400
200
100
80
500
240
120
100
W
Maximum Off−Channel Leakage Current,
Any One Channel
Common Channel
Vin = VCC or GND
6.0
±0.1
±0.2
±0.5
±2.0
±1.0
±4.0
6.0
±0.2
±2.0
±4.0
VCC
−55 to 25°C
≤85°C
≤125°C
Unit
Maximum Propagation Delay, Analog Input to Analog Output
2.0
3.0
4.5
6.0
160
80
40
30
180
90
45
35
200
100
50
40
ns
Maximum Propagation Delay, Enable or Channel−Select to Analog Output
2.0
3.0
4.5
6.0
260
160
80
60
280
180
90
70
300
200
100
80
ns
10
35
130
10
35
130
10
35
130
pF
Maximum On−Channel Leakage
Vin = VCC or GND
Channel−to−Channel
mA
mA
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol
tPHL,
tPLH
tPHL,
tPHZ,PZH
tPLH,
tPLZ,PZL
Parameter
Cin
Maximum Input Capacitance
(All Switches Off)
(All Switches Off)
CPD
Power Dissipation Capacitance
Digital Pins
Any Single Analog Pin
Common Analog Pin
Typical
5.0
20
pF
INJECTION CURRENT COUPLING SPECIFICATIONS (VCC = 5V, TA = −55°C to +125°C)
Symbol
VDout
Parameter
Condition
Maximum Shift of Output Voltage of Enabled Analog Channel
Iin* ≤ 1 mA, RS ≤ 3,9 kW
Iin* ≤ 10 mA, RS ≤ 3,9 kW
Iin* ≤ 1 mA, RS ≤ 20 kW
Iin* ≤ 10 mA, RS ≤ 20 kW
* Iin = Total current injected into all disabled channels.
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4
Typ
Max
Unit
0.1
1.0
0.5
5.0
1.0
5.0
2.0
20
mV
MC74HC4851A, MC74HC4852A
900
−55°C
800
+25°C
700
+125°C
600
500
400
300
200
R on , ON RESISTANCE (OHMS)
1100
1000
R on , ON RESISTANCE (OHMS)
1100
1000
100
800
700
600
500
+25°C
300
+125°C
200
0.4
0.8
1.2
1.6
0
0.0
2.0
0.6
1.2
1.8
2.4
Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND
Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND
Figure 5. Typical On Resistance VCC = 2V
Figure 6. Typical On Resistance VCC = 3V
660
440
600
400
540
360
480
420
360
−55°C
300
+25°C
240
+125°C
180
−55°C
280
160
120
40
2.7
3.6
+125°C
200
60
1.8
+25°C
240
80
0.9
0
0.0
4.5
1.2
2.4
3.6
4.8
Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND
Vin, INPUT VOLTAGE (VOLTS), REFERENCED TO GND
Figure 7. Typical On Resistance VCC = 4.5V
Figure 8. Typical On Resistance VCC = 6V
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5
3.0
320
120
0
0.0
−55°C
400
100
R on , ON RESISTANCE (OHMS)
R on , ON RESISTANCE (OHMS)
0
0.0
900
6.0
MC74HC4851A, MC74HC4852A
VCC = 5V
Iin
Vin2 < VSS or VCC < Vin2
Any Disabled Channel
VSS < Vin1 < VCC
Enabled Channel
Vout = Vin1 ±VDout
RS
Figure 9. Injection Current Coupling Specification
5V
6V
5V
HC4051A
Sensor
VCC
VCC
Microcontroller
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Channel 8
(8x Identical Circuitry)
Common Out
A/D − Input
Figure 10. Actual Technology
Requires 32 passive components and one extra 6V regulator
to suppress injection current into a standard HC4051 multiplexer
5V
VCC
HC4851A
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Channel 8
Sensor
(8x Identical Circuitry)
VCC
Common Out
Microcontroller
A/D − Input
Figure 11. MC74HC4851A Solution
Solution by applying the HC4851A multiplexer
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6
MC74HC4851A, MC74HC4852A
PLOTTER
VCC
PROGRAMMABLE
POWER
SUPPLY
MINI COMPUTER
DC ANALYZER
16
VEE
VCC
OFF
−
+
VCC
VCC
A
COMMON O/I
OFF
NC
DEVICE
UNDER TEST
ANALOG IN
VIH
COMMON OUT
6
8
GND
Figure 13. Maximum Off Channel Leakage Current,
Any One Channel, Test Set−Up
Figure 12. On Resistance Test
Set−Up
VCC
16
VEE
ANALOG I/O
16
A
OFF
VCC
OFF
VIH
VCC
VCC
VCC
ON
VEE
COMMON O/I
VCC
N/C
ANALOG I/O
VIL
6
COMMON O/I
OFF
6
8
8
Figure 14. Maximum Off Channel Leakage Current,
Common Channel, Test Set−Up
Figure 15. Maximum On Channel Leakage Current,
Channel to Channel, Test Set−Up
VCC
VCC
16
VCC
CHANNEL
SELECT
ON/OFF
50%
OFF/ON
GND
tPLH
ANALOG
OUT
COMMON O/I
ANALOG I/O
TEST
POINT
C L*
tPHL
6
50%
8
CHANNEL SELECT
*Includes all probe and jig capacitance
Figure 16. Propagation Delays, Channel Select
to Analog Out
Figure 17. Propagation Delay, Test Set−Up Channel
Select to Analog Out
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7
MC74HC4851A, MC74HC4852A
VCC
16
VCC
ANALOG
IN
COMMON O/I
ANALOG I/O
ON
50%
TEST
POINT
C L*
GND
tPLH
tPHL
ANALOG
OUT
6
8
50%
*Includes all probe and jig capacitance
Figure 18. Propagation Delays, Analog In
to Analog Out
tf
tr
tPZL
ANALOG
OUT
2
GND
tPLZ
16
HIGH
IMPEDANCE
10%
VCC
VCC
1
TEST
POINT
ON/OFF
C L*
VOL
tPHZ
ENABLE
VOH
90%
10kW
ANALOG I/O
2
50%
tPZH
POSITION 1 WHEN TESTING tPHZ AND tPZH
POSITION 2 WHEN TESTING tPLZ AND tPZL
1
VCC
90%
50%
10%
ENABLE
ANALOG
OUT
Figure 19. Propagation Delay, Test Set−Up
Analog In to Analog Out
50%
8
HIGH
IMPEDANCE
Figure 20. Propagation Delays, Enable to
Analog Out
6
Figure 21. Propagation Delay, Test Set−Up
Enable to Analog Out
VCC
A
VCC
16
ON/OFF
COMMON O/I
NC
ANALOG I/O
OFF/ON
VCC
6
8
11
CHANNEL SELECT
Figure 22. Power Dissipation Capacitance,
Test Set−Up
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8
MC74HC4851A, MC74HC4852A
Gate = VCC
(Disabled)
Disabled Analog Mux Input
Vin > VCC + 0.7V
P+
Common Analog Output
Vout > VCC
P+
+
+
+
N − Substrate (on VCC potential)
Figure 23. Diagram of Bipolar Coupling Mechanism
Appears if Vin exceeds VCC, driving injection current into the substrate
A
B
C
ENABLE
11
10
9
6
Figure 24. Function Diagram, HC4851A
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9
INJECTION
CURRENT
CONTROL
13
INJECTION
CURRENT
CONTROL
14
INJECTION
CURRENT
CONTROL
15
INJECTION
CURRENT
CONTROL
12
INJECTION
CURRENT
CONTROL
1
INJECTION
CURRENT
CONTROL
5
INJECTION
CURRENT
CONTROL
2
INJECTION
CURRENT
CONTROL
4
INJECTION
CURRENT
CONTROL
3
X0
X1
X2
X3
X4
X5
X6
X7
X
MC74HC4851A, MC74HC4852A
A
B
ENABLE
10
9
6
Figure 25. Function Diagram, HC4852A
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10
INJECTION
CURRENT
CONTROL
13
INJECTION
CURRENT
CONTROL
14
INJECTION
CURRENT
CONTROL
15
INJECTION
CURRENT
CONTROL
12
INJECTION
CURRENT
CONTROL
13
INJECTION
CURRENT
CONTROL
1
INJECTION
CURRENT
CONTROL
5
INJECTION
CURRENT
CONTROL
2
INJECTION
CURRENT
CONTROL
4
INJECTION
CURRENT
CONTROL
3
X0
X1
X2
X3
X
Y0
Y1
Y2
Y3
Y
MC74HC4851A, MC74HC4852A
ORDERING INFORMATION
Package
Shipping †
MC74HC4851AN
PDIP−16
500 Units / Box
MC74HC4851ANG
PDIP−16
(Pb−Free)
500 Units / Box
MC74HC4851AD
SOIC−16
48 Units / Rail
MC74HC4851ADG
SOIC−16
(Pb−Free)
48 Units / Rail
MC74HC4851ADR2
SOIC−16
2500 Units / Tape & Reel
MC74HC4851ADR2G
SOIC−16
(Pb−Free)
2500 Units / Tape & Reel
MC74HC4851ADTR2
TSSOP−16*
2500 Units / Tape & Reel
MC74HC4851ADTR2G
TSSOP−16*
2500 Units / Tape & Reel
MC74HC4851ADW
SOIC−16 WIDE
48 Units / Rail
MC74HC4851ADWG
SOIC−16 WIDE
(Pb−Free)
48 Units / Rail
MC74HC4851ADWR2
SOIC−16 WIDE
1000 Units / Tape & Reel
MC74HC4851ADWR2G
SOIC−16 WIDE
(Pb−Free)
1000 Units / Tape & Reel
MC74HC4852AN
PDIP−16
500 Units / Box
MC74HC4852ANG
PDIP−16
(Pb−Free)
500 Units / Box
MC74HC4852AD
SOIC−16
48 Units / Rail
MC74HC4852ADG
SOIC−16
(Pb−Free)
48 Units / Rail
MC74HC4852ADR2
SOIC−16
2500 Units / Tape & Reel
MC74HC4852ADR2G
SOIC−16
(Pb−Free)
2500 Units / Tape & Reel
MC74HC4852ADTR2
TSSOP−16*
2500 Units / Tape & Reel
MC74HC4852ADTR2G
TSSOP−16*
2500 Units / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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11
MC74HC4851A, MC74HC4852A
PACKAGE DIMENSIONS
PDIP−16
N SUFFIX
CASE 648−08
ISSUE T
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
−A−
16
9
1
8
B
F
C
L
DIM
A
B
C
D
F
G
H
J
K
L
M
S
S
−T−
SEATING
PLANE
K
H
D
M
J
G
16 PL
0.25 (0.010)
T A
M
M
INCHES
MIN
MAX
0.740 0.770
0.250 0.270
0.145 0.175
0.015 0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008 0.015
0.110 0.130
0.295 0.305
0_
10 _
0.020 0.040
MILLIMETERS
MIN
MAX
18.80 19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
SOIC−16
D SUFFIX
CASE 751B−05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
−A−
16
9
−B−
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
16 PL
0.25 (0.010)
M
T B
S
A
S
http://onsemi.com
12
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
MC74HC4851A, MC74HC4852A
SOIC−16 WIDE
DW SUFFIX
CASE 751G−03
ISSUE C
A
D
9
h X 45 _
E
0.25
H
8X
M
B
M
16
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN
EXCESS OF THE B DIMENSION AT MAXIMUM
MATERIAL CONDITION.
q
1
MILLIMETERS
DIM MIN
MAX
A
2.35
2.65
A1 0.10
0.25
B
0.35
0.49
C
0.23
0.32
D 10.15 10.45
E
7.40
7.60
e
1.27 BSC
H 10.05 10.55
h
0.25
0.75
L
0.50
0.90
q
0_
7_
8
B
B
16X
M
T A
14X
e
S
B
S
L
A
0.25
A1
SEATING
PLANE
C
T
TSSOP−16
DT SUFFIX
CASE 948F−01
ISSUE A
16X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
K
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
ÇÇÇ
K1
2X
L/2
16
9
J1
B
−U−
L
SECTION N−N
J
PIN 1
IDENT.
8
1
N
0.25 (0.010)
0.15 (0.006) T U
S
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
N
F
DETAIL E
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
H
D
DETAIL E
G
http://onsemi.com
13
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193 0.200
0.169 0.177
−−− 0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.007
0.011
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0_
8_
MC74HC4851A, MC74HC4852A
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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14
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