PRELIMINARY Advanced Micro Devices Am53CF94/Am53CF96 Enhanced SCSI-2 Controller (ESC) DISTINCTIVE CHARACTERISTICS ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Pin/function compatible with Emulex FAS216/236 AMD’s Patented programmable GLITCH EATERTM Circuitry on REQ and ACK inputs 10 Mbytes/s synchronous Fast SCSI transfer rate 20 Mbytes/s DMA transfer rate 16-Bit DMA interface plus 2 bits of parity Flexible three bus architecture Single-ended SCSI bus supported by Am53CF94 Differential SCSI bus supported by Am53CF96 Selection of multiplexed or non-multiplexed address and data bus High current drivers (48 mA) for direct connection to the single-ended SCSI bus Supports Disconnect and Reselect commands Supports burst mode DMA operation with a threshold of eight Supports 3-byte tagged-queueing as per the SCSI-2 specification Supports group 2 and 5 command recognition as per the SCSI-2 specification Advanced CMOS process for lower power consumption ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ AMD’s exclusive programmable power-down feature 24-Bit extended transfer counter allows for data block transfer of up to 16 Mbytes Independently programmable 3-byte message and group 2 identification Additional check for ID message during bus-initiated Select with ATN Reselection has QTAG features of ATN3 Access FIFO Command Delayed enable signal for differential drivers avoid contention on SCSI differential lines Programmable Active Negation on REQ, ACK and Data lines Register programmable control of assertion/ deassertion delay for REQ and ACK lines Part-unique ID code Am53CF94 available in 84-pin PLCC package Am53CF96 available in 100-pin PQFP package Am53CF94 available in 3.3 V version Supports clock operating frequencies from 10 MHz–40 MHz Supports Scatter-Gather or Back-to-Back synchronous data transfers GENERAL DESCRIPTION The Enhanced SCSI-2 Controller (ESC) was designed to support Fast SCSI-2 transfer rates of up to 10 Mbytes/s in synchronous mode and up to 7 Mbytes/s in the asynchronous mode. The ESC is downward compatible with the Am53C94/96, combining its functionality with features such as Fast SCSI, programmable Active Negation, a 24-bit transfer counter, and a part-unique ID code containing manufacturer and serial # information. AMD’s proprietary features such as power-down mode for SCSI transceivers, programmable GLITCH EATER, and extended Target command set are also included for improved product performance. The Enhanced SCSI-2 Controller (ESC) has a flexible three bus architecture. The ESC has a 16-bit DMA interface, an 8-bit host data interface and an 8-bit SCSI data interface. The ESC is designed to minimize host intervention by implementing common SCSI sequences in hardware. An on-chip state machine reduces protocol overheads by performing the required sequences in response to a single command from the host. Selection, reselection, information transfer and disconnection commands are directly supported. The 16-byte-internal FIFO further assists in minimizing host involvement. The FIFO provides a temporary storage for all command, data, status and message bytes as they are transferred between the 16-bit host data bus and the 8-bit SCSI data bus. During DMA operations the FIFO acts as a buffer to allow greater latency in the DMA channel. This permits the DMA channel to be suspended for higher priority operations such as DRAM refresh or reception of an ISDN packet. Parity on the DMA bus is optional. Parity can either be generated and checked or it can be simply passed through. The Target command set for the Am53CF94/96 includes an additional command, the Access FIFO command, to allow the host or DMA controller to remove remaining FIFO data following the host’s issuance of a Target abort DMA command or following an abort due to This document contains information on a product under development at Advanced Micro Devices Inc. The information is intended to help you to evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Publication# 17348 Rev. B Issue Date: May 1993 Amendment /0 AMD PRELIMINARY parity error. This command facilitates data recovery and thereby minimizes the need to re-transmit data. AMD’s exclusive power-down feature can be enabled to help reduce power consumption during the chip’s sleep mode. The receivers on the SCSI bus may be turned off to eliminate current that may flow because termination power (~3 V) is close to the trip point of the input buffers. The patented GLITCH EATER Circuitry in the Enhanced SCSI-2 Controller can be programmed to filter glitches with widths up to 35 ns. It is designed to dramatically increase system reliability by detecting and removing glitches that may cause system failure. The GLITCH EATER Circuitry is implemented on the ACK and REQ lines since they are most susceptible to electrical anomalies such as reflections and voltage spikes. Such signal inconsistencies can trigger false REQ/ACK handshaking, false data transfers, addition of random data, and double clocking. AMD’s GLITCH EATER Circuitry therefore maintains system performance and improves reliability. The following diagram illustrates this circuit’s operation. The Am53CF94 is also available in a 3.3 V version. GLITCH EATER Circuitry in SCSI Environment SCSI Environment Device without the GLITCH EATER Circuit Glitch Window AMD’s Device with the GLITCH EATER Circuit Note: The Glitch Window is programmable via Control Register Four (0DH), bits 6 & 7. Window may be set to 35 ns (max). Default setting is 12 ns (single-ended). 17348B-1 SYSTEM BLOCK DIAGRAM Addr 4 CPU 9 16 8 Data SCSI Data Am53CF94/96 9 SCSI Control 16 DMA 16 Memory 16 DMA 17348B-2 2 Am53CF94/Am53CF96 PRELIMINARY AMD SYSTEM BUS MODE DIAGRAMS BUSMD 1 DMAWR BUSMD 0 WR RD Address Bus Am53CF94/96 A 3–0 Host Processor 8-Bit Data Bus DMA 7–0 DACK Bus Controller DREQ DMA Controller 17348B-3 Bus Mode 0 Single Bus Architecture: 8-Bit DMA, 8-Bit Processor VDD BUSMD 1 DMAWR BUSMD 0 WR Am53CF94/96 RD Address Bus A 3–0 Data Bus Host Processor DMA 15–0 DACK DREQ Bus Controller 8 16 DMA Controller Bus Mode 1 17348B-4 Single Bus Architecture: 16-Bit DMA, 8-Bit Processor Am53CF94/Am53CF96 3 AMD PRELIMINARY SYSTEM BUS MODE DIAGRAMS VDD BUSMD 1 BUSMD 0 WR RD Host Processor ALE 8-Bit Data Bus AD 7–0 Am53CF94/96 16-Bit Data Bus DMA 15–0 AS0 BHE DMA Controller DMARD DMAWR DREQ DACK Bus Mode 2 17348B-5 Dual Bus Architecture: 16-Bit DMA with Byte Control, 8-Bit Multiplexed Processor Address Data VDD BUSMD 1 WR BUSMD 0 RD Address Bus A 3–0 Host Processor 8-Bit Data Bus AD 7–0 Am53CF94/96 16-Bit Data Bus DMA 15–0 DMA Controller DMAWR DREQ DACK Bus Mode 3 Dual Bus Architecture: 16-Bit DMA, 8-Bit Processor 4 Am53CF94/Am53CF96 17348B-6 PRELIMINARY AMD 18 16 x 9 FIFO (including parity) DMAP1-0 CS BUSMD1-0 6 8 MUX AD 7-0 Host Control Parity Logic 4 Bus Interface Unit DMA Control 8 Register Bank DFMODE CLK RESET 9 9 SCSI Bus Data + Parity (Single Ended) SCSI Bus Data + Parity Direction Control Main Sequencer 8 SCSI Sequencer SCSI Control 18 DMA 15-0 Data Tranceivers BLOCK DIAGRAM 9 7 SCSI Control SCSI Control Direction Control 17348B-7 Am53CF94/Am53CF96 5 AMD PRELIMINARY VSS VSS DMA1 DMA0 DMA3 1 84 83 82 81 80 79 78 77 76 75 13 74 73 DMAWR DACK SD2 14 72 DREQ SD3 SD4 15 16 71 70 AD7 SD5 17 69 SD6 SD7 18 68 19 67 AD4 VSS SDP VDD VSS 20 66 AD3 65 64 AD2 AD1 SDC0 SDC1 23 24 63 62 VDD Am53CF94 84-Pin PLCC 21 22 AD6 AD5 AD0 SDC2 25 61 CLK SDC3 26 60 ALE [A3] VSS 27 59 DMARD [A2] SDC4 28 58 BHE [A1] SDC5 29 57 SDC6 SDC7 30 56 AS0 [A0] CS RESET SDC P VSS NC SELC VSS 17348B-8 BSYC REQC ACKC BUSMD 1 BUSMD 0 INT VSS VSS RST MSG ACK REQ C/D I/O ATN RSTC RSTC VSS SEL BSY VSS I/O ATN SEL VSS BSY MSG C/D REQ ACKC VSS ACK RST BSYC REQC BUSMD 1 BUSMD 0 VSS INT RESET SELC 55 32 54 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 NC WR RD RD WR 31 SDCP SDC 7 3 2 4 DMA2 5 DMA4 6 DMA6 DMA5 DMA8 7 DMA7 DMA10 DMA9 VSS DMAP0 DMA11 11 10 9 8 12 SD0 SD1 DMA12 DMA14 DMA13 DMAP1 DMA15 CONNECTION DIAGRAMS Top View 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 CS AS0 [A0] 81 82 50 SDC 6 49 SDC 5 BHE [A1] 83 48 SDC 4 DMARD [A2] 84 47 VSS ALE [A3] 85 46 VSS CLK 86 45 SDC 3 DFMODE VDD 87 44 SDC 2 88 43 SDC 1 NC 89 42 SDC 0 AD0 90 41 VSS AD1 91 40 VSS AD2 92 39 NC AD3 93 38 VDD VSS 94 37 SD P VSS 95 36 SD 7 AD4 96 35 SD 6 AD5 97 34 SD 5 AD6 98 33 SD 4 AD7 99 32 SD 3 DREQ 100 31 SD 2 SD 1 SD 0 NC DMAP1 DMA15 DMA1 DMA14 DMA0 DMA13 VSS DMA12 TSEL DMA11 VSS DMA10 ISEL DMA9 NC DMA8 DACK VSS 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 VSS 8 DMA7 7 DMAP0 6 DMA6 5 DMA5 4 DMA4 3 DMA3 2 DMA2 1 DMAWR Am53CF96 100-Pin PQFP 17348B-9 6 Am53CF94/Am53CF96 PRELIMINARY AMD LOGIC SYMBOL SD 7–0 SD P SDC 7–0 DMA 15–0 DMAP 1–0 SDC P ALE [A3] MSG DMARD [A2] BHE [A1] C/D AS0 [A0] I/O DREQ ATN DACK BSY AD 7–0 Am53CF94/96 DMAWR SEL RST REQ RD ACK WR CS BSYC INT BUSMD 1–0 RSTC SELC REQC *DFMODE CLK RESET ACKC *ISEL *TSEL Note: 17348B-10 *Pins available on the Am53CF96 only. RELATED AMD PRODUCTS Part Number 85C30 26LSXX 33C93A 80C186 80C286 80286 Description Part Number Enhanced Serial Communication Controller Line Drivers/Receivers Enhanced CMOS SCSI Bus Interface Controller Highly Integrated 16-Bit Microprocessor High-Performance 16-Bit Microprocessor TM Am386 53C80A 80188 85C80 53C94LV Am53CF94/Am53CF96 Description High-Performance 32-Bit Microprocessor SCSI Bus Controller Highly Integrated 8-Bit Microprocessor Combination 53C80A SCSI and 85C30 ESCC Low Voltage, High Performance SCSI Controller 7 AMD PRELIMINARY ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM53CF96 K C /W ALTERNATE PACKAGING OPTION /W = Trimmed and Formed in a Tray Blank = Molded Carrier Ring (36 mm) TEMPERATURE RANGE C = Commercial PACKAGE TYPE J = 84-Pin PLCC (PL 084) K = 100-Pin Metric PQFP (PQR100) DEVICE NUMBER/DESCRIPTION Am53CF94/Am53CF96 Enhanced SCSI-2 Controller Valid Combinations AM53CF94 AM53CF96 8 JC KC, KC/W Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations or to check on newly released combinations. Am53CF94/Am53CF96 PRELIMINARY AMD SCSI OUTPUT CONNECTIONS Am53CF94 SD 7–0, P SDC 7–0, P SEL, BSY, REQ, ACK, RST SELC, BSYC, REQC, ACKC, RSTC MSG, C/D, I/O, ATN 17348B-11 Am53CF94 Single Ended SCSI Bus Configuration Am53CF94/Am53CF96 9 AMD PRELIMINARY SCSI OUTPUT CONNECTIONS Am53CF96 SD 7–0, P SDC 7–0, P SEL, BSY, REQ, ACK, RST SELC, BSYC, REQC, ACKC, RSTC MSG, C/D, I/O, ATN DFMODE VCC 17348B-12 Am53CF96 Single Ended SCSI Bus Configuration Am53CF96 SD 7–0, P DT SDC 7–0, P SEL, BSY, RST DT SELC, BSYC, RSTC ATN, ACK DT ISEL MSG, C/D, I/O, REQ DT TSEL DFMODE 17348B-13 Am53CF96 Differential SCSI Bus Configuration 10 Am53CF94/Am53CF96 PRELIMINARY AMD TSEL MSG – MSG + MSG TSEL C/D – C/D + C/D SDC 0 SD 0 TSEL – SD 0 + SD 0 I/O – I/O + I/O SDC 1 SD 1 75ALS170 – SD 1 + SD 1 ISEL SDC 2 ATN – ATN + ATN SD 2 – SD 2 + SD 2 75ALS170 SDC 3 SD 3 – SD 3 + SD 3 SDC 4 SD 4 75ALS170 – SD 4 + SD 4 Vcc SELC GND SDC 5 SD 5 – SEL + SEL SEL – SD 5 + SD 5 BSYC 75ALS170 GND – BSY + BSY BSY RSTC GND SDC 6 SD 6 – RST + RST RST GND – SD 6 + SD 6 SDC 7 SD 7 75ALS171 – SD 7 + SD 7 Vcc TSEL REQC SDC P – REQ + REQ REQ SD P – SD P + SD P ISEL ACKC 75ALS170 – ACK + ACK ACK GND 75ALS171 17348B-14 Differential Transceiver Connections for the Differential SCSI Bus Configuration Using 75ALS170 and 75ALS171 Transceivers Am53CF94/Am53CF96 11 AMD PRELIMINARY TSEL SDC 0 MSG SD 0 MSG – MSG + MSG SD 0 TSEL SDC 0 TSEL SDC 1 C/D C/D SD 1 – C/D + C/D SD 1 TSEL SDC 1 TSEL SDC 2 – I/O + I/O SD 2 TSEL SDC 2 ISEL SDC 3 ATN SD 3 ATN – ATN + ATN SD 3 ISEL SDC 3 SELC SDC 4 GND SEL SD 4 SD 5 – BSY + BSY SD 5 GND SDC 5 RSTC SDC 6 – SD 5 + SD 5 SD 6 GND – RST + RST SD 6 GND SDC 6 TSEL SDC 7 REQC – SD 6 + SD 6 SD 7 – REQ + REQ SD 7 GND SDC 7 ISEL SDC P ACKC SD P ACK – SD 4 + SD 4 SDC 5 GND REQ – SD 3 + SD 3 SDC 4 BSYC RST – SD 2 + SD 2 SD 4 – SEL + SEL GND BSY – SD 1 + SD 1 SD 2 I/O I/O – SD 0 + SD 0 – ACK + ACK SD P – SD 7 + SD 7 – SD P + SD P SDC P GND 17348B-15 Differential Transceiver Connections for the Differential SCSI Bus Configuration Using 75176A Transceiver 12 Am53CF94/Am53CF96 PRELIMINARY PIN DESCRIPTION Host Interface Signals AMD AS0 [A0] DMA 15–0 Data/DMA Bus (Input/Output, Active High, Internal Pull-up) The configuration of this bus depends on the Bus Mode 1–0 (BUSMD 1–0) inputs. When the device is configured for single bus operation, the host can access the internal register set on the lower eight lines while DMA accesses can be made to the FIFO using the entire bus. When using the Byte Mode via the BHE and A0 inputs the data can be transferred on either the upper or lower half of the DMA 15–0 bus. DMAP 1–0 Address Status [Address 0] (Input, Active High) This is a dual function input. When the device is configured for the dual bus mode (two buses, multiplexed and byte control), this input acts as AS0. As AS0, this input works in conjunction with BHE to indicate the lines on which data transfer will take place. When the device is configured for all other bus modes, this input acts as A0. As A0, this input is the zeroth bit of the address bus. The following is the decoding for the BHE and AS0 inputs: BHE AS0 Data/DMA Parity Bus (Input/Output, Active High, Internal Pull-up) 1 1 Upper Bus – DMA 15–8, DMAP 1 These lines are odd parity for the DMA 15–0 bus. DMAP 1 is the parity for the upper half of the bus (DMA 15–8) and DMAP 0 is the parity for the lower half of the bus (DMA 7–0). 1 0 Full Bus – DMA 15–0, DMAP 1–0 0 1 Reserved 0 0 Lower Bus – DMA 7–0, DMAP 0 ALE [A3] Bus Used DREQ Address Latch Enable [Address 3] (Input, Active High) This is a dual function input. When the device is configured for the dual bus mode (two buses, multiplexed and byte control), this input acts as ALE. As ALE, this input latches the address on the AD 7–0 bus on its low going edge. When the device is configured for all other bus modes, this input acts as A3. As A3, this input is the third bit of the address bus. DMARD [A2] DMA Request (Output, Active High, Hi-Z) This output signal to the DMA controller will be active during DMA read and write cycles. During a DMA read cycle it will be active as long as there is a word (or a byte in the byte mode) in the FIFO to be transferred to memory. During a DMA write cycle it will be active as long as there is an empty space for a word (or a byte in mode 2) in the FIFO. DACK DMA Read [Address 2] (Input, Active Low [Active High]) This is a dual function input. When the device is configured for the dual bus mode (two buses, multiplexed and byte control), this input acts as DMARD. As DMARD, this input is the read signal for the DMA 15–0 bus. When the device is configured for all other bus modes, this input acts as A2. As A2, this input is the second bit of the address bus. DMA Acknowledge (Input, Active Low) This input signal from the DMA controller will be active during DMA read and write cycles. The DACK signal is used to access the DMA FIFO only and should never be active simultaneously with the CS signal, which accesses the registers only. AD 7–0 BHE [A1] Host Address Data Bus (Input/Output, Active High, Internal Pull-up) Bus High Enable [Address 1] (Input, Active High) This bus is used only in the dual bus mode. This bus allows the host processor to access the device’s internal registers while the DMA bus is transferring data. When using multiplexed bus, these lines can be used for address and data. When using non multiplexed bus these lines can be used for the data only. This is a dual function input. When the device is configured for the dual bus mode (two buses, multiplexed and byte control), this input acts as BHE. As BHE, this input works in conjunction with AS0 to indicate the lines on which data transfer will take place. When the device is configured for all other bus modes this input acts as A1. As A1, this input is the first bit of the address bus. Am53CF94/Am53CF96 13 AMD PRELIMINARY DMAWR BUSMD 1–0 DMA Write (Input, Active Low) Bus Mode (Input, Active High) This signal writes the data onto the DMA 15–0 and DMAP 1–0 bus into the internal FIFO when DACK is also active. When in the single bus mode this signal must be tied to the WR signal. These inputs configure the device for single bus or dual bus operation and the DMA bus width. BUSMD1 RD BUSMD0 Bus Configuration 1 1 Two buses: 8-bit Host Bus and 16-bit DMA Bus Register Address on A 3–0 and Data on AD Bus 1 0 Two buses: Multiplexed and byte control Register Address on AD 3–0 and Data on AD Bus 0 1 Single bus: 8-bit Host Bus and 16-bit DMA Bus Register Address on A 3–0 and Data on DMA Bus 0 0 Single bus: 8-bit Host Bus and 8-bit DMA Bus Register Address on A 3–0 and Data on DMA Bus Read (Input Active Low) This signal reads the internal device registers and places their contents on the data bus, when either CS signal or DACK signal is active. WR Write (Input Active Low) This signal writes the internal device registers with the value present on the (AD 7–0 bus or the DMA 15–0 and DMAP 1–0 bus), when the CS signal is also active. CS Chip Select (Input Active Low) This signal enables the read and write of the device registers. CS enables access to any register (including the FIFO) while the DACK enables access only to the FIFO. CS and DACK should never be active simultaneously in the single bus mode, they may however be active simultaneously in the dual bus mode provided the CS signal is not enabling access to the FIFO. INT CLK Clock (Input) Clock input used to generate all the internal device timings. The maximum frequency of this input is 40 MHz. and a minimum of 10 MHz to maintain the SCSI bus timings. RESET Interrupt (Output, Active Low, Open Drain) This signal is a non-maskable interrupt flag to the host processor. This signal is latched on the output on the high going edge of the clock. This flag may be cleared by reading the Interrupt Status Register (ISTAT) or by performing a device reset (hard or soft). This flag is not cleared by a SCSI reset. Reset (Input, Active High) This input when active resets the device. The RESET input must be active for at least two CLK periods after the voltage on the power inputs have reached Vcc minimum. DFMODE SCSI Interface Signals Differential Mode (Input, Active Low) SD 7–0 This input is available only on the Am53CF96. This input configures the SCSI bus to either single ended or differential mode. When this input is active, the device operates in the differential SCSI mode. The SCSI data is available on the SD 7–0 lines and the high active transceiver enables on the SDC 7–0 outputs. When this input is inactive, the device operates in the single ended SCSI mode. The SCSI input data is available on SD 7–0 lines and the output data is available on SDC 7–0 lines. In the single ended SCSI mode, the SD 7–0 and the SDC 7–0 buses can be tied together externally. 14 SCSI Data (Input/Output, Active Low, Schmitt Trigger) When the device is configured in the Single Ended SCSI Mode (DFMODE inactive) these pins are defined as inputs for the SCSI data bus. When the device is configured in the Differential SCSI Mode (DFMODE active) these pins are defined as bidirectional SCSI data bus. Am53CF94/Am53CF96 PRELIMINARY SD P SCSI Data Parity (Input/Output, Active Low, Schmitt Trigger) When the device is configured in the Single Ended SCSI Mode (DFMODE inactive) this pin is defined as the input for the SCSI data parity. When the device is configured in the Differential SCSI Mode (DFMODE active) this pin is defined as bidirectional SCSI data parity. SDC 7–0 AMD be asserted when the Initiator detects a parity error or it can be asserted via certain Initiator commands. BSY Busy (Input, Active Low, Schmitt Trigger) This is a SCSI input signal with a Schmitt trigger. SEL Select (Input, Active Low, Schmitt Trigger) SCSI Data Control (Output, Active Low, Open Drain) This is a SCSI input signal with a Schmitt trigger. When the device is configured in the Single Ended SCSI Mode (DFMODE inactive) these pins are defined as outputs for the SCSI data bus. When the device is configured in the Differential SCSI Mode (DFMODE active) these pins are defined as direction controls for the external differential transceivers. In this mode, a signal high state corresponds to an output to the SCSI bus and a low state corresponds to an input from the SCSI bus. SDC P RST Reset (Input, Active Low, Schmitt Trigger) This is a SCSI input signal with a Schmitt trigger. REQ Request (Input, Active Low, Schmitt Trigger) This is a SCSI input signal with a Schmitt trigger. SCSI Data Control Parity (Output, Active Low, Open Drain) When the device is configured in the Single Ended SCSI Mode (DFMODE inactive) this pin is defined as an output for the SCSI data parity. When the device is configured in the Differential SCSI Mode (DFMODE active) this pin is defined as the direction control for the external differential transceiver. In this mode, a signal high state corresponds to an output to the SCSI bus and a low state corresponds to an input from the SCSI bus. ACK Acknowledge (Input, Active Low, Schmitt Trigger) This is a SCSI input signal with a Schmitt trigger. BSYC Busy Control (Output, Active Low, Open Drain) C/D This is a SCSI output with 48 mA drive. When the device is configured in the Single Ended SCSI Mode (DFMODE inactive) this pin is defined as a BSY output for the SCSI bus. When the device is configured in the Differential SCSI Mode (DFMODE active) this pin is defined as the direction control for the external differential transceiver. In this mode, a signal high state corresponds to an output to the SCSI bus and a low state corresponds to an input from the SCSI bus. Command/Data (Input/Output, Schmitt Trigger) SELC MSG Message (Input/Output, Active Low, Schmitt Trigger) This is a bidirectional signal with 48 mA output driver. It is an output in the Target mode and a Schmitt trigger input in the Initiator mode. This is a bidirectional signal with 48 mA output driver. It is an output in the Target mode and a Schmitt trigger input in the Initiator mode. I/O Input/Output (Input/Output, Schmitt Trigger) This is a bidirectional signal with 48 mA output driver. It is an output in the Target mode and a Schmitt trigger input in the Initiator mode. Select Control (Output, Active Low, Open Drain) This is a SCSI output with 48 mA drive. When the device is configured in the Single Ended SCSI Mode (DFMODE inactive) this pin is defined as a SEL output for the SCSI bus. When the device is configured in the Differential SCSI Mode (DFMODE active) this pin is defined as the direction control for the external differential transceiver. In this mode, a signal high state corresponds to an output to the SCSI bus and a low state corresponds to an input from the SCSI bus. ATN Attention (Input/Output, Active Low, Schmitt Trigger) This signal is a 48 mA output in the Initiator mode and a Schmitt trigger input in the Target mode. This signal will Am53CF94/Am53CF96 15 AMD PRELIMINARY RSTC ACKC Reset Control (Output, Active Low, Open Drain) Acknowledge Control (Output, Active Low, Open Drain) This is a SCSI output with 48 mA drive. The Reset SCSI command will cause the device to drive RSTC active for 25 ms–40 ms, which will depend on the CLK frequency and the conversion factor. When the device is configured in the Single Ended SCSI Mode (DFMODE inactive) this pin is defined as a RST output for the SCSI bus. When the device is configured in the Differential SCSI Mode (DFMODE active) this pin is defined as the direction control for the external differential transceiver. In this mode, a signal high state corresponds to an output to the SCSI bus and a low state corresponds to an input from the SCSI bus. This is a SCSI output with 48 mA drive. This signal is activated only in the Initiator mode. REQC TSEL ISEL Initiator Select (Output, Active High) This signal is available on the Am53CF96 only. This signal is active whenever the device is in the Initiator mode. In the differential mode this signal is used to enable the Initiator signals ACKC and ATN and the device also drives these signals. Target Select (Output, Active High) Request Control (Output, Active Low, Open Drain) This is a SCSI output with 48 mA drive. This signal is activated only in the Target mode. This signal is available on the Am53CF96 only. This signal is active whenever the device is in the Target mode. In the differential mode this signal is used to enable the Target signals REQC, MSG, C/D and I/O and the device also drives these signals. FUNCTIONAL DESCRIPTION Register Map Address (Hex.) Operation 00 Read 00 Write 01 Read 01 Write 02 03 04 04 05 05 06 06 Read/Write Read/Write Read Write Read Write Read Write Address (Hex.) Operation Register Current Transfer Count Register Low Start Transfer Count Register Low Current Transfer Count Register Middle Start Transfer Count Register Middle FIFO Register Command Register Status Register SCSI Destination ID Register Interrupt Status Register SCSI Timeout Register Internal State Register Synchronous Transfer Period Register 07 Read 07 08 09 0A 0B 0C 0D 0E Write Read/Write Write Write Read/Write Read/Write Read/Write Read 0E Write 0F Write Register Current FIFO/Internal State Register Synchronous Offset Register Control Register 1 Clock Factor Register Forced Test Mode Register Control Register 2 Control Register 3 Control Register 4 Current Transfer Count Register High Start Transfer Count Register High Data Alignment Register Note: Not all registers in this device are both readable and writable. Some read only registers share the same address with write only registers. The registers can be accessed by asserting the CS signal and then asserting either RD or WR signal depending on the operation to be performed. Only the FIFO Register can be accessed by asserting either CS or DACK in conjunction with RD and WR signals or DMARD and DMAWR signals. The register address inputs are ignored when DACK is used but must be valid when CS is used. 16 Am53CF94/Am53CF96 PRELIMINARY Current Transfer Count Register (00H, 01H, 0EH) Read Only Current Transfer Count Register CTCREG 23 CRVL23 x 22 21 CRVL22 CRVL21 x x 20 Address: 00H, 01H, 0EH Type: Read 19 18 CRVL20 CRVL19 CRVL18 x x x 17 16 CRVL17 CRVL16 x x AMD In the Initiator mode, the counter is decremented by the active edge of DACK during the Synchronous Data-In phase or by ACKC during the Asynchronous Data-In phase and by DACK during the Data-Out phase. Start Transfer Count Register (00H, 01H, 0EH) Write Only Start Transfer Count Register STCREG 23 15 14 CRVL15 CRVL14 x x 7 CRVL7 x 6 CRVL6 x 13 12 11 10 CRVL13 CRVL12 CRVL11 CRVL10 x x x x 9 8 CRVL9 CRVL8 x x 5 4 3 2 1 0 CRVL5 CRVL4 CRVL3 CRVL2 CRVL1 CRVL0 x x x x x x 17348B-16 CTCREG – Bits 23:0 – CRVL 23:0 – Current Value 23:0 This is a three-byte register which decrements to keep track of the number of bytes transferred during a DMA transfer. Reading these registers returns the current value of the counter. The counter will decrement by one for every byte and by two for every word transferred. The transaction is complete when the count reaches zero, and bit 4 of the Status Register (04H) is set. Should the sequence terminate early, the sum of the values in the Current FIFO (07H) and the Current Transfer Count Register reflect the number of bytes remaining. The least significant byte is located at address 00H, the middle byte is located at address 01H, and the most significant byte is located at address 0EH. Register 0EH extends the total width of the register from 16 to 24 bits, and is only enabled when the Enable Features bit (bit 6) of Control Register Two is set to a value of ‘1’. These registers are automatically loaded with the values in the Start Transfer Count Register every time a DMA command is issued. However, following a chip or power on reset, up until the time register 0EH is loaded, the Am53CF94/96’s part-unique ID can be obtained by reading register 0EH. In the Target mode, this counter is decremented by the active edge of DACK during the Data-In phase and by REQC during the Data-Out phase. 22 21 20 Address: 00H–01H Type: Write 19 STVL21 STVL20 STVL19 18 16 STVL23 STVL22 x x x x x x 15 14 13 12 11 10 9 8 STVL15 STVL14 STVL13 STVL12 STVL11 STVL10 STVL9 STVL8 x x x x x x x x 7 6 5 4 3 2 1 0 STVL7 STVL6 STVL5 STVL3 STVL2 STVL1 STVL0 x x x x x x x STVL4 x STVL18 17 STVL17 STVL16 x x 17348B-17 STCREG – Bits 15:0 – STVL 15:0 – Start Value 15:0 This is a three-byte register which contains the number of bytes to be transferred during a DMA operation. The value in the Start Transfer Count Register must be programmed prior to command execution. The least significant byte is located at address 00H, the middle byte is located at address 01H, and the most significant byte is located at address 0EH. Register 0EH extends the total width of the register from 16 to 24 bits, and is only enabled when the Enable Features bit (bit 6) of Control Register Two is set to a value of ‘1’. This sets the maximum transfer count to 16.78 MBytes. When a value of ‘0’ is written to these registers, the transfer count will be set to the maximum. A DMA NOP command must be issued before the transfer counter values can be written to 00H, 01H, and 0EH. These registers retain their value until overwritten, and are therefore unaffected by a hardware or software reset. This reduces programming redundancy since it is no longer necessary to reprogram the count for subsequent DMA transfers of the same size. Am53CF94/Am53CF96 17 AMD PRELIMINARY FIFO Register (02H) Read/Write FIFO Register FFREG Address: 02H Type: Read/Write 7 6 5 4 3 2 1 0 FF7 FF6 FF5 FF4 FF3 FF2 FF1 FF0 0 0 0 0 0 0 0 0 17348B-18 FFREG – Bits 7:0 – FF 7:0 – FIFO 7:0 The FIFO on the Am53CF94/96 is 16 bytes deep and is used to transfer SCSI data to and from the ESC. The bottom of the FIFO may be accessed via a read or write to this register. This is the only register that can also be accessed by DACK along with DMARD or DMAWR or with REQ or ACK. This register is reset to zero by hardware or software reset, or at the start of a selection or reselection sequence, or if Clear FIFO command is issued. Command Register (03H) Read/Write Command Register CMDREG Address: 03H Type: Read/Write 7 6 5 4 3 2 1 0 DMA CMD6 CMD5 CMD4 CMD3 CMD2 CMD1 CMD0 x x x x x x x x Commands to the ESC are issued by writing to this register which is two bytes deep. Commands may be queued, and will be read from the bottom of the queue. At the completion of the bottom command, the top command, if present, will drop to the bottom of the register to begin execution. All commands are executed within six clock cycles of dropping to the bottom of the Command Register, with the exception of the Reset SCSI Bus, Reset Device, and DMA Stop commands. These commands are not queued and are executed within four clock cycles of being loaded into the top this register. Interrupts are sometimes generated upon command completion. Should both commands generate interrupts, and the first interrupt has not been serviced, the interrupt from the second (top) command will be stacked behind the first. The Status Register, Interrupt Register, and Internal State Register will be updated to apply to the second interrupt after the microprocessor services the first interrupt. Reading this register will return the command currently being executed (or the last command executed if there are no pending commands). When this register is cleared, existing commands will be terminated and any queued commands will be ignored. However, it does not reset the register bits to ‘00H’. CMDREG – Bit 7 – DMA – Direct Memory Access When set, this bit notifies the device that the command is a DMA instruction, when reset it is a non-DMA instruction. For DMA instructions the Current Transfer Count Register (CTCREG) will be loaded with the contents of the Start Transfer Count Register (STCREG). The data is then transferred and the CTCREG is decremented for each byte until it reaches zero. Command 6:0 CMDREG – Bits 6:0 – CMD 6:0 – Command 6:0 Direct Memory Access 17348B-19 18 These command bits decode the commands that the device needs to perform. There are a total of 31 commands grouped into four categories. The groups are Initiator Commands, Target Commands, Selection/ Reselection Commands and General Purpose Commands. Am53CF94/Am53CF96 PRELIMINARY AMD Initiator Commands CMD6 0 0 0 0 0 0 CMD5 0 0 0 0 0 0 CMD4 1 1 1 1 1 1 CMD3 0 0 0 1 1 1 CMD2 0 0 0 0 0 0 CMD1 0 0 1 0 1 1 CMD0 0 1 0 0 0 1 Command Information Transfer Initiator Command Complete Steps Message Accepted Transfer Pad Bytes *Set ATN *Reset ATN CMD4 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD3 0 0 0 0 0 0 0 1 1 1 1 0 0 CMD2 0 0 0 0 1 1 1 0 0 0 0 1 1 CMD1 0 0 1 1 0 0 1 0 0 1 1 0 0 CMD0 0 1 0 1 0 1 1 0 1 0 1 0 1 Command Send Message Send Status Send Data Disconnect Steps Terminate Steps Target Command Complete Steps *Disconnect Receive Message Steps Receive Command Receive Data Receive Command Steps *DMA Stop Access FIFO Command CMD4 0 0 0 0 0 0 0 0 CMD3 0 0 0 0 0 0 0 0 CMD2 0 0 0 0 1 1 1 1 CMD1 0 0 1 1 0 0 1 1 CMD0 0 1 0 1 0 1 0 1 Command Reselect Steps Select without ATN Steps Select with ATN Steps Select with ATN and Stop Steps *Enable Selection/Reselection Disable Selection/Reselection Select with ATN3 Steps Reselect with ATN3 Steps CMD4 0 0 0 0 CMD3 0 0 0 0 CMD2 0 0 0 0 CMD1 0 0 1 1 CMD0 0 1 0 1 Command *No Operation *Clear FIFO *Reset Device Reset SCSI Bus Target Commands CMD6 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD5 1 1 1 1 1 1 1 1 1 1 1 0 0 Idle Commands CMD6 1 1 1 1 1 1 1 1 CMD5 0 0 0 0 0 0 0 0 General Commands CMD6 0 0 0 0 CMD5 0 0 0 0 Note: *Denotes commands which do not generate interrupts upon completion. Am53CF94/Am53CF96 19 AMD PRELIMINARY Status Register (04H) Read Status Register STATREG Address: 04H Type: Read 7 6 5 4 3 2 1 0 INT IOE PE CTZ GCV MSG C/D I/O 0 0 0 0 x x x 0 Input/Output Command/Data Message Group Code Valid Count to Zero Parity Error Illegal Operation Error Interrupt 17348B-20 This read only register contains flags to indicate the status and phase of the SCSI transactions. It indicates whether an interrupt or error condition exists. It should be read every time the host is interrupted to determine which device is asserting an interrupt. If the ENF bit is set (CNTLREG2, bit 6), the SCSI bus phase of the last complete command (preceding the interrupt) will be latched until the Interrupt Status Register (INSTREG) is read. If the ENF bit is disabled, this register will reflect the current bus phase. If command stacking is used, two interrupts might occur. Reading this register will clear the status information for the first interrupt and update the Status Register for the second interrupt. STATREG – Bit 7 – INT – Interrupt The INT bit is set when the device asserts the interrupt output. This bit will be cleared by a hardware or software reset. Reading the Interrupt Status Register (INSTREG) will deassert the interrupt output and also clear this bit. STATREG – Bit 6 – IOE – Illegal Operation Error The IOE bit is set when an illegal operation is attempted. This condition will not cause an interrupt, it will be detected by reading the Status Register (STATREG) while servicing another interrupt. The following conditions will cause the IOE bit to be set: ■ ■ ■ DMA and SCSI transfer directions are opposite. FIFO overflows or data is overwritten. In Initiator mode an unexpected phase change detected during synchronous data transfer. ■ Command Register overwritten. This bit will be cleared by reading the Interrupt Status Register (INSTREG) or by a hard or soft reset. STATREG – Bit 5 – PE – Parity Error The PE bit is set if any of the parity checking options are enabled and the device detects a parity error on bytes sent or received on the SCSI Bus. Parity options are controlled by bits 5:4 in Control Register One (CNTLREG1), and by bits 2:0 in Control Register Two 20 (CNTLREG2). The combination of enabled options will determine if parity is generated from the data bytes internally by the chip, or if it is passed between buffer and SCSI Bus without being altered. Detection of a parity error condition will not cause an interrupt but will be reported with other interrupt causing conditions. This bit will be cleared by reading the Interrupt Status Register (INSTREG) or by a hard or soft reset. STATREG – Bit 4 – CTZ – Count To Zero The CTZ bit is set when the Current Transfer Count Register (CTCREG) has counted down to zero. This bit will be reset when the CTCREG is written with a nonzero value. Reading the Interrupt Status Register (INSTREG) will not affect this bit. This bit will however be cleared by a hard or soft reset. Note: A non-DMA NOP will not reset the CTZ bit since it does not load the CTCREG. However, a DMA NOP will reset this bit since it loads the CTCREG. STATREG – Bit 3 – GCV – Group Code Valid The GCV bit is set if the group code field in the Command Descriptor Block (CDB) is one that is defined by the ANSI Committee in their document X3.131 – 1986. If the SCSI-2 Feature Enable (S2FE) bit in the Control Register 2 (CNTLREG2) is set, Group 2 commands will be treated as ten byte commands and the GCV bit will be set. If S2FE is reset then Group 2 commands will be treated as reserved commands. Group 3 and 4 commands will always be considered reserved commands. The device will treat all reserved commands as six byte commands. Group 6 commands will always be treated as vendor unique six byte commands and Group 7 commands will always be treated as vendor unique ten byte commands. The GCV bit is cleared by reading the Interrupt Status Register (INSTREG) or by a hard or soft reset. Am53CF94/Am53CF96 PRELIMINARY STATREG – Bit 2 – MSG – Message AMD The MSG, C/D and I/O bits together can be referred to as the SCSI Phase bits. They indicate the phase of the SCSI bus. These bits may be latched or unlatched depending on whether or not the ENF bit in Control Register Two is set. STATREG – Bit 1 – C/D – Command/Data STATREG – Bit 0 – I/O – Input/Output Bit2 MSG Bit1 C/D Bit0 I/O SCSI Phase 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 Message In Message Out Reserved Reserved Status Command Data_In Data_Out In the latched mode the SCSI phase bits are latched at the end of a command and the latch is opened when the Interrupt Status Register (INSTREG) is read. In the unlatched mode, they indicate the phase of the SCSI bus when this register is read. SCSI Destination ID Register (04H) Write SCSI Destination ID Register SDIDREG Address: 04H Type: Write 7 6 5 4 3 2 1 0 RES RES RES RES RES DID2 DID1 DID0 0 0 0 0 0 x x x SCSI Destination ID 2:0 Reserved Reserved Reserved Reserved Reserved 17348B-21 SDIDREG – Bits 7:3 – RES – Reserved SDIDREG – Bits 2:0 – DID 2:0 – Destination ID 2:0 The DID 2:0 bits are the encoded SCSI ID of the device on the SCSI bus which needs to be selected or reselected. At power-up the state of these bits is undefined. The DID 2:0 bits are not affected by reset. DID2 DID1 DID0 SCSI ID 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 7 6 5 4 3 2 1 0 Am53CF94/Am53CF96 21 AMD PRELIMINARY Interrupt Status Register (05H) Read Interrupt Status Register INSTREG 7 SRST 0 6 ICMD 0 Address: 05h Type: READ 5 4 3 2 1 0 DIS SR SO RESEL SELA SEL 0 0 0 0 0 0 Selected Selected with Attention Reselected Successful Operation Service Request Disconnected Invalid Command SCSI Reset 17348B-22 The Interrupt Status Register (INSTREG) will indicate the reason for the interrupt. This register is used with the Status Register (STATREG) and Internal State Register (ISREG) to determine the reason for the interrupt. Reading the INSTREG will clear all three registers. Therefore the Status Register (STATREG) and Internal State Register (ISREG) should be examined prior to reading the INSTREG. INSTREG – Bit 7 – SRST – SCSI Reset The SRST bit will be set if a SCSI Reset is detected and SCSI reset reporting is enabled via the DISR (bit 6) of Control Register One (CNTLREG1). INSTREG – Bit 6 – ICMD – Invalid Command request. In the Target mode this bit will be set when the Initiator asserts the ATN signal. In the Initiator mode this bit is set when a Command Steps Successfully Completed Command is issued. INSTREG – Bit 3 – SO – Successful Operation The SO bit can be set in the Target or the Initiator mode when an operation has successfully completed. In the Target mode this bit will be set when any Target or Idle state command is completed. In the Initiator mode this bit is set after a Target has been successfully selected, after a command has successfully completed and after an information transfer command when the Target requests a Message In phase. The ICMD bit will be set if the device detects an illegal command code. This bit is also set if a command code is detected from a mode that is different from the mode the device is currently in. Once this bit is set, and invalid command interrupt will be generated. INSTREG – Bit 2 – RESEL – Reselected INSTREG – Bit 5 – DIS – Disconnected The SELA bit is set at the end of the selection phase indicating that the device has been selected as a Target by the Initiator and that the ATN signal was active during the selection. The DIS bit can be set in the Target or the Initiator mode when the device disconnects from the SCSI bus. In the Target mode this bit will be set if a Terminate or a Command Complete steps causes the device to disconnect from the SCSI bus. In the Initiator mode this bit will be set if the Target disconnects; while in Idle mode, this bit will be set if a selection or reselection timeout occurs. INSTREG – Bit 4 – SR – Service Request The RESEL bit is set at the end of the reselection phase indicating that the device has been reselected as an Initiator. INSTREG – Bit 1 – SELA – Selected with Attention INSTREG – Bit 0 – SEL – Selected The SEL bit is set at the end of the selection phase indicating that the device has been selected as a Target by the Initiator and that the ATN signal was inactive during the selection. The SR bit can be set in the Target or the Initiator mode when another device on the SCSI bus has a service 22 Am53CF94/Am53CF96 PRELIMINARY STIMREG – Bits 7:0 – STIM 7:0 – SCSI Timer 7:0 SCSI Timeout Register (05H) Write SCSI Timeout Register STIMREG AMD Address: 05H Type: Write 7 6 5 4 3 2 1 0 STIM7 STIM6 STIM5 STIM4 STIM3 STIM2 STIM1 STIM0 x x x x x x x x The value loaded in STIM 7:0 can be calculated as shown below: STIM 7:0 = [(SCSI Time Out) (Clock Frequency) / (8192 (Clock Factor))] Example: 17348B-23 This register determines how long the Initiator (Target) will wait for a response to a Selection (Reselection) before timing out. It should be set to yield 250 ms to comply with ANSI standards for SCSI, but the maximum time out period may be calculated using the following formulas. SCSI Time Out (in seconds): 250 ms. (Recommended by the ANSI Standard) = 250 x 10–3 s. Clock Frequency: 20 MHz. (assume) = 20 x 106 Hz. Clock Factor: CLKF 2:0 from Clock Conversion Register (09H) = 5 STIM 7:0 = (250 x 10–3) X (20 x 106) / (8192 (5)) = 122 decimal Note: A hardware reset will clear this register. Internal State Register (06H) Read Internal State Register ISREG Address: 06H Type: Read 7 6 5 4 3 2 1 0 RES RES RES RES SOF IS2 IS1 IS0 x x x x 0 0 0 0 Internal State 2:0 Synchronous Offset Flag Reserved Reserved Reserved Reserved 17348B-24 The Internal State Register (ISREG) tracks the progress of a sequence-type command. It is updated after each successful completion of an intermediate operation. If an error occurs, the host can read this register to determine the point where the command failed and take the necessary procedure for recovery. Reading the Interrupt Status Register (INSTREG) while an interrupt is pending will clear this register. A hard or soft reset will also zero this register . ISREG – Bits 7:4 – RES – Reserved ISREG – Bit 3 – SOF – Synchronous Offset Flag The SOF is reset when the Synchronous Offset Register (SOFREG) has reached its maximum value. Note: The SOF bit is active Low. ISREG – Bits 2:0 – IS 2:0 – Internal State 2:0 The IS 2:0 bits along with the Interrupt Status Register (INSTREG) indicates the status of the successfully completed intermediate operation. Refer to the Status Decode section for more details. Am53CF94/Am53CF96 23 AMD PRELIMINARY Initiator Select without ATN Steps Internal State Register (06H) Bits 2:0 (Hex) 0 4 3 Interrupt Status Register (05H) Bits 7:0 (Hex) 20 18 18 2 18 Explanation Arbitration steps completed. Selection time-out occurred, then disconnected Selection without ATN steps fully executed Sequence halted during command transfer due to premature phase change (Target) Arbitration and selection completed; sequence halted because Target failed to assert command phase Initiator Select with ATN Steps Internal State Register (06H) Bits 2:0 (Hex) 0 4 3 Interrupt Status Register (05H) Bits 7:0 (Hex) 20 18 18 2 18 0 18 Explanation Arbitration steps completed. Selection time-out occurred then disconnected Selection with ATN steps fully executed Sequence halted during command transfer due to premature phase change; some CDB bytes may not have been sent; check FIFO flags Message out completed; sent one message byte with ATN true, then released ATN; sequence halted because Target failed to assert command phase after message byte was sent Arbitration and selection completed; sequence halted because Target did not assert message out phase; ATN still driven by ESC Initiator Select with ATN3 Steps Internal State Register (06H) Bits 2:0 (Hex) 0 4 3 Interrupt Status Register (05H) Bits 7:0 (Hex) 20 18 18 2 18 0 18 Explanation Arbitration steps completed. Selection time-out occurred then disconnected Selection with ATN3 steps fully executed Sequence halted during command transfer due to premature phase change; some CDB bytes may not have been sent; check FIFO flags One, two, or three message bytes sent; sequence halted because Target failed to assert command phase after third message byte, or prematurely released message out phase; ATN released only if third message byte was sent Arbitration and selection completed; sequence halted because Target failed to assert message out phase; ATN still driven by ESC Initiator Select with ATN and Stop Steps Internal State Register (06H) Bits 2:0 (Hex) 0 0 Interrupt Status Register (05H) Bits 7:0 (Hex) 20 18 1 18 24 Explanation Arbitration steps completed. Selection time-out occurred then disconnected Arbitration and selection completed; sequence halted because Target failed to assert message out phase; ATN still asserted by ESC Message out completed; one message byte sent; ATN on Am53CF94/Am53CF96 PRELIMINARY AMD Target Select without ATN Steps Internal State Register (06H) Bits 2:0 (Hex) 2 1 Interrupt Status Register (05H) Bits 7:0 (Hex) 11 11 2 1 01 01 0 01 Explanation Selected; received entire CDB; check group code valid bit Sequence halted in command phase due to parity error; some CDB bytes may not have been received; check FIFO flags; Initiator asserted ATN in command phase Selected; received entire CDB; check group code valid bit Sequence halted in command phase because of parity error; some CDB bytes may not have been received; check FIFO flags Selected; loaded bus ID into FIFO; null-byte message loaded into FIFO Target Select with ATN Steps, SCSI-2 Bit NOT SET Internal State Register (06H) Bits 2:0 (Hex) 2 Interrupt Status Register (05H) Bits 7:0 (Hex) 12 1 0 12 12 2 1 02 02 0 02 Explanation Selection complete; received one message byte and entire CDB; Initiator asserted ATN during command phase Halted in command phase; parity error and ATN true Selected with ATN; stored bus ID and one message byte; sequence halted because ATN remained true after first message byte Selection completed; received one message byte and the entire CDB Sequence halted in command phase because of parity error; some CDB bytes not received; check group code valid bit and FIFO flags Selected with ATN; stored bus ID and one message byte; sequence halted because of parity error or invalid ID message Target Select with ATN Steps, SCSI-2 Bit SET Internal State Register (06H) Bits 2:0 (Hex) 6 5 4 2 Interrupt Status Register (05H) Bits 7:0 (Hex) 12 12 12 12 1 12 0 12 6 5 02 02 4 2 02 02 1 02 0 02 Explanation Selection completed; received three message bytes and entire CDB. ATN is true Halted in command phase; parity error and ATN true ATN remained true after third message byte Selection completed; Initiator deasserts ATN after receipt of one message byte; entire CDB received. ATN asserted during command phase Sequence halted during command phase because of parity error; one message byte received; some bytes of CDB not received; parity error and ATN true Selected with ATN; stored bus ID and one message byte; sequence halted because of parity error or invalid ID message; ATN is true Selection completed; received three message bytes and the entire CDB Received three message bytes then halted in command phase because of parity error; some CDB bytes not received; check group code valid bit and FIFO flags Parity error during second or third message byte Selection completed; Initiator deasserts ATN after receipt of one message byte; entire CDB received Sequence halted during command phase because of parity error; one message byte received; some bytes of CDB not received; check FIFO flags and group code valid bit Selected with ATN; stored bus ID and one message byte; sequence halted because of parity error or invalid ID message Am53CF94/Am53CF96 25 AMD PRELIMINARY Target Receive Command Steps Internal State Register (06H) Bits 2:0 (Hex) 2 1 Interrupt Status Register (05H) Bits 7:0 (Hex) 18 18 2 1 08 08 Explanation Received entire CDB; Initiator asserted ATN Sequence halted during command transfer due to parity error; ATN asserted by Initiator Received entire CDB Sequence halted during command transfer due to parity error; check FIFO flags Target Disconnect Steps Internal State Register (06H) Bits 2:0 (Hex) 2 1 0 Interrupt Status Register (05H) Bits 7:0 (Hex) 28 18 18 Explanation Disconnect steps fully executed; disconnected; bus is free Two message bytes sent; sequence halted because Initiator asserted ATN One message byte sent; sequence halted because Initiator asserted ATN Target Terminate Steps Internal State Register (06H) Bits 2:0 (Hex) 2 1 0 26 Interrupt Status Register (05H) Bits 7:0 (Hex) 28 18 18 Explanation Terminate steps fully executed; disconnected; bus is free Status and message bytes sent; sequence halted because Initiator asserted ATN Status byte sent; sequence halted because Initiator asserted ATN Am53CF94/Am53CF96 PRELIMINARY AMD Synchronous Transfer Period Register (06H) Write Synchronous Transfer Period Register STPREG 7 6 5 4 3 RES RES RES STP4 x x x 0 STP3 0 Address: 06H Type: Write 1 0 2 STP2 STP1 STP0 1 0 1 Synchronous Transfer Period 4:0 Reserved Reserved Reserved 17348B-25 The Synchronous Transfer Period Register (STPREG) contains a 5-bit value indicating the number of clock cycles each byte will take to be transferred over the SCSI bus in synchronous mode. The minimum value allowed is 4. The STPREG defaults to 5 clocks/byte after a hard or soft reset. STPREG – Bits 7:5 – RES – Reserved STPREG – Bits 4:0 – STP 4:0 – Synchronous Transfer Period 4:0 The STP 4:0 bits are programmed to specify the synchronous transfer period or the number of clock cycles for each byte transfer in the synchronous mode. The minimum value for STP 4:0 is 4 clocks/byte. Missing table entries follow the binary code. STP4 0 0 0 0 • • 1 0 0 0 0 Am53CF94/Am53CF96 STP3 0 0 0 0 • • 1 0 0 0 0 STP2 1 1 1 1 • • 1 0 0 0 0 STP1 0 0 1 1 • • 1 0 0 1 1 STP0 0 1 0 1 • • 1 0 1 0 1 Clocks/ Byte 4 5 6 7 • • 31 32 33 34 35 27 AMD PRELIMINARY Current FIFO/Internal State Register (07H) Read Current FIFO/Internal State Register CFISREG Address: 07H Type: Read 7 6 5 4 3 2 1 0 IS2 IS1 IS0 CF4 CF3 CF2 CF1 CF0 0 0 0 0 0 0 0 0 Current FIFO 4:0 Internal State 2:0 17348B-26 This register has two fields, the Current FIFO field and the Internal State field. CFISREG – Bits 7:5 – IS 2:0 – Internal State 2:0 transfer can continue. A zero value indicates that the synchronous offset count has been reached and no more data can be transferred until an acknowledge is received. The Internal State Register (ISREG) tracks the progress of a sequence-type command. CFISREG – Bits 4:0 – CF 4:0 – Current FIFO 4:0 The CF 4:0 bits are the binary coded value of the number of bytes in the FIFO. These bits should not be read when the device is transferring data since this count may not be stable. The IS 2:0 bits are duplicated from the IS 2:0 field in the Internal State Register (ISREG) in the normal mode. If the device is in the test mode, (see CNTLREG1, bit 3) IS 0 is set to indicate that the offset value is non-zero. A non-zero value indicates that synchronous data Synchronous Offset Register (07H) Write Synchronous Offset Register SOFREG Address: 07H Type: Write 7 6 5 4 3 2 1 0 RAD1 RAD0 RAA1 RAA0 SO3 SO2 SO1 SO0 0 0 0 0 0 0 0 0 Synchronous Offset 3:0 REQ/ACK Assertion 1:0 REQ/ACK Deassertion 1:0 17348B-27 The Synchronous Offset Register (SOFREG) controls REQ/ACK deassertion/assertion delay and stores a 4-bit count of the number of bytes that can be sent to (or received from) the SCSI bus during synchronous transfers without an ACK (or REQ). Bytes exceeding the threshold will be sent one byte at a time (asynchronously). That is, each byte will require an ACK/REQ handshake. To set up an asynchronous transfer, the SOFREG is set to zero. The SOFREG is set to zero after a hard or soft reset. 28 SOFREG – Bits 7:6 – RAD 1:0 These bits may be programmed to control the deassertion delay of the REQ and ACK signals during synchronous transfers. Deassertion delay is expressed as input clock cycles, and depends on the implementation of FASTCLK. (See CNTLREG3, bit 3) Am53CF94/Am53CF96 PRELIMINARY SOFREG FASTCLK Bits 7:6 Ctrl 3, Bit 3 00 01 10 11 00 01 10 11 0 0 0 0 1 1 1 1 Deassertion Delay REQ/ACK Input CLK Cycles Default – 0 cycles 1/2 cycle early 1 cycle delay 1/2 cycle delay Default – 0 cycles 1/2 cycle delay 1 cycle delay 1 1/2 cycles delay AMD SOFREG Bits 5:4 Assertion Delay REQ/ACK Input CLK Cycles 00 01 10 11 Default – 0 cycles 1/2 cycle delay 1 cycle delay 1 1/2 cycles delay SOFREG – Bits 3:0 – SO 3:0 – Synchronous Offset 3:0 The SO 3:0 bits are the binary coded value of the number of bytes that can be sent to (or received from) the SCSI bus without an ACK (or REQ) signal. A zero value designates Asynchronous xfer, while a non-zero value designates the number of bytes for synchronous transfer. SOFREG – Bits 5:4 – RAA 1:0 These bits may be programmed to control the assertion delay of the REQ and ACK signals during synchronous transfers. Unlike deassertion delay, assertion delay is independent of the FASTCLK setting. Control Register One (08H) Read/Write Control Register One CNTLREG1 Address: 08H Type: Read/Write 7 6 5 4 3 2 1 0 ETM DISR PTE PERE STE CID2 CID1 CID0 0 0 0 0 x x x 0 Chip ID 2:0 Self Test Enable Parity Error Reporting Enable Parity Test Enable Disable Interrupt on SCSI Reset Extended Timing Mode 17348B-28 The Control Register 1 (CNTLREG1) sets up the device with various operating parameters. CNTLREG1 – Bit 7 – ETM – Extended Timing Mode Enabling this feature will increase the minimum setup time for data being transmitted on the SCSI bus. This bit should only be set if the external cabling conditions produce SCSI timing violations. FASTCLK operation is unaffected by this feature. CNTLREG1 – Bit 6 – DISR – Disable Interrupt on SCSI Reset The DISR bit masks the reporting of the SCSI reset. When the DISR bit is set and a SCSI reset is asserted, the device will disconnect from the SCSI bus and remain idle without interrupting the host processor. When the DISR bit is reset and a SCSI reset is asserted the device will respond by interrupting the host processor. The DISR bit is reset to zero by a hard or soft reset. CNTLREG1 – Bit 5 – PTE – Parity Test Enable The PTE bit is for test use only. When the PTE bit is set the parity on the output (SCSI or host processor) bus is forced to the value of the MSB (bit 7) of the output data from the internal FIFO. This allows parity errors to be created to test the hardware and software. The PTE bit is reset to zero by a hard or soft reset. This bit should not be set in normal operation. CNTLREG1 – Bit 4 – PERE – Parity Error Reporting Enable The PERE bit enables the checking and reporting of parity errors on incoming SCSI bytes during the information transfer phase. When the PERE bit set and bad parity is detected, the PE bit in the STATREG is will be set but an interrupt will not be generated. In the Initiator mode the ATN signal will also be asserted on the SCSI bus. When Am53CF94/Am53CF96 29 AMD PRELIMINARY the PERE bit is reset and bad parity occurs it is not detected and no action is taken. CNTLREG1 – Bit 2:0 – CID 2:0 – Chip ID 2:0 The Chip ID 2:0 bits specify the binary coded value of the device ID on the SCSI bus. The device will arbitrate with this ID and will respond to Selection or Reselection to this ID. At power-up the state of these bit are undefined. These bits are not affected by hard or soft reset. CNTLREG1 – Bit 3 – STE – Self Test Enable The STE bit is for test use only. When the STE bit is set the device is placed in a test mode which enables the device to access the test register at address 0AH. To reset this bit and to resume normal operation the device must be issued a hard or soft reset. Clock Factor Register (09H) Write Clock Factor Register CLKFREG Address: 09H Type: Write 7 6 5 4 3 2 1 0 RES RES RES RES RES CLKF2 CLKF1 CLKF0 x x x x x 0 1 0 Clock Factor 2:0 Reserved Reserved Reserved Reserved Reserved The Clock Factor Register (CLKFREG) must be set to indicate the input frequency range of the device. This value is crucial for controlling various timings to meet the SCSI specification. The value of bits CLKF 2:0 can be calculated by rounding off the quotient of (Input Clock Frequency in MHz)/(5 MHz). The device has a frequency range of 10 to 40 MHz. CLKFREG – Bits 7:3 – RES – Reserved CLKFREG – Bits 2:0 – CLKF 2:0 – Clock Factor 2:0 The CLKF 2:0 bits specify the binary coded value of the clock factor. The CLKF 2:0 bits will default to a value of 2 by a hard or soft reset. 30 17348B-29 Input Clock CLKF0 Frequency in MHz CLKF2 CLKF1 0 1 0 10 0 1 1 10.01 to 15 1 0 0 15.01 to 20 1 0 1 20.01 to 25 1 1 0 25.01 to 30 1 1 1 30.01 to 35 0 0 0 35.01 to 40 Am53CF94/Am53CF96 PRELIMINARY AMD Forced Test Mode Register (0AH) Write Forced Test Mode Register FTMREG Address: 0AH Type: Write 7 6 5 4 3 2 1 0 RES RES RES RES RES FHI FIM FTM x x x x x 0 0 0 Forced Target Mode Forced Initiator Mode Forced High Impedance Mode Reserved Reserved Reserved Reserved Reserved 17348B-30 The Forced Test Mode Register (FTMREG) is for test use only. The STE bit in the Control Register One (CNTLREG1) must be set for the FTMREG to operate. FTMREG – Bits 7:3 – RES – Reserved FTMREG – Bit 2 – FHI – Forced High Impedance Mode the command loaded in the Command Register). The ESC will remain in this mode for as long as BSY is asserted, or until a Reset SCSI Bus or Reset Device command occurs. During normal operation this bit must not be set. FTMREG – Bit 0 – FTM – Forced Target Mode The FHI bit when set places all the output and bidirectional pins into a high impedance state. It is zeroed by a hardware or chip reset. FTMREG – Bit 1 – FIM – Forced Initiator Mode The FIM bit when set forces the ESC into the Initiator mode. As an Initiator, the device will drive SCSI data lines, and ACK or ATN (depending on the bus phase and The FTM bit when set forces the ESC into the Target mode. As a Target, the device does not assert BSY; rather, it drives SCSI data lines, REQ, MSG, C/D or I/O (depending on the command loaded in the Command Register). The ESC will remain in this mode until a Disconnect Steps, Reset SCSI Bus, or Reset Device command occurs. During normal operation this bit must not be set. Control Register Two (0BH) Read/Write Control Register Two CNTLREG2 Address: 0BH Type: Read/Write 7 6 5 4 3 2 1 0 DAE ENF SBO TSDR S2FE ACDPE PGRP PGDP 0 0 0 0 0 0 0 0 Pass Through/Generate Data Parity Pass Through/Generate Register Parity Abort on Command/Data Parity Error SCSI-2 Features Enable Tri-State DMA Request Select Byte Order Enable Features Data Alignment Enable 17348B-31 The Control Register Two (CNTLREG2) sets up the device with various operating parameters. transferred to the memory, the upper byte being the first byte of the first word received from the SCSI bus. CNTLREG2 – Bit 7 – DAE – Data Alignment Enable Note: If an interrupt is received for a misaligned boundary on a phase change to synchronous data the following recovery procedure may be followed. The host processor should copy the byte at the start address in the host memory to the Data Alignment Register 0FH (DALREG) The DAE bit is used in the Initiator Synchronous Data-In phase only. When the DAE bit is set one byte is reserved at the bottom of the FIFO when the phase changes to the Synchronous Data-In phase. The contents of this byte will become the lower byte of the DMA word (16-bit) Am53CF94/Am53CF96 31 AMD PRELIMINARY and then issue an information transfer command. The first word the device will write to the memory (via DMA) will consists of the lower byte from the DALREG and the upper byte from the first byte received from the SCSI bus. The DAE bit must be set before the phase changes to the Synchronous Data-In. The DAE bit is reset to zero by a hard or soft reset or by writing the DALREG when interrupted in the Synchronous Data-In phase. CNTLREG2 – Bit 6 – ENF – Enable Features A software or hardware reset will clear this bit to its default value of ‘0’; a SCSI reset will leave this bit unaffected. When set to a value of ‘1’, this bit activates the following product enhancements: 1) The Current Transfer Count Register High (0EH) will be enabled, extending the transfer counter from 16 to 24 bits to allow for larger transfers. 2) Following a chip or power on reset, up until the point where the Current Transfer Count Register High (0EH) is loaded with a value, it is possible to read the part-unique ID from this register. 3) The SCSI phase will be latched at the completion of each command by bits 2:0 in the Status Register (STATREG). When this bit is ‘0’, the Status Register (STATREG) will reflect real-time SCSI phases. 4) The enable signal for the differential drivers may be delayed to avoid bus contention on the SCSI differential lines when the direction for I/O is switching. When the SCSI bus changes direction from input to output, the output drivers are not asserted for two clock cycles to avoid bus contention. When the bus changes from output to input, SDC7:0 are given time to switch direction before the SCSI drivers are asserted. CNTLREG2 – Bit 5 – SBO – Select Byte Order The SBO bit is used only when the BUSMD 1:0 = 10 to enable or disable the byte control on the DMA interface. When SBO is set and the BUSMD 1:0 = 10, the byte control inputs BHE and AS0 control the byte positions. When SBO is reset the byte control inputs BHE and AS0 are ignored. CNTLREG2 – Bit 3 – S2FE – SCSI-2 Features Enable The S2FE bit allows the device to recognize two SCSI-2 features: the extended message feature and the Group 2 command recognition. (These features can also be controlled independently by bits 6:5 in CNTLREG3). Extended Message Feature: When the S2FE bit is set and the device is selected with attention, the device will monitor the ATN signal at the end of the first message byte. If the ATN signal is active, the device will request two more message bytes before switching to the command phase. If the ATN signal is inactive the device will switch to the Command phase. When the S2FE bit is reset as a Target the device will request a single message byte. As an Initiator, the device will abort the selection sequence if the Target does not switch to the Command phase after receiving a single message byte. Group 2 Command Recognition: When the S2FE bit is set, the GCV (Group Code Valid) bit in the STATREG (04H) is set, allowing the Group 2 commands to be recognized as 10 byte commands. When the S2FE bit is reset, the GCV bit in the STATREG is not set, and the device will interpret the Group 2 commands as reserved commands and will request 6 byte commands. CNTLREG2 – Bit 2 – ACDPE – Abort on Command/ Data Parity Error The ACDPE bit when set allows the device to abort a command or data transfer when a parity error is detected. When the ACDPE bit is reset parity error is ignored. CNTLREG2 – Bit 1 – PGRP – Pass Through/Generate Register Parity The PGRP bit, when set, allows parity from DMAP1–0 to pass during register writes to the FIFO. Enabling this bit also causes parity checking as data is unloaded from the FIFO to the SCSI bus. When this bit is reset to zero, parity is generated for register writes to the FIFO, however no additional checking will be done as FIFO data is unloaded to the SCSI bus unless the PGDP bit is set. CNTLREG2 – Bit 4 – TSDR – Tri-State DMA Request CNTLREG2 – Bit 0 – PGDP – Pass Through/Generate Data Parity The TSDR bit when set sends the DREQ output signal to high impedance state and the device ignores all activity on the DMA request (DREQ) input. This is useful for wiring-OR several devices that share a common DMA request line. When the TSDR bit is reset the DREQ output is driven to TTL levels. The PGDP bit, when set, allows parity from DMAP1–0 to pass during DMA writes to the FIFO. Parity checking will also be performed as data is unloaded from the FIFO to the SCSI bus. 32 When this bit is reset to zero, parity is generated during DMA Writes to the FIFO, however no additional checking will be done as FIFO data is unloaded, unless the PGRP bit is set. Am53CF94/Am53CF96 PRELIMINARY AMD Control Register Three (0CH) Read/Write Control Register Three CNTLREG3 Address: 0CH Type: Read/Write 7 6 5 4 3 2 1 0 ADID CHK QTAG G2CB FAST SCSI FAST CLK LBTM MDM BS8 0 0 0 0 0 0 0 0 Burst Size 8 Modify DMA Mode Last Byte Transfer Mode FASTCLK FASTSCSI Group 2 Command Block QTAG Control Additional ID Check CNTLREG3 – Bit 7 – ADIDCHK – Additional ID Check Enables additional check on ID message during businitiated Select or Reselect with ATN. The ESC will check bits 7, and bits 5:3 in the first byte of the ID message during Selection of Reselection. An interrupt will be generated if bit 7 is ‘0’, or if bits 5, 4, or 3 are ‘1’. CNTLREG3 – Bit 6 – QTAG – QTAG Control 17348B-32 CNTLREG3 – Bit 4 – FASTSCSI – Fast SCSI CNTLREG3 – Bit 3 – FASTCLK – Fast SCSI Clocking These bits configure the ESC’s state machine to support both Fast SCSI timings and SCSI-1 timings. These bits will affect the SCSI transfer rate, and must be considered in conjunction with the ESC’s clock frequency and mode of operation. This bit controls the Queue Tag feature in the ESC. When enabled, the ESC is capable of receiving 3-byte messages during bus-initiated Select/Reselect with ATN. (Bit 3, Control Register Two also enables this feature). The 3-byte message consists of one byte Identify Message and two bytes of Queue Tag message. The ESC will check the second byte for values of 20h, 21h, and 22h. If this condition is not satisfied, the sequence halts and the ESC generates an interrupt. CNTLREG3 Bit 6 QTAG CNTLREG3 Bit 5 G2CB CNTLREG2 Bit 3 S2FE –– –– 1 10-byte CDB, 3-byte message 1 0 0 3-byte message 0 1 0 10-byte CDB When the QTAG feature is not enabled, the ESC halts the Selected with ATN sequence following the receipt of one ID message byte if ATN is still true. 1 1 0 10-byte CDB, 3-byte message 0 0 0 Features disabled CNTLREG3 – Bit 5 – G2CB – Group 2 Command Block Enabled Features –– = don’t care When this bit is set, the ESC is capable of recognizing 10-byte Group 2 Commands as valid CDBs (Command Descriptor Blocks). (This feature is also controlled by bit 3 of CNTLREG2). When this feature is enabled, the Target receives 10 bytes of Group 2 commands, and sets the group code valid bit (bit 3) in Status Register (STATREG). When this feature is disabled, the Target receives only 6 bytes of command code, and does not set bit 3 in register (04H). This bit may be programmed in conjunction with bit 6 (described above) to send 1 or 3 byte messages with 6 or 10 byte CDBs. The following table illustrates the transmission options: Am53CF94/Am53CF96 33 AMD PRELIMINARY CNTLREG3 FASTSCSI Bit 4 CNTLREG3 FASTCLK Bit 3 Clock Frequency Mode of Operation 1 1 25–40 MHz 10 MBytes/ sec, Fast SCSI 0 1 25–40 MHz 5 MBytes/sec, SCSI-1 –– 0 < = 25 MHz 5 MBytes/sec, SCSI-1 –– = don’t care CNTLREG3 – Bit 2 – LBTM – Last Byte Transfer Mode The LBTM bit specifies how the last byte in an odd byte transfer is handled during 16-bit DMA transfers (modes 1, 2, 3). This mode is not used if byte control is selected via BUSMD 1:0 = 10 and SBO (Select Byte Order) bit in the CNTLREG2is set to ‘1’. This mode has no affect during 8-bit DMA transfers (mode 0) and on transfers on the SCSI bus. When the LBTM bit is set the DREQ signal will not be asserted for the last byte, instead the host will read or write the last byte from or to the FIFO. When the LBTM bit is reset the DREQ signal will be asserted for the last byte and the following 16-bit DMA transfer will contain the last byte on the lower bus. While the upper bus (DMA 15:8/DMAP 1) will be all ones. The LBTM bit is reset by hard or soft reset. CNTLREG3 – Bit 1 – MDM – Modify DMA Mode The MDM bit is used to modify the timing of the DACK signal with respect to the DMARD and DMAWR signals. The MDM bit is used in conjunction with the Burst Size 8 (BS8) bit in the CNTLREG3. Both bits have to be set for proper operation. When the MDM bit is set and the device is in a DMA read or write mode the DACK signal will remain asserted while the data is strobed by the DMARD or DMAWR signals. In the DMA read mode when BUSMD 1:0 = 11 the DACK signal will toggle for every DMA read. When the MDM bit is reset and the device is in a DMA read or write mode the DACK signal will toggle every time the data is strobed by the DMARD or DMAWR signals. The BS8 bit is used in conjunction with the Modify DMA Mode (MDM) bit in the CNTLREG3. Both bits have to be set for proper operation. When the BS8 bit is set the device delays the assertion of the DREQ signal until 8 bytes or 4 words transfer is possible. When the BS8 bit is set and the device is in a DMA write mode the DREQ signal will be asserted only when 8 byte locations are available for writing. In the DMA read mode the DREQ signal will go active under the following circumstances: At the end of a transfer, ■ ■ In the Target mode, – when the transfer is complete or – when the ATN signal is active In the Initiator mode, – when the Current Transfer Register (CTCREG) is decremented to zero or – after any phase change In the middle of a transfer ■ In the Initiator mode, – when the last 8 bytes of the FIFO are full – during Synchronous Data-In transfer when the Event Transfer Count Register is greater than 7 and the last 8 bytes of the FIFO are full. When the BS8 bit is reset and the device is in a DMA read or write mode the DREQ signal will toggle every time the data is strobed by the DMARD or DMAWR signals. Using (Bit 0 (BS8) and Bit 1 (MDM) of Control Register Three (CNTLREG3), one can enable the different combination modes shown in the table below. (MDM) Bit 1 (BS8) Bit 0 Function Maximum Synchronous Offset 0 0 Normal DMA Mode 15 0 1 Burst Size 8 Mode 7 1 0 Reserved – 1 1 Modified DMA Mode 7 CNTLREG3 – Bit 0 – BS8 – Burst Size 8 The BS8 bit is used to modify the timing of the DREQ signal with respect to the DMARD and DMAWR signals. 34 Am53CF94/Am53CF96 PRELIMINARY AMD Control Register Four (0DH) Control Register Four CNTLREG4 7 6 5 Address: 00H 4 3 2 1 RADE RES NU 0 X X GE1 GE0 PWD RES RES (R) RAE(W) 0 0 0 X 0 0 Transfer Count Test Enable Active Negation Ctl. RES (R)/Active Negation Ctl (W) Reserved Power-Down GLITCH EATER 17348B-33 This register is used to control several AMD proprietary features implemented in the Am53CF94/96. At power up, this register will show a ‘0’ value on all bits except bit 4. CNTLREG4 – Bit 3 (Write Only) – RAE – Active Negation Control CNTLREG4 – Bit 7:6 – GE1:0 – GLITCH EATER Bits 2 and 3 control the Active Negation Drivers which may be enabled on REQ, ACK, or DATA lines. The following table shows the programming options for this feature: The GLITCH EATER circuitry has been implemented on all SCSI input lines and are controlled by bits 7and 6. The valid signal window may be adjusted by setting the bits in the combinations listed below. CNTLREG4 Bit 7 GE1 CNTLREG4 Bit 6 GE0 Singleended 0 0 12 ns 0 ns 1 0 25 ns 25 ns 0 1 35 ns 35 ns 1 1 0 ns 12 ns Differential CNTLREG4 – Bit 2 – RADE – Active Negation Control CNTLREG4 Bit 3 RAE CNTLREG4 Bit 2 RADE 0 0 Active Negation Disabled 1 0 Active Negation on REQ and ACK only –– 1 Active Negation on REQ, ACK and DATA Function Selected –– = don’t care CNTLREG4 – Bit 5 – PWD – Power-Down Feature Setting this bit to ‘1’ will enable AMD’s exclusive powerdown feature. This will turn off the input buffers on all the SCSI bus signal lines to reduce power consumption during the chip’s sleep mode. CNTLREG4 – Bit 4 – RES This bit is reserved for internal use. CNTLREG4 – Bit 1 – RES This bit is reserved for internal use. CNTLREG4 – Bit 0 – NU – Not Used The NCR53CF94/96 uses this bit to control back-toback transfers. This bit may be read or written but is not used by the Am53CF94/96. Back-to-Back transfers are always enabled. CNTLREG4 – Bit 3 (Read Only) – RES This bit is reserved for internal use. Am53CF94/Am53CF96 35 AMD PRELIMINARY Data Alignment Register (0FH) Write Data Alignment Register DALREG Part-Unique ID Register (0EH) Read Only Address: OF H Type: Write 7 6 5 4 3 2 1 0 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 0 0 0 0 0 0 0 0 17348B-34 The Data Alignment Register (DALREG) is used if the first byte of a 16-bit DMA transfer from the SCSI bus to the host processor is misaligned. Prior to issuing an information transfer command, the host processor must set the Data Alignment Enable (DAE) bit in Control Register Two (CNTLREG2). This register may be loaded immediately following the phase change to Synchronous Data In. This byte will become the LSB of the first word transmitted from the FIFO to the DMA controller. The MSB will be comprised of the first byte received over the SCSI bus. Together, these bytes constitute the first 16-bit word transferred to memory. This register extends the transfer counter from 16 to 24 bits and is only enabled when the ENF bit is set (bit 6, Control Register Two). The descriptions accompanying the Start Transfer Count Registers and the Current Count Registers should be referenced for more information regarding the transfer counter. This register is also used to store the part-unique ID code for the Am53CF94/96. This information may be accessed when all of the following are true: 1) A value has not been loaded into this register 2) A DMA NOP command has been issued (code 80h) 3) Bit 6 in Control Register Two is set (ENF bit) 4) A power up or chip reset has taken place When the above conditions are satisfied, the following bit descriptions apply: ID Am53CF94, 3 V 12 Am53CF94, 5 V 12 DALREG – Bits 7:0 – DA 7:0 – Data Alignment 7:0 36 Am53CF94/Am53CF96 PRELIMINARY AMD COMMANDS The device commands can be broadly divided into two categories, DMA commands and non-DMA commands. DMA commands are those which cause data movement between the host memory and the SCSI bus while non- DMA commands are those that cause data movement between the device FIFO and the SCSI bus. The MSB of the command byte differentiate the DMA from the nonDMA commands. Summary of Commands Command Code (Hex.) Command NonDMA Mode Command Code (Hex.) Command DMA Mode NonDMA Mode DMA Mode Idle State Commands Initiator Commands Information Transfer 10 90 Reselect Steps 40 C0 Initiator Command Complete Steps 11 91 Select without ATN Steps 41 C1 Message Accepted 12 – Select with ATN Steps 42 C2 Transfer Pad Bytes 18 98 Select with ATN and Stop Steps 43 C3 Set ATN 1A – Enable Selection/Reselection 44 C4 Reset ATN 1B – Disable Selection/Reselection 45 C5 Select With ATN3 Steps 46 C6 Reselect with ATN3 Steps 47 C7 Target Commands Send Message 20 A0 Send Status 21 A1 General Commands Send Data 22 A2 No Operation 00 80 Disconnect Steps 23 A3 Clear FIFO 01 81 Terminate Steps 24 A4 Reset Device 02 82 Target Command Complete Steps 25 A5 Reset SCSI bus 03 83 Disconnect 27 A7 Receive Message 28 A8 Receive Command Steps 29 A9 Receive Data 2A AA Receive Command Steps 2B AB DMA Stop Command 04 84 Access FIFO Command 05 85 Am53CF94/Am53CF96 37 AMD PRELIMINARY COMMAND DESCRIPTION Initiator Commands Initiator commands are executed by the device when it is in the Initiator mode. If the device is not in the Initiator mode and an Initiator command is received the device will ignore the command, generate an Invalid Command interrupt and clear the Command Register (CMDREG). Should the Target disconnect from the SCSI bus by deasserting the BSY signal line while the ESC (Initiator) is waiting for the Target to assert REQ, a Disconnected Interrupt will be issued 1.5 to 3.5 clock cycles following BSY going false. Upon receipt of the last byte during Msg In phase, ACK will remain asserted to prevent the Target from issuing any additional bytes, while the Initiator decides to accept/reject the message. If non-DMA commands are used, the last byte signals the FIFO is empty. If DMA commands are used, the transfer counter signals the last byte. If parity checking is enabled in the Initiator mode and an error is detected, ATN will be asserted for the erroneous byte before deasserting ACK. An exception to this is following a phase change to Synchronous Data In. To program Synchronous Transfer, the Synchronous Offset Register (SOFREG) must be set to a non-zero value. While in this mode, if the phase changes to Data In, the DMA interface is disabled, and parity generation is delayed. The Data In phase will latch the FIFO flags to indicate the number of bytes in the FIFO, clear the FIFO, load the FIFO with the first byte of Data In, generate an interrupt, and continue to load the FIFO with incoming bytes up to the synchronous offset. Information Transfer Command (Command Code 10H/90H) The Information Transfer command is used to transfer information bytes over the SCSI bus. This command may be issued during any SCSI Information Transfer phase. Synchronous data transmission requires use of the DMA mode. The device will continue to transfer information until it is terminated by any one of the following conditions: ■ The Target changes the SCSI bus phase before the expected number of bytes are transferred. The device clears the Command Register (CMDREG), and generates a service interrupt when the Target asserts REQ. ■ Transfer is successfully complete. If the phase is Message Out, the device deasserts ATN before asserting ACK for the last byte of the message. When the Target asserts REQ, a service interrupt is generated. ■ In the Message In phase when the device receives the last byte. The device keeps the ACK signal asserted and generates a Successful Operation interrupt. 38 During synchronous data Transfers the Target may send up to the maximum synchronous threshold number of REQ pulses to the Initiator. If it is the Synchronous Data-In phase then the Target sends the data and the REQ pulses. These bytes are stored by the Initiator in the FIFO as they are received. Information Transfer Command, when issued during the following SCSI phases and terminated in synchronous data phases, is handled as described below: ■ Message In/Status Phase – When a phase change to Synchronous Data-In or Synchronous Data-Out is detected by the device, the Command Register (CMDREG) is cleared and the DMA interface is disabled to disallow any transfer of data phase bytes. If the phase change is to Synchronous Data-In and bad parity is detected on the data bytes coming in, it is not reported since the Status Register (STATREG) will report the status of the command just completed. The parity error flag and the ATN signal will be asserted when the Transfer Information command begins execution. ■ Message Out/Command Phase – When a phase change to Synchronous Data-In or Synchronous Data-Out is detected by the device, the Command Register (CMDREG) is cleared and the DMA interface is disabled to disallow any transfer of data phase bytes. If the phase change is to Synchronous Data-In and bad parity is detected on the data bytes coming in, it is not reported since the Status Register (STATREG) will report the status of the command just completed. The parity error flag and the ATN signal will be asserted when the Transfer Information command begins execution. The FIFO Register (FFREG) will be latched and will remain in that condition until the next command begins execution. The value in the FFREG indicates the number of bytes in the FIFO when the phase changed to Synchronous Data-In. These bytes are cleared from the FIFO, which now contains only the incoming data bytes. ■ In the Synchronous Data-Out phase, the threshold counter is incremented as REQ pulses are received. The transfer is completed when the FIFO is empty and the Current Transfer Count Register (CTCREG) is zero. The threshold counter will not be zero. ■ In the Synchronous Data-In phase, the Current Transfer Count Register (CTCREG) is decremented as bytes are read from the FIFO rather than being decremented when the bytes are being written to the FIFO. The transfer is completed when Current Transfer Count Register (CTCREG) is zero but the FIFO may not be empty. Am53CF94/Am53CF96 PRELIMINARY Initiator Command Complete Steps (Command Code 11H/91H) The Initiator Command Complete Steps command is normally issued when the SCSI bus is in the Status In phase. One Status byte followed by one Message byte is transferred if this command completes normally. After receiving the message byte the device will keep the ACK signal asserted to allow the Initiator to examine the message and assert the ATN signal if it is unacceptable. The command terminates early if the Target does not switch to the Message In phase or if the Target disconnects from the SCSI bus. AMD the end of this command. The ATN signal is deasserted before asserting the ACK signal during the last byte of the Message Out phase. Note: The ATN signal is asserted by the device without this command in the following cases: ■ If any select with ATN command is issued and the arbitration is won. ■ An Initiator needs the Target’s attention to send a message. The ATN signal is asserted before deasserting the ACK signal. Reset ATN Command (Command Code 1BH) Message Accepted Command (Command Code 12H) The Message Accepted Command is used to release the ACK signal. This command is normally used to complete a Message In handshake. Upon execution of this command the device generates a service request interrupt after REQ is asserted by the Target. After the device has received the last byte of message, it keeps the ACK signal asserted. This allows the device to either accept or reject the message. To accept the message, Message Accepted Command is issued. To reject the message the ATN signal must be asserted (with the help of the Set ATN Command) before issuing the Message Accepted Command. In either case the Message Accepted Command has to be issued to release the ACK signal. Transfer Pad Bytes Command (Command Code 18H/98H) The Transfer Pad Bytes Command is used to recover from an error condition. This command is similar to the Information Transfer Command, only the information bytes consists of null data. It is used when the Target expects more data bytes than the Initiator has to send. It is also used when the Initiator receives more information than expected from the Target. When sending data to the SCSI bus, the FIFO is loaded with null bytes which are sent out to the SCSI bus. Although an actual DMA request is not made, DMA must be enabled when pad bytes are transmitted since the ESC uses Current Transfer Count Register (CTCREG) to terminate transmission. When receiving data from the SCSI bus, the device will receive the pad bytes and place them on the top of the FIFO and unload them from the bottom of the FIFO. This command terminates under the same conditions as the Information Transfer Command, but the device does not keep the ACK signal asserted during the last byte of the Message In phase. Should this command terminate prematurely due to a disconnect or a phase change, (before the Current Transfer Count Register (CTCREG) decrements to zero), the FIFO may contain residual pad bytes. Set ATN Command (Command Code 1AH) The Set ATN Command is used to drive the ATN signal active on the SCSI bus. An interrupt is not generated at The Reset ATN Command is used to deassert the ATN signal on the SCSI bus. An interrupt is not generated at the end of this command. This command is used only when interfacing with devices that do not support the Common Command Set (CCS). These older devices do not deassert their ATN signal automatically on the last byte of the Message Out phase. This device does deassert its ATN signal automatically on the last byte of the Message Out phase. Target Commands Target commands are executed by the device when it is in the Target mode. If the device is not in the Target mode and a Target command is received the device will ignore the command, generate an Invalid Command interrupt and clear the Command Register (CMDREG). A SCSI bus reset during any Target command will cause the device to abort the command sequence , flag a SCSI bus reset interrupt (if the interrupt is enabled) and disconnect from the SCSI bus. Normal or successful completion of a Target command will cause a Successful Operation interrupt to be flagged. If the ATN signal is asserted during a Target command sequence the Service Request bit is asserted in the Interrupt Status Register (INSTREG). If the ATN signal is asserted when the device is in an Idle state a Service Request interrupt will be generated, the Successful Operation bit in the Interrupt Status Register (INSTREG) will be reset and the Command Register (CMDREG) cleared. Send Message Command (Command Code 20H/A0H) The Send Message Command is used by the Target to inform the Initiator to receive a message. The SCSI bus phase lines are set to the Message In Phase and message bytes are transferred from the device FIFO to the buffer memory. Send Status Command (Command Code 21H/A1H) The Send Status Command is used by the Target to inform the Initiator to receive status information. The SCSI bus phase lines are set to the Status Phase and status bytes are transferred from the Target device to the Initiator device. Am53CF94/Am53CF96 39 AMD PRELIMINARY Send Data Command (Command Code 22H/A2H) The Send Data Command is used by the Target to inform the Initiator to receive data bytes. The SCSI bus phase lines are set to the Data-In Phase and data bytes are transferred from the Target device to the Initiator device. Disconnect Steps Command (Command Code 23H/A3H) The Disconnect Steps Command is used by the Target to disconnect from the SCSI bus. This command is executed in two steps. In the Message In phase, the Target sends two bytes of the Save Data Pointers commands. Following transmission, the Target disconnects from the SCSI bus. Successful Operation and Disconnected bits are set in the Interrupt Status Register (INSTREG) upon command completion. If ATN signal is asserted by the Initiator then Successful Operation and Service Request bits are set in the INSTREG, the Command Register (CMDREG) is cleared and Disconnect Steps Command terminates without disconnecting. and clock factor). Interrupt is not generated to the microprocessor. Receive Message Steps Command (Command Code 28H/A8H) The Receive Message Steps Command is used by the Target to request message bytes from the Initiator. The Target receives the message bytes from the Initiator while the SCSI bus is in the Message Out Phase. The Successful Operation bit is set in the Interrupt Status Register (INSTREG) upon command completion. If ATN signal is asserted by the Initiator then Successful Operation and Service Request bits are set in the INSTREG, the Command Register (CMDREG) is cleared, but if a parity error is detected, the device ignores the received message bytes until ATN signal is deasserted, the Successful Operation bit is set in the INSTREG, and the CMDREG is cleared. Receive Commands Command (Command Code 29H/A9H) The Terminate Steps Command is used by the Target to disconnect from the SCSI bus. This command is executed in three steps. While in Status phase, the Target first sends a 1 byte status message. Following the Status phase the Target moves to the Message In phase and sends another 1 byte message. Lastly, the Target disconnects from the SCSI bus. The Disconnected bit is set in the Interrupt Status Register (INSTREG) upon command completion. If ATN signal is asserted by the Initiator, then Successful Operation and Service Request bits are set in the INSTREG, an interrupt is generated and the Command Register (CMDREG) is cleared and Terminate Steps Command terminates without disconnecting. The Receive Commands Command is used by the Target to request command bytes from the Initiator. The Target receives the command bytes from the Initiator while the SCSI bus is in the Command Phase. The Successful Operation bit is set in the Interrupt Status Register (INSTREG) upon command completion. If ATN signal is asserted by the Initiator then Successful Operation and Service Request bits are set in the INSTREG, the Command Register (CMDREG) is cleared and the command terminates prematurely. If a parity error is detected, the device continues to receive command bytes until the transfer is complete. However, if the Abort on Command Data/Parity Error (ACDPE) bit in Control Register Two (CNTLREG2) bit is set, the command is terminated immediately. The Parity Error (PE) bit in the Status Register (STATREG) is set and CMDREG is cleared. Target Command Complete Steps Command (Command Code 25H/A5H) Receive Data Command (Command Code 2AH/AAH) The Target Command Complete Steps Command is used by the Target to inform the Initiator of a linked command completion. This command consists of two steps. In the first step, the Target sends one status byte to the Initiator in the Status Phase. The Target then sends one message byte to the Initiator in the Message In Phase. The Successful Operation bit is set in the Interrupt Status Register (INSTREG) upon command completion. If ATN signal is asserted by the Initiator then Successful Operation and Service Request bits are set in the INSTREG, the Command Register (CMDREG) is cleared and Target Command Complete Steps Command terminates prematurely. The Receive Data Command is used by the Target to request data bytes from the Initiator. During this command the Target receives the data bytes from the Initiator while the SCSI bus is in the Data-Out Phase. The Successful Operation bit is set in the Interrupt Status Register (INSTREG) upon command completion. If ATN signal is asserted by the Initiator then Successful Operation and Service Request bits are set in the INSTREG, the Command Register (CMDREG) is cleared and the command terminates prematurely. If a parity error is detected, the device continues to receive data bytes until the transfer is complete (Abort on Command/Data Parity Error (ACDPE) bit in Control Register Two (CNTLREG2) is reset). If the ACDPE bit is set, the command is terminated immediately. The Parity Error (PE) bit in the Status Register (STATREG) is set and CMDREG is cleared. Terminate Steps Command (Command Code 24H/A4H) Disconnect Command (Command Code 27H/A7H) The Disconnect Command is used by the Target to disconnect from the SCSI bus. All SCSI bus signals except RSTC are released and the device returns to the Disconnected state. The RSTC signal is driven active for about 25 micro seconds (depending on clock frequency 40 Am53CF94/Am53CF96 PRELIMINARY Receive Command Steps Command (Command Code 2BH/ABH) The Receive Command Steps Command is used by the Target to request command information bytes from the Initiator. During this command the Target receives the command information bytes from the Initiator while the SCSI bus is in the Command Phase. The Target device determines the command block length from the first byte. If an unknown length is received, the Start Transfer Count Register (STCREG) is loaded with five and the Group Code Valid (GCV) bit in the Status Register (STATREG) is reset. If a valid length is received, the STCREG is loaded with the appropriate value and the GCV bit in the STATREG is set. If ATN signal is asserted by the Initiator then the Service Request bit is set in the Interrupt Status Register (INSTREG), and the Command Register (CMDREG) is cleared. If a parity error is detected, the command is terminated prematurely and the CMDREG is cleared. DMA Stop Command (Command Code 04H/84H) The DMA Stop Command is used by the Target to allow the microprocessor to discontinue data transfers due to a lack of activity on the DMA channel. This command is executed from the top of the command queue. If there is a queued command waiting execution, it will be overwritten and the Illegal Operation Error (IOE) bit in the Status Register (STATREG) will be set. This command is cleared from the command queue once it is decoded. Caution must be exercised when using this command. The following conditions must be true: ■ The DMA Stop Command can be used only during DMA Target Send Data Command or DMA Target Receive Data Command execution. In both cases the DMA controller and the ESC must be in the idle state. ■ During a DMA Target Send Data Command: the FIFO is empty or the Current FIFO (CF 4:0) bits in the Current FIFO/Internal State Register (CFISREG) are zero. ■ During a DMA Synchronous Target Receive Data Command: the Current Transfer Count Register (CTCREG) is zero, (indicated by the Count to Zero (CTZ) bit of the Status Register (STATREG)), or the Synchronous Offset Register (SOFREG) has reached its maximum value (indicated by the Synchronous Offset Flag (SOF) bit of the Internal State Register (ISREG)). ■ During a DMA Asynchronous Target Receive Data Command: the FIFO is full (CF 4:0 set to ‘1’ in the Current FIFO/Internal State Register (CFISREG)), or Current Transfer Count Register (CTCREG) is zero (indicated by the Count to Zero (CTZ) bit of the Status Register (STATREG)). When conditions are satisfied, the ESC halts, asserts DREQ, and then waits for the DMA channel. If the ESC halted during Synchronous Transfer, the ACK pulses not received from the SCSI bus remain outstanding. AMD Upon receipt of the DMA Stop Command, the ESC resets the DMA interface and DREQ pin, then terminates the command in progress. Ongoing SCSI sequences are completed as follows: ■ Synch Data Send: completes when CTZ bit in Status Register is ‘1’. ■ Synch Data Receive: when all outstanding ACKs received, command completes ■ Asynchronous Data Send: immediately completes ■ Asynchronous Data Receive: immediately completes. Remaining data in FIFO should be removed by microprocessor. Access FIFO Command (Command Code 05H/85H) The host may issue the Access FIFO command following a Target Abort DMA or abort due to parity error. This command will give the DMA controller access to the data remaining in the FIFO. The following shall be true depending on the status of the DAE bit in CNTRLREG2: DAE=1: DREQ will be asserted if the FIFO has two or more bytes of data, and will deassert if the FIFO contains one or zero bytes of data. DAE=0: DREQ will be asserted if the FIFO is not empty, and will deassert when the FIFO is empty. While DREQ is asserted, the DMA controller may read the data. This command is supported only in normal DMA mode. Idle State Commands The Idle State Commands can be issued to the device only when the device is disconnected from the SCSI bus. If these commands are issued to the device when it is logically connected to the SCSI bus, the commands are ignored, and the device will generate an Invalid Command interrupt and clear the Command Register (CMDREG). Reselect Steps Command (Command Code 40H/C0H) The Reselect Steps Command is used by the Target device to reselect an Initiator device. When this command is issued the device arbitrates for the control of the SCSI bus. If the device wins arbitration, it Reselects the Initiator device and transfers a single byte identify message. Before issuing this command the SCSI Timeout Register (STIMREG), the Control Register One (CNTLREG1) and the SCSI Destination ID Register (SDIDREG) must be set to the proper values. If DMA is enabled, the Start Transfer Count Register (STCREG) must be set to one. If DMA is not enabled, the single byte identify message must be loaded into the FIFO before issuing this command. This command will be terminated early if the SCSI Timeout Register times out, or if sequence terminates normally, a Successful Operation interrupt will be issued. This command also resets the Internal State Register (ISREG). Am53CF94/Am53CF96 41 AMD PRELIMINARY Select without ATN Steps Command (Command Code 41H/C1H) The Select without ATN Steps Command is used by the Initiator to select a Target. When this command is issued the device arbitrates for the control of the SCSI bus. When the device wins arbitration, it selects the Target device and transfers the Command Descriptor Block (CDB). Before issuing this command the SCSI Timeout Register (STIMREG), the Control Register One (CNTLREG1) and the SCSI Destination ID Register (SDIDREG) must be set to the proper values. If DMA is enabled, the Start Transfer Count Register (STCREG) must be set to the total length of the command. If DMA is not enabled, the data must be loaded into the FIFO before issuing this command. This command will be terminated early if the SCSI Timeout Register times out or if the Target does not go to the Command Phase following the Selection Phase or if the Target exits the Command Phase prematurely. A Successful Operation interrupt will be generated following normal command execution. Select with ATN Steps Command (Command Code 42H/C2H) The Select with ATN Steps Command is used by the Initiator to select a Target. When this command is issued the device arbitrates for the control of the SCSI bus. When the device wins arbitration, it selects the Target device with the ATN signal asserted and transfers the Command Descriptor Block (CDB) and a one byte message. Before issuing this command the SCSI Timeout Register (STIMREG), the Control Register One (CNTLREG1) and the SCSI Destination ID Register (SDIDREG) must be set to the proper values. If DMA is enabled, the Start Transfer Count Register (STCREG) must be set to the total length of the command and message. If DMA is not enabled, the data must be loaded into the FIFO before issuing this command. This command will be terminated early in the following situations: ■ The SCSI Timeout Register times out ■ The Target does not go to the Message Out Phase following the Selection Phase ■ The Target exits the Message Phase early ■ The Target does not go to the Command Phase following the Message Out Phase ■ The Target exits the Command Phase early A Successful Operation/Service Request interrupt is generated when this command is completed successfully. Select with ATN and Stop Steps Command (Command Code 43H/C3H) The Select with ATN and Stop Steps Command is used by the Initiator to send messages with lengths other than 1 or 3 bytes. When this command is issued, the device executes the Selection process, transfers the first message byte, then STOPS the sequence. ATN is not deasserted at this time, allowing the Initiator to send additional message bytes after the ID message. To send these additional bytes, the Initiator must write the trans42 fer counter with the number of bytes which will follow, then issue an information transfer command. (Note: the Target is still in the message out phase when this command is issued). ATN will remain asserted until the transfer counter decrements to zero. The SCSI Timeout Register (STIMREG), Control Register One (CNTLREG1), and the SCSI Destination ID Register (SDIDREG) must be set to the proper values before beginning the Initiator issues this command. This command will be terminated early if the STIMREG times out or if the Target does not go to the Message Out Phase following the Selection Phase. Enable Selection/Reselection Command (Command Code 44H/C4H) The Enable Selection/Reselection Command is used by the Target to respond to a bus-initiated Selection or Reselection. Upon disconnecting from the bus the Selection/Reselection circuit is automatically disabled by device. This circuit has to be enabled for the device to respond to subsequent reselection attempts and the Enable Selection/Reselection Command is issued to do that. This command is normally issued within 250 ms (select/reselect timeout) after the device disconnects from the bus. If DMA is enabled the device loads the received data to the buffer memory, but if the DMA is disabled, the received data stays in the FIFO. Disable Selection/Reselection Command (Command Code 45H/C5H) The Disable Selection/Reselection Command is used by the Target to disable response to a bus-initiated Reselection. When this command is issued before a bus initiated Selection or Reselection is initiated, it resets the internal mode bits previously set by the Enable Selection/Reselection Command. The device also generates a function complete interrupt to the processor. If however, this command is issued after a bus initiated Selection/Reselection has already begun the command is ignored since the Command Register (CMDREG) is held reset and all incoming commands are ignored. The device generates a selected or reselected interrupt when the sequence is complete. Select with ATN3 Steps Command (Command Code 46H/C6H) The Select with ATN3 Steps Command is used by the Initiator to select a Target. This command is similar to the Select with ATN Steps Command, except that it sends exactly three message bytes. When this command is issued the ESC arbitrates for the control of the SCSI bus. When the device wins arbitration, it selects the Target device with the ATN signal asserted and transfers the Command Descriptor Block (CDB) and three message bytes. Before issuing this command the SCSI Timeout Register (STIMREG), the Control Register One (CNTLREG1) and the SCSI Destination ID Register (SDIDREG) must be set to the proper values. If DMA is enabled, the Start Transfer Count Register (STCREG) must be set to the total length of the command. If DMA is not enabled, the data must be loaded Am53CF94/Am53CF96 PRELIMINARY into the FIFO before issuing this command. This command will be terminated early in the following situations: ■ The SCSI Timeout Register times out ■ The Target does not go to the Message Out Phase following the Selection Phase ■ The Target removes Command Phase early ■ The Target does not go to the Command Phase following the Message Out Phase ■ The Target exits the Command Out Phase early A Successful Operation/Service Request interrupt is generated when this command is executed successfully. AMD A No Operation Command in the DMA mode may be used to verify the contents of the Start Transfer Count Register (STCREG). After the STCREG is loaded with the transfer count and a DMA No Operation Command is issued, reading the Current Transfer Count Register (CTCREG) will give the transfer count value. Clear FIFO Command (Command Code 01H/81H) The Clear FIFO Command is used to initialize the FIFO to the empty condition. The Current FIFO Register (CFISREG) reflects the empty FIFO status and the bottom of the FIFO is set to zero. No interrupt is generated at the end of this command. Reset Device Command (Command Code 02H/82H) Reselect with ATN3 Steps Command (Command Code 47H/C7H) The Queue Tag feature of the Select with ATN3 command has been implemented in the Reselection command. Therefore, a Target reselecting an Initiator can use the QTAG feature of ATN3. Following Reselection, one message byte and 2 bytes QTAG will be sent. The three message bytes must be loaded into the FIFO before this command is issued if DMA is not enabled. The Reset Device Command immediately stops any device operation and resets all the functions of the device. It returns the device to the disconnected state and it also generates a hard reset. The Reset Device Command remains on the top of the Command Register FIFO holding the device in the reset state until the No Operation Command is loaded. The No Operation command serves to enable the Command Register. General Commands Reset SCSI Bus Command (Command Code 03H/83H) No Operation Command (Command Code 00H/80H) The Reset SCSI Bus Command forces the RSTC signal active for a period of 25 µs, and drives the chip to the Disconnected state. An interrupt is not generated upon command completion, however, if bit 6 is not disabled in Control Register One (CNTLREG1), a SCSI reset interrupt will be issued. The No Operation Command administers no operation, therefore an interrupt is not generated upon completion. This command is issued following the Reset Device Command to clear the Command Register (CMDREG). Am53CF94/Am53CF96 43 AMD PRELIMINARY ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature . . . . . . . . . . . –65°C to +150°C Ambient Temperature Under Bias . . . . . . . . . . . . . . . . . . . –55°C to +125°C VDD . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +7.0 V DC Voltage Applied to Any Pin . . . . . . . . . . . . . . . . . –0.5 to (VDD + 0.5) V Input Static Discharge Protection . . . . 4K V pin-to-pin (Human body model: 100 pF at 1.5K Ω) Commercial Devices Ambient Temperature (TA) . . . . . . . 0°C to +70°C Supply Voltage (VDD) . . . . . . . . . . . 4.5 V to 5.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. 44 Am53CF94/Am53CF96 PRELIMINARY AMD DC OPERATING CHARACTERISTICS Parameter Symbol Parameter Description Pin Names Test Conditions Min Max Unit IDDS Static Supply Current VDD MAX 4.0 mA IDDD Dynamic Supply Current VDD MAX 30 mA ILU C Latch Up Current Capacitance All I/O All Pins – 100 +100 10 mA pF VLU ≤ 10 V SCSI Pins VIH Input High Voltage All SCSI Inputs 2.0 VDD + 0.5 V VIL Input Low Voltage All SCSI Inputs VSS – 0.5 0.8 V VIHST Input Hysterisis All SCSI Inputs 4.5 V < VDD < 5.5 V 300 VOH Output High Voltage SD 7–0, SD P IOH = – 2 mA 2.4 VDD V IOL= 4 mA VSOL1 SCSI Output Low Voltage SD 7–0, SD P VSOL2 SCSI Output Low Voltage SDC 7–0, SDC P, IOL= 48 mA MSG, C/D, I/O, ATN, RSTC, SELC, BSYC, ACKC and REQC IIL Input Low Leakage IIH IOZ VSS 0.4 V VSS 0.5 V 0.0 V < VIN < 2.7 V –10 +10 µA Input High Leakage 2.7 V < VIN < VDD –10 +10 µA High Impedance Leakage 0 V < VOUT < VDD –10 +10 µA 2.0 VDD + 0.5 V VSS – 0.5 0.8 V 2.4 VDD V VSS 0.4 V Bidirectional Pins VIH Input High Voltage VIL Input Low Voltage VOH Output High Voltage VOL mV Output Low Voltage DMA 15–0 and DMAP 1–0 AD 7–0 IOH = – 2 mA IOH = – 1 mA DMA 15–0 and DMAP 1–0 AD 7–0 IOL= 4 mA IOL = 2 mA IIL Input Low Leakage DMA 15–0, DMAP 1–0 and AD 7–0 0 V < VIN < VIL – 10 +10 µA IIH Input High Leakage DMA 15–0, DMAP 1–0 and AD 7–0 VIH < VIN < VDD –10 +10 µA 0 V < VOUT < VDD –10 +10 µA High Impedance Leakage IOZ Output Pins VOH Output High Voltage DREQ, ISEL, TSEL, REQC*, ACKC* IOH = – 2 mA 2.4 VDD V VOL Output Low Voltage DREQ, ISEL, TSEL, REQC*, ACKC* IOL= 4 mA VSS 0.4 V IOZ High Impedance Leakage 0 V < VOUT < VDD –10 +10 µA *REQC and ACKC in Differential Mode only. Am53CF94/Am53CF96 45 AMD PRELIMINARY DC OPERATING CHARACTERISTICS (continued) Parameter Symbol Parameter Description Pin Names Test Conditions Min Max Unit Input Pins VIH Input High Voltage A 3-0, CS, RD, WR, DMAWR, CLK, BUSMD 1–0, DACK, RESET, and DFMODE 2.0 VDD + 0.5 V VIL Input Low Voltage A 3-0, CS, RD, WR, DMAWR, CLK, BUSMD 1–0, DACK, RESET, and DFMODE VSS +0.5 0.8 V IIL Input Low Voltage A 3-0, CS, RD, WR, DMAWR, CLK, BUSMD 1–0, DACK, RESET, and DFMODE 0 < VIN < VIL –10 +10 µA IIH Input High Voltage A 3-0, CS, RD, WR, DMAWR, CLK, BUSMD 1–0, DACK, RESET, and DFMODE VIH < VIN < VDD –10 +10 µA SWITCHING TEST CIRCUIT IOL From Output Under Test VT CL 0V IOH 17348B-35 SWITCHING TEST WAVEFORMS 3.0 V All Inputs 1.5 V 0.0 V 2.3 V 0.8 V VOH 2.0 V VOL True Data Outputs AD 7–0, DMA 15–0, DMAP1–0 VOH –0.3 V 2.0 V VOL +0.3 V Hi-Z Outputs AD 7–0, DMA 15–0, DMAP1–0 2.0 V All Open Drain Outputs and INT 0.8 V VOL SD 7–0, SD P, DREQ, ISEL, TSEL 46 Am53CF94/Am53CF96 VOH 2.3 V 0.8 V VOL 17348B-36 PRELIMINARY AMD KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Must be Steady Will be Steady May Change from H to L Will be Changing from H to L May Change from L to H Will be Changing from L to H Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is HighImpedance “Off” State KS000010 Am53CF94/Am53CF96 47 AMD PRELIMINARY CLK 4 1 2 3 3A Clock Input 17348B-37 FastClk Disabled (Control Register Three (0CH) bit 3=0) No. Parameter Symbol 1 2 tPWL1 tCP 3 4 tL 1 tPWH Parameter Description Min Max Unit Clock Pulse Width Low Clock period (1 ÷ Clock Frequency) 14.58 40 0.65 • tCP 100 ns ns Synchronization latency Clock Pulse Width High 54.58 14.58 tPWL + tCP 0.65 • tCP ns ns Note: Clock Frequency Range for Fast Clk disabled. = 10 MHz to 25 MHz for Asynchronous transmission = 12 MHz to 25 MHz for Synchronous transmission Test Conditions 1 For Synchronous data transmissions, the following conditions must be true: 2tCP + tPWL > 97.92 ns 2tCP + tPWH > 97.92 ns FastClk Enabled (Control Register Three (0CH) bit 3=1) No. Parameter Symbol 1 2 tPWL tCP 3A 4 tL tPWH Parameter Description Test Conditions Min Max Unit Clock Pulse Width Low Clock period (1 ÷ Clock Frequency) 0.4 • tCP 25 0.6 • tCP 50 ns ns Synchronization latency Clock Pulse Width High 54.58 0.4 • tCP 2 • tCP 0.6 • tCP ns ns Note: Clock Frequency Range for Fast Clk enabled. = 20 MHz to 40 MHz for Asynchronous Transmission = 20 MHz to 40 MHz for Synchronous Transmission 48 Am53CF94/Am53CF96 PRELIMINARY AMD RESET 5 17348B-38 Reset Input No. Parameter Symbol 5 tPWH Parameter Description Test Conditions Reset Pulse Width High Min Max 500 Unit ns Note: There is a one-to-one relationship between every AMD and Emulex Parameter (refer to Appendix B). 7 INT RD 6 8 9 17348B-39 Interrupt Output No. Parameter Symbol 6 7 8 tS tPD tPWL 9 tPD Parameter Description Min Max Unit INT to RD Set Up Time RD to INT Delay RD Pulse Width Low 0 0 50 100 ns ns ns RD tL to INT Test Conditions Delay ns Note: There is a one-to-one relationship between every AMD and Emulex Parameter (refer to Appendix B). Am53CF94/Am53CF96 49 AMD PRELIMINARY A 3–0 10 11 20 19 CS 16 RD 12 14 15 22 17 13 21 18 AD 7–0 DMA 7–0 DMAP 0 17348B-40 Register Read with Non-Multiplexed Address Data Bus A 3–0 10 11 19 26 CS 27 23 24 28 WR 31 30 25 29 AD 7–0 DMA 7–0 DMAP 0 17348B-41 Register Write with Non-Multiplexed Address Data Bus 50 Am53CF94/Am53CF96 PRELIMINARY AMD Register Read/Write with Non-Multiplexed Address Data Bus No. Parameter Symbol 10 tS Address to CS Set Up Time 0 ns 11 tH Address to CS Hold Time 30 ns 12 tS CS Set Up Time 0 ns 13 14 tPD tPWL CS to Data Valid Delay RD Pulse Width Low 15 tPD RD 16 17 18 19 tH tZ tH tPWH RD to CS Hold Time RD to Data High Impedance RD to Data Hold Time CS Pulse Width High 20 21 22 tS tH tZ 23 24 tS tPWL 25 Parameter Description RD CS CS to RD Test Conditions Min Unit 65 ns ns 30 ns 30 to Data Valid Delay to CS Set Up Time to Data Hold Time to Data High Impedance Max 0 30 2 30 40 2 30 ns ns ns ns ns ns ns CS to WR Set Up Time WR Pulse Width Low 0 30 ns ns tS Data to WR 15 ns 26 tH WR 0 ns 27 28 tS tPWH WR to CS Set Up Time WR Pulse Width High 30 40 ns ns 29 30 tH tH Data to WR Hold Time CS to Data Hold 0 30 ns ns 31 tS Data to CS 10 ns to CS Set Up Time Hold Time Setup Time Note: There is a one-to-one relationship between every AMD and Emulex Parameter (refer to Appendix B). Am53CF94/Am53CF96 51 AMD PRELIMINARY 32 ALE 33 34 35 AD 7–0 Address Address Data 36 Data 40 46 47 43 38 CS 37 39 41 42 RD 17348B-42 Register Read with Muliplexed Address Data Bus 32 ALE 33 34 51 35 AD 7–0 Address Data Address Data 54 57 52 43 50 CS 48 49 53 WR 17348B-43 Register Write with Multiplexed Address Data Bus 52 Am53CF94/Am53CF96 PRELIMINARY AMD Register Read/Write with Multiplexed Address Data Bus No. Parameter Symbol 32 tPWH 33 Parameter Description Test Conditions Min Max Unit ALE Pulse Width High 20 ns tS Address to ALE Set Up Time 10 ns Hold Time 10 ns Set Up Time 10 ns 34 tH Address to ALE 35 tS ALE to CS 36 tPD CS to Data Valid Delay 37 tS CS to RD 38 39 40 tPD tPWL tH 41 42 tH tZ RD RD 43 44 45 tS CS to ALE Set Up Time PARAMETER DOES NOT EXIST PARAMETER DOES NOT EXIST 50 ns 46 47 tPD tZ CS CS 2 ns ns 48 49 tS tPWL CS to WR Set Up Time WR Pulse Width Low 0 30 ns ns 50 tS Data to WR 15 ns 51 tS WR 50 ns 52 tH Data to WR Hold Time 0 ns 53 tH WR Hold Time 0 ns 54 55 56 57 tH CS to Data Hold Time PARAMETER DOES NOT EXIST PARAMETER DOES NOT EXIST Data Setup to CS 30 ns 10 ns tS Set Up Time RD to Data Valid Delay RD Pulse Width Low RD to Data Hold Time to CS Hold Time to Data High Impedance to Data Hold Time to Data High Impedance to ALE to CS Set Up Time Set Up Time 65 ns 30 ns ns ns 0 ns 30 2 0 30 30 ns ns Note: There is a one-to-one relationship between every AMD and Emulex Parameter (refer to Appendix B). Am53CF94/Am53CF96 53 AMD PRELIMINARY DREQ 58 62 63 59 DACK 60 64 65 66 61 DMA 15–0 DMAP 1–0 17348B-44 DMA Read without Byte Control DREQ 58 62 59 63 DACK 64 60 68 69 71 DMAWR 74 75 DMA 15–0 DMAP 1–0 73 17348B-45 DMA Write without Byte Control 54 72 70 Am53CF94/Am53CF96 PRELIMINARY AMD DMA Read/Write without Byte Control No. Parameter Symbol 58 tPD DACK 59 60 tP tPWL DACK to DACK period DACK Pulse Width Low 61 tPD DACK to Data Valid Delay 30 ns 62 tPD DACK to DREQ 30 ns 63 64 65 66 67 tP tPWH tZ tH DACK to DACK period DACK Pulse Width High DACK to Data High Impedance DACK to Data Hold Time PARAMETER DOES NOT EXIST 68 69 tS tPWL 70 tS 71 72 tH tPWH 73 74 75 Parameter Description to DREQ Test Conditions Min Valid Delay Max Unit 30 ns 95 45 Valid Delay ns ns 2 ns ns ns ns DACK to DMAWR Set Up Time DMAWR Pulse Width Low 0 30 ns ns Data to DMAWR 15 ns DMAWR to DACK Hold Time DMAWR Pulse Width High 0 25 ns ns tH Data to DMAWR Hold Time 0 ns tS tH Data to DACK Set Up Time DACK to Data Hold Time 10 10 ns ns Set Up Time tL+25 12 25 Note: There is a one-to-one relationship between every AMD and Emulex Parameter (refer to Appendix B). Am53CF94/Am53CF96 55 AMD PRELIMINARY DREQ 76 87 77 88 DACK 78 89 AS 0 BHE 80 79 81 83 84 DMARD 92 82 85 86 93 91 DMA 15–0 DMAP 1–0 17348B-46 DMA Read with Byte Control DREQ 76 87 77 88 DACK 78 89 AS 0 BHE 99 95 94 96 98 DMAWR 103 102 DMA 15–0 DMAP 1–0 100 101 17348B-47 DMA Write with Byte Control 56 97 Am53CF94/Am53CF96 PRELIMINARY AMD DMA Read/Write with Byte Control No. Parameter Symbol 76 tPD DACK 77 78 tP tPWL DACK to DACK period DACK Pulse Width Low 95 45 ns ns 79 tS DACK 0 ns 80 81 tS tPWL BHE, AS0 to DMARD Set Up Time DMARD Pulse Width Low 20 35 ns ns 82 tPD DMARD 83 tH BHE, AS0 to DMARD 84 85 86 tH tZ tH DMARD DMARD DMARD 87 tPD DACK 88 89 90 tP tPWH DACK to DACK period DACK Pulse Width High PARAMETER DOES NOT EXIST 91 92 tPD tH DACK DACK to Data Valid Delay to Data Hold Time 93 tz DACK to Data High Impedance 94 tS DACK to DMAWR 95 96 tS tPWL 97 Parameter Description to DREQ Test Conditions Min Valid Delay to DMARD Set Up Time to Data Valid Delay Hold Time to DACK Hold Time to Data High Impedance to Data Hold Time to DREQ Unit 30 ns 35 20 ns ns 0 35 ns ns ns 30 ns 2 Valid Delay Set Up Time Max tL + 25 12 ns ns 30 ns ns 25 ns 2 0 ns BHE, AS0 to DMAWR Set Up Time DMAWR Pulse Width Low 20 30 ns ns tS Data to DMAWR 15 ns 98 tH BHE, AS0 to DMAWR Hold Time 20 ns 99 100 tH tPWH DMAWR to DACK Hold Time DMAWR Pulse Width High 0 25 ns ns 101 102 tH tH Data to DMAWR Hold Time DACK to Data Hold Time 0 10 ns ns 103 tS Data to DACK 10 ns Set Up Time Set Up Time Note: There is a one-to-one relationship between every AMD and Emulex Parameter (refer to Appendix B). Am53CF94/Am53CF96 57 AMD PRELIMINARY DREQ 115 116 104 105 DACK 112 109 107 RD 106 DMA 15–0 DMAP 1–0 119 118 113 114 110 108 117 17348B-48 Burst DMA Read without Byte Control—Modes 0 and 1 DREQ 104 115 116 105 DACK 121 126 124 DMAWR 120 122 125 123 DMA 15–0 DMAP 1–0 17348B-49 Burst DMA Write without Byte Control—Modes 0 and 1 58 Am53CF94/Am53CF96 PRELIMINARY AMD Burst DMA Read/Write Mode 0, 1 No. Parameter Symbol 104 105 tPD tPWL 106 107 108 109 110 111 112 113 114 Parameter Description Test Conditions Min Max Unit 30 DACK to DREQ Valid Delay DACK Pulse Width Low 70 ns ns tS DACK 0 ns tP RD 0 ns tPD tPD tZ tH RD to Data Valid Delay RD Pulse Width High RD Pulse Width Low PARAMETER DOES NOT EXIST RD to DREQ Valid Delay RD to Data High Impedance RD to Data Hold Time 115 116 117 tPD tPWH tPD DACK to DREQ Valid Delay DACK Pulse Width High DACK to Data Valid Delay 60 2 tPWH tPWL to RD Set Up Time to DACK Hold Time 55 ns ns ns 90 45 ns ns ns 30 ns ns ns 60 70 2 35 118 tH DACK to Data Hold Time 119 tZ DACK to Data High Impedance 120 121 122 tS tPWH tPWL DACK to DMAWR Set Up Time DMAWR Pulse Width High DMAWR Pulse Width Low 0 60 70 ns ns ns 123 tS Data to DMAWR 15 ns 124 tPD DMAWR 125 tH Data to DMAWR 126 tH DMAWR Set Up Time to DREQ Valid Delay Hold Time to DACK Hold Time ns 25 90 ns ns 0 ns 0 ns Note: There is a one-to-one relationship between every AMD and Emulex Parameter (refer to Appendix B). Am53CF94/Am53CF96 59 AMD PRELIMINARY DREQ 138 127 128 139 DACK 140 AS 0 BHE 129 134 132 135 DMARD 130 133 136 137 131 142 DMA 15–0 DMAP 1–0 144 143 17348B-50 Burst DMA Read with Byte Control—Mode 2 DREQ 127 138 139 128 DACK AS 0 BHE 146 149 147 150 153 DMAWR 145 148 151 152 DMA 15–0 DMAP 1–0 17348B-51 Burst DMA Write with Byte Control—Mode 2 60 Am53CF94/Am53CF96 PRELIMINARY Burst DMA–Mode 2 Parameter No. Symbol Parameter Description Test Conditions AMD Min Max Unit 30 DACK to DREQ Valid Delay DACK Pulse Width Low 70 ns ns tS BHE, AS0 to DMARD 20 ns 130 tS DACK 0 ns 131 132 133 tPD tPWH tPWL 134 135 136 137 tH tPD tZ tH 138 139 140 141 tPD tPWH tH 142 143 144 tPD tH tZ DACK DACK DACK to Data Valid Delay to Data Hold Time to Data High Impendance 2 145 tS DACK to DMAWR 0 ns 146 147 148 tS tPWH tPWL BHE, AS0 to DMAWR Set Up Time DMAWR Pulse Width High DMAWR Pulse Width Low 20 60 70 ns ns ns 149 tH BHE, AS0 to DMAWR Hold Time 20 ns 150 tPD DMAWR Valid Delay 151 tH Data to DMAWR Hold Time 0 152 tS Data to DMAWR Set Up Time 15 ns 153 tH DMAWR 0 ns 127 128 tPD tPWL 129 to DMARD Set Up Time Set Up Time DMARD to Data Valid Delay DMARD Pulse Width High DMARD Pulse Width Low BHE, AS0 to DMARD Hold Time DMARD to DREQ Valid Delay DMARD to Data High Impedance DMARD to Data Hold Time DACK to DREQ Valid Delay DACK Pulse Width High DMARD to DACK Hold Time PARAMETER DOES NOT EXIST to DREQ to DACK Set Up Time Hold Time 55 60 70 20 90 45 2 ns ns ns ns ns ns ns 30 ns ns ns 35 ns ns ns 60 0 25 90 ns ns Note: There is a one-to-one relationship between every AMD and Emulex Parameter (refer to Appendix B). Am53CF94/Am53CF96 61 AMD PRELIMINARY DREQ 154 157 158 DACK 159 160 155 156 DMA 15–0 DMAP 1–0 17348B-52 Burst DMA Read without Byte Control—Mode 3 DREQ 154 157 168 158 DACK 155 162 165 166 DMAWR/ 163 167 164 DMA 15–0 DMAP 1–0 17348B-53 Burst DMA Write without Byte Control—Mode 3 62 Am53CF94/Am53CF96 PRELIMINARY AMD Burst DMA Mode 3 No. Parameter Symbol Parameter Description 154 155 tPD tPWL DACK to DREQ Valid Delay DACK Pulse Width Low 156 tPD DACK 157 158 159 160 161 tPD DACK to DREQ Valid Delay DACK Pulse Width High DACK to Data High Impedance DACK to Data Hold Time PARAMETER DOES NOT EXIST tPWH tZ tH tS Test Conditions Min Max Unit 30 ns ns 70 to Data Valid Delay 35 ns 30 2 ns ns ns ns DACK to DMAWR Set Up Time DMAWR Pulse Width Low 0 70 ns ns 15 ns 60 25 162 163 tPWL 164 tS Data to DMAWR 165 166 tH tPWH DMAWR to DACK Hold Time DMAWR Pulse Width High 0 60 ns ns 167 tH Data to DMAWR 0 ns 168 tPD DACK Set Up Time Hold Time to DREQ Valid Delay 90 ns Note: There is a one-to-one relationship between every AMD and Emulex Parameter (refer to Appendix B). Am53CF94/Am53CF96 63 AMD PRELIMINARY SDC 7–0 SDCP 169 170 ACKC 172 171 REQ 17348B-54 Asynchronous Initiator Send Single Ended: No. Parameter Symbol 169 tS Data to ACKC 170 tPD REQ to Data Delay 171 tPD REQ to ACKC Delay 50 ns 172 tPD REQ to ACKC Delay 50 ns Max Unit Parameter Description Test Conditions Set Up Time Min Max Unit 60 ns 5 ns Differential: No. Parameter Symbol Parameter Description Test Conditions Min 169 tS Data to ACKC 170 tPD REQ to Data Delay 171 tPD REQ to ACKC Delay 25 ns 172 tPD REQ to ACKC Delay 30 ns Set Up Time 70 ns 5 ns Note: There is a one-to-one relationship between every AMD and Emulex Parameter (refer to Appendix B). 64 Am53CF94/Am53CF96 PRELIMINARY AMD SD 7–0 SDP 176 ACKC 173 175 174 REQ 17348B-55 Asynchronous Initiator Receive Single Ended: No. Parameter Symbol 173 tPD REQ to ACKC 174 tPD REQ to ACKC 175 tS Data to REQ 176 tH REQ Parameter Description Test Conditions Max Unit Delay 50 ns Delay 50 ns Set Up Time to Data Hold Time Min 0 ns 18 ns Differential: No. Parameter Symbol 173 tPD REQ to ACKC Delay 174 tPD REQ to ACKC Delay 175 tS Data to REQ 176 tH REQ Parameter Description Test Conditions Set Up Time to Data Hold Time Min Max Unit 25 ns 30 ns 0 ns 18 ns Note: There is a one-to-one relationship between every AMD and Emulex Parameter (refer to Appendix B). Am53CF94/Am53CF96 65 AMD PRELIMINARY SD 7–0 SDP 177 178 REQC 179 180 ACK 17348B-56 Asynchronous Target Send Single Ended: No. Parameter Symbol 177 tS Data to REQC 178 tH ACK to Data Hold Time 179 tPD ACK to REQC Delay 50 ns 180 tPD ACK to REQC Delay 45 ns Max Unit Parameter Description Test Conditions Set Up Time Min Max Unit 60 ns 5 ns Differential: No. Parameter Symbol 177 tS Data to REQC 178 tH ACK to Data Hold Time 179 tPD ACK to REQC Delay 30 ns 180 tPD ACK to REQC Delay 30 ns Parameter Description Test Conditions Set Up Time Min 70 ns 5 ns Note: There is a one-to-one relationship between every AMD and Emulex Parameter (refer to Appendix B). 66 Am53CF94/Am53CF96 PRELIMINARY AMD SDC 7–0 SDCP 183 184 REQC 181 182 ACK 17348B-57 Asynchronous Target Receive Single Ended: No. Parameter Symbol 181 tPD ACK to REQC 182 tPD ACK to REQC 183 tS Data to ACK 184 tH ACK Parameter Description Test Conditions Max Unit Delay 50 ns Delay 45 ns Set Up Time to Data Hold Time Min 0 ns 18 ns Differential: No. Parameter Symbol 181 tPD ACK to REQC 182 tPD ACK to REQC 183 tS Data to ACK 184 tH ACK Parameter Description Test Conditions Max Unit Delay 30 ns Delay 30 ns Set Up Time to Data Hold Time Min 0 ns 18 ns Note: There is a one-to-one relationship between every AMD and Emulex Parameter (refer to Appendix B). Am53CF94/Am53CF96 67 AMD PRELIMINARY SDC 7–0 SDCP 185 188 187 186 REQC ACKC 17348B-58 Synchronous Initiator Target Transmit Normal SCSI: (Single Ended) No. Parameter Symbol 185 tS 186 187 188 tPWL tPWH tH Parameter Description Test Conditions ACKC or REQC to Data Set Up Time REQC or ACKC Pulse Width Low REQC or ACKC Pulse Width High ACKC or REQC to Data Hold Time Min Max Unit 55 ns 90 90 100 ns ns ns Fast SCSI: (Single Ended) No. Parameter Symbol 185 tS 186 187 188 tPWL tPWH tH Parameter Description Test Conditions ACKC or REQC to Data Set Up Time REQC or ACKC Pulse Width Low REQC or ACKC Pulse Width High ACKC or REQC to Data Hold Time Min Max Unit 25 ns 30 30 35 ns ns ns Normal SCSI: (Differential) No. Parameter Symbol 185 tS 186 187 188 tPWL tPWH tH Parameter Description Test Conditions ACKC or REQC to Data Set Up Time REQC or ACKC Pulse Width Low REQC or ACKC Pulse Width High ACKC or REQC to Data Hold Time Min Max Unit 65 ns 96 96 110 ns ns ns Fast SCSI: (Differential) No. Parameter Symbol 185 tS 186 187 188 tPWL tPWH tH Parameter Description Test Conditions ACKC or REQC to Data Set Up Time REQC or ACKC Pulse Width Low REQC or ACKC Pulse Width High ACKC or REQC to Data Hold Time Min Max Unit 35 ns 40 40 45 ns ns ns * The minimum values have a wide range since they depend on the Synchronization latency. The synchronization latency, in turn, depends on the operating frequency of the device. Note: There is a one-to-one relationship between every AMD and Emulex Parameter (refer to Appendix B). 68 Am53CF94/Am53CF96 PRELIMINARY AMD SDC 7–0 SDCP 192 191 190 189 REQ ACK 17348B-59 Synchronous Initiator Target Receive No. Parameter Symbol 189 189 190 190 191 192 tPWL tPWL tPWH tPWH tS tH Parameter Description Test Conditions REQ Pulse Width Low ACK Pulse Width Low REQ Pulse Width High ACK Pulse Width High Data to REQor ACK Set Up Time REQ or ACK to Data Hold Time Min 27 20 20 20 5 15 Max Unit ns ns ns ns ns ns Note: There is a one-to-one relationship between every AMD and Emulex Parameter (refer to Appendix B). Am53CF94/Am53CF96 69 AMD PRELIMINARY APPENDIX A Pin Connection Cross Reference for Am53CF94 Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 70 AMD DMAP0 VSS DMA8 DMA9 DMA10 DMA11 DMA12 DMA13 DMA14 DMA15 DMAP1 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SDP VDD VSS SDC0 SDC1 SDC2 SDC3 VSS SDC4 SDC5 SDC6 SDC7 SDCP VSS SELC BSYC REQC ACKC VSS MSG C/D I/O ATN Emulex DBP0 VSS DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 DBP1 SDI0N SDI1N SDI2N SDI3N SDI4N SDI5N SDI6N SDI7N SDIPN VDD VSS SDO0N SDO1N SDO2N SDO3N VSS SDO4N SDO5N SDO6N SDO7N SDOPN VSS SELON BSYON REQON ACKON VSS MSGION CDION IOION ATNION Pin# 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Am53CF94/Am53CF96 AMD RSTC VSS SEL BSY REQ ACK RST BUSMD 1 BUSMD 0 INT RESET WR RD CS ASO [A0] BHE [A1] DMARD [A2] ALE [A3] CLK VDD AD0 AD1 AD2 AD3 VSS AD4 AD5 AD6 AD7 DREQ DACK DMAWR VSS VSS DMA0 DMA1 DMA2 DMA3 DMA4 DMA5 DMA6 DMA7 Emulex RSTON VSS SELIN BSYIN REQIN ACKIN RSTIN MODE 1 MODE 0 INTN RESET WRN RDN CSN A0/SA0 A1/BHE A2/DBRDN A3/ALE CK VDD PAD0 PAD1 PAD2 PAD3 VSS PAD4 PAD5 PAD6 PAD7 DREQ DACKN DBWRN VSS VSS DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 PRELIMINARY AMD APPENDIX A Pin Connection Cross Reference for Am53CF96 Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 AMD DACK DMAWR NC ISEL VSS TSEL VSS DMA0 DMA1 DMA2 DMA3 DMA4 DMA5 DMA6 DMA7 DMAP0 VSS VSS DMA8 DMA9 DMA10 DMA11 DMA12 DMA13 DMA14 DMA15 DMAP1 NC SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SDP VDD NC VSS VSS SDC0 SDC1 SDC2 SDC3 VSS VSS SDC4 SDC5 SDC6 Emulex DACKN DBWRN NC IGS VSS TGS VSS DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DBP0 VSS VSS DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 DBP1 NC SDI0N SDI1N SDI2N SDI3N SDI4N SDI5N SDI6N SDI7N SDIPN VDD NC VSS VSS SDO0N SDO1N SDO2N SDO3N VSS VSS SDO4N SDO5N SDO6N Pin# 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Am53CF94/Am53CF96 AMD SDC 7 SDC P NC VSS VSS SELC BSYC REQC ACKC VSS VSS MSG C/D I/O ATN RSTC VSS VSS SEL BSY REQ ACK RST BUSMD 1 BUSMD 0 INT RESET NC WR RD CS ASO [A0] BHE [A1] DMARD [A2] ALE [A3] CLK DFMODE VDD NC AD0 AD1 AD2 AD3 VSS VSS AD4 AD5 AD6 AD7 DREQ Emulex SDO7N SDOPN NC VSS VSS SELON BSYON REQON ACKON VSS VSS MSGION CDION IOION ATNION RSTON VSS VSS SELIN BSYIN REQIN ACKIN RSTIN MODE 1 MODE 0 INTN RESET NC WRN RDN CSN A0/SA0 A1/BHE A2/DBRDN A3/ALE CK DIFFMN VDD NC PAD0 PAD1 PAD2 PAD3 VSS VSS PAD4 PAD5 PAD6 PAD7 DREQ 71 AMD PRELIMINARY APPENDIX B Emulex to AMD Timing Parameters Cross Reference Emulex Parameter # AMD Parameter # Clock Input, Reset Input, Interrupt Output: 1 2 3 4 5 6 2 4 1 5 7 9 Register Interface Timing: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 72 10 11 33 34 32 35 43 19 12, 37 14, 39 16, 41 20 13, 36 15, 38 21, 46 (min) 22, 47 (max) 18, 40 (min) 17, 42 (max) 23, 48 24, 49 26, 53 27 28 51 25, 50 29, 52 31, 57 30, 54 Emulex Parameter # AMD Parameter # DMA Interface Timing: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 58, 76 62, 87 64, 89 60, 78 59, 77 63, 88 80 83 79 81 84 None 61, 91 82 66, 92 (min) 65, 93 (max) 86 (min) 85 (max) 95 98 68, 94 69, 96 71, 99 72, 100 70, 97 73,101 74, 103 75, 102 Alternate DMA Interface Timing: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 104, 127, 154 115, 138, 157 116, 139, 158 105, 128, 155 129 134 106, 130 110, 133 107, 140 112, 135 109, 132 None 117, 142, 156 108, 131 Am53CF94/Am53CF96 Emulex Parameter # AMD Parameter # Alternate DMA Interface Timing: (Continued) 15 16 17 18 19 20 21 22 23 24 25 118, 143, 160 (min) 119, 144, 159 (max) 114, 137 (min) 113, 136 (max) 146 149 120, 145, 162 122, 148, 163 126, 153, 165 124, 150, 168 121, 147, 166 123, 152, 164 125, 151, 167 Asynchronous Timing: 1 2 3 4 5 (REQON) 5 (ACKON) 6 (REQIN) 6 (ACKIN) 7 (REQIN) 7 (ACKIN) 8 (REQIN) 8 (ACKIN) 179, 181 180, 182 171, 173 172, 174 177 169 170 178 175 183 176 184 Synchronous Timing: 1 2 3 4 5 6 7 8 9 10 186 187 185 188 189 190 189 190 191 192 PRELIMINARY AMD PHYSICAL DIMENSIONS* PL 084 Plastic Leaded Chip Carrier (measured in inches) .042 .048 .020 MIN .050 REF .042 .056 .025 R .045 .013 .021 .026 .032 1.185 1.150 1.195 1.156 1.000 1.090 REF 1.130 1.150 1.156 1.185 1.195 TOP VIEW .007 .013 .165 .180 .090 .130 09980B CG08 PL 084 8/14/92 c dc SIDE VIEW * For reference only. BSC is an ANSI standard for Basic Space Centering. Am53CF94/Am53CF96 73 AMD PRELIMINARY PHYSICAL DIMENSIONS* PQR100 Plastic Quad Flatpack Trimmed and Formed (measured in millimeters) PQJ 100 (Plastic Quad Flat Pack; Trimmed and Formed) (measured in millimeters) 17.10 13.90 12.35 REF 17.30 14.10 0.22 0.38 18.85 REF 19.90 20.10 23.00 23.40 0.65 REF Pin 1 I.D. TOP VIEW 2.60 3.35 MAX 3.00 0.70 0.90 0.25 MIN SIDE VIEW * For reference only. BSC is an ANSI standard for Basic Space Centering. 74 Am53CF94/Am53CF96 15590D BX 45 9/6/91 SG PRELIMINARY AMD PHYSICAL DIMENSIONS* PQR100 Plastic Quad Flatpack with Molded Carrier Ring (measured in millimeters) 35.87 36.13 31.37 35.50 35.90 31.63 25.15 25.20 BSC 25.25 27.87 28.13 22.15 13.80 22.25 14.10 50 30 35.50 27.87 22.15 35.90 28.13 22.25 35.87 31.37 25.15 19.80 36.13 31.63 25.25 20.10 Pin 1 I.D. 80 100 0.22 0.38 TOP VIEW .65 NOM .45 Typ .65 Pitch 2.00 4.80 1.80 .65 Typ SIDE VIEW CB 48 6/25/92 SG * For reference only. Not drawn to scale. BSC is an ANSI standard for Basic Space Centering. Am53CF94/Am53CF96 75 AMD PRELIMINARY Trademarks Copyright 1993 Advanced Micro Devices. All rights reserved. AMD and Am386 are registered trademarks of Advanced Micro Devices, Inc. GLITCH EATER is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. 76 Am53CF94/Am53CF96