CY15B101N 1-Mbit (64K × 16) Automotive F-RAM Memory 1-Mbit (64K × 16) Automotive F-RAM Memory Features ■ 1-Mbit ferroelectric random access memory (F-RAM™) logically organized as 64K × 16 ❐ Configurable as 128K × 8 using UB and LB 14 ❐ High-endurance 100 trillion (10 ) read/writes ❐ 151-year data retention (see the Data Retention and Endurance table) ❐ NoDelay™ writes ❐ Page-mode operation for 30-ns cycle time ❐ Advanced high-reliability ferroelectric process ■ SRAM compatible ❐ Industry-standard 64K × 16 SRAM pinout ❐ 60-ns access time, 90-ns cycle time ■ Superior to battery-backed SRAM modules ❐ No battery concerns ❐ Monolithic reliability ❐ True surface-mount solution, no rework steps ❐ Superior for moisture, shock, and vibration ■ Low power consumption ❐ Active current 7 mA (typ) ❐ Standby current 120 A (typ) ■ Low-voltage operation: VDD = 2.0 V to 3.6 V ■ Automotive-A temperature: –40 C to +85 C ■ 44-pin thin small outline package (TSOP) Type II ■ Restriction of hazardous substances (RoHS)-compliant Functional Description The CY15B101N is a 64K × 16 nonvolatile memory that reads and writes similar to a standard SRAM. A ferroelectric random access memory or F-RAM is nonvolatile, which means that data is retained after power is removed. It provides data retention for over 151 years while eliminating the reliability concerns, functional disadvantages, and system design complexities of battery-backed SRAM (BBSRAM). Fast write-timing and high write-endurance make the F-RAM superior to other types of memory. The CY15B101N operation is similar to that of other RAM devices, and, therefore, it can be used as a drop-in replacement for a standard SRAM in a system. Read cycles may be triggered by CE or simply by changing the address and write cycles may be triggered by CE or WE. The F-RAM memory is nonvolatile due to its unique ferroelectric memory process. These features make the CY15B101N ideal for nonvolatile memory applications requiring frequent or rapid writes. The device is available in a 400-mil, 44-pin TSOP-II surface-mount package. Device specifications are guaranteed over the Automotive-A temperature range –40 °C to +85 °C. For a complete list of related resources, click here. A 1-0 64K x 16 block F-RAM Array ... A 15-2 Block & Row Decoder A15-0 Address Latch & Write Protect Logic Block Diagram ... CE Column Decoder WE I/O Latch & Bus Driver Control Logic UB, LB DQ15-0 OE ZZ Cypress Semiconductor Corporation Document Number: 001-96058 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised January 16, 2018 CY15B101N Contents Pinout ................................................................................ 3 Pin Definitions .................................................................. 3 Device Operation .............................................................. 4 Memory Operation ....................................................... 4 Read Operation ........................................................... 4 Write Operation ........................................................... 4 Page Mode Operation ................................................. 4 Precharge Operation ................................................... 4 Sleep Mode ................................................................. 5 SRAM Drop-In Replacement ....................................... 5 Endurance ................................................................... 5 Maximum Ratings ............................................................. 6 Operating Range ............................................................... 6 DC Electrical Characteristics .......................................... 6 Data Retention and Endurance ....................................... 7 Capacitance ...................................................................... 7 Thermal Resistance .......................................................... 7 AC Test Conditions .......................................................... 7 Document Number: 001-96058 Rev. *E AC Switching Characteristics ......................................... 8 SRAM Read Cycle ...................................................... 8 SRAM Write Cycle ....................................................... 9 Power Cycle and Sleep Mode Timing ........................... 13 Functional Truth Table ................................................... 14 Byte Select Truth Table .................................................. 14 Ordering Information ...................................................... 15 Ordering Code Definitions ......................................... 15 Package Diagram ............................................................ 16 Acronyms ........................................................................ 17 Document Conventions ................................................. 17 Units of Measure ....................................................... 17 Document History Page ................................................. 18 Sales, Solutions, and Legal Information ...................... 19 Worldwide Sales and Design Support ....................... 19 Products .................................................................... 19 PSoC® Solutions ...................................................... 19 Cypress Developer Community ................................. 19 Technical Support ..................................................... 19 Page 2 of 19 CY15B101N Pinout Figure 1. 44-Pin TSOP II Pinout A4 A3 A2 A1 A0 CE DQ0 DQ1 DQ2 DQ3 VDD VSS DQ4 DQ5 DQ6 DQ7 WE VSS A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44-pin TSOP II (× 16) Top View (not to scale) A5 A6 A7 OE UB 44 43 42 41 40 39 38 37 36 35 34 33 32 31 LB DQ15 DQ14 DQ13 DQ12 VSS VDD DQ11 DQ10 30 29 28 27 26 25 24 23 DQ9 DQ8 ZZ A8 A9 A10 A11 NC Pin Definitions Pin Name I/O Type Description A0–A15 Input Address inputs: The 16 address lines select one of 64K words in the F-RAM array. The lowest two address lines A1–A0 may be used for page mode read and write operations. DQ0–DQ15 Input/Output Data I/O Lines: 16-bit bidirectional data bus for accessing the F-RAM array. WE Input Write Enable: A write cycle begins when WE is asserted. The rising edge causes the CY15B101N to write the data on the DQ bus to the F-RAM array. The falling edge of WE latches a new column address for page mode write cycles. CE Input Chip Enable: The device is selected and a new memory access begins on the falling edge of CE. The entire address is latched internally at this point. Subsequent changes to the A1–A0 address inputs allow page mode operation. OE Input Output Enable: When OE is LOW, the CY15B101N drives the data bus when the valid read data is available. Deasserting OE HIGH tristates the DQ pins. UB Input Upper Byte Select: Enables DQ15–DQ8 pins during reads and writes. These pins are HI-Z if UB is HIGH. If the user does not perform byte writes and the device is not configured as a 128K × 8, the UB and LB pins may be tied to ground. LB Input Lower Byte Select: Enables DQ7–DQ0 pins during reads and writes. These pins are HI-Z if LB is HIGH. If the user does not perform byte writes and the device is not configured as a 128 K × 8, the UB and LB pins may be tied to ground. ZZ Input Sleep: When ZZ is LOW, the device enters a low-power sleep mode for the lowest supply current condition. ZZ must be HIGH for a normal read/write operation. This pin must be tied to VDD if not used. VSS Ground VDD NC Ground for the device. Must be connected to the ground of the system. Power supply Power supply input to the device. No connect No connect. This pin is not connected to the die. Document Number: 001-96058 Rev. *E Page 3 of 19 CY15B101N Device Operation Users access 65,536 memory locations, each with 16 data bits through a parallel interface. The F-RAM array is organized as eight blocks, each having 2048 rows. Each row has four column locations, which allow fast access in page-mode operation. When an initial address is latched by the falling edge of CE, subsequent column locations may be accessed without the need to toggle CE. When CE is deasserted (HIGH), a precharge operation begins. Writes occur immediately at the end of the access with no delay. The WE pin must be toggled for each write operation. The write data is stored in the nonvolatile memory array immediately, which is a feature unique to F-RAM called “NoDelay” writes. In a CE-controlled write, the WE signal is asserted before beginning the memory cycle. That is, WE is LOW when CE falls. In this case, the device begins the memory cycle as a write. The CY15B101N will not drive the data bus regardless of the state of OE as long as WE is LOW. Input data must be valid when CE is deasserted HIGH. In a WE-controlled write, the memory cycle begins on the falling edge of CE. The WE signal falls some time later. Therefore, the memory cycle begins as a read. The data bus will be driven if OE is LOW; however, it will be HI-Z when WE is asserted LOW. The CE- and WE-controlled write timing cases are shown on the page 10 and page 11. Write access to the array begins on the falling edge of WE after the memory cycle is initiated. The write access terminates on the rising edge of WE or CE, whichever comes first. A valid write operation requires the user to meet the access time specification before deasserting WE or CE. The data setup time indicates the interval during which data cannot change before the end of the write access (rising edge of WE or CE). Unlike other nonvolatile memory technologies, there is no write delay with F-RAM. Because the read and write access times of the underlying memory are the same, the user experiences no delay through the bus. The entire memory operation occurs in a single bus cycle. Data polling, a technique used with EEPROMs to determine if a write is complete, is unnecessary. Read Operation Page Mode Operation A read operation begins on the falling edge of CE. The falling edge of CE causes the address to be latched and starts a memory read cycle if WE is HIGH. Data becomes available on the bus after the access time is met. When the address is latched and the access completed, a new access to a random location (different row) may begin while CE is still LOW. The minimum cycle time for random addresses is tRC. Note that unlike SRAMs, the CY15B101N's CE-initiated access time is faster than the address access time. The CY15B101N will drive the data bus when OE and at least one of the byte enables (UB, LB) is asserted LOW. The upper data byte is driven when UB is LOW, and the lower data byte is driven when LB is LOW. If OE is asserted after the memory access time is met, the data bus will be driven with valid data. If OE is asserted before completing the memory access, the data bus will not be driven until valid data is available. This feature minimizes the supply current in the system by eliminating transients caused by invalid data being driven to the bus. When OE is deasserted HIGH, the data bus will remain in a HI-Z state. The F-RAM array is organized as eight blocks, each having 2048 rows. Each row has four column-address locations. Address inputs A1–A0 define the column address to be accessed. An access can start on any column address, and other column locations may be accessed without the need to toggle the CE pin. For fast access reads, after the first data byte is driven to the bus, the column address inputs A1–A0 may be changed to a new value. A new data byte is then driven to the DQ pins no later than tAAP, which is less than half the initial read access time. For fast access writes, the first write pulse defines the first write access. While CE is LOW, a subsequent write pulse along with a new column address provides a page mode write access. The CY15B101N is a word-wide F-RAM memory logically organized as 65,536 × 16 and accessed using an industry-standard parallel interface. All data written to the part is immediately nonvolatile with no delay. The device offers page-mode operation, which provides high-speed access to addresses within a page (row). Access to a different page requires that either CE transitions LOW or the upper address (A15–A2) changes. See the Functional Truth Table on page 14 for a complete description of read and write modes. Memory Operation Write Operation In the CY15B101N, writes occur in the same interval as reads. The CY15B101N supports both CE- and WE-controlled write cycles. In both cases, the address A15–A2 is latched on the falling edge of CE. Document Number: 001-96058 Rev. *E Precharge Operation The precharge operation is an internal condition in which the memory state is prepared for a new access. Precharge is user-initiated by driving the CE signal HIGH. It must remain HIGH for at least the minimum precharge time, tPC. Precharge is also activated by changing the upper addresses, A15–A2. The current row is first closed before accessing the new row. The device automatically detects an upper order address change, which starts a precharge operation. The new address is latched and the new read data is valid within the tAA address access time; see Figure 5 on page 10. A similar sequence occurs for write cycles; see Figure 10 on page 11. The rate at which random addresses can be issued is tRC and tWC, respectively. Page 4 of 19 CY15B101N Sleep Mode The device incorporates a sleep mode of operation, which allows the user to achieve the lowest-power-supply-current condition. It enters a low-power sleep mode by asserting the ZZ pin LOW. Read and write operations must complete before the ZZ pin going LOW. When ZZ is LOW, all pins are ignored except the ZZ pin. When ZZ is deasserted HIGH, there is some time delay (tZZEX) before the user can access the device. If sleep mode is not used, the ZZ pin must be tied to VDD. Figure 2. Sleep/Standby State Diagram Power Applied CE HIGH, ZZ HIGH Standby ZZ LOW For applications that require the lowest power consumption, the CE signal should be active (LOW) only during memory accesses. The CY15B101N draws supply current while CE is LOW, even if addresses and control signals are static. While CE is HIGH, the device draws no more than the maximum standby current, ISB. The UB and LB byte select pins are active for both read and write cycles. They may be used to allow the device to be wired as a 128K × 8 memory. The upper and lower data bytes can be tied together and controlled with the byte selects. Individual byte enables or the next higher address line A16 may be available from the system processor. Figure 4. CY15B101N Wired as 128 K x 8 Initialize CE LOW, ZZ HIGH CE HIGH, ZZ HIGH CE LOW, ZZ HIGH WE OE Normal Operation A 16 ZZ LOW Sleep ZZ CE A 15-0 UB LB A 15-0 1-Mbit F-RAM CY15B101N DQ 15-8 D DQ 7-0 7-0 ZZ HIGH Endurance SRAM Drop-In Replacement The CY15B101N is designed to be a drop-in replacement for standard asynchronous SRAMs. The device does not require CE to toggle for each new address. CE may remain LOW indefinitely. While CE is LOW, the device automatically detects address changes and a new access begins. This functionality allows CE to be grounded, similar to an SRAM. It also allows page mode operation at speeds up to 33 MHz. Note that if CE is tied to ground, the user must be sure WE is not LOW at power-up or power-down events. If CE and WE are both LOW during power cycles, data will be corrupted. Figure 3 shows a pull-up resistor on WE, which will keep the pin HIGH during power cycles, assuming the MCU/MPU pin tristates during the reset condition. The pull-up resistor value should be chosen to ensure the WE pin tracks VDD to a high enough value, so that the current drawn when WE is LOW is not an issue. A 10-k resistor draws 330 µA when WE is LOW and VDD = 3.3 V. Figure 3. Use of Pull-up Resistor on WE VDD CY15B101N CE WE MCU / MPU OE A15-0 DQ15-0 Document Number: 001-96058 Rev. *E The CY15B101N is capable of being accessed at least 1014 times – reads or writes. An F-RAM memory operates with a read and restore mechanism. Therefore, an endurance cycle is applied on a row basis. The F-RAM architecture is based on an array of rows and columns. Rows are defined by A15-2 and column addresses by A1-0. The array is organized as 16K rows of four words each. The entire row is internally accessed once whether a single 16-bit word or all four words are read or written. Each word in the row is counted only once in an endurance calculation. The user may choose to write CPU instructions and run them from a certain address space. Table 1 shows endurance calculations for a 256-byte repeating loop, which includes a starting address, three-page mode accesses, and a CE precharge. The number of bus clock cycles needed to complete a four-word transaction is 4 + 1 at lower bus speeds, but 5 + 2 at 33 MHz due to initial read latency and an extra clock cycle to satisfy the device's precharge timing constraint tPC. The entire loop causes each byte to experience only one endurance cycle. The F-RAM read and write endurance is virtually unlimited even at a 33-MHz system bus clock rate. Table 1. Time to Reach 100 Trillion Cycles for Repeating 256-byte Loop Bus Freq (MHz) Bus 256-byte Endurance Endurance Cycle Transaction Cycles/sec Cycles/year Time Time (s) (ns) Years to Reach 1014 Cycles 33 30 10.56 94,690 2.98 x 1012 33.5 25 40 12.8 78,125 2.46 x 1012 40.6 10 100 28.8 34,720 1.09 x 1012 91.7 5 200 57.6 17,360 5.47 x 1011 182.8 Page 5 of 19 CY15B101N Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Storage temperature ................................ –55 C to +125 C Maximum accumulated storage time At 125 °C ambient temperature ................................. 1000 h At 85 °C ambient temperature ................................ 10 Years Ambient temperature with power applied ................................... –55 °C to +125 °C Supply voltage on VDD relative to VSS ........–1.0 V to + 4.5 V Voltage applied to outputs in High Z state .................................... –0.5 V to VDD + 0.5 V Input voltage .......... –1.0 V to + 4.5 V and VIN < VDD + 1.0 V Transient voltage (< 20 ns) on any pin to ground potential ................. –2.0 V to VCC + 2.0 V Package power dissipation capability (TA = 25 °C) ................................................. 1.0 W Surface mount Pb soldering temperature (3 seconds) ......................................... +260 C DC output current (1 output at a time, 1s duration) .... 15 mA Static discharge voltage Human Body Model (AEC-Q100-002 Rev. E) ............... 2 kV Charged Device Model (AEC-Q100-011 Rev. B) ......... 500 V Latch-up current ................................................... > 140 mA Operating Range Range Ambient Temperature (TA) VDD Automotive-A –40 C to +85 C 2.0 V to 3.6 V DC Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min Typ [1] Max Unit 2.0 3.3 3.6 V VDD Power supply voltage IDD VDD supply current VDD = 3.6 V, CE cycling at min. cycle time. All inputs toggling at CMOS levels (0.2 V or VDD – 0.2 V), all DQ pins unloaded. – 7 12 mA ISB Standby current VDD = 3.6 V, CE at VDD, All other pins are static and at CMOS levels (0.2 V or VDD – 0.2 V), ZZ is HIGH TA = 25 C – 120 150 µA TA = 85 C – – 250 µA TA = 25 C – 3 5 µA TA = 85 C – – 8 µA IZZ Sleep mode current VDD = 3.6 V, ZZ is LOW, All other inputs VSS or VDD. ILI Input leakage current VIN between VDD and VSS – – +1 µA ILO Output leakage current VOUT between VDD and VSS – – +1 µA VIH1 Input HIGH voltage VDD = 2.7 V to 3.6 V 2.2 – VDD + 0.3 V VIH2 Input HIGH voltage VDD = 2.0 V to 2.7 V 0.7 × VDD – – V VIL1 Input LOW voltage VDD = 2.7 V to 3.6 V – 0.3 – 0.8 V VIL2 Input LOW voltage VDD = 2.0 V to 2.7 V – 0.3 – 0.3 × VDD V VOH1 Output HIGH voltage IOH = –1 mA, VDD > 2.7 V 2.4 – – V VOH2 Output HIGH voltage IOH = –100 µA VDD – 0.2 – – V VOL1 Output LOW voltage IOL = 2 mA, VDD > 2.7 V – – 0.4 V VOL2 Output LOW voltage IOL = 150 µA – – 0.2 V Note 1. Typical values are at 25 °C, VDD = VDD (typ). Not 100% tested. Document Number: 001-96058 Rev. *E Page 6 of 19 CY15B101N Data Retention and Endurance Parameter TDR NVC Description Data retention Endurance Test condition TA = 85 C Min Max Unit 10 – Years TA = 75 C 38 – TA = 65 C 151 – Over operating temperature 1014 – Cycles Max Unit Capacitance Parameter Description Test Conditions TA = 25 C, f = 1 MHz, VDD = VDD(Typ) CI/O Input/Output capacitance (DQ) 8 pF CIN Input capacitance 6 pF CZZ Input capacitance of ZZ pin 8 pF Thermal Resistance Parameter Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. 44-pin TSOP II Unit 107 C/W 25 C/W AC Test Conditions Input pulse levels ...................................................0 V to 3 V Input rise and fall times (10%–90%) ........................... < 3 ns Input and output timing reference levels ....................... 1.5 V Output load capacitance ............................................... 30 pF Document Number: 001-96058 Rev. *E Page 7 of 19 CY15B101N AC Switching Characteristics Over the Operating Range Parameters [2] Cypress Parameter VDD = 2.0 V to 2.7 V Description Alt Parameter VDD = 2.7 V to 3.6 V Unit Min Max Min Max – 70 – 60 ns 105 – 90 – ns SRAM Read Cycle tCE tACE Chip enable access time tRC – Read cycle time tAA – Address access time, A15-2 – 105 – 90 ns tOH tOHA Output hold time, A15-2 20 – 20 – ns tAAP – Page mode access time, A1-0 – 40 – 30 ns tOHP – Page mode output hold time, A1-0 3 – 3 – ns tCA – Chip enable active time 70 – 60 – ns tPC – Precharge time 35 – 30 – ns tBA tBW UB, LB access time – 25 – 15 ns tAS tSA Address setup time (to CE LOW) 0 – 0 – ns tAH tHA Address hold time (CE Controlled) 70 – 60 – ns tOE tDOE Output enable access time – 25 – 15 ns tHZ[3, 4] tHZCE Chip enable to output HI-Z – 15 – 10 ns tOHZ[3, 4] tHZOE Output enable HIGH to output HI-Z – 15 – 10 ns tBHZ[3, 4] tHZBE UB, LB HIGH to output HI-Z – 15 – 10 ns Notes 2. Test conditions assume a signal transition time of 3 ns or less, timing reference levels of 0.5 × VDD, input pulse levels of 0 to 3 V, output loading of the specified IOL/IOH and 30-pF load capacitance shown in AC Test Conditions on page 7. 3. tHZ, tOHZ and tBHZ are specified with a load capacitance of 5 pF. Transition is measured when the outputs enter a high impedance state. 4. This parameter is characterized but not 100% tested. Document Number: 001-96058 Rev. *E Page 8 of 19 CY15B101N AC Switching Characteristics (continued) Over the Operating Range Parameters [2] Cypress Parameter VDD = 2.0 V to 2.7 V Description Alt Parameter VDD = 2.7 V to 3.6 V Min Max Min Max Unit SRAM Write Cycle tWC tWC Write cycle time 105 – 90 – ns tCA – Chip enable active time 70 – 60 – ns tCW tSCE Chip enable to write enable HIGH 70 – 60 – ns tPC – Precharge time 35 – 30 – ns tPWC – Page mode write enable cycle time 40 – 30 – ns tWP tPWE Write enable pulse width 22 – 18 – ns tWP2 tBW UB, LB pulse width 22 – 18 – ns tWP3 tPWE WE LOW to UB, LB HIGH 22 – 18 – ns tAS tSA Address setup time (to CE LOW) 0 – 0 – ns tAH tHA Address hold time (CE Controlled) 70 – 60 – ns tASP – Page mode address setup time (to WE LOW) 8 – 5 – ns tAHP – Page mode address hold time (to WE LOW) 20 – 15 – ns tWLC tPWE Write enable LOW to chip disabled 30 – 25 – ns tBLC tBW UB, LB LOW to chip disabled 30 – 25 – ns tWLA – Write enable LOW to address change, A15-2 30 – 25 – ns tAWH – Address change to write enable HIGH, A15-2 105 – 90 – ns tDS tSD Data input setup time 20 – 15 – ns tHD Data input hold time 0 – 0 – ns tHZWE Write enable LOW to output HI-Z – 10 – 10 ns tWX[6] – Write enable HIGH to output driven 8 – 5 – ns tBDS – Byte disable setup time (to WE LOW) 8 – 5 – ns tBDH – Byte disable hold time (to WE HIGH) 8 – 5 – ns tDH tWZ [5, 6] Notes 5. tWZ is specified with a load capacitance of 5 pF. Transition is measured when the outputs enter a high-impedance state. 6. This parameter is characterized but not 100% tested. Document Number: 001-96058 Rev. *E Page 9 of 19 CY15B101N Figure 5. Read Cycle Timing 1 (CE LOW, OE LOW) tRC tRC A15-2 tOH tAA tAA tOH Previous Data DQ 15-0 Valid Data Valid Data Figure 6. Read Cycle Timing 2 (CE Controlled) tCA tPC CE tAH tAS A 15-0 tOE OE tHZ tCE tOHZ tOH DQ 15-0 tBA tBHZ UB / LB Figure 7. Page Mode Read Cycle Timing [7] tPC tCA CE tAS A 15-2 Col 0 A1-0 Col 1 tAAP tOE OE tHZ tOHZ tOHP tCE DQ15-0 Col 2 Data 0 Data 1 Data 2 Note 7. Although sequential column addressing is shown, it is not required. Document Number: 001-96058 Rev. *E Page 10 of 19 CY15B101N Figure 8. Write Cycle Timing 1 (WE Controlled) [8] tCA tPC tCW CE tAS tWLC A15-0 tWP tWX WE DQ15-0 tWZ tDH tDS D out D in tHZ D out Figure 9. Write Cycle Timing 2 (CE Controlled) tCA tPC CE tBLC tAS A15-0 WE tDH tDS DQ 15-0 D in UB/LB Figure 10. Write Cycle Timing 3 (CE LOW) [8] tWC tAWH A15-0 tWLA tWX WE tWZ tDS DQ15-0 D out D in tDH D out D in Note 8. OE (not shown) is LOW only to show the effect of WE on DQ pins. Document Number: 001-96058 Rev. *E Page 11 of 19 CY15B101N Figure 11. Write Cycle Timing 4 (CE LOW) [9] A15-0 tWP3 WE tBDH tBDS tWP2 UB/LB tDS DQ15-0 tDH tDS D in tDH D in Figure 12. Page Mode Write Cycle Timing tCA tPC tCW CE tWLC tAS A15-2 tAHP A 1-0 Col 0 tASP Col 1 Col 2 tPWC tWP WE OE tDH tDS DQ15-0 Data 0 Data 1 Data 2 Note 9. UB and LB to show byte enable and byte masking cases. Document Number: 001-96058 Rev. *E Page 12 of 19 CY15B101N Power Cycle and Sleep Mode Timing Over the Operating Range Parameter tPU tPD tVR [10] Description Min Max Unit Power-up (after VDD min. is reached) to first access time 1 – ms Last write (WE HIGH) to power down time 0 – ms VDD power-up ramp rate 50 – µs/V tVF[10] VDD power-down ramp rate 100 – µs/V tZZH ZZ active to DQ HI-Z time – 20 ns tWEZZ Last write to sleep mode entry time 0 – µs tZZL ZZ active LOW time 1 – µs tZZEN Sleep mode entry time (ZZ LOW to CE don’t care) – 0 µs – 450 µs tZZEX Sleep mode exit time (ZZ HIGH to 1st access after wakeup) Figure 13. Power Cycle and Sleep Mode Timing VDD t VR t PU CE VDD min. VDD min. t ZZEN t ZZEX R/W Allowed t ZZEX R/W Allowed t VF R/W Allowed t ZZL ZZ t PD t WEZZ WE t ZZH DQ D out D in Note 10. Slope measured at any point on the VDD waveform. Document Number: 001-96058 Rev. *E Page 13 of 19 CY15B101N Functional Truth Table Operation [11, 12] CE WE A15-2 A1-0 ZZ X X X X L Sleep Mode H X X X H Standby/Idle H H V V V V H H Read L L H No Change Change H Page Mode Read L H Change V H Random Read V V V V H H CE-Controlled Write[12] L L L L V V H WE-Controlled Write [12, 13] L No Change V H Page Mode Write [14] X X X X H H Starts precharge L X X Byte Select Truth Table Operation [15] WE OE LB UB H H X X X H H L H L Read upper byte; HI-Z lower byte L H Read lower byte; HI-Z upper byte L L Read both bytes H L Write upper byte; Mask lower byte L H Write lower byte; Mask upper byte L L Write both bytes H L X Read; Outputs disabled Notes 11. H = Logic HIGH, L = Logic LOW, V = Valid Data, X = Don't Care, = toggle LOW, = toggle HIGH. 12. For write cycles, data-in is latched on the rising edge of CE or WE, whichever comes first. 13. WE-controlled write cycle begins as a Read cycle and then A15-2 is latched. 14. Addresses A1-0 must remain stable for at least 15 ns during page mode operation. 15. The UB and LB pins may be grounded if 1) the system does not perform byte writes and 2) the device is not configured as a 128K x 8. Document Number: 001-96058 Rev. *E Page 14 of 19 CY15B101N Ordering Information Access Time (ns) 60 Ordering Code CY15B101N-ZS60XAT CY15B101N-ZS60XA Package Diagram Package Type 51-85087 44-pin TSOP II with sleep mode Operating Range Automotive-A All the above parts are Pb-free. Ordering Code Definitions CY 15 B 101 N - ZS 60 X A T Option: Blank = Standard; T = Tape and Reel Temperature: A = Automotive-A (–40 °C to +85 °C) X = Pb-free Speed: 60 = 60 ns Package Type: ZS = 44-pin TSOP II Data Bus: N = x16 Density: 101 = 1-Mbit Voltage: B = 2.0 V to 3.6 V F-RAM Cypress Document Number: 001-96058 Rev. *E Page 15 of 19 CY15B101N Package Diagram Figure 14. 44-pin TSOP Package Outline, 51-85087 51-85087 *E Document Number: 001-96058 Rev. *E Page 16 of 19 CY15B101N Acronyms Acronym UB Document Conventions Description Units of Measure Symbol Upper Byte Unit of Measure LB Lower Byte °C CE CMOS Chip Enable Hz hertz Complementary Metal Oxide Semiconductor kHz kilohertz EIA Electronic Industries Alliance k kilohm F-RAM Ferroelectric Random Access Memory MHz megahertz I/O Input/Output A microampere OE RoHS Output Enable F microfarad s microsecond RW Read and Write mA milliampere ms millisecond SRAM Static Random Access Memory M megaohm TSOP Thin Small Outline Package ns nanosecond WE Write Enable ohm % percent pF picofarad V volt W watt Restriction of Hazardous Substances Document Number: 001-96058 Rev. *E degree Celsius Page 17 of 19 CY15B101N Document History Page Document Title: CY15B101N, 1-Mbit (64K × 16) Automotive F-RAM Memory Document Number: 001-96058 ECN No. Orig. of Change Submission Date ** 4630415 ZSK / LIZB 01/21/2015 New data sheet. *A 4746319 GVCH 04/28/2015 Changed status from Advance to Preliminary. Rev. Description of Change *B 4774256 GVCH 06/04/2015 Changed status from Preliminary to Final. *C 4766039 GVCH 06/22/2015 Updated Functional Truth Table: Fixed typo (Included “Toggle LOW” and “Toggle HIGH” condition in “CE” and “WE” columns). *D 4883462 ZSK / PSR 09/04/2015 Updated Functional Description: Added “For a complete list of related resources, click here.” at the end. Updated Maximum Ratings: Removed “Maximum junction temperature”. Added “Maximum accumulated storage time”. Added “Ambient temperature with power applied”. *E 6033841 GVCH 01/16/2018 Updated to the new template. Completing the Sunset review. Document Number: 001-96058 Rev. *E Page 18 of 19 CY15B101N Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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Document Number: 001-96058 Rev. *E Revised January 16, 2018 Page 19 of 19