Cypress CY7C144AV-25AXC 3.3v 4k/8k/16k/32k x 8/9 dual-port static ram Datasheet

CY7C138AV CY7C139AV CY7C144AV CY7C145AV CY7C006AV CY7C016AV CY7C007AV CY7C017AV 3.3V 4K/8K/16K/32K x 8/9
Dual-Port Static RAM
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
3.3V 4K/8K/16K/32K x 8/9
Dual-Port Static RAM
Features
• True Dual-Ported memory cells which allow
simultaneous access of the same memory location
• Automatic power-down
• Expandable data bus to 16/18 bits or more using Master/
Slave chip select when using more than one device
• 4K/8K/16K/32K x 8 organizations
(CY7C0138AV/144AV/006AV/007AV)
• On-chip arbitration logic
• 4K/8K/16K/32K x 9 organizations
(CY7C0139AV/145AV/016AV/017AV)
• Semaphores included to permit software handshaking
between ports
• 0.35-micron CMOS for optimum speed/power
• INT flag for port-to-port communication
• High-speed access: 20/25 ns
• Pin select for Master or Slave
• Low operating power
• Commercial and Industrial Temperature Ranges
— Active: ICC = 115 mA (typical)
— Standby: ISB3 = 10 µA (typical)
• Available in 68-pin PLCC (all) and 64-pin TQFP
(7C006AV & 7C144AV)
• Pb-Free packages available
• Fully asynchronous operation
Logic Block Diagram
R/WL
R/WR
CEL
CER
OEL
OER
[1]
8/9
8/9
I/O0L–I/O7/8L
[2]
A0L–A11–14L
[2]
I/O
Control
12–15
Address
Decode
I/O
Control
Address
Decode
True Dual-Ported
RAM Array
12–15
12–15
[2]
A0R–A11–14R
12–15
A0L–A11–14L
CEL
OEL
R/WL
SEML
BUSYL
INTL
[1]
I/O0R–I/O7/8R
[2]
A0R–A11–14R
CER
OER
R/WR
SEMR
Interrupt
Semaphore
Arbitration
[3]
[3]
BUSYR
INTR
M/S
For the most recent information, visit the Cypress web site at www.cypress.com
Notes:
1. I/O0–I/O7 for x8 devices; I/O0–I/O8 for x9 devices.
2. A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K devices; A0–A14 for 32K devices;
3. BUSY is an output in master mode and an input in slave mode.
Cypress Semiconductor Corporation
Document #: 38-06051 Rev. *C
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised June 6, 2005
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Pin Configurations
9 8 7 6
A6L
A8L
A7L
5 4 3 2 1 68 67 66 65 64 63 62 61
60
59
58
57
56
55
54
53
CY7C138AV (4K x 8)
52
CY7C139AV (4K x 9)
51
50
49
48
47
46
45
44
A5L
A4L
A3L
A2L
A1L
A0L
INTL
BUSYL
GND
M/S
BUSYR
INTR
A0R
A1R
A2R
A3R
A4R
A5R
A7R
A6R
A
9R
A8R
2728 29 30 3132 33 34 35 36 37 38 39 40 41 42 43
R/W
R
SEM
R
CER
NC
NC
GND
NC
A
11R
A10R
21
22
23
24
25
26
I/O7R
I/O3R
I/O4R
I/O5R
I/O6R
10
11
12
13
14
15
16
17
18
19
20
NC [5]
OER
I/O2L
I/O3L
I/O4L
I/O5L
GND
I/O6L
I/O7L
VCC
GND
I/O0R
I/O1R
I/O2R
VCC
NC
NC
VCC
NC
A
11L
A
10L
A9L
NC [4]
OE L
R/W L
SEM
L
CEL
I/O 1L
I/O 0L
68-Pin PLCC
Top View
9 8 7 6
A6L
A8L
A7L
5 4 3 2 1 68 67 66 65 64 63 62 61
60
59
58
57
56
55
54
53
CY7C144AV (8K x 8)
52
CY7C145AV (8K x 9)
51
50
49
48
A2L
A1L
A0L
INTL
BUSYL
GND
M/S
BUSYR
INTR
A0R
A1R
A2R
A3R
A4R
A5R
47
46
45
44
A5L
A4L
A3L
A7R
A6R
A
9R
A8R
2728 29 30 3132 33 34 35 36 37 38 39 40 41 42 43
R/W
R
SEM
R
CER
NC
NC
GND
A12R
A
11R
A10R
21
22
23
24
25
26
I/O7R
I/O3R
I/O4R
I/O5R
I/O6R
10
11
12
13
14
15
16
17
18
19
20
NC [7]
OER
I/O2L
I/O3L
I/O4L
I/O5L
GND
I/O6L
I/O7L
VCC
GND
I/O0R
I/O1R
I/O2R
VCC
NC
NC
VCC
A12L
A
11L
A
10L
A9L
NC [6]
OE L
R/W L
SEM
L
CEL
I/O 1L
I/O 0L
68-Pin PLCC
Top View
Notes:
4. I/O8L on the CY7C139AV.
5. I/O8R on the CY7C139AV.
6. I/O8L on the CY7C145AV.
7. I/O8R on the CY7C145AV.
Document #: 38-06051 Rev. *C
Page 2 of 20
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Pin Configurations (continued)
A6L
A5L
49
54
A7L
A12L
56
55
A8L
VCC
57
51
50
CEL
NC
A9L
SEML
59
52
R/WL
60
53
OEL
62
61
A11L
A10L
I/O0L
63
58
I/O1L
64
64-Pin TQFP
Top View
I/O2L
1
48
A4L
I/O3L
I/O4L
2
47
3
4
46
45
A3L
A2L
5
44
A0L
I/O6L
I/O7L
6
43
7
42
INTL
BUSYL
GND
M/S
I/O5L
GND
A1L
VCC
8
GND
I/O0R
I/O1R
9
10
11
38
INTR
I/O2R
12
37
VCC
13
36
A0R
A1R
I/O3R
I/O4R
14
15
35
34
A2R
I/O5R
16
33
A4R
41
30
31
A7R
32
29
BUSYR
A3R
A6R
A5R
28
25
26
A12R
A8R
24
GND
40
39
A9R
23
27
22
CER
NC
A11R
A10R
21
19
20
OER
SEMR
18
R/WR
17
I/O6R
I/O7R
CY7C144AV (8K x 8)
I/O2L
I/O3L
I/O4L
10
I/O5L
GND
I/O6L
I/O7L
13
A8L
A7L
A6L
64
63
62
61
68
67
A9L
VCC
2
1
65
A14L
A13L
3
A11L
A10L
CEL
4
66
SEML
5
A12L
R/WL
[9]
I/O8L
OEL
I/O0L
8
58
12
57
56
55
14
15
16
17
CY7C006AV (16K x 8)
CY7C007AV (32K x 8)
CY7C016AV (16K x 9)
CY7C017AV (32K x 9)
GND
I/O0R
I/O1R
18
I/O2R
VCC
21
22
23
24
19
20
BUSYL
GND
M/S
52
51
50
41
42
43
A6R
A5R
40
A8R
A7R
37
A11R
A10R
A9R
36
A12R
38
39
35
GND
A13R
32
33
34
31
CER
44
SEMR
26
30
46
45
29
A0L
53
25
OER
R/WR
A3L
A2L
A1L
INTL
47
27
28
A5L
A4L
54
49
48
I/O7R
I/O8R[8]
I/O3R
I/O4R
I/O5R
I/O6R
7
6
I/O1L
9
60
59
11
A14R[9]
VCC
[8]
68-Pin PLCC
Top View
BUSYR
INTR
A0R
A1R
A2R
A3R
A4R
Notes:
8. I/O for CY7C016AV and CY7C017AV only. NC for other parts.
9. Address line for CY7C007AV and CY7C017AV only. NC for other parts.
Document #: 38-06051 Rev. *C
Page 3 of 20
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Pin Configurations (continued)
A6L
A5L
49
54
A7L
A12L
56
55
A8L
VCC
57
51
50
CEL
A13L
A9L
SEML
59
52
R/WL
60
53
OEL
62
61
A11L
A10L
I/O0L
63
58
I/O1L
64
64-Pin TQFP
Top View
I/O2L
1
48
A4L
I/O3L
I/O4L
2
47
3
4
46
45
A3L
A2L
5
44
A0L
I/O6L
I/O7L
6
43
7
42
INTL
BUSYL
GND
M/S
I/O5L
GND
A1L
VCC
8
GND
I/O0R
I/O1R
9
10
11
38
INTR
I/O2R
12
37
VCC
13
36
A0R
A1R
I/O3R
I/O4R
14
15
35
34
A2R
I/O5R
16
33
A4R
41
30
31
A7R
32
29
BUSYR
A3R
A6R
A5R
28
25
26
A12R
A8R
24
GND
40
39
A9R
23
27
22
CER
A13R
A11R
A10R
21
19
20
OER
SEMR
18
R/WR
17
I/O6R
I/O7R
CY7C006AV (16K x 8)
Selection Guide
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
-20
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
-25
Maximum Access Time (ns)
20
25
Typical Operating Current (mA)
120
115
Typical Standby Current for ISB1 (mA) (Both
Ports TTL level)
35
30
10 µA
10 µA
Typical Standby Current for ISB3 (µA)
(Both Ports CMOS level)
Document #: 38-06051 Rev. *C
Page 4 of 20
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Pin Definitions
Left Port
Right Port
Description
CEL
CER
Chip Enable
R/WL
R/WR
Read/Write Enable
OEL
OER
Output Enable
A0L–A14L
A0R–A14R
Address (A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K devices; A0–A14 for 32K)
I/O0L–I/O8L
I/O0R–I/O8R
Data Bus Input/Output (I/O0–I/O7 for x8 devices and I/O0–I/O8 for x9)
SEML
SEMR
Semaphore Enable
INTL
INTR
Interrupt Flag
BUSYL
BUSYR
Busy Flag
M/S
Master or Slave Select
VCC
Power
GND
Ground
NC
No Connect
Architecture
The CY7C138AV/144AV/006AV/007AV and CY7C139AV/
145AV/016AV/017AV consist of an array of 4K, 8K, 16K, and
32K words of 8 and 9 bits each of dual-port RAM cells, I/O and
address lines, and control signals (CE, OE, R/W). These
control pins permit independent access for reads or writes to
any location in memory. To handle simultaneous writes/reads
to the same location, a BUSY pin is provided on each port. Two
interrupt (INT) pins can be utilized for port-to-port communication. Two semaphore (SEM) control pins are used for
allocating shared resources. With the M/S pin, the device can
function as a master (BUSY pins are outputs) or as a slave
(BUSY pins are inputs). The device also has an automatic
power-down feature controlled by CE. Each port is provided
with its own output enable control (OE), which allows data to
be read from the device.
Functional Description
The CY7C138AV/144AV/006AV/007AV and CY7C139AV/
145AV/ 016AV/017AV are low-power CMOS 4K, 8K, 16K, and
32K x8/9 dual-port static RAMs. Various arbitration schemes
are included on the devices to handle situations when multiple
processors access the same piece of data. Two ports are
provided, permitting independent, asynchronous access for
reads and writes to any location in memory. The devices can
be utilized as standalone 8/9-bit dual-port static RAMs or
multiple devices can be combined in order to function as a
16/18-bit or wider master/slave dual-port static RAM. An M/S
pin is provided for implementing 16/18-bit or wider memory
applications without the need for separate master and slave
devices or additional discrete logic. Application areas include
interprocessor/multiprocessor designs, communications
status buffering, and dual-port video/graphics memory.
Each port has independent control pins: Chip Enable (CE),
Read or Write Enable (R/W), and Output Enable (OE). Two
flags are provided on each port (BUSY and INT). BUSY
signals that the port is trying to access the same location
currently being accessed by the other port. The Interrupt flag
(INT) permits communication between ports or systems by
means of a mail box. The semaphores are used to pass a flag,
Document #: 38-06051 Rev. *C
or token, from one port to the other to indicate that a shared
resource is in use. The semaphore logic is comprised of eight
shared latches. Only one side can control the latch
(semaphore) at any time. Control of a semaphore indicates
that a shared resource is in use. An automatic power-down
feature is controlled independently on each port by a Chip
Select (CE) pin.
Read and Write Operations
When writing data must be set up for a duration of tSD before
the rising edge of R/W in order to guarantee a valid write. A
write operation is controlled by either the R/W pin (see Write
Cycle No. 1 waveform) or the CE pin (see Write Cycle No. 2
waveform). Required inputs for non-contention operations are
summarized in Table 1.
If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flowthrough
delay must occur before the data is read on the output;
otherwise the data read is not deterministic. Data will be valid
on the port tDDD after the data is presented on the other port.
When reading the device, the user must assert both the OE
and CE pins. Data will be available tACE after CE or tDOE after
OE is asserted. If the user wishes to access a semaphore flag,
then the SEM pin must be asserted instead of the CE pin and
OE must also be asserted.
Interrupts
The upper two memory locations may be used for message
passing. The highest memory location (FFF for the
CY7C138AV/9AV, 1FFF for the CY7C144AV/5AV, 3FFF for the
CY7C006AV/16AV, 7FFF for the CY7C007AV/17AV) is the
mailbox for the right port and the second-highest memory
location (FFE for the CY7C138AV/9AV, 1FFE for the
CY7C144AV/5AV, 3FFE for the CY7C006AV/16AV, 7FFE for
the CY7C007AV/17AV) is the mailbox for the left port. When
one port writes to the other port’s mailbox, an interrupt is
generated to the owner. The interrupt is reset when the owner
reads the contents of the mailbox. The message is user
defined.
Each port can read the other port’s mailbox without resetting
the interrupt. The active state of the busy signal (to a port)
Page 5 of 20
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
prevents the port from setting the interrupt to the winning port.
Also, an active busy to a port prevents that port from reading
its own mailbox and, thus, resetting the interrupt to it. If an
application does not require message passing, do not connect
the interrupt pin to the processor’s interrupt request input pin.
The operation of the interrupts and their interaction with Busy
are summarized in Table 2.
Busy
The CY7C138AV/144AV/006AV/007AV and CY7C139AV/
145AV/016AV/017AV provide on-chip arbitration to resolve
simultaneous memory location access (contention). If both
ports’ CEs are asserted and an address match occurs within
tPS of each other, the busy logic will determine which port has
access. If tPS is violated, one port will definitely gain
permission to the location, but it is not predictable which port
will get that permission. BUSY will be asserted tBLA after an
address match or tBLC after CE is taken LOW.
Master/Slave
An M/S pin is provided in order to expand the word width by
configuring the device as either a master or a slave. The BUSY
output of the master is connected to the BUSY input of the
slave. This will allow the device to interface to a master device
with no external components. Writing to slave devices must be
delayed until after the BUSY input has settled (tBLC or tBLA),
otherwise, the slave chip may begin a write cycle during a
contention situation. When tied HIGH, the M/S pin allows the
device to be used as a master and, therefore, the BUSY line
is an output. BUSY can then be used to send the arbitration
outcome to a slave.
Semaphore Operation
The CY7C138AV/144AV/006AV/007AV and CY7C139AV/
145AV/016AV/017AV provide eight semaphore latches, which
are separate from the dual-port memory locations.
Semaphores are used to reserve resources that are shared
between the two ports. The state of the semaphore indicates
that a resource is in use. For example, if the left port wants to
Document #: 38-06051 Rev. *C
request a given resource, it sets a latch by writing a zero to a
semaphore location. The left port then verifies its success in
setting the latch by reading it. After writing to the semaphore,
SEM or OE must be deasserted for tSOP before attempting to
read the semaphore. The semaphore value will be available
tSWRD + tDOE after the rising edge of the semaphore write. If
the left port was successful (reads a zero), it assumes control
of the shared resource, otherwise (reads a one) it assumes the
right port has control and continues to poll the semaphore.
When the right side has relinquished control of the semaphore
(by writing a one), the left side will succeed in gaining control
of the semaphore. If the left side no longer requires the
semaphore, a one is written to cancel its request.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip select for the semaphore latches (CE
must remain HIGH during SEM LOW). A0–2 represents the
semaphore address. OE and R/W are used in the same
manner as a normal memory access. When writing or reading
a semaphore, the other address pins have no effect.
When writing to the semaphore, only I/O0 is used. If a zero is
written to the left port of an available semaphore, a one will
appear at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing zero
(the left port in this case). If the left port now relinquishes
control by writing a one to the semaphore, the semaphore will
be set to one for both sides. However, if the right port had
requested the semaphore (written a zero) while the left port
had control, the right port would immediately own the
semaphore as soon as the left port released it. Table 3 shows
sample semaphore operations.
When reading a semaphore, all data lines output the
semaphore value. The read value is latched in an output
register to prevent the semaphore from changing state during
a write from the other port. If both ports attempt to access the
semaphore within tSPS of each other, the semaphore will
definitely be obtained by one side or the other, but there is no
guarantee which side will control the semaphore.
Page 6 of 20
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Maximum Ratings[10]
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage........................................... >2001V
(Above which the useful life may be impaired. For user guidelines, not tested.)
Latch-Up Current.................................................... >200 mA
Storage Temperature .................................–65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground Potential ............... –0.5V to +4.6V
DC Voltage Applied to
Outputs in High Z State............................–0.5V to VCC+0.5V
DC Input
Voltage[11]
Range
Ambient
Temperature
VCC
Commercial
0°C to +70°C
3.3V ± 300 mV
Industrial[12]
–40°C to +85°C
3.3V ± 300 mV
.
.................................–0.5V to VCC+0.5V
Electrical Characteristics Over the Operating Range
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
-20
Parameter
Description
VOH
Output HIGH Voltage (VCC = 3.3V)
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IOZ
Output Leakage Current
ICC
Operating Current (VCC = Max.,
IOUT = 0 mA) Outputs Disabled
ISB1
ISB2
ISB3
ISB4
Min.
Typ.
-25
Max.
2.4
Min.
Typ.
2.0
V
0.4
Standby Current (Both Ports CMOS
Level) CEL & CER ≥ VCC – 0.2V, f = 0[13]
Standby Current (One Port CMOS Level)
CEL | CER ≥ VIH, f = fMAX[13]
–10
10
Com’l.
120
175
Ind.[12]
140
195
Com’l.
35
45
[12]
Ind.
45
55
Com’l.
75
110
[12]
Ind.
85
130
Com’l.
10
500
[12]
Ind.
10
500
Com’l.
70
95
[12]
80
105
Ind.
V
2.0
V
0.8
Standby Current (One Port TTL Level)
CEL | CER ≥ VIH, f = fMAX[13]
Unit
2.4
0.4
Standby Current (Both Ports TTL Level)
CEL & CER ≥ VIH, f = fMAX[13]
Max.
0.8
V
10
µA
115
165
mA
30
40
–10
mA
mA
mA
65
95
mA
10
500
mA
µA
µA
60
80
mA
mA
Capacitance[14]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 3.3V
Max.
Unit
10
pF
10
pF
Notes:
10. The Voltage on any input or I/O pin can not exceed the power pin during power-up.
11. Pulse width < 20 ns.
12. Industrial parts are available in CY7C007AV and CY7C017AV only.
13. fMAX = 1/tRC. All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level
standby ISB3.
14. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-06051 Rev. *C
Page 7 of 20
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
AC Test Loads and Waveforms
3.3V
3.3V
OUTPUT
R1 = 590Ω
OUTPUT
C = 30 pF
RTH = 250Ω
R1 = 590Ω
C = 30 pF
OUTPUT
C = 5 pF
VTH = 1.4V
R2 = 435Ω
(a) Normal Load (Load 1)
(b) Thévenin Equivalent (Load 1)
ALL INPUT PULSES
3.0V
10%
GND
90%
R2 = 435Ω
(c) Three-State Delay (Load 2)
(Used for tLZ, tHZ, tHZWE & tLZWE
including scope and jig)
90%
10%
≤ 3 ns
≤ 3 ns
.
Switching Characteristics Over the Operating Range[15]
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
-20
Parameter
Description
Min.
-25
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
20
tAA
Address to Data Valid
tOHA
Output Hold From Address Change
tACE[16]
CE LOW to Data Valid
20
25
ns
tDOE
OE LOW to Data Valid
12
13
ns
tLZOE[17, 18, 19]
tHZOE[17, 18, 19]
tLZCE[17, 18, 19]
tHZCE[17, 18, 19]
tPU[19]
tPD[19]
OE Low to Low Z
20
3
CE LOW to Power-Up
25
12
0
CE HIGH to Power-Down
ns
15
3
12
ns
ns
15
0
20
ns
ns
3
3
CE HIGH to High Z
ns
3
3
OE HIGH to High Z
CE LOW to Low Z
25
ns
ns
25
ns
WRITE CYCLE
tWC
Write Cycle Time
20
25
ns
tSCE[16]
CE LOW to Write End
16
20
ns
tAW
Address Valid to Write End
16
20
ns
tHA
Address Hold From Write End
0
0
ns
tSA[16]
Address Set-Up to Write Start
0
0
ns
tPWE
Write Pulse Width
16
20
ns
tSD
Data Set-Up to Write End
12
15
ns
Notes:
15. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOI/IOH and 30-pF load capacitance.
16. To access RAM, CE=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire tSCE time.
17. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
18. Test conditions used are Load 3.
19. This parameter is guaranteed but not tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with
Busy waveform.
Document #: 38-06051 Rev. *C
Page 8 of 20
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Switching Characteristics Over the Operating Range[15] (continued)
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
-20
Parameter
Description
tHD
Data Hold From Write End
tHZWE[18, 19]
tLZWE[18, 19]
tWDD[20]
tDDD[20]
R/W LOW to High Z
BUSY TIMING
Min.
-25
Max.
0
Min.
Max.
0
ns
12
R/W HIGH to Low Z
Unit
3
15
ns
3
ns
Write Pulse to Data Delay
40
50
ns
Write Data Valid to Read Data Valid
30
35
ns
[21]
tBLA
BUSY LOW from Address Match
20
20
ns
tBHA
BUSY HIGH from Address Mismatch
20
20
ns
tBLC
BUSY LOW from CE LOW
20
20
ns
tBHC
BUSY HIGH from CE HIGH
16
17
ns
tPS
Port Set-Up for Priority
5
5
ns
tWB
R/W HIGH after BUSY (Slave)
0
0
ns
tWH
R/W HIGH after BUSY HIGH (Slave)
15
17
ns
tBDD[22]
BUSY HIGH to Data Valid
INTERRUPT TIMING
20
25
ns
[21]
tINS
INT Set Time
20
20
ns
tINR
INT Reset Time
20
20
ns
SEMAPHORE TIMING
tSOP
SEM Flag Update Pulse (OE or SEM)
10
12
ns
tSWRD
SEM Flag Write to Read Time
5
5
ns
tSPS
SEM Flag Contention Window
5
5
ns
tSAA
SEM Address Access Time
Data Retention Mode
The
CY7C0138AV/144AV/006AV/007AV
and
CY7C139AV/145AV/016AV/017AV are designed with battery
backup in mind. Data retention voltage and supply current are
guaranteed over temperature. The following rules ensure data
retention:
1. Chip enable (CE) must be held HIGH during data retention,
within VCC to VCC – 0.2V.
20
25
ns
Timing
Data Retention Mode
VCC
3.0V
VCC > 2.0V
3.0V
VCC to VCC – 0.2V
CE
tRC
V
IH
2. CE must be kept between VCC – 0.2V and 70% of VCC
during the power-up and power-down transitions.
3. The RAM can begin operation >tRC after VCC reaches the
minimum operating voltage (3.0 volts).
Parameter
ICCDR1
Test Conditions[23]
@ VCCDR = 2V
Max.
Unit
50
µA
Notes:
20. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
21. Test conditions used are Load 2.
22. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual).
23. CE = VCC, Vin = GND to VCC, TA = 25°C. This parameter is guaranteed but not tested.
Document #: 38-06051 Rev. *C
Page 9 of 20
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Switching Waveforms
Read Cycle No. 1 (Either Port Address Access)[24, 25, 26]
tRC
ADDRESS
tOHA
DATA OUT
tAA
tOHA
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (Either Port CE/OE Access)[24, 27, 28]
tACE
CE
tDOE
OE
tHZCE
tHZOE
tLZOE
DATA VALID
DATA OUT
tLZCE
tPU
tPD
ICC
CURRENT
ISB
Read Cycle No. 3 (Either Port)[24, 26, 27, 28]
tRC
ADDRESS
tOHA
tAA
tLZCE
tABE
CE
tHZCE
tACE
tLZCE
DATA OUT
Notes:
24. R/W is HIGH for read cycles.
25. Device is continuously selected CE = VIL. This waveform cannot be used for semaphore reads.
26. OE = VIL.
27. Address valid prior to or coincident with CE transition LOW.
28. To access RAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL.
Document #: 38-06051 Rev. *C
Page 10 of 20
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Switching Waveforms (continued)
Write Cycle No. 1: R/W Controlled Timing[29, 30, 31, 32]
tWC
ADDRESS
tHZOE [33]
OE
tAW
CE
[34]
tPWE[32]
tSA
tHA
R/W
tHZWE[33]
tLZWE
Note 35
Note 35
DATA OUT
tSD
tHD
DATA IN
Write Cycle No. 2: CE Controlled Timing[29, 30, 31, 36]
tWC
ADDRESS
tAW
CE
[34]
tSA
tSCE
tHA
R/W
tSD
tHD
DATA IN
Notes:
29. R/W must be HIGH during all address transitions.
30. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM.
31. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
32. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data
to be placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be
as short as the specified tPWE.
33. Transition is measured ±500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
34. To access RAM, CE = VIL, SEM = VIH.
35. During this period, the I/O pins are in the output state, and input signals must not be applied.
36. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
Document #: 38-06051 Rev. *C
Page 11 of 20
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Switching Waveforms (continued)
Semaphore Read After Write Timing, Either Side[37]
tOHA
tSAA
A 0–A 2
VALID ADRESS
VALID ADRESS
tAW
tACE
tHA
SEM
tSCE
tSOP
tSD
I/O 0
DATAIN VALID
tSA
tPWE
DATAOUT VALID
tHD
R/W
tSWRD
tDOE
tSOP
OE
WRITE CYCLE
READ CYCLE
Timing Diagram of Semaphore Contention[38, 39, 40]
A0L –A2L
MATCH
R/WL
SEM L
tSPS
A 0R –A 2R
MATCH
R/WR
SEM R
Notes:
37. CE = HIGH for the duration of the above timing (both write and read cycle).
38. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH.
39. Semaphores are reset (available to both ports) at cycle start.
40. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable.
Document #: 38-06051 Rev. *C
Page 12 of 20
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Switching Waveforms (continued)
Timing Diagram of Read with BUSY (M/S=HIGH)[41]
tWC
ADDRESSR
MATCH
tPWE
R/WR
tSD
DATA INR
tHD
VALID
tPS
ADDRESSL
MATCH
tBLA
tBHA
BUSYL
tBDD
tDDD
DATA OUTL
VALID
tWDD
Write Timing with Busy Input (M/S=LOW)
tPWE
R/W
BUSY
tWB
tWH
Note:
41. CEL = CER = LOW.
Document #: 38-06051 Rev. *C
Page 13 of 20
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Switching Waveforms (continued)
Busy Timing Diagram No. 1 (CE Arbitration)[42]
CELValid First:
ADDRESS L,R
ADDRESS MATCH
CEL
tPS
CER
tBLC
tBHC
BUSYR
CER Valid First:
ADDRESS L,R
ADDRESS MATCH
CER
tPS
CE L
tBLC
tBHC
BUSYL
Busy Timing Diagram No. 2 (Address Arbitration)[42]
Left Address Valid First
tRC or tWC
ADDRESS L
ADDRESS MATCH
ADDRESS MISMATCH
tPS
ADDRESSR
tBLA
tBHA
BUSY R
Right Address Valid First:
tRC or tWC
ADDRESSR
ADDRESS MATCH
ADDRESS MISMATCH
tPS
ADDRESSL
tBLA
tBHA
BUSY L
Note:
42. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.
Document #: 38-06051 Rev. *C
Page 14 of 20
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Switching Waveforms (continued)
Interrupt Timing Diagrams
Left Side Sets INTR :
ADDRESSL
tWC
WRITE FFF (See Functional Description)
tHA[43]
CE L
R/W L
INT R
tINS [44]
Right Side Clears INT R :
tRC
READ FFF
(See Functional Description)
ADDRESSR
CE R
tINR [44]
R/WR
OE R
INTR
Right Side Sets INT L:
tWC
ADDRESSR
WRITE FFE (See Functional Description)
tHA[43]
CE R
R/W R
INT L
tINS[44]
Left Side Clears INT L:
tRC
READ FFE
(See Functional Description)
ADDRESSR
CE L
tINR[44]
R/W L
OE L
INT L
Notes:
43. tHA depends on which enable pin (CEL or R/WL) is deasserted first.
44. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last.
Document #: 38-06051 Rev. *C
Page 15 of 20
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Table 1. Non-Contending Read/Write
Inputs
Outputs
CE
R/W
OE
SEM
H
X
X
H
High Z
Deselected: Power-Down
H
H
L
L
Data Out
Read Data in Semaphore Flag
X
X
H
X
High Z
I/O Lines Disabled
X
L
Data In
Write into Semaphore Flag
H
I/O0–I/O8
Operation
L
H
L
H
Data Out
Read
L
L
X
H
Data In
Write
L
X
X
L
Not Allowed
Table 2. Interrupt Operation Example (assumes BUSYL = BUSYR = HIGH)
Left Port
Right Port
R/WL
CEL
OEL
A0L–14L
INTL
R/WR
CER
OER
A0R–14R
INTR
Set Right INTR Flag
L
L
X
FFF[45]
X
X
X
X
X
L[46]
Reset Right INTR Flag
X
X
X
X
X
X
L
L
FFF[45]
H[47]
Set Left INTL Flag
X
X
X
X
L[47]
L
L
X
1FFE[45]
X
L
1FFE[45]
H[46]
X
X
X
X
X
Function
Reset Left INTL Flag
X
L
Table 3. Semaphore Operation Example
Function
I/O0–I/O8 Left
I/O0–I/O8 Right
No action
1
1
Semaphore free
Left port writes 0 to semaphore
0
1
Left Port has semaphore token
Right port writes 0 to semaphore
0
1
No change. Right side has no write access to semaphore
Left port writes 1 to semaphore
1
0
Right port obtains semaphore token
Left port writes 0 to semaphore
1
0
No change. Left port has no write access to semaphore
Right port writes 1 to semaphore
0
1
Left port obtains semaphore token
Left port writes 1 to semaphore
1
1
Semaphore free
Right port writes 0 to semaphore
1
0
Right port has semaphore token
Right port writes 1 to semaphore
1
1
Semaphore free
Left port writes 0 to semaphore
0
1
Left port has semaphore token
Left port writes 1 to semaphore
1
1
Semaphore free
Status
Note:
45. See Functional Description for specific addresses by device part number.
46. If BUSYL = L, then no change.
47. If BUSYR = L, then no change.
Document #: 38-06051 Rev. *C
Page 16 of 20
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Ordering Information
Package Availability Guide
Device
Organization
68-Pin PLCC
CY7C138AV
4K x 8
X
CY7C139AV
4K x 9
X
CY7C144AV
8K x 8
X
CY7C145AV
8K x 9
X
CY7C006AV
16K x 8
X
CY7C016AV
16K x 9
X
CY7C007AV
32K x 8
X
CY7C017AV
32K x 9
X
64-Pin TQFP
X
X
4K x8 3.3V Asynchronous Dual-Port SRAM
Speed
(ns)
Ordering Code
Package
Name
Package Type
Operating
Range
20
CY7C138AV–20JC
J81
68-Pin Plastic Leaded Chip Carrier
Commercial
25
CY7C138AV–25JC
J81
68-Pin Plastic Leaded Chip Carrier
Commercial
4K x9 3.3V Asynchronous Dual-Port SRAM
Speed
(ns)
Ordering Code
Package
Name
Package Type
Operating
Range
20
CY7C139AV–20JC
J81
68-Pin Plastic Leaded Chip Carrier
Commercial
25
CY7C139AV–25JC
J81
68-Pin Plastic Leaded Chip Carrier
Commercial
8K x8 3.3V Asynchronous Dual-Port SRAM
Speed
(ns)
20
25
Ordering Code
Package
Name
Package Type
CY7C144AV–20AC
A65
64-Pin Thin Quad Flat Pack
CY7C144AV–20JC
J81
68-Pin Plastic Leaded Chip Carrier
CY7C144AV–25AC
A65
64-Pin Thin Quad Flat Pack
CY7C144AV-25AXC
A65
64-Pin Pb-Free Thin Quad Flat Pack
CY7C144AV–25JC
J81
68-Pin Plastic Leaded Chip Carrier
CY7C144AV-25JXC
J81
68-Pin Pb-Free Plastic Leaded Chip Carrier
Operating
Range
Commercial
Commercial
8K x9 3.3V Asynchronous Dual-Port SRAM
Speed
(ns)
Ordering Code
Package
Name
Package Type
Operating
Range
20
CY7C145AV–20JC
J81
68-Pin Plastic Leaded Chip Carrier
Commercial
25
CY7C145AV–25JC
J81
68-Pin Plastic Leaded Chip Carrier
Commercial
16K x8 3.3V Asynchronous Dual-Port SRAM
Speed
(ns)
20
25
Ordering Code
Package
Name
Package Type
CY7C006AV–20AC
A65
64-Pin Thin Quad Flat Pack
CY7C006AV–20JC
J81
68-Pin Plastic Leaded Chip Carrier
CY7C006AV–25AC
A65
64-Pin Thin Quad Flat Pack
CY7C006AV-25AXC
A65
64-Pin Pb-Free Thin Quad Flat Pack
CY7C006AV–25JC
J81
68-Pin Plastic Leaded Chip Carrier
Document #: 38-06051 Rev. *C
Operating
Range
Commercial
Commercial
Page 17 of 20
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Ordering Information (continued)
16K x9 3.3V Asynchronous Dual-Port SRAM
Speed
(ns)
Ordering Code
Package
Name
Package Type
Operating
Range
20
CY7C016AV–20JC
J81
68-Pin Plastic Leaded Chip Carrier
Commercial
25
CY7C016AV–25JC
J81
68-Pin Plastic Leaded Chip Carrier
Commercial
32K x8 3.3V Asynchronous Dual-Port SRAM
Speed
(ns)
20
25
Ordering Code
Package
Name
Package Type
Operating
Range
CY7C007AV–20JC
J81
68-Pin Plastic Leaded Chip Carrier
Commercial
CY7C007AV–20JI
J81
68-Pin Plastic Leaded Chip Carrier
Industrial
CY7C007AV–25JC
J81
68-Pin Plastic Leaded Chip Carrier
Commercial
32K x9 3.3V Asynchronous Dual-Port SRAM
Speed
(ns)
20
25
Ordering Code
Package
Name
Package Type
Operating
Range
CY7C017AV–20JC
J81
68-Pin Plastic Leaded Chip Carrier
Commercial
CY7C017AV–20JI
J81
68-Pin Plastic Leaded Chip Carrier
Industrial
CY7C017AV–25JC
J81
68-Pin Plastic Leaded Chip Carrier
Commercial
Document #: 38-06051 Rev. *C
Page 18 of 20
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Package Diagrams
64-Lead Thin Plastic Quad Flat Pack (14 x 14 x 1.4 mm) A65
64-Lead Pb-Free Thin Plastic Quad Flat Pack (14 x 14 x 1.4mm) A65
51-85046-*B
68-Lead Plastic Leaded Chip Carrier J81
68-Lead Pb-Free Plastic Leaded Chip Carrier J81
51-85005-*A
All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-06051 Rev. *C
Page 19 of 20
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Document History Page
Document Title: CY7C138AV/144AV/006AV/CY7C139AV/145AV/016AV/CY7C007AV/017AV 3.3V 4K/8K/16K/32K x 8/9
Dual Port SRAM
Document Number: 38-06051
REV.
ECN NO.
Issue
Date
Orig. of
Change
**
110203
12/02/01
SZV
Change from Spec number: 38-00837 to 38-06051
*A
122301
12/27/02
RBI
Power up requirements added to Maximum Ratings Information
*B
237623
See ECN
YDT
Removed cross information from features section
*C
373615
See ECN
PCX
Added Pb-Free Logo
Added Pb-Free parts to ordering information:
CY7C144AV-25AXC, CY7C144AV-25JXC, CY7C006AV-25AXC
Document #: 38-06051 Rev. *C
Description of Change
Page 20 of 20
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